Feedback dac circuit based on deltasigma dac and fir filter and calibration method thereof

Abstract

This application relates to the field of mixed-signal circuit technology, and in particular to a feedback DAC circuit based on DeltaSigma DAC and FIR filter and its calibration method. The circuit is used to calibrate the feedback DAC in a Delta-Sigma ADC. The circuit includes a calibration excitation source module, which includes a ROM storage module, a digital DeltaSigma modulator, an FIR filter, and a single-bit DAC module. The FIR filter processes the two-level digital code signal output by the digital DeltaSigma modulator to obtain a three-level digital code signal, filtering out high-frequency quantization noise and reducing instantaneous jump amplitude of the two-level digital code signal. The single-bit DAC module then outputs an amplitude-discrete analog signal. The processing by the FIR filter makes the amplitude-discrete analog signal input to the ADC integrator smoother, thereby controlling the output swing of the integrator within the normal operating range and avoiding saturation.

Description

Technical Field

[0001] This application relates to the field of mixed-signal circuit technology, and in particular to a feedback DAC circuit based on DeltaSigmaDAC and FIR filters and its calibration method. Background Technology

[0002] In wideband CTDelta-Sigma ADCs, multi-bit quantization is typically used to reduce sensitivity to clock jitter and improve the signal-to-noise ratio. Therefore, in multi-bit feedback DACs, parameter mismatches among multiple DAC components inevitably lead to significant static errors in the feedback DAC, even with the same number of bits as the quantizer. Related technologies typically employ digital calibration algorithms for wideband CTDelta-Sigma ADCs. This involves using out-of-band or in-band two-tone signals as the excitation source during the calibration phase, finding and minimizing the energy at two specific frequency points in the frequency domain—essentially solving for an approximate solution to the static error of the feedback DAC in the digital domain. However, digital calibration algorithms must be performed in the frequency domain, meaning that on-chip implementation requires a large number of FTT units, increasing hardware costs.

[0003] To avoid digital calibration in the frequency domain, another related technique utilizes a single-bit Delta-Sigma DAC as the input excitation signal for the calibration stage. Since the output signal of a single-bit DAC is intrinsically linear, it does not introduce harmonics due to mismatch, thus ensuring that the noise floor of the input signal does not degrade the SNDR of the Delta-Sigma ADC being calibrated. However, while using a single-bit DAC as the calibration source offers intrinsic linearity, calibrating a wideband CTDelta-Sigma ADC with high quantization levels (e.g., 4-bit, 15-level) requires a significant increase in the input signal amplitude to traverse all DAC units. This can lead to integrator oversaturation, preventing the accurate extraction of the DAC mismatch estimate (static error information) from the feedback DAC.

[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0005] In view of this, the main objective of the embodiments of this application is to propose a feedback DAC circuit based on DeltaSigmaDAC and FIR filter, which can significantly increase the input signal amplitude during the calibration of the feedback DAC circuit to ensure that the input signal amplitude can call all DAC units to be calibrated, and avoid the integrator from oversaturating due to the large signal amplitude.

[0006] To achieve the above objectives, one aspect of this application proposes a feedback DAC circuit based on DeltaSigmaDAC and FIR filters. The feedback DAC circuit includes a calibration excitation source module, which generates an amplitude-discrete analog signal. The amplitude-discrete analog signal is input to the back end for solving the DAC mismatch estimate. The DAC mismatch estimate is used to calibrate the mismatch error of the feedback DAC in the ADC circuit. The calibration excitation source module includes a ROM storage module, a digital Delta-Sigma modulator, an FIR filter, and a single-bit DAC module. The output of the ROM storage module is connected to the input of the digital Delta-Sigma modulator, the output of the digital Delta-Sigma modulator is connected to the input of the FIR filter, and the output of the FIR filter is connected to the input of the single-bit DAC module. The analog signal includes a single-tone sine wave signal and a high-frequency noise signal. The ROM storage module is used to store the sine wave oversampled digital code signal. The digital Delta-Sigma modulator is used to oversample and noise-shape the sine wave oversampled digital code signal to obtain a two-level digital code signal. The FIR filter is used to filter out the high-frequency quantization noise and reduce the instantaneous jump amplitude of the two-level digital code signal to obtain a three-level digital code signal. The single-bit DAC module is used to discretize the three-level digital code signal to obtain the amplitude-discrete analog signal.

[0007] In some implementations, the feedback DAC circuit further includes an ADC module to be calibrated and a processing module; The output of the calibration excitation source module is connected to the input of the ADC module to be calibrated, and the output of the ADC module to be calibrated is connected to the input of the arithmetic module. The ADC module to be calibrated is used to quantize the amplitude discrete analog signal to obtain a quantization result, and the arithmetic module is used to fit and solve the quantization result to obtain the DAC mismatch estimate.

[0008] In some embodiments, the FIR filter is provided with several delay units, which are used to convert the currently input two-level digital code signal into a discrete time sequence. The output of each delay unit is multiplied by a preset filter coefficient and then accumulated by an adder to obtain the three-level digital code signal.

[0009] In some implementations, the output of the FIR filter is obtained by averaging the currently input two-level digital code signal with the two-level digital code signals input over several past cycles.

[0010] In some embodiments, the ADC module to be calibrated includes a loop filter, a multi-bit quantizer, and a multi-bit DAC module, with the output of the multi-bit DAC module connected to the loop filter. The output of the loop filter is connected to the input of the multi-bit quantizer, and the output of the multi-bit quantizer is fed back to the input of the multi-bit DAC module, wherein: The loop filter is used for noise shaping, modulating quantization noise from in-band to out-of-band to improve in-band SNR; The multi-bit quantizer is used to quantize the output signal of the loop filter, including the input signal and high-frequency quantization noise, to obtain digital code output and control code fed back to the multi-bit DAC module; The multi-bit DAC module is used to receive the digital code output, output an analog signal and feed it back to the virtual point of the first-stage integrator of the loop filter, and integrate the residual signal obtained by subtracting it from the input signal of the loop filter.

[0011] In some embodiments, the computation module includes a binary code to thermometer code decoder, a first digital decimation filter, a second digital decimation filter, a time-domain fitting circuit, an equation solving module, and a lookup table module. The output of the binary code to thermometer code decoder is connected to the input of the first digital decimation filter, the output of the first digital decimation filter is connected to the first input of the equation solving module, the output of the second digital decimation filter is connected to the input of the time-domain fitting circuit, the output of the time-domain fitting circuit is connected to the second input of the equation solving module, and the output of the equation solving module is connected to the input of the lookup table module. The binary code to thermometer code decoder is used to acquire the control code of the quantization result; the first digital decimation filter is used to perform decimation filtering on the output result of the binary code to thermometer code decoder to obtain a first decimation filtered signal; the second digital decimation filter is used to perform decimation filtering on the quantization result to obtain a second decimation filtered signal; the time-domain fitting circuit is used to perform time-domain fitting calculation on the second decimation filtered signal to obtain a residual signal; the equation solving module is used to solve the first decimation filtered signal and the residual signal to obtain the DAC mismatch estimate; and the lookup table module is used to store the DAC mismatch estimate.

[0012] In some embodiments, the feedback DAC circuit further includes: performing feedback DAC error correction processing on the output of the ADC module to be calibrated through the lookup table module.

[0013] To achieve the above objectives, another aspect of this application provides a calibration method for a feedback DAC circuit based on DeltaSigmaDAC and an FIR filter, the calibration method comprising: Acquire the pre-stored sinusoidal oversampled digital code signal; The sinusoidal oversampled digital code signal is subjected to oversampling and noise shaping processing to obtain a two-level digital code signal; By filtering out high-frequency quantization noise and reducing instantaneous jump amplitude of the two-level digital code signal, a three-level digital code signal is obtained. The three-level digital code signal is discretized to obtain the amplitude-discrete analog signal.

[0014] In some embodiments, the calibration method further includes: The analog signal with discrete amplitude is quantized to obtain the quantization result; The control code of the quantization result is obtained and combined with the quantization result for decimation filtering to obtain a decimation filtered signal, which includes a first decimation filtered signal and a second decimation filtered signal. The second decimated filtered signal is subjected to time-domain fitting calculation to obtain the residual signal; The first decimation filter signal and the residual signal are solved by the least mean square method to obtain the DAC mismatch estimate.

[0015] In some embodiments, the calibration method further includes: storing the DAC mismatch estimate in a lookup table module, and using the lookup table module to perform feedback DAC error correction processing on the output of the ADC module to be calibrated.

[0016] The embodiments of this application include at least the following beneficial effects: This application provides a feedback DAC circuit based on DeltaSigma DAC and FIR filter and its calibration method. This scheme calibrates the mismatch error of the feedback DAC unit of the ADC circuit by outputting a discrete-amplitude analog signal from the calibration excitation source module. The calibration excitation source module includes a ROM storage module, a digital DeltaSigma modulator, an FIR filter, and a single-bit DAC module. During calibration, the FIR filter processes the two-level digital code signal output by the digital DeltaSigma modulator to obtain a three-level digital code signal, filtering out high-frequency quantization noise and reducing instantaneous jump amplitude. The discrete-amplitude analog signal is then output by the single-bit DAC module. The FIR filter's processing makes the discrete-amplitude analog signal input to the ADC integrator smoother, thereby controlling the integrator's output swing within the normal operating range and avoiding saturation. Attached Figure Description

[0017] Figure 1 This is a structural diagram of the feedback DAC circuit provided in an embodiment of this application; Figure 2 Another structural diagram of the feedback DAC circuit provided in the embodiments of this application; Figure 3 A logic structure diagram of the FIR filter in the feedback DAC circuit provided in the embodiments of this application; Figure 4 This is a schematic diagram of the output simulation results of the FIR filter in the feedback DAC circuit provided in the embodiments of this application; Figure 5 The waveform of the Delta-Sigma ADC circuit after injecting a calibration signal before adding an FIR filter; Figure 6 A schematic diagram of the output spectrum and SNDR performance before and after calibration when injecting a calibration signal before adding an FIR filter; Figure 7 The waveform of the Delta-Sigma ADC circuit after adding an FIR filter and injecting a calibration signal. Figure 8 A schematic diagram showing the output spectrum and SNDR performance before and after calibration when a calibration signal is injected after adding an FIR filter; Figure 9 This is a schematic flowchart of the calibration method provided in the embodiments of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0019] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0020] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0022] Before providing a detailed description of the embodiments of this application, some of the nouns and terms involved in the embodiments of this application will be explained first. The nouns and terms involved in the embodiments of this application are subject to the following interpretations.

[0023] Analog-to-digital converters (ADCs) play an increasingly important role as a bridge between the digital and analog worlds, while the requirements for their accuracy, speed, area, and power consumption are also gradually increasing. Delta-Sigma ADCs are widely used, serving as crucial modules in communications, instrumentation, and consumer electronics. Compared to discrete-time Delta-Sigma ADCs, which can achieve ultra-high precision, continuous-time (CT) Delta-Sigma ADCs are easier to achieve with wideband, medium-precision performance, and offer advantages such as easy driving with resistive inputs and built-in anti-aliasing capabilities, thus finding wider applications in audio and wireless communications. With the development of wireless communication protocols, the bandwidth requirements for continuous-time Delta-Sigma ADCs are continuously increasing.

[0024] The basic structure of a continuous-time (CT) Delta-Sigma ADC includes a loop filter, a quantizer, and a feedback DAC. Its loop filter is implemented as a continuous-time integrator, avoiding rapid charging and discharging of the capacitor and facilitating higher sampling rates. However, the integrator coefficients are determined by the absolute value of RC, requiring a capacitor tuning array to adapt to variations in process corners, making it difficult to achieve accuracy above 18 bits. The quantizer is located inside the loop; non-ideal factors and noise are shaped by the high-pass filter, so their impact on the overall ADC is minimal. Depending on the loop filter structure, one or more feedback DACs are needed. Regardless of the structure, one feedback DAC will always directly feed into the input of the first-stage integrator. This means that any non-idealities in this feedback DAC will be directly transmitted to the final output without attenuation. Therefore, the non-idealities of this outermost feedback DAC are crucial to the entire ADC, and the errors it causes mainly originate from static errors, dynamic errors, and clock jitter. The static error of a feedback DAC mainly originates from the mismatch of the DAC unit, and is therefore prevalent in multi-bit quantized deltasigma ADCs, causing the amplitude of the DAC output waveform to deviate from the ideal value. The dynamic error of a feedback DAC mainly stems from the inconsistent slopes of the rising and falling edges of its output square wave, resulting in varying output waveform area depending on the input bitstream; this is also known as inter-symbol interference (ISI). The clock jitter of a feedback DAC primarily originates from the DAC's clock generation circuit, causing the area of ​​the DAC output waveform to deviate from the ideal value.

[0025] Multilevel quantization is essential in wideband high-speed continuous-time (CT) Delta-Sigma ADCs. The core reason is that it significantly reduces the system's sensitivity to clock jitter. By reducing the step height of the feedback DAC, noise charge generated by high-frequency jitter is greatly suppressed. At the same time, each additional bit in multi-bit quantization can improve the signal-to-noise ratio by 6dB. This allows the ADC to maintain high accuracy even at low oversampling rates (LowOSR) in high-speed scenarios. It can also ensure the stability of high-order loops by providing more deterministic linear gain. In addition, it can reduce the error jump amplitude at the integrator input, thereby reducing the stringent requirements on the op-amp slew rate and power consumption.

[0026] Multi-bit quantization in wideband high-speed continuous-time (CT) Delta-Sigma ADCs introduces static error issues in the feedback DAC, making feedback DAC mismatch a major factor affecting overall ADC performance. At lower bandwidths, static error suppression of the feedback DAC is typically achieved by inserting a digital calibration (DWA) between the quantizer and the feedback DAC, usually manifested as first-order noise shaping. However, this method is difficult to extend to higher bandwidth scenarios because the increased loop delay leads to loop instability, and higher bandwidth often comes with lower oversampling rates, significantly reducing the shaping effect of the DWA. Therefore, using digital calibration without introducing loop delay to suppress the static error of the feedback DAC has become the primary choice for higher bandwidth CT Delta-Sigma ADCs.

[0027] In related technologies, digital calibration algorithms use out-of-band or in-band two-tone signals as the excitation source for the calibration stage. They find and minimize the energy at these two specific frequency points in the frequency domain, essentially solving for an approximate solution to the static error of the feedback DAC in the digital domain. However, digital calibration algorithms must be performed in the frequency domain, which means that on-chip implementation requires a large number of FTT units, leading to increased hardware costs.

[0028] In another related technique, to avoid digital calibration in the frequency domain, a single-bit Delta-Sigma DAC is used as the input excitation signal for the calibration stage. Since the output signal of a single-bit DAC is intrinsically linear, it will not introduce harmonics due to mismatch, thus ensuring that the noise floor of the input signal will not degrade the SNDR of the Delta-Sigma ADC to be calibrated. However, although using a single-bit DAC as the calibration source has intrinsic linearity, when calibrating a wideband CTDelta-Sigma ADC with high quantization levels (e.g., 4-bit, 15-level), the input signal amplitude needs to be significantly increased to traverse all DAC units. This can lead to integrator oversaturation, making it impossible to correctly extract the DAC mismatch estimate (static error information) from the feedback DAC.

[0029] In view of this, this application provides a feedback DAC circuit based on DeltaSigmaDAC and an FIR filter, using a single-bit signal as the calibration source (to ensure intrinsic linearity). The single-bit signal must exhibit a large-amplitude, low-frequency sinusoidal wave characteristic. After Delta-Sigma modulation, it appears in the time domain as a square wave with abrupt jumps between positive and negative full-scale ranges. When such a large-amplitude, rapidly jumping signal is directly input to the ADC, the first-stage integrator of the ADC will fail to establish up in time due to excessive instantaneous error energy, causing the output signal to exceed the dynamic range of the op-amp and saturate. Once saturated, not only will the correct mismatch information be unable to be extracted, but calibration may even fail. This solution utilizes an FIR filter as a low-pass filter to filter out a large amount of high-frequency quantization noise in the input digital bitstream. It smooths the abrupt instantaneous jumps of the single-bit signal and reduces the instantaneous error amplitude of the signal. This makes the signal input to the ADC integrator smoother, thereby controlling the output swing of the integrator within the normal operating range and avoiding saturation.

[0030] Figure 1 This is a structural diagram of a feedback DAC circuit based on DeltaSigmaDAC and FIR filter provided in an embodiment of this application.

[0031] Please see Figure 1 The feedback DAC circuit includes a calibration excitation source module, which generates an amplitude-discrete analog signal. The amplitude-discrete analog signal is input to the back end to solve for the DAC mismatch estimate. The DAC mismatch estimate is used to calibrate the mismatch error of the feedback DAC in the ADC circuit.

[0032] It is understandable that a continuous-time (CT) Delta-Sigma ADC includes a loop filter, a quantizer, and a feedback DAC. Figure 1 The illustrated feedback DAC circuit is used to output an analog signal with discrete amplitude. This analog signal is input into a continuous-time (CT) Delta-Sigma ADC and output after passing through the feedback DAC. This output can be used to solve for the DAC mismatch estimate, which is used to calibrate the mismatch error of the feedback DAC in the ADC circuit.

[0033] Specifically, the calibration excitation source module includes a ROM storage module, a digital Delta-Sigma modulator, an FIR filter, and a single-bit DAC module. The output of the ROM storage module is connected to the input of the digital Delta-Sigma modulator, the output of the digital Delta-Sigma modulator is connected to the input of the FIR filter, and the output of the FIR filter is connected to the input of the single-bit DAC module. The analog signal includes a single-tone sine wave signal and a high-frequency noise signal. The ROM storage module is used to store the sine wave oversampled digital code signal. The digital Delta-Sigma modulator is used to oversample and noise-shape the sine wave oversampled digital code signal to obtain a two-level digital code signal. The FIR filter is used to filter out the high-frequency quantization noise and reduce the instantaneous jump amplitude of the two-level digital code signal to obtain a three-level digital code signal. The single-bit DAC module is used to discretize the three-level digital code signal to obtain the amplitude-discrete analog signal.

[0034] This scheme calibrates the mismatch error of the feedback DAC unit of the ADC circuit by outputting a discrete-amplitude analog signal from the calibration excitation source module. The calibration excitation source module includes a ROM storage module, a digital DeltaSigma modulator, an FIR filter, and a single-bit DAC module. During calibration, the FIR filter processes the two-level digital code signal output by the digital DeltaSigma modulator to obtain a three-level digital code signal, filtering out high-frequency quantization noise and reducing instantaneous jump amplitude in the two-level digital code signal. The discrete-amplitude analog signal is then output by the single-bit DAC module. The processing by the FIR filter makes the discrete-amplitude analog signal input to the ADC integrator smoother, thereby controlling the output swing of the integrator within the normal operating range and avoiding saturation.

[0035] Figure 2 Another structural diagram of the feedback DAC circuit provided in the embodiments of this application. Please see Figure 2 In some embodiments, the feedback DAC circuit further includes an ADC module to be calibrated and a computation module. It is understood that, in this embodiment, by combining the calibration excitation source module in the feedback DAC circuit shown in the above embodiments with the ADC module to be calibrated and the computation module, a continuous-time (CT) Delta-Sigma ADC with self-calibration function can be obtained.

[0036] The output of the calibration excitation source module is connected to the input of the ADC module to be calibrated, and the output of the ADC module to be calibrated is connected to the input of the arithmetic module. The ADC module to be calibrated is used to quantize the amplitude discrete analog signal to obtain a quantization result, and the arithmetic module is used to fit and solve the quantization result to obtain the DAC mismatch estimate.

[0037] Specifically, the computation module includes a binary-to-thermometer code decoder, a digital decimation filter, a time-domain fitting circuit, an equation-solving module, and a lookup table. The decoder obtains the control code for each bit of the DAC unit. The digital decimation filter removes out-of-band quantization noise and can reuse the digital decimation filter from the normal operation phase of the ADC. The output digital code of the ADC to be calibrated is obtained after decimation filtering and then fed into the time-domain fitting module to obtain the residual signal. The decoder output, after decimation, along with the residual signal, is fed into the equation-solving module to obtain an estimate of the feedback DAC mismatch, which is then stored in the lookup table, ending the calibration phase. During normal operation, the ADC output digital code is corrected in real time, thereby eliminating the static error of the feedback DAC in the output.

[0038] The output of a continuous-time (CT) Delta-Sigma ADC is multi-bit, meaning its feedback DAC has multiple units. Therefore, the calibration signal must have a large amplitude to activate and traverse the outermost feedback DAC units. The calibration source uses a single-bit signal (to ensure intrinsic linearity). This single-bit signal must exhibit a large-amplitude, low-frequency sinusoidal wave characteristic. After Delta-Sigma modulation, it appears in the time domain as a square wave with abrupt jumps between positive and negative full-scale values. When such a large-amplitude, rapidly jumping signal is directly input to the ADC, the first-stage integrator of the ADC will fail to establish up in time due to the excessive instantaneous error energy, causing the output signal to exceed the dynamic range of the op-amp and saturate. Once saturated, not only will the correct mismatch information be unable to be extracted, but calibration may even fail.

[0039] This application inserts an FIR filter between the digital DeltaSigma modulator and the single-bit DAC module, acting as a low-pass filter to remove a significant amount of high-frequency quantization noise from the input digital bitstream. It smooths out the sharp transient transitions of the single-bit signal, reducing the amplitude of the signal's instantaneous error. This makes the signal input to the ADC integrator more "smooth," thereby keeping the integrator's output swing within its normal operating range and avoiding saturation.

[0040] Figure 3 The diagram shows the logic structure of the FIR filter in the feedback DAC circuit provided in the embodiments of this application.

[0041] Specifically, the FIR filter includes several delay units, which convert the currently input two-level digital code signal into a discrete time sequence. The output of each delay unit is multiplied by preset filter coefficients and then accumulated by an adder to obtain the three-level digital code signal. The output of the FIR filter is obtained by averaging the currently input two-level digital code signal with the two-level digital code signals input over several past cycles.

[0042] In this structure, the input signal A discrete time series is formed by sequentially passing the signal through a series of delay units. The signal at each delay node is extracted and compared with preset filter coefficients. Perform multiplication. Finally, all product terms are processed by the adder ( Accumulate to generate an output signal. The mathematical description of this physical process is defined by the following difference equation: , This equation shows that the output y(n) of the FIR filter is a discrete convolution of the input sequence x(n) and the unit impulse response h(k). Physically, the current output value depends not only on the current input but also on the input values ​​from the past N-1 time points. The coefficient h(k) acts as a weighting factor, determining the degree to which the filter weights the signal at different time points, thus enabling frequency selection functions such as low-pass, high-pass, or band-pass.

[0043] The system transfer function of the FIR filter is obtained by performing Z-transform domain representation as follows: , The transfer function is about The polynomial has no poles. This means the system is essentially stable in the Z-plane and avoids the risk of self-oscillation caused by feedback, as seen in infinite impulse response (IIR) filters. Since there is no denominator term (i.e., no feedback), when a pulse signal is input, the output only exhibits a finite number of terms. The FIR filter is non-zero within each sampling point. Therefore, the FIR filter is a non-recursive, stable, and linear time-invariant (LTI) system based on a weighted moving average.

[0044] Understandably, a two-level digital signal jumps directly from -1 to +1, a change of 2. After passing through an FIR filter, the signal change is gradual (multi-bit), for example, -1... -0.8 -0.5... +1. This gradual change significantly reduces the signal conversion rate. For integrators, the smoother the change in the input signal, the easier it is for the loop to track, the smaller the error difference at the input, and the lower the output swing of the integrator can be controlled.

[0045] It should be noted that without an FIR filter, the calibration source is a single-bit signal modulated with Delta-Sigma. This signal exhibits extreme characteristics in both the frequency and time domains; in the time domain, it is a square wave that can only reach two extreme values ​​( and The signal jumps drastically between these two extreme values. To simulate an intermediate level, it must rapidly switch back and forth between these two extreme values. In the frequency domain: to ensure a high signal-to-noise ratio for low-frequency signals, the Delta-Sigma modulator uses "noise shaping" technology, pushing a large amount of quantization noise to higher frequencies. This means that although the average value of the signal is the desired sine wave, it is superimposed with noise components of huge amplitude and extremely high frequency. The first-stage integrator of the Delta-Sigma ADC is an analog circuit whose input is the difference between the "input signal" and the "feedback signal". When the calibration signal is injected directly: because the input signal is a drastically jumping square wave, and the ADC's feedback loop bandwidth is limited, it cannot respond instantaneously to such high-frequency jumps. Therefore, at the moment of the jump, a huge error peak appears at the integrator input. The function of the integrator is to accumulate ( Although the integrator itself has low-pass characteristics ( While integrators can suppress high frequencies to some extent, when the input high-frequency noise amplitude and density are extremely high, the charge on the integrator capacitors accumulates rapidly, causing the output voltage to spike very high instantaneously. This results in a huge "ripple" or "glitches" superimposed on the integrator's output waveform, making it easy for the signal to touch the op-amp's power rails and cause saturation. Existing solutions require artificially reducing the amplitude of the input signal to avoid saturation. After reducing the amplitude, the calibration signal can only cover the middle few DAC units, failing to cover the outermost DAC units. This means that the mismatch of the outermost DACs cannot be measured and calibrated.

[0046] Therefore, the FIR filter provided in this application solves the saturation problem, allowing the ADC to safely inject a calibration signal close to full scale. The FIR filter enables the calibration signal to powerfully drive the ADC, utilizing all feedback DAC units, thus ensuring that the calibration algorithm can extract complete DAC mismatch information. The calibration algorithm (LMS) relies on the ADC's response in the linear region. The FIR filter not only prevents hard saturation but also reduces nonlinear harmonic components in the input signal, ensuring that the input signal is mainly concentrated within the frequency band required by the algorithm, thereby improving the accuracy of solving the LMS equation.

[0047] In some embodiments, the ADC module to be calibrated includes a loop filter, a multi-bit quantizer, and a multi-bit DAC module, with the output of the multi-bit DAC module connected to the loop filter. The output of the loop filter is connected to the input of the multi-bit quantizer, and the output of the multi-bit quantizer is fed back to the input of the multi-bit DAC module, wherein: The loop filter is used for noise shaping, modulating quantization noise from in-band to out-of-band to improve in-band SNR; The multi-bit quantizer is used to quantize the output signal of the loop filter, including the input signal and high-frequency quantization noise, to obtain digital code output and control code fed back to the multi-bit DAC module; The multi-bit DAC module is used to receive the digital code output, output an analog signal and feed it back to the virtual point of the first-stage integrator of the loop filter, and integrate the residual signal obtained by subtracting it from the input signal of the loop filter.

[0048] In some embodiments, the computation module includes a binary code to thermometer code decoder, a first digital decimation filter, a second digital decimation filter, a time-domain fitting circuit, an equation solving module, and a lookup table module. The output of the binary code to thermometer code decoder is connected to the input of the first digital decimation filter, the output of the first digital decimation filter is connected to the first input of the equation solving module, the output of the second digital decimation filter is connected to the input of the time-domain fitting circuit, the output of the time-domain fitting circuit is connected to the second input of the equation solving module, and the output of the equation solving module is connected to the input of the lookup table module. The binary code to thermometer code decoder is used to acquire the control code of the quantization result; the first digital decimation filter is used to perform decimation filtering on the output result of the binary code to thermometer code decoder to obtain a first decimation filtered signal; the second digital decimation filter is used to perform decimation filtering on the quantization result to obtain a second decimation filtered signal; the time-domain fitting circuit is used to perform time-domain fitting calculation on the second decimation filtered signal to obtain a residual signal; the equation solving module is used to solve the first decimation filtered signal and the residual signal to obtain the DAC mismatch estimate; and the lookup table module is used to store the DAC mismatch estimate.

[0049] In some implementations, the method further includes performing feedback DAC error correction processing on the output of the ADC module to be calibrated through the lookup table module.

[0050] The following section provides a detailed description and explanation of the FIR filter design in the embodiments of this application, using specific application examples: (1) The transfer function of the FIR filter is designed as follows: , In the time domain, this means that the current output is equal to the average of the current input and the input from 6 cycles ago.

[0051] The mathematical expression for the output of the FIR filter is: , A comparative analysis of the input signal before and after passing through this filter reveals a two-level digital code signal ( The signal has two voltage levels, and its time-domain characteristics are: the waveform looks like a chaotic square wave. and The values ​​change drastically between these values. To represent intermediate values ​​(such as 0V), it must be displayed at extremely high frequencies. and It switches quickly between these states. Each transition is at full scale, with a change of [value missing]. Its frequency domain characteristics include low-frequency useful signals as well as extremely high-amplitude out-of-band high-frequency noise.

[0052] For the FIR filter output signal ( ),go through After processing, the signal changed: due to only and Given two possible values, what are their combinations? The following three possible outcomes may occur: , , , Understandably, the signal changed from a 2-level (1-bit) to a 3-level (1.5-bit / ternary). The signal is no longer simply "0 and 1," but now includes a buffered "0" level. Previously, the signal had to... Jump directly to The transition amplitude is 2. The signal can then start from... Change to , and then from Change to Each transition may only be 1. The slew rate of the signal is reduced. The input becomes more moderate for the integrator.

[0053] The frequency response of this filter is a cosine-shaped comb filter. It will at specific frequency points (such as...) (etc.) generates zeros, meaning the gain at these frequencies is 0. This "averaging" operation cancels out some of the energy from the rapid high-frequency flips. The violent high-frequency oscillations that would normally be generated to represent the average value are smoothed out by this "6-cycle delayed averaging."

[0054] like Figure 7As shown, the FIR filter transforms a rapidly changing 2-level signal into a mild 3-level signal. Although it sacrifices the purity of a single bit, this averaging operation significantly reduces the high-frequency energy of the signal, thereby avoiding saturation.

[0055] (2) The hardware implementation of FIR filters includes the following three methods: 1. FPGA-based implementation: Benefiting from its parallel processing capabilities, FPGA is often the preferred platform for implementing high-performance FIR filters. Its development process mainly includes: 1.1 HDL code writing (VHDL / Verilog): This is a low-level design method that directly describes logical resources such as delay registers, multipliers, and adders through code. This method offers the strongest control over hardware resources, but the development cycle is relatively long.

[0056] 1.2 IP Core Calling: Utilizing the FIRCompiler IP core provided by chip manufacturers (such as Xilinx or Intel) for design. Designers only need to configure parameters such as passband, stopband, and order, and EDA tools can automatically generate the optimal circuit structure based on distributed algorithms (DA) or DSPSlice.

[0057] 1.3 Model-Based Design: also known as the Xilinx System Generator method. This tool, based on the MATLAB / Simulink environment, allows users to build systems in a modular manner and automatically generates FPGA configuration files (Bitstream).

[0058] 2. DSP Processor-Based Implementation: This method typically employs a dedicated digital signal processor (such as the TIC6000 series). These chips utilize a Harvard architecture and are equipped with dedicated MAC (multiply-accumulate) instructions, enabling them to complete one multiply-accumulate operation within one clock cycle. They are usually implemented using software programming in C or assembly language.

[0059] 3. ASIC-based implementation involves integrating the FIR filter logic onto an application-specific integrated circuit (ASIC) chip through digital circuit design and synthesis processes to meet specific power consumption or size requirements.

[0060] (3) The following is an example of an FIR filter implementation based on HDL code: 3.1 For the transfer function of an FIR filter: , Its Verilog code implementation is as follows: timescale 1ns / 1ps module fir_filter_z6#( parameter DATA_WIDTH = 16 )( input wire clk, / / Clock signal input wire rst_n, / / Reset signal input wire signed [DATA_WIDTH - 1:0] x_in, / / Input signal (x[n]) output reg signed [DATA_WIDTH - 1:0] y_out / / Output signal (y[n]) ); reg signed [DATA_WIDTH - 1:0] delay_line[0:5]; reg signed [DATA_WIDTH:0] sum_temp; integer i; always @(posedge clk or negedge rst_n) begin if (!rst_n) begin / / Reset y_out <= 0; sum_temp <= 0; for (i = 0; i < 6; i = i + 1) begin delay_line[i] <= 0; end end else begin delay_line[0] <= x_in; for (i = 1; i < 6; i = i + 1) begin ​​​​​​​​​​​​​​3.2 Test the FIR filter. The test code is as follows: `timescale 1ns / 1ps` moduletb_fir; regclk; regrst_n; regsigned[15:0]x_in; wiresigned[15:0]y_out; fir_filter_z6#(.DATA_WIDTH(16))u_fir( .clk(clk), .rst_n(rst_n), .x_in(x_in), .y_out(y_out) ); initialclk=0; always#0.0625clk=~clk; taskdrive_bipolar_random; inputintegernum_samples; integeri; reg[31:0]rand_val; begin for(i=0;i <num_samples;i=i+1)begin @(posedgeclk); rand_val = $random; if(rand_val[0]==1'b1) x_in<=16'sd1; / / Send +1 else x_in<=-16'sd1; / / Send -1 end end endtask initialbegin / / 1. Initialization rst_n=0; x_in=0; #20rst_n=1; $display("StartingRandomBipolarPattern(+1 / -1)..."); drive_bipolar_random(500000); end initialbegin $monitor("Time=%t|x_in=%d|y_out=%d",$time,x_in,y_out); end Endmodule Figure 4 A schematic diagram of the FIR filter output simulation results is shown, such as... Figure 4 As shown, after passing through the FIR filter, the two-level signal becomes a three-level signal, consistent with the MATLAB simulation.

[0061] (4) Verification: The verification was performed using a single-loop CRFF third-order CT Delta-Sigma ADC with a sampling rate of 1600MS / s and a bandwidth of 40MHz. It has 4 quantization bits and 15 DAC units, with an artificially added outermost feedback DAC mismatch of 1.7% and an inner feedback DAC mismatch of 1.7%.

[0062] Figure 5 The waveforms at each node after injecting a 5.265 LSB calibration signal are shown. Figure 6 The output spectrum and SNDR performance before and after calibration when injecting a 5.265 LSB calibration signal are shown. Before calibration, SNR=76.8dB and SNDR=62.4dB; after calibration, SNR=46.1dB and SNDR=36.8dB. Due to the injection of a square wave with a large signal amplitude, the integrator saturates, and mismatch information cannot be extracted, or incorrect mismatch information is extracted.

[0063] like Figure 3 As shown, an FIR filter is added before the single-bit DAC to avoid integrator saturation while ensuring as much mismatch information as possible.

[0064] Figure 7 The waveforms at each node are shown after injecting a 5.265 LSB calibration signal, at which point the integrators at each node are not saturated. Figure 8 The output spectrum and SNDR performance before and after calibration when a 5.265 LSB calibration signal is injected are shown. It can be seen that before calibration, SNR=76.8dB and SNDR=62.4dB; after calibration, SNR=86.6dB and SNDR=84.2dB. With the addition of FIR, the technique of injecting a single-bit DAC into a DDSM to calibrate DSM mismatch can be extended to multi-level application scenarios.

[0065] Figure 9 A calibration method for a feedback DAC circuit based on a DeltaSigma DAC and an FIR filter is provided for embodiments of this application.

[0066] This application provides a calibration method for a feedback DAC circuit based on DeltaSigmaDAC and FIR filters, the calibration method including, but not limited to, steps 10 to 40: Step 10: Obtain the pre-stored sine wave oversampled digital code signal; Step 20: Perform oversampling and noise shaping processing on the sinusoidal oversampled digital code signal to obtain a two-level digital code signal; Step 30: Filter out the high-frequency quantization noise and reduce the instantaneous jump amplitude of the two-level digital code signal to obtain a three-level digital code signal; Step 40: Discretize the three-level digital code signal to obtain the amplitude-discrete analog signal.

[0067] In some embodiments, the calibration method further includes: Step 50: Quantize the acquired amplitude discrete analog signal to obtain the quantization result; Step 60: Obtain the control code of the quantization result and perform decimation filtering processing on the quantization result to obtain a decimation filtered signal, wherein the decimation filtered signal includes a first decimation filtered signal and a second decimation filtered signal. Step 70: Perform time-domain fitting calculation on the second decimation-filtered signal to obtain the residual signal; Step 80: The first decimation filter signal and the residual signal are solved and processed by the least mean square method to obtain the DAC mismatch estimate.

[0068] In some embodiments, the calibration method further includes step 90: storing the DAC mismatch estimate into a lookup table module, and using the lookup table module to perform feedback DAC error correction processing on the output of the ADC module to be calibrated.

[0069] During the calibration phase, the output of the single-bit Delta-Sigma DAC contains a low-frequency sine wave and shaped quantization noise, which serves as the input signal for the Delta-Sigma ADC calibration phase. The quantization result of the Delta-Sigma ADC on the output of the single-bit Delta-Sigma DAC is a digital code. Its expression is shown in the following formula: , in, The quantization results are for the Delta-Sigma ADC. Indicates the input signal. This represents the quantization noise shaped by the Delta-Sigma ADC. This represents the quantization noise shaped by the digital Delta-Sigma modulator. This represents the static error of the feedback DAC.

[0070] like Figure 2 As shown, Figure 2 In this context, L(z) represents the digital decimation filter, which converts the digital code... By extracting the OSR factor and filtering out out-of-band high-frequency quantization noise, the expression is as follows: , , in, and The noise floor within the band is only a relatively small value. The static error of the feedback DAC can be expressed as the digital code of each bit multiplied by the DAC mismatch value, as shown in the formula above. This represents the result of decimation filtering for each digit of the code. This represents the mismatch value of each bit in the DAC. This indicates the number of sampling points involved in the calculation.

[0071] Due to the presence of in-band noise terms, this system of equations is overdetermined and has no exact solution. Therefore, the least mean square method is required to obtain the solution. The approximate solution is obtained by the following set of error estimation equations: , in, This represents the estimated mismatch value for each DAC unit, where L is the number of bits in the DAC. By solving this system of error estimation equations, the estimated mismatch value of the DAC is obtained and stored in a lookup table, thus ending the calibration phase. During normal operation, the output digital code is corrected in real time by the lookup table, thereby eliminating the feedback DAC static error in the output.

[0072] It is understood that the content of the above method embodiments is applicable to the present device embodiments. The specific functions implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0073] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described method. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0074] It is understood that the content of the above method embodiments is applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0075] Please see Figure 9 , Figure 9 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes: The processor 901 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 902 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 902 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 902 and is called and executed by the processor 901 using the methods described in the embodiments of this application. The 903 input / output interface is used to implement information input and output. The communication interface 904 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 905 transmits information between various components of the device (e.g., processor 901, memory 902, input / output interface 903, and communication interface 904); The processor 901, memory 902, input / output interface 903, and communication interface 904 are connected to each other within the device via bus 905.

[0076] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0077] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0078] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0079] It is understood that the content of the above method embodiments is applicable to the embodiments of this program product. The specific functions implemented by the embodiments of this program product are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0080] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0081] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0082] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0083] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0084] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0085] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0086] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0087] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0088] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0089] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0090] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0091] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A feedback DAC circuit based on DeltaSigmaDAC and FIR filter, characterized in that, The feedback DAC circuit includes a calibration excitation source module; The calibration excitation source module is used to generate an analog signal with discrete amplitude. The analog signal with discrete amplitude is used as input to the back end to solve for the DAC mismatch estimate. The DAC mismatch estimate is used to calibrate the mismatch error of the feedback DAC in the ADC circuit. The calibration excitation source module includes a ROM storage module, a digital Delta-Sigma modulator, an FIR filter, and a single-bit DAC module. The output of the ROM storage module is connected to the input of the digital Delta-Sigma modulator, the output of the digital Delta-Sigma modulator is connected to the input of the FIR filter, and the output of the FIR filter is connected to the input of the single-bit DAC module. The analog signal includes a single-tone sine wave signal and a high-frequency noise signal. The ROM storage module is used to store the sine wave oversampled digital code signal. The digital Delta-Sigma modulator is used to oversample and noise-shape the sine wave oversampled digital code signal to obtain a two-level digital code signal. The FIR filter is used to filter out the high-frequency quantization noise and reduce the instantaneous jump amplitude of the two-level digital code signal to obtain a three-level digital code signal. The single-bit DAC module is used to discretize the three-level digital code signal to obtain the amplitude-discrete analog signal.

2. The feedback DAC circuit as described in claim 1, characterized in that, The feedback DAC circuit also includes an ADC module to be calibrated and a processing module; The output of the calibration excitation source module is connected to the input of the ADC module to be calibrated, and the output of the ADC module to be calibrated is connected to the input of the arithmetic module. The ADC module to be calibrated is used to quantize the amplitude discrete analog signal to obtain a quantization result, and the arithmetic module is used to fit and solve the quantization result to obtain the DAC mismatch estimate.

3. The feedback DAC circuit as described in claim 1, characterized in that, The FIR filter is provided with several delay units. The delay units are used to convert the currently input two-level digital code signal into a discrete time sequence. The output of each delay unit is multiplied by a preset filter coefficient and then accumulated by an adder to obtain the three-level digital code signal.

4. The feedback DAC circuit as described in claim 3, characterized in that, The output of the FIR filter is obtained by averaging the currently input two-level digital code signal and the two-level digital code signals input in the past several cycles.

5. The feedback DAC circuit according to claim 1, characterized in that, The ADC module to be calibrated includes a loop filter, a multi-bit quantizer, and a multi-bit DAC module. The output of the multi-bit DAC module is connected to the loop filter. The output of the loop filter is connected to the input of the multi-bit quantizer, and the output of the multi-bit quantizer is fed back to the input of the multi-bit DAC module, wherein: The loop filter is used for noise shaping, modulating quantization noise from in-band to out-of-band to improve in-band SNR; The multi-bit quantizer is used to quantize the output signal of the loop filter, including the input signal and high-frequency quantization noise, to obtain digital code output and control code fed back to the multi-bit DAC module; The multi-bit DAC module is used to receive the digital code output, output an analog signal and feed it back to the virtual point of the first-stage integrator of the loop filter, and integrate the residual signal obtained by subtracting it from the input signal of the loop filter.

6. The feedback DAC circuit according to claim 1, characterized in that, The computation module includes a binary code to thermometer code decoder, a first digital decimation filter, a second digital decimation filter, a time-domain fitting circuit, an equation solving module, and a lookup table module. The output of the binary code to thermometer code decoder is connected to the input of the first digital decimation filter, the output of the first digital decimation filter is connected to the first input of the equation solving module, the output of the second digital decimation filter is connected to the input of the time-domain fitting circuit, the output of the time-domain fitting circuit is connected to the second input of the equation solving module, and the output of the equation solving module is connected to the input of the lookup table module. The binary code to thermometer code decoder is used to acquire the control code of the quantization result; the first digital decimation filter is used to perform decimation filtering on the output result of the binary code to thermometer code decoder to obtain a first decimation filtered signal; the second digital decimation filter is used to perform decimation filtering on the quantization result to obtain a second decimation filtered signal; the time-domain fitting circuit is used to perform time-domain fitting calculation on the second decimation filtered signal to obtain a residual signal; the equation solving module is used to solve the first decimation filtered signal and the residual signal to obtain the DAC mismatch estimate; and the lookup table module is used to store the DAC mismatch estimate.

7. The feedback DAC circuit according to claim 6, characterized in that, The feedback DAC circuit further includes: performing feedback DAC error correction processing on the output result of the ADC module to be calibrated through the lookup table module.

8. A calibration method for a feedback DAC circuit based on DeltaSigmaDAC and FIR filters, characterized in that, The calibration method includes: Acquire the pre-stored sinusoidal oversampled digital code signal; The sinusoidal oversampled digital code signal is subjected to oversampling and noise shaping processing to obtain a two-level digital code signal; By filtering out high-frequency quantization noise and reducing instantaneous jump amplitude of the two-level digital code signal, a three-level digital code signal is obtained. The three-level digital code signal is discretized to obtain the amplitude-discrete analog signal.

9. The calibration method as described in claim 8, characterized in that, The calibration method further includes: The analog signal with discrete amplitude is quantized to obtain the quantization result; The control code of the quantization result is obtained and combined with the quantization result for decimation filtering to obtain a decimation filtered signal, which includes a first decimation filtered signal and a second decimation filtered signal. The second decimated filtered signal is subjected to time-domain fitting calculation to obtain the residual signal; The first decimation filter signal and the residual signal are solved by the least mean square method to obtain the DAC mismatch estimate.

10. The calibration method as described in claim 8, characterized in that, The calibration method further includes: storing the DAC mismatch estimate into a lookup table module, and using the lookup table module to perform feedback DAC error correction processing on the output of the ADC module to be calibrated.

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