RS485 hub and communication system

Abstract

This invention belongs to the technical field of hubs, specifically relating to an RS485 hub and communication system, including: an internal bus and a transceiver unit; the transceiver unit includes a transceiver, a logic control module, a direction control module, and a receive isolation module; the transceiver is used for signal conversion; the logic control module is used to provide data signals to the input terminal of the transceiver according to the level state of the internal bus and the level state of the transceiver's output terminal; the direction control module is connected to the control terminals of the logic control module and the transceiver respectively, and is used to control the working state of the transceiver according to the output signal of the logic control module; the receive isolation module is connected between the output terminal of the transceiver and the internal bus, and is used to transmit a low-level signal to the internal bus when the output terminal is low, and to isolate the internal bus from the output terminal when the output terminal is high. These improvements enhance the reliability of the RS485 hub.

Description

Technical Field

[0001] This invention belongs to the technical field of hubs, specifically relating to an RS485 hub and communication system. Background Technology

[0002] RS485 buses are widely used in industrial automation, building control, and other fields, with a standard bus topology. When multiple branches need to be connected, hubs are often used to build tree or star networks. However, most RS485 hubs on the market are actually "splitters" or "isolation devices," internally employing a master port (usually labeled UPLINK) and multiple slave ports (branch ports). In this architecture, the data forwarding path is unidirectional and centralized: the master port can communicate with any slave port, but data from a slave port can only be sent to the master port and cannot be forwarded directly or indirectly (through the hub's internal mechanisms) between other slave ports. This results in isolation between slave devices, making them unable to perceive each other's status or data, limiting applications in scenarios requiring broadcast notifications, data monitoring, network diagnostics, or multi-slave synchronization.

[0003] Disadvantages of existing technology: 1. Its function is essentially that of a "splitter" rather than a "hub": Existing devices only achieve physical branching of connections, not logical full mesh connectivity. Complete data isolation between ports violates the fundamental functional expectation of a "hub"—data interoperability between ports.

[0004] 2. Limited communication model: It forces a "master-slave" single-hop communication model. Any information exchange between slave devices must be forwarded twice through the host software protocol layer, which increases the host's burden and communication latency, and makes it impossible to achieve real-time broadcasting of slave data.

[0005] 3. Poor network transparency: Due to the isolation between slave devices, one slave device cannot listen to the responses of other slave devices to the master device, which is not conducive to network debugging, troubleshooting and overall monitoring of system status.

[0006] 4. Application scenario limitations: It cannot be used in applications that require mutual awareness or synchronization between slave devices, such as multiple devices needing to receive and execute the same command simultaneously and then confirm with each other, or devices needing to compete to report. Summary of the Invention

[0007] This application discloses an RS485 hub and communication system, which can improve the reliability of the RS485 hub.

[0008] The first aspect of this application discloses an RS485 hub, comprising: an internal bus and a transceiver unit; the transceiver unit includes a transceiver, a logic control module, a direction control module, and a receive isolation module; The transceiver is used to convert signals and has two working states: receive mode and transmit mode. The logic control module is connected to the internal bus, the output terminal of the transceiver, and the input terminal of the transceiver, respectively, and is used to provide data signals to the input terminal of the transceiver according to the level state of the internal bus and the level state of the output terminal of the transceiver; The direction control module is connected to the logic control module and the control terminal of the transceiver, respectively, and is used to control the working state of the transceiver according to the output signal of the logic control module. The receiving isolation module is connected to the output terminal of the transceiver and the internal bus respectively. It is used to transmit a low-level signal to the internal bus when the output terminal of the transceiver is low, and to isolate the internal bus from the output terminal of the transceiver when the output terminal of the transceiver is high.

[0009] As an optional implementation, in the first aspect of the embodiments of this application, the logic control module includes: NOT gate U2, whose input is connected to the internal bus; NAND gate U3 has its first input connected to the output of NOT gate U2, its second input connected to the output of the transceiver, and its output connected to the input of the transceiver. Specifically, when the output of the transceiver is high, the NAND gate U3 outputs the signal on the internal bus; when the output of the transceiver is low, the NAND gate U3 outputs a high level.

[0010] As an optional implementation, in the first aspect of the embodiments of this application, the direction control module includes: NOT gate U4; The delay circuit is connected to the output terminal of the logic control module and the input terminal of the NOT gate U4, respectively. The output of the NOT gate U4 is connected to the control terminal of the transceiver.

[0011] As an optional implementation, in the first aspect of the embodiments of this application, the delay circuit includes: resistor R4, resistor R5 and capacitor C1; One end of resistor R4 is connected to the common connection point between the input terminal of the transceiver and the logic control module; the other end of resistor R4 is connected to one end of resistor R5; one end of resistor R5 is connected to one end of capacitor C1; the input terminal of NOT gate U4 is connected to the common connection point between resistor R4 and resistor R5; the output terminal of NOT gate U4 is connected to one end of resistor R2 and the control terminal of the transceiver.

[0012] As an optional implementation, in the first aspect of the present application, the delay circuit further includes: a diode D2; the cathode of the diode D2 is connected to the input terminal of the transceiver and the common connection point of the logic control module; the anode of the diode D2 is connected to the common connection point of the resistor R4 and the resistor R5.

[0013] As an optional implementation, in the first aspect of the embodiments of this application, the receiving isolation module includes: a diode D1 and a resistor R1; The anode of diode D1 is connected to the internal bus; the cathode of diode D1 and one end of resistor R1 are connected to the output of the transceiver and the common connection point of the logic control module.

[0014] As an optional implementation, in the first aspect of the embodiments of this application, the control terminal of the transceiver includes a first enable terminal and a second enable terminal, the first enable terminal and the second enable terminal are shorted to form a common control terminal, and the common control terminal is connected to the output terminal of the direction control module.

[0015] As an optional implementation, in the first aspect of the present application, the transceiver unit has multiple units, and the multiple transceiver units are interconnected through the internal bus.

[0016] As an optional implementation, in the first aspect of the present application, the internal bus is electrically connected to a resistor R3.

[0017] The second aspect of this application discloses an RS485 hub communication system, including an RS485 hub as disclosed in any embodiment of the first aspect of this application.

[0018] Compared with related technologies, the embodiments of this application have the following beneficial effects: The circuit is extremely simple and the cost is extremely low: it only requires a transceiver chip and a small number of passive components, without any control chips such as CPLD, MCU, or logic gate array, which greatly reduces material costs and power consumption. Zero forwarding delay: The data path has no switching switches or logical processing steps, and the signal transmission delay is only the physical link delay, realizing true real-time transparent transmission; Extremely high reliability: With no active control circuitry, there are very few points of failure, and the MTBF (Mean Time Between Failures) is significantly improved, making it particularly suitable for harsh industrial environments; Completely transparent and compatible: It has no requirements for upper-layer protocols, the baud rate is fully adaptive, and it can be plug-and-play to replace traditional splitters without any configuration. Achieve true hub functionality: Break down communication barriers between ports in the simplest way, enabling every device in a star network to listen to all data communications on the network. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is one of the structural schematic diagrams of an RS485 hub disclosed in an embodiment of this application; Figure 2 This is a schematic diagram of the transceiver unit of an RS485 hub disclosed in an embodiment of this application; Figure 3 This is the second schematic diagram of the structure of an RS485 hub disclosed in the embodiments of this application.

[0021] The components are: 1. Internal bus; 2. Transceiver unit; 21. Transceiver; 22. Logic control module; 23. Direction control module; 24. Receiver isolation module. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] The terms “comprising” and “having”, and any variations thereof, in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0024] In the embodiments of this application, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0025] The technical solution of this application will be described in detail below with reference to specific embodiments.

[0026] Please see Figure 1 An RS485 hub includes: an internal bus 1 and a transceiver unit 2; the transceiver unit 2 includes a transceiver 21, a logic control module 22, a direction control module 23, and a receive isolation module 24; Transceiver 21 is used to convert signals and has two working states: receive mode and transmit mode. Transceiver 21 can be an RS485 transceiver 21. The logic control module 22 is connected to the internal bus 1, the output terminal (i.e., the RO terminal) of the transceiver 21 and the input terminal (i.e., the DI terminal) of the transceiver 21, respectively, and is used to provide data signals to the input terminal of the transceiver 21 according to the level state of the internal bus 1 and the level state of the output terminal of the transceiver 21. The direction control module 23 is connected to the control terminals (i.e. / RE terminal and DE terminal) of the logic control module 22 and the transceiver 21 respectively, and is used to control the working state of the transceiver 21 according to the output signal of the logic control module 22. The receiving isolation module 24 is connected between the output of transceiver 21 and the internal bus 1. It is used to transmit a low-level signal to the internal bus 1 when the output of transceiver 21 is low, and to isolate the internal bus 1 from the output of transceiver 21 when the output of transceiver 21 is high.

[0027] In some embodiments, there are multiple transceiver units 2, and the multiple transceiver units 2 are interconnected through an internal bus 1.

[0028] In some embodiments, the logic control module 22 includes a NOT gate U2 and a NAND gate U3; the direction control module 23 includes a resistor R4, a resistor R5, a capacitor C1, a diode D2, and a NOT gate U4; the receive isolation module 24 includes a diode D1 and a resistor R1; the anode of diode D1 is connected to the input of NAND gate U2, the common connection point of the anode of diode D1 and the input of NAND gate U2 is connected to the internal bus 1, the cathode of diode D1 is connected to one input of NAND gate U3, the output of NOT gate U2 is connected to the other input of NAND gate U3, the output of NOT gate U3 is connected to the DI terminal of RS485 transceiver 21, and the common connection point of the cathode of diode D1 and the input of NAND gate U3 is... Connect one end of resistor R1 to the RO terminal of RS485 transceiver 21; connect the other end of resistor R1 to a high level; connect the RE and DE terminals of RS485 transceiver 21, and connect the common connection point of the RE and DE terminals to one end of resistor R2; connect the other end of resistor R2 to ground; connect one end of resistor R5 to one end of capacitor C1, connect the other end of capacitor C1 to ground, connect the other end of resistor R5 to one end of resistor R4, connect the common connection point of resistors R4 and R5 to the anode of diode D2 and the input terminal of NOT gate U4, connect the output terminal of NOT gate U4 to the common connection point of RS485 transceiver 21 and resistor R2, and connect RS485 transceiver 21 and the NOT gate U4 to the input terminal of the NAND gate U4. The common connection point of gate U3 is connected to the cathode of diode D2 and the other end of resistor R4, respectively; transceiver 21 has RO, / RE, DE, DI, A, and B terminals; terminals A and B of transceiver 21 are electrically connected to the RS485 bus, respectively; internal bus 1 is electrically connected to resistor R3, which serves as the central pull-up resistor for internal bus 1 and is the default level maintenance element; the combination of diode D1 and resistor R1 enables this invention to have level following and unidirectional drive isolation functions, wherein, level following: when this unit is in receive mode and the RO terminal outputs a low level, diode D1 is turned on, pulling internal bus 1 low; when the RO terminal outputs a high level, diode D1 is turned off. The internal bus 1 is pulled high by other units; unidirectional drive isolation: ensures that only the receiver with a low output level can control the internal bus 1, avoiding level conflicts caused by multiple units driving the bus at the same time; NOT gate U2 and NAND gate U3 work together: NOT gate U2 inverts the level of internal bus 1 and inputs it into NAND gate U3, forming an interlock with the RO terminal signal of transceiver 21; when data appears on internal bus 1, this unit can immediately sense it and prepare to switch to the transmit state; when this unit is receiving external 485 signals, the change generated at the RO terminal is fed back to the DI terminal through logic, and NAND gate U3 acts as a logic threshold, working with the enable signal to prevent the signal sent by this unit from being received by itself, forming an infinite loop;The combination of NOT gate U4, diode D2, resistors R4 and R5, and capacitor C1 enables this invention to have automatic transmit / receive switching, asymmetric delay maintenance, and fast start-up functions. Automatic transmit / receive switching: When a low level appears on internal bus 1, NOT gate U4, in conjunction with NOT gate U3, outputs a high level to drive the DE and / RE pins of transceiver 21, causing transceiver 21 to immediately enter transmit mode. Asymmetric delay maintenance: An RC integrator circuit composed of resistors R4, R5, and capacitor C1 provides continuous charge maintenance during the high-level range of the data stream (stop bit or logic 1), preventing the transmit driver from turning off prematurely. Fast start-up: Diode D2 and resistor R5 ensure that capacitor C1 charges rapidly when the start bit arrives, achieving zero-delay forwarding. This structure does not require external clock synchronization or software baud rate detection; its delay parameter is achieved by adjusting the product of (R4 / R5) x C1. By setting this constant to meet the minimum baud rate requirement of the target application, it is backward compatible with transparent forwarding at all higher baud rates.

[0029] In some embodiments, the logic control module 22 includes: NOT gate U2, whose input is connected to internal bus 1; NAND gate U3 has its first input connected to the output of NAND gate U2, its second input connected to the output of transceiver 21, and its output connected to the input of transceiver 21. Specifically, when the output of transceiver 21 is high, NAND gate U3 outputs the signal on internal bus 1; when the output of transceiver 21 is low, NAND gate U3 outputs a high level.

[0030] In some embodiments, the direction control module 23 includes: NOT gate U4; The delay circuit is connected between the output of the logic control module 22 and the input of the NOT gate U4; The output of NOT gate U4 is connected to the control terminal of transceiver 21.

[0031] In some embodiments, the delay circuit includes: resistor R4, resistor R5, and capacitor C1; One end of resistor R4 is connected to the common connection point of the input terminals of logic control module 22 and transceiver 21, and the other end of resistor R4 is connected to one end of resistor R5; one end of resistor R5 is connected to one end of capacitor C1; the input terminal of NOT gate U4 is connected to the common connection point of resistors R4 and R5; the output terminal of NOT gate U4 is connected to one end of resistor R2 and the control terminal of transceiver 21.

[0032] In some embodiments, the delay circuit further includes: a diode D2; the cathode of the diode D2 is connected to the common connection point of the input terminals of the logic control module 22 and the transceiver 21; the anode of the diode D2 is connected to the common connection point of the resistors R4 and R5.

[0033] In some embodiments, the receiving isolation module 24 includes: a diode D1 and a resistor R1; The anode of diode D1 is connected to internal bus 1; the cathode of diode D1 and one end of resistor R1 are connected to the common connection point of transceiver 21 and logic control module 22.

[0034] In some embodiments, the control terminal of transceiver 21 includes a first enable terminal (i.e., / RE terminal) and a second enable terminal (i.e., DE terminal). The first enable terminal and the second enable terminal are interconnected to form a common control terminal, which is connected to the output terminal of the direction control module 23.

[0035] In some embodiments, the internal bus 1 is electrically connected to a resistor R3.

[0036] This invention provides an extremely simple, reliable, zero-latency, and completely transparent RS485 hub circuit that can automatically, simultaneously, and indiscriminately broadcast data received at any port to all other ports without requiring any microcontroller (MCU), programmable logic device (CPLD), or field-programmable gate array (FPGA), thereby achieving full-port data communication within an RS485 star network with the lowest cost and highest reliability.

[0037] This application discloses an RS485 hub communication system, including the RS485 hub disclosed in the above embodiments.

[0038] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also recognize that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0039] In the various embodiments of this application, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0040] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they can be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0041] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0042] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-accessible memory. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several requests to cause a computer device (which can be a personal computer, server, or network device, specifically a processor in the computer device) to execute some or all of the steps of the methods described in the various embodiments of this application.

[0043] Based on the disclosure and teachings of the foregoing specification, those skilled in the art can make changes and modifications to the above embodiments. Therefore, the invention is not limited to the specific embodiments described above, and any obvious improvements, substitutions, or modifications made by those skilled in the art based on this invention are within the scope of protection of this invention. Furthermore, although some specific terms are used in this specification, these terms are only for convenience of explanation and do not constitute any limitation on the invention.

Claims

1. An RS485 hub, characterized in that, include: Internal bus (1) and transceiver unit (2); the transceiver unit (2) includes transceiver (21), logic control module (22), direction control module (23) and receive isolation module (24). The transceiver (21) is used to convert signals; The logic control module (22) is connected to the internal bus (1), the output terminal of the transceiver (21), and the input terminal of the transceiver (21), respectively. The direction control module (23) is connected to the control terminals of the logic control module (22) and the transceiver (21) respectively, and is used to control the working state of the transceiver (21) according to the output signal of the logic control module (22); The receiving isolation module (24) is connected to the output terminal of the transceiver (21) and the internal bus (1), respectively.

2. The RS485 hub as described in claim 1, characterized in that, The logic control module (22) includes: NOT gate U2, whose input is connected to the internal bus (1); NAND gate U3 has its first input connected to the output of NOT gate U2, its second input connected to the output of transceiver (21), and its output connected to the input of transceiver (21).

3. The RS485 hub as described in claim 1, characterized in that, The direction control module (23) includes: NOT gate U4; The delay circuit is connected to the output terminal of the logic control module (22) and the input terminal of the NOT gate U4, respectively; The output terminal of the NOT gate U4 is connected to the control terminal of the transceiver (21).

4. The RS485 hub as described in claim 3, characterized in that, The delay circuit includes: resistor R4, resistor R5, and capacitor C1; One end of resistor R4 is connected to the common connection point between the input terminal of the transceiver (21) and the logic control module (22), and the other end of resistor R4 is connected to one end of resistor R5; one end of resistor R5 is connected to one end of capacitor C1; the input terminal of NOT gate U4 is connected to the common connection point between resistor R4 and resistor R5; the output terminal of NOT gate U4 is connected to one end of resistor R2 and the control terminal of transceiver (21).

5. The RS485 hub as described in claim 4, characterized in that, The delay circuit further includes: a diode D2; the cathode of the diode D2 is connected to the common connection point of the input terminal of the transceiver (21) and the logic control module (22); the anode of the diode D2 is connected to the common connection point of the resistor R4 and the resistor R5.

6. The RS485 hub as described in claim 1, characterized in that, The receiving isolation module (24) includes: a diode D1 and a resistor R1; The anode of the diode D1 is connected to the internal bus (1); the cathode of the diode D1 and one end of the resistor R1 are connected to the common connection point of the transceiver (21) and the logic control module (22).

7. The RS485 hub as described in claim 1, characterized in that, The control terminal of the transceiver (21) includes a first enable terminal and a second enable terminal. The first enable terminal and the second enable terminal are shorted to form a common control terminal, which is connected to the output terminal of the direction control module (23).

8. The RS485 hub as described in claim 1, characterized in that, The transceiver unit (2) has multiple units, and the multiple transceiver units (2) are interconnected through the internal bus (1).

9. The RS485 hub as described in claim 1, characterized in that, The internal bus (1) is electrically connected to a resistor R3.

10. An RS485 hub communication system, characterized in that, Including the RS485 hub as described in any one of claims 1 to 9.

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