A trench-type SiC MOSFET structure
By introducing a P-type region and a hafnium dioxide dielectric layer into the trench SiC MOSFET structure, the bottom electric field of the channel is optimized, solving the problem of excessively high gate oxide bottom electric field. This achieves higher cell integration density and avalanche tolerance, reduces gate-drain capacitance, and improves switching speed and product reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHUZHOU HRM ELECTRONIC TECH CO LTD
- Filing Date
- 2026-04-01
- Publication Date
- 2026-07-03
AI Technical Summary
In existing trench-type SiC MOSFET structures, the electric field at the bottom of the gate oxide is too high, and the channel carrier mobility is low, resulting in the performance not being fully utilized. Existing technologies have not effectively solved the problem of electric field concentration at the bottom of the trench, and the gate oxide structure faces a high risk of breakdown.
A P-type region and a thick oxide layer are introduced at the bottom of the trench. Hafnium dioxide is used as the gate dielectric layer material. The design of the P-type body region and the N+ source region are combined to form a composite structure, which optimizes the electric field at the bottom of the channel and reduces the gate leakage capacitance through the high breakdown field strength hafnium dioxide material.
It achieves higher cell integration density, improves avalanche tolerance and product reliability, reduces gate-drain capacitance, increases switching speed, and reduces process costs.
Smart Images
Figure CN122340862A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically, to a trench-type SiC MOSFET structure. Background Technology
[0002] The critical breakdown electric field of silicon carbide is 10 times that of silicon, which results in a significantly higher breakdown voltage for silicon carbide devices compared to their silicon counterparts for the same drift region length. The electron saturation drift velocity of silicon carbide is approximately 2.5 times that of silicon, thus silicon carbide devices offer faster switching speeds and lower switching losses. Silicon carbide MOSFETs are widely used in new energy vehicle motor drive systems, photovoltaic power generation and storage systems, industrial power supplies, and smart grid systems.
[0003] Compared to planar structures, trench-type SiC MOSFETs offer higher cell density and lower specific on-resistance. However, this structure also faces inherent challenges such as excessively high gate oxide bottom electric field and low channel carrier mobility, limiting its full performance potential. To address these issues, current technical solutions mainly focus on asymmetric and dual-trench structures, specifically as follows: Figure 2 As shown.
[0004] Asymmetric structures employ a single-channel design, surrounding one side of the trench gate with a P-type region to improve the electric field distribution at the bottom of the gate oxide. Dual-trench structures, on the other hand, form dual trenches by etching the gate and source regions separately, and injecting P-type doped regions into the source trench, aiming to alleviate electric field concentration under the gate and suppress gate oxide breakdown under electrical stress. However, these existing structures still fail to completely solve the problem of electric field concentration at the bottom of the trench, and the gate oxide structure still faces a high risk of breakdown.
[0005] No effective solutions have yet been proposed to address the problems in the relevant technologies. Summary of the Invention
[0006] In view of the problems in the related technologies, the present invention proposes a trench-type SiC MOSFET structure to overcome the above-mentioned technical problems existing in the existing related technologies.
[0007] Therefore, the specific technical solution adopted by the present invention is as follows: According to one aspect of the present invention, a trench-type SiC MOSFET structure is provided, the SiC MOSFET structure including a back metal, an N+ substrate disposed on top of the back metal, an N- epitaxial layer disposed on top of the N+ substrate, a trench etched on top of the N- epitaxial layer, and a P-type region disposed at the bottom of the trench; A thick oxide layer is provided at the bottom of the trench, and a gate dielectric layer is covered on the inner sidewall of the trench. The gate dielectric layer is filled with a polycrystalline gate. P-type body regions are distributed on the top of the N- epitaxial layer and on both sides of the trench. N+ source regions are embedded in the P-type body regions. An interlayer dielectric layer is provided on the top of the N+ source regions, and a front metal is provided on the top of the interlayer dielectric layer.
[0008] Preferably, the thickness of the gate dielectric layer is 500 Å-1000 Å.
[0009] According to another aspect of the present invention, a method for manufacturing a trench-type SiC MOSFET structure is also provided, the method comprising: An N-type SiC substrate was selected as the N+ substrate, and an N- epitaxial layer with a predetermined epitaxial doping concentration and thickness was epitaxially generated on the surface of the N+ substrate. After photolithography and etching of the N-epitaxial layer surface, trenches are formed, and Al ions are implanted into the bottom of the trenches. After implantation, high-temperature annealing is performed to form a P-type region in the N-epitaxial layer at the bottom of the trench. Hafnium dioxide material is deposited at the bottom of the trench and etched back. Then, a gate dielectric layer of a predetermined thickness is grown on the sidewall of the trench. The trench is then annealed in an N2O gas atmosphere. After annealing, polysilicon is deposited inside the trench and then photolithography and etching are performed to form a polysilicon gate structure. Al ions and N ions are implanted on the wafer with the completed polycrystalline gate structure, and after uniform high-temperature annealing, P-type body region and N+ source region are simultaneously formed above the epitaxial layer on both sides of the trench. An interlayer dielectric layer is deposited on the wafer surface where P-type body region and N+ source region are formed, and then contact holes are formed in the interlayer dielectric layer through photolithography and etching processes. A pre-defined thickness of aluminum is deposited on the surface of a wafer with contact holes. The aluminum is then photolithographically and etched to form interconnected front-side metals. The wafer with the front-side metallization is then thinned on the back side, and titanium-nickel-silver metal layers are sequentially evaporated on the back side to form the back-side metal, thus completing the device fabrication.
[0010] Preferably, after photolithography and etching, aluminum metal is used to form interconnected front-side metals, which also serve as gate lead-out metals and source metals.
[0011] Preferably, a thick oxide layer is formed in the trench by depositing hafnium dioxide, which serves as a dielectric shielding layer.
[0012] Preferably, the breakdown field strength of hafnium dioxide is 12 MV / cm.
[0013] Preferably, the dielectric constant of hafnium dioxide is 22.
[0014] Preferably, the deposition thickness of metallic aluminum is 4 μm.
[0015] The beneficial effects of this invention are as follows: 1. Compared with the asymmetric and double trench structures in the prior art, the present invention has lower process costs and can achieve higher cell integration density. In addition, the P-type region at the bottom of the trench and the insulating dielectric layer in the trench can cooperate to optimize the electric field at the bottom of the channel, thereby significantly improving the avalanche resistance of the device. The composite structure can also effectively shield the coupling between the gate and drain electrodes, thereby reducing the gate-drain capacitance.
[0016] 2. In this invention, hafnium dioxide material is deposited at the bottom of the trench to replace conventional silicon dioxide material as the insulating dielectric layer. By utilizing the high breakdown field strength of hafnium dioxide material, the avalanche resistance and reliability of the product are improved, the gate leakage capacitance is reduced, and the switching speed of the product is increased. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of a trench-type SiC MOSFET structure according to an embodiment of the present invention; Figure 2 These are schematic diagrams of existing SiC MOSFET structures, where Figure a) shows an asymmetric structure and Figure b) shows a double-trench structure. Figure 3 This is a schematic diagram of the process for preparing a substrate and growing an epitaxial layer in a method for manufacturing a trench-type SiC MOSFET structure according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the trench etching process in a method for manufacturing a trench-type SiC MOSFET structure according to an embodiment of the present invention. Figure 5 This is a schematic diagram of the ion implantation process in the P-type region at the bottom of the trench in a method for manufacturing a trench-type SiC MOSFET structure according to an embodiment of the present invention. Figure 6 This is a schematic diagram of the process for forming thick oxide at the bottom of the trench in a method for manufacturing a trench-type SiC MOSFET structure according to an embodiment of the present invention. Figure 7 This is a schematic diagram of the process for forming the gate dielectric layer in a method for manufacturing a trench-type SiC MOSFET structure according to an embodiment of the present invention; Figure 8This is a schematic diagram of the polysilicon gate formation process in a method for manufacturing a trench-type SiC MOSFET structure according to an embodiment of the present invention. Figure 9 This is a schematic diagram of the process for forming the Pbody region and N+ region in a method for manufacturing a trench-type SiC MOSFET structure according to an embodiment of the present invention. Figure 10 This is a schematic diagram of the process of depositing a dielectric layer and etching to form a hole in a method for manufacturing a trench SiC MOSFET structure according to an embodiment of the present invention; Figure 11 This is a schematic diagram of the process for forming the front metal in a method for manufacturing a trench-type SiC MOSFET structure according to an embodiment of the present invention. Figure 12 This is a schematic diagram of the back metal formation process in a method for manufacturing a trench-type SiC MOSFET structure according to an embodiment of the present invention.
[0019] In the picture: 1. Backside metal; 2. N+ substrate; 3. N- epitaxial layer; 4. Trench; 5. P-type region; 6. Thick oxide layer; 7. Gate dielectric layer; 8. Polycrystalline gate; 9. P-type body region; 10. N+ source region; 11. Interlayer dielectric layer; 12. Frontside metal. Detailed Implementation
[0020] To further illustrate the various embodiments, the present invention provides accompanying drawings, which are part of the disclosure of the present invention. These drawings are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these drawings, those skilled in the art should be able to understand other possible implementation methods and the advantages of the present invention. The components in the drawings are not drawn to scale, and similar component symbols are generally used to represent similar components.
[0021] According to an embodiment of the present invention, a trench-type SiC MOSFET structure is provided.
[0022] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments, such as... Figure 1As shown, according to an embodiment of the present invention, the trench-type SiC MOSFET structure includes a back metal 1, an N+ substrate 2 on top of the back metal 1, an N- epitaxial layer 3 on top of the N+ substrate 2, a trench 4 etched on top of the N- epitaxial layer 3, a P-type region 5 at the bottom of the trench 4, a thick oxide layer 6 at the bottom of the trench 4, a gate dielectric layer 7 covering the inner sidewall of the trench 4, a polysilicon gate 8 filled inside the gate dielectric layer 7, P-type body regions 9 distributed on top of the N- epitaxial layer 3 and on both sides of the trench 4, and an N+ source region 10 embedded inside the P-type body region 9, an interlayer dielectric layer 11 on top of the N+ source region 10, and a front metal 12 on top of the interlayer dielectric layer 11.
[0023] In one embodiment, the thickness of the gate dielectric layer 7 is 500 Å to 1000 Å.
[0024] Specifically, this invention injects a P-type region 5 at the bottom of the trench 4, which can alleviate the electric field concentration phenomenon caused by the curvature effect at the trench gate corner under high voltage. This region forms a PN junction with the N-EPI (which is the N-epitaxy layer 3), thereby improving the withstand voltage. In addition, this region plays a certain role in shielding the coupling of the gate and drain electrodes, effectively reducing the gate and drain capacitance.
[0025] A thicker dielectric shielding layer is formed by depositing hafnium dioxide (HFO2) in trench 4. Because the breakdown field strength of HFO2 can reach 12MV / cm, which is higher than that of silicon dioxide (SiO2), and the dielectric constant reaches 22, which is better than that of SiO2 (3.9), it can improve the ability of strong electric field impact at the bottom of trench 4, while reducing the gate leakage capacitance.
[0026] According to another embodiment of the present invention, a method for manufacturing a trench-type SiC MOSFET structure is also provided, the method comprising: An N-type SiC substrate is selected as the N+ substrate 2, and an N- epitaxial layer 3 with a preset epitaxial doping concentration and thickness is epitaxially generated on the surface of the N+ substrate 2. After photolithography and etching of the surface of the N-epitaxial layer 3, a trench 4 is formed, and Al ions are implanted into the bottom of the trench 4. After implantation, a high-temperature annealing process is performed to form a P-type region 5 in the N-epitaxial layer 3 at the bottom of the trench. Hafnium dioxide material is deposited at the bottom of the trench 4 and etched back. Then, a gate dielectric layer 7 of a predetermined thickness is grown on the sidewall of the trench 4. An annealing process is carried out in an N2O gas atmosphere. After annealing, polysilicon is deposited inside the trench 4 and formed into a polysilicon gate 8 structure by photolithography and etching. Al ions and N ions were implanted on the wafer with the polygate 8 structure, and after uniform high-temperature annealing, P-type body region 9 and N+ source region 10 were simultaneously formed above the epitaxial layer on both sides of the trench. An interlayer dielectric layer 11 is deposited on the wafer surface where a P-type body region 9 and an N+ source region 10 are formed, and then contact holes are formed in the interlayer dielectric layer by photolithography and etching processes. A pre-defined thickness of aluminum is deposited on the surface of a wafer with contact holes. After photolithography and etching, the aluminum forms interconnected front metals 12. The wafer with the front metallization is then subjected to back thinning, and titanium-nickel-silver metal layers are sequentially evaporated on its back side to form back metal 1, thus completing the device fabrication.
[0027] In one embodiment, aluminum metal is photolithographically and etched to form interconnected front-side metals, which also serve as gate lead-out metals and source metals.
[0028] In one embodiment, a thick oxide layer is formed in the trench by depositing hafnium dioxide and serves as a dielectric shielding layer.
[0029] In one embodiment, the breakdown field strength of hafnium dioxide is 12 MV / cm.
[0030] In one embodiment, the dielectric constant of hafnium dioxide is 22.
[0031] In one embodiment, the deposition thickness of metallic aluminum is 4 μm.
[0032] like Figures 3-12 As shown, in order to facilitate understanding of the above technical solutions of the present invention, the operation of the present invention in actual process will be described in detail below.
[0033] Step 1: Substrate material preparation: The epitaxial wafer is made on an N-type SiC substrate. Epitaxial growth is performed on the substrate. The doping concentration and thickness of the grown epitaxial wafer are determined by the breakdown voltage of different devices. Generally, the doping concentration can be 1E16-3E6, and the thickness is 4um-5um.
[0034] Step 2, Trench Etching: Trench photolithography and etching are performed on the wafer to form the trench structure; Step 3: Ion implantation into the P-type region at the bottom of the trench: The bottom of the trench is implanted using the masking layer etched by the trench. The implanted ions are AL ions. After implantation, high-temperature annealing is performed to form a P-type region. Step 4: Formation of thick oxide layer at the bottom of the trench: A thick oxide layer is formed at the bottom of the trench by deposition and etching back HfO2; Step 5: Gate dielectric layer formation: An oxide layer with a thickness of 500 Å-1000 Å is grown on the trench sidewall. Step 6, Polycrystalline gate formation: polycrystalline deposition, photolithography, etching.
[0035] Step 7, Pbody and N+ formation: Pbody region (P-type body region 9) and N+ region (N+ source region 10) are formed by implanting Al and N ions and annealing them together. Step 8: Deposit dielectric layer and etch to form holes: dielectric deposition and hole etching; Step 9, Front-side metal formation: Deposit 4µm thick aluminum metal, which may be doped with 0.5%-1% Cu to prevent aluminum-silicon miscibility. Then, photolithographically etch the aluminum to serve as the Gate metal and Source metal.
[0036] Step 10, Backside Metal Formation: Reduce the thickness of the wafer and evaporate Ti-Ni-Ag (titanium-nickel-silver) on the backside.
[0037] In summary, by utilizing the above-mentioned technical solutions of this invention, compared with the asymmetric and double-trench structures in the prior art, this invention has lower process costs and can achieve higher cell integration density. In addition, the P-type region at the bottom of the trench, in conjunction with the insulating dielectric layer inside the trench, can synergistically optimize the electric field at the bottom of the trench, thereby significantly improving the avalanche withstand capability of the device. This composite structure can also effectively shield the coupling between the gate and drain electrodes, thereby reducing the gate-drain capacitance. This invention deposits hafnium dioxide material at the bottom of the trench instead of conventional silicon dioxide material as the insulating dielectric layer, utilizing the high breakdown field strength of hafnium dioxide material to improve the avalanche withstand capability and reliability of the product, reduce the gate-drain capacitance, and improve the switching speed of the product.
[0038] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A trench-type SiC MOSFET structure, characterized in that, The SiC MOSFET structure includes a back metal, an N+ substrate on top of the back metal, an N- epitaxial layer on top of the N+ substrate, a trench etched on top of the N- epitaxial layer, and a P-type region at the bottom of the trench. The bottom of the trench is provided with a thick oxide layer, the inner sidewall of the trench is covered with a gate dielectric layer, the gate dielectric layer is filled with a polycrystalline gate, P-type body regions are distributed on the top of the N- epitaxial layer and on both sides of the trench, and N+ source regions are embedded in the P-type body regions. An interlayer dielectric layer is provided on the top of the N+ source regions, and a front metal is provided on the top of the interlayer dielectric layer.
2. The trench-type SiC MOSFET structure according to claim 1, characterized in that, The thickness of the gate dielectric layer is 500Å-1000Å.
3. A method for manufacturing a trench-type SiC MOSFET structure, used to realize the manufacturing of the trench-type SiC MOSFET structure according to any one of claims 1-2, characterized in that, The method includes: An N-type SiC substrate was selected as the N+ substrate, and an N- epitaxial layer with a predetermined epitaxial doping concentration and thickness was epitaxially generated on the surface of the N+ substrate. After photolithography and etching of the N-epitaxial layer surface, trenches are formed, and Al ions are implanted into the bottom of the trenches. After implantation, high-temperature annealing is performed to form a P-type region in the N-epitaxial layer at the bottom of the trench. Hafnium dioxide material is deposited at the bottom of the trench and etched back. Then, a gate dielectric layer of a predetermined thickness is grown on the sidewall of the trench. The trench is then annealed in an N2O gas atmosphere. After annealing, polysilicon is deposited inside the trench and then photolithography and etching are performed to form a polysilicon gate structure. Al ions and N ions are implanted on the wafer with the completed polycrystalline gate structure, and after uniform high-temperature annealing, P-type body region and N+ source region are simultaneously formed above the epitaxial layer on both sides of the trench. An interlayer dielectric layer is deposited on the wafer surface where P-type body region and N+ source region are formed, and then contact holes are formed in the interlayer dielectric layer through photolithography and etching processes. A pre-defined thickness of aluminum is deposited on the surface of a wafer with contact holes. The aluminum is then photolithographically and etched to form interconnected front-side metals. The wafer with the front-side metallization is then thinned on the back side, and titanium-nickel-silver metal layers are sequentially evaporated on the back side to form the back-side metal, thus completing the device fabrication.
4. The method for manufacturing a trench-type SiC MOSFET structure according to claim 3, characterized in that, The aluminum metal is photolithographically and etched to form interconnected front-side metals, which also serve as gate lead-out metals and source metals.
5. The method for manufacturing a trench-type SiC MOSFET structure according to claim 3, characterized in that, A thick oxide layer is formed by depositing hafnium dioxide in the trench, which serves as a dielectric shielding layer.
6. The method for manufacturing a trench-type SiC MOSFET structure according to claim 4, characterized in that, The breakdown field strength of the hafnium dioxide is 12 MV / cm.
7. The method for manufacturing a trench-type SiC MOSFET structure according to claim 6, characterized in that, The dielectric constant of the hafnium dioxide is 22.
8. The method for manufacturing a trench-type SiC MOSFET structure according to claim 3, characterized in that, The thickness of the deposited aluminum is 4 μm.