Monolithically integrated gallium nitride cascode transistor

Abstract

A monolithically integrated gallium nitride (GaN) stacked transistor includes a substrate, a buffer layer, a GaN channel layer, an aluminum gallium nitride (AGaN) layer, a source, a drain, an E-type gate, a D-type gate, and a node electrode. The E-type gate is disposed on the AGaN layer and includes a P-type doped GaN layer and an E-type gate conductive layer disposed on the P-type doped GaN layer. The D-type gate is electrically connected to the source and includes a dielectric layer and a D-type gate conductive layer. The node electrode is electrically connected to the D-type gate. The P-type doped GaN layer indirectly alters the bandgap characteristics at the junction of the AGaN layer and the GaN channel layer, giving the transistor normally-off characteristics. Since this transistor does not have a fluoride ion implantation region, it exhibits superior electrical characteristics compared to existing technologies.

Description

Technical Field

[0001] This invention relates to a stacked transistor, and more particularly to a gallium nitride stacked transistor. Background Technology

[0002] Gallium nitride high electron mobility transistors (GaN HEMTs) are widely used in integrated circuits. Because the two-dimensional electron gas (2DEG) in GaN naturally forms a conductive channel, it can function as a normally-on transistor and possesses high electron mobility. However, compared to normally-on transistors, normally-off transistors have a wider range of applications due to the higher safety operating conditions and the convenience of gate drive circuitry.

[0003] One common technique for implementing normally-off GaN transistors is cascaded transistors. This involves connecting a normally-on (depletion mode, D mode) GaN HEMT in series with a normally-off (enhancement mode, E mode) silicon metal-oxide-semiconductor field-effect transistor (Si MOSFET). The Si MOSFET acts as the driver, and the GaN HEMT as the load, thus achieving characteristics equivalent to a normally-off GaN transistor. However, this structure of a D-mode GaN HEMT connected in series with an E-mode Si MOSFET has several drawbacks. For example, Si MOSFETs limit high-temperature operation, increase packaging complexity, increase overall structural size, and introduce parasitic inductance, which can negatively impact the transistor's switching characteristics.

[0004] Another technique for implementing normally-off GaN transistors is the integration of gallium nitride stacked transistors. (See also...) Figure 1The integrated gallium nitride (GaN) stacked transistor comprises a silicon substrate P1, a buffer layer P2, a gallium nitride channel layer P3, an aluminum gallium nitride (AGaN) barrier layer P4, a gallium nitride capping layer P5, a dielectric layer P6, a source P7, a drain P8, an E-type gate P9, a D-type gate P10, a passivation layer P11, and a source field plate P12. The region below the E-type gate P9, where the GaN capping layer P5 and the AGaN barrier layer P4 are located, forms a fluorine ion implantation region F through fluorine ion implantation. Because this fluorine ion implantation region F alters the interface characteristics between the AGaN barrier layer P4 and the GaN channel layer P3, it blocks the formation of a two-dimensional electron gas (2DEG), giving the E-type gate P9 the characteristics of a normally-off gate. Furthermore, the region below the D-type gate P10, having not undergone fluorine ion implantation, retains the characteristics of a normally-on gate. Therefore, the series connection of the two forms an integrated gallium nitride stacked transistor with normally-off characteristics. However, since the aforementioned integrated gallium nitride stacked transistor undergoes an ion implantation process, the bombardment of high-energy ions during the process can damage the crystal structure, thereby degrading the transistor's electrical performance. Summary of the Invention

[0005] The purpose of this invention is to provide a monolithic integrated gallium nitride stacked transistor that can at least overcome the shortcomings of the prior art.

[0006] The monolithic integrated gallium nitride stacked transistor of the present invention includes a substrate, a buffer layer, a gallium nitride channel layer, an aluminum gallium nitride layer, a source, a drain, an E-type gate, a D-type gate, and a node electrode.

[0007] A buffer layer is disposed on the substrate. A gallium nitride (GaN) channel layer is disposed on the buffer layer. An aluminum gallium nitride (AGaN) layer is disposed on the GaN channel layer. The source electrode is disposed on the AGaN layer. The drain electrode is disposed on the AGaN layer. The E-type gate is located between the source and the drain, and is disposed on the AGaN layer, including a P-type doped GaN layer and an E-type gate conductive layer disposed on the P-type doped GaN layer. The D-type gate is located between the source and the drain, and is electrically connected to the source electrode, and is disposed on the AGaN layer, including a D-type gate conductive layer. The node electrode is disposed on the AGaN layer, and is located between the E-type gate and the D-type gate, and is electrically connected to the D-type gate.

[0008] The monolithic integrated gallium nitride stacked transistor of the present invention further includes a dielectric layer located between the E-type gate conductive layer and the P-type doped gallium nitride layer.

[0009] The monolithic integrated gallium nitride stacked transistor of the present invention further includes a dielectric layer located between the D-type gate conductive layer and the aluminum gallium nitride layer.

[0010] The monolithic integrated gallium nitride stacked transistor of the present invention further includes a dielectric layer located between the E-type gate conductive layer and the P-type doped gallium nitride layer, and between the D-type gate conductive layer and the aluminum gallium nitride layer.

[0011] The monolithic integrated gallium nitride stacked transistor of the present invention has its source embedded in the aluminum gallium nitride layer and the gallium nitride channel layer.

[0012] The monolithic integrated gallium nitride stacked transistor of the present invention has a drain embedded in the aluminum gallium nitride layer and the gallium nitride channel layer.

[0013] The monolithic integrated gallium nitride stacked transistor of the present invention further includes a source field plate, which is spaced apart on the side of the D-type gate away from the substrate and electrically connected to the source.

[0014] The monolithic integrated gallium nitride stacked transistor of the present invention has a substrate selected from one of a silicon substrate, a silicon carbide substrate, a sapphire substrate, and an insulator silicon substrate.

[0015] The beneficial effects of this invention are as follows: Since the E-type gate of this invention includes a P-type doped gallium nitride layer disposed within the aluminum gallium nitride layer, it indirectly alters the bandgap characteristics at the interface between the aluminum gallium nitride layer and the gallium nitride channel layer, thereby blocking the formation of a two-dimensional electron gas and giving the E-type gate the characteristics of a normally-off gate. Therefore, the series connection of the normally-on GaN HEMT and the normally-off GaN HEMT constitutes a gallium nitride stacked transistor with normally-off characteristics. Because this transistor does not have a fluoride ion implantation region, its crystal structure will not be destroyed by high-energy ions, resulting in better electrical characteristics compared to existing integrated gallium nitride stacked transistors that use fluoride ion implantation regions to form the E-type gate. Furthermore, this transistor, composed of a normally-on GaN HEMT and a normally-off GaN HEMT, offers advantages such as high temperature resistance, reduced packaging complexity, and reduced parasitic inductance compared to existing stacked transistors composed of GaN HEMTs and SiMOSFETs. Attached Figure Description

[0016] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the accompanying drawings, wherein:

[0017] Figure 1 This is a schematic diagram of an existing integrated gallium nitride stacked transistor.

[0018] Figure 2 This is a circuit diagram of the first embodiment of the monolithic integrated gallium nitride stacked transistor of the present invention.

[0019] Figure 3 This is a schematic diagram of the first embodiment.

[0020] Figure 4This is a schematic diagram of the energy band structure of a D-type gate without a dielectric layer.

[0021] Figure 5 This is a schematic diagram of the energy band structure of an E-type gate.

[0022] Figure 6 This is a schematic diagram of a second embodiment of the monolithically integrated gallium nitride stacked transistor of the present invention.

[0023] Figure 7 This is a comparison graph of the transistor characteristic curves and external conduction of the silicon carbide substrate and the silicon substrate used in the second embodiment.

[0024] Figure 8 This is a comparison chart of the output characteristics of the silicon carbide substrate and the silicon substrate used in the second embodiment.

[0025] Figure 9 This is a comparison chart of the breakdown voltages of a silicon carbide substrate and a silicon substrate used in the second embodiment.

[0026] Figure 10 This is a comparison chart of the output characteristics of the silicon carbide substrate and the silicon substrate at different temperatures in the second embodiment.

[0027] Figure 11 This is a waveform diagram of a double-pulse test using a silicon carbide substrate in the second embodiment.

[0028] Figure 12 This is a waveform diagram of a double-pulse test using a silicon substrate in the second embodiment. Detailed Implementation

[0029] Before the invention is described in detail, it should be noted that similar components are represented by the same numbers in the following description.

[0030] See Figure 2 The first embodiment of the monolithically integrated gallium nitride stacked transistor of the present invention consists of a normally on GaN HEMT and a normally off GaN HEMT connected in series. See also... Figure 3 The first embodiment includes a substrate 1, a buffer layer 2, a gallium nitride channel layer 3, an aluminum gallium nitride layer 4, a source electrode 5, a drain electrode 6, an E-type gate 7, a D-type gate 8, a node electrode 9, an insulating layer 10, a protective layer 11, a source field plate 12, and a dielectric layer 13.

[0031] The substrate 1 is, for example but not limited to, a silicon substrate, a silicon carbide substrate, a sapphire substrate, or an insulating silicon substrate. The buffer layer 2 is disposed on the substrate 1. The gallium nitride channel layer 3 is disposed on the buffer layer 2. The aluminum gallium nitride layer 4 is disposed on the gallium nitride channel layer 3.

[0032] The source electrode 5 is disposed on the upper side of the aluminum gallium nitride layer 4 and includes a source layer 51, a source conductive pillar 52, and a source pad 53 arranged sequentially from bottom to top. The drain electrode 6 is disposed on the upper side of the aluminum gallium nitride layer 4 and includes a drain layer 61, a drain conductive pillar 62, and a drain pad 63 arranged sequentially from bottom to top on the aluminum gallium nitride layer 4. The source layer 51 and the drain layer 61 are, for example, but not limited to, Ti / Al / Ti / Au metal layers. The source conductive pillar 52, the drain conductive pillar 62, the source pad 53, and the drain pad 63 are, for example, but not limited to, Ni / Au metal layers.

[0033] The E-type gate 7 is located between the source 5 and the drain 6, and is disposed on the aluminum gallium nitride layer 4. It includes, from bottom to top, a P-type doped gallium nitride layer 71, an E-type gate conductive layer 72, and an E-type gate pad 73. The D-type gate 8 is located between the source 5 and the drain 6, and is disposed on the aluminum gallium nitride layer 4. It includes, from bottom to top, a D-type gate conductive layer 81 and a D-type gate pad 82. The D-type gate pad 82 is electrically connected to the source pad 53 (not shown). The E-type gate conductive layer 72, the D-type gate conductive layer 81, the E-type gate pad 73, and the D-type gate pad 82 are, for example, but not limited to, Ni / Au metal layers.

[0034] The node electrode 9 is disposed on the upper side of the aluminum gallium nitride layer 4, between the E-type gate 7 and the D-type gate 8, and includes a node electrode layer 91, a node electrode conductive pillar 92, and a node electrode pad 93 arranged sequentially from bottom to top. The node electrode pad 93 is electrically connected to the D-type gate pad 82. The node electrode 9 serves as a shared electrode for both normally-on GaN HEMT and normally-off GaN HEMT, and as a node connecting the two in series.

[0035] The insulating layer 10 fills the space between the source electrode 5, the E-type gate 7, the node electrode 9, the D-type gate 8, and the drain electrode 6, thus providing insulation. The protective layer 11 covers the source electrode 5, the drain electrode 6, the E-type gate 7, the D-type gate 8, and the node electrode 9, and is located above the insulating layer 10, thus preventing external moisture from entering. The materials of the insulating layer 10 and the protective layer 11 are, for example, but not limited to, silicon nitride (SiN). x ).

[0036] The source field plate 12 is located at a distance from the substrate 1 on the side of the D-type gate conductive layer 81 and is electrically connected to the source 5. The arrangement of the source field plate 12 enables the bias voltage applied to the D-type gate 8 to more effectively dissipate the hot electrons in the aluminum gallium nitride layer 4, so as to avoid the hot electrons repelling the electrons in the gallium nitride channel layer 3.

[0037] The dielectric layer 13 is located between the aluminum gallium nitride layer 4 and the D-type gate conductive layer 81. Furthermore, the dielectric layer 13 extends to cover the outside of the D-type gate conductive layer 81, and extends to the outside of the drain layer 61 of the drain 6, the outside of the node electrode 9, the outside of the E-type gate conductive layer 72 of the E-type gate 7, and the outside of the source layer 51 of the source 5.

[0038] In this first embodiment, since the dielectric layer 13 is not provided between the E-type gate conductive layer 72 and the P-type doped gallium nitride layer 71 of the E-type gate 7, the E-type gate conductive layer 72 directly contacts the P-type doped gallium nitride layer 71, thus forming a metal-semiconductor (MS) structure. The dielectric layer 13 is provided between the D-type gate conductive layer 81 and the aluminum gallium nitride layer 4 of the D-type gate 8, thus forming a metal-insulator-semiconductor (MIS) structure.

[0039] In a variation of the first embodiment, the dielectric layer 13 is located between the E-type gate conductive layer 72 and the P-type doped gallium nitride layer 71 of the E-type gate 7, forming a MIS structure on the E-type gate 7. However, the dielectric layer 13 is not provided between the D-type gate conductive layer 81 and the aluminum gallium nitride layer 4 of the D-type gate 8, and the D-type gate conductive layer 81 of the D-type gate 8 directly contacts the aluminum gallium nitride layer 4 to form an MS structure.

[0040] In another variation of the first embodiment, the dielectric layer 13 is not provided between the E-type gate conductive layer 72 and the P-type doped gallium nitride layer 71 of the E-type gate 7, nor between the D-type gate conductive layer 81 and the aluminum gallium nitride layer 4 of the D-type gate 8. Therefore, the E-type gate 7 and the D-type gate 8 are both MS structures.

[0041] In another variation of the first embodiment, the dielectric layer 13 may be located simultaneously between the E-type gate conductive layer 72 and the P-type doped gallium nitride layer 71 of the E-type gate 7, and between the D-type gate conductive layer 81 and the aluminum gallium nitride layer 4 of the D-type gate 8. Therefore, the E-type gate 7 and the D-type gate 8 are both MIS structures.

[0042] Figure 4 This is a schematic diagram of the energy band structure of the D-type gate 8, omitting the dielectric layer 13. As a normally open gate, the D-type gate 8, based on the energy band characteristics of the interface between the aluminum gallium nitride layer 4 and the gallium nitride channel layer 3, naturally forms a two-dimensional electron gas (2DEG) in the gallium nitride channel layer 3, thus exhibiting a negative threshold voltage. (See also...) Figure 5The E-type gate 7 is a normally off gate. By setting the P-type doped gallium nitride layer 71 between the aluminum gallium nitride layer 4 and the E-type gate conductive layer 72, the energy band characteristics of the junction between the aluminum gallium nitride layer 4 and the gallium nitride channel layer 3 are indirectly changed, thus blocking the formation of the two-dimensional electron gas 2DEG and having a positive threshold voltage.

[0043] Therefore, the cascaded connection of the normally-on GaN HEMT and the normally-off GaN HEMT constitutes a monolithic integrated gallium nitride stacked transistor with normally-off characteristics. Furthermore, since this first embodiment does not have a fluorine ion implantation region, the transistor's crystal structure will not be destroyed by high-energy ions, resulting in superior electrical characteristics compared to existing technologies.

[0044] See Figure 6 The second embodiment of the monolithically integrated gallium nitride stacked transistor of the present invention differs from the first embodiment in that the source layer 51 of the source 5 and the drain layer 61 of the drain 6 are embedded in the aluminum gallium nitride layer 4 and the gallium nitride channel layer 3. Since the structure of the second embodiment is largely the same as that of the first embodiment, only the differences will be described below, and the similarities will not be repeated.

[0045] In this second embodiment, since the source layer 51 and the drain layer 61 are embedded in the aluminum gallium nitride layer 4 and the gallium nitride channel layer 3, and the source layer 51 and the drain layer 61 are in direct contact with the gallium nitride channel layer 3, the series resistance of the source 5 and the drain 6 can be reduced.

[0046] As mentioned above, the substrate 1 of the monolithically integrated gallium nitride stacked transistor of the present invention can be selected from a silicon substrate, a silicon carbide substrate, a sapphire substrate, or an insulating silicon substrate. Among them, the silicon carbide substrate has higher hardness and excellent thermal conductivity and high voltage resistance compared with other substrates, and can enable the transistor to have better switching characteristics.

[0047] Figure 7 This is a comparison chart of the transistor characteristic curves and external transconductance of the silicon carbide substrate and the silicon substrate used in the second embodiment. In this second embodiment, the threshold voltage of the silicon carbide substrate is 0.7V, the drain current is 15.2A, the maximum external transconductance is 15.5mS / mm, and the current on / off ratio (I0) is... on / I off The ratio is 5.4 × 10 6 In contrast, the second embodiment uses a silicon substrate with a threshold voltage of 0.5V, a drain current of 10.6A, a maximum external transconductance of 15.3mS / mm, and a current on / off ratio (I0). on / I off (ratio) of 2.7×105 .

[0048] Figure 8 This is a comparison chart of the output characteristics of the silicon carbide substrate and the silicon substrate used in the second embodiment. The on-resistance of the silicon carbide substrate used in the second embodiment is 52 Ω-mm, while the on-resistance of the silicon substrate used in the second embodiment is 65 Ω-mm.

[0049] Figure 9 This is a comparison chart of the breakdown voltages of the silicon carbide substrate and the silicon substrate used in the second embodiment. Under a leakage current of 1 mA / mm, the breakdown voltage of the silicon carbide substrate in the second embodiment is 984 V. In contrast, the breakdown voltage of the silicon substrate in the second embodiment is 783 V.

[0050] Therefore, from Figure 7 , 8 As can be seen from point 9, the use of silicon carbide substrates has higher drain current, higher current switching ratio and higher breakdown voltage compared to silicon substrates, thus exhibiting better switching characteristics and high voltage resistance.

[0051] Figure 10 This is a comparison chart of the output characteristics of the silicon carbide substrate and the silicon substrate used in the second embodiment at different temperatures. Specifically, the output current attenuation rates of the silicon carbide substrate in the second embodiment at temperatures of 300K, 350K, 400K, and 450K are 0%, 6.5%, 18.2%, and 27.8%, respectively, and its normalized on-resistance is 1, 1.09, 1.2, and 1.81, respectively. In contrast, the output current attenuation rates of the silicon substrate in the second embodiment at temperatures of 300K, 350K, 400K, and 450K are 0%, 14.3%, 22.7%, and 41.2%, respectively, and its normalized on-resistance is 1, 1.21, 1.37, and 1.71, respectively.

[0052] Therefore, from Figure 10 It can be seen that the silicon carbide substrate used in the second embodiment has better thermal conductivity and heat dissipation than the silicon substrate, resulting in a smaller current decay rate in high-temperature environments and better heat resistance.

[0053] Figure 11 , 12 These are waveform diagrams from the dual-pulse test using a silicon carbide substrate and a silicon substrate in the second embodiment. In the second embodiment, the turn-on and turn-off times using the silicon carbide substrate are 71 ns and 52 ns, respectively, with corresponding total energy losses of 17 μJ and 8.2 μJ. In contrast, the turn-on and turn-off times using the silicon substrate in the second embodiment are 103 ns and 191 ns, respectively, with corresponding total energy losses of 26 μJ and 14.9 μJ.

[0054] Therefore, from Figure 11 , 12 It can be seen that the silicon carbide substrate used in the second embodiment has a shorter turn-on and turn-off time and a smaller energy loss compared to the silicon substrate, thus exhibiting better switching characteristics.

[0055] In summary, the monolithic integrated gallium nitride stacked transistor of the present invention indirectly alters the junction band characteristics of the aluminum gallium nitride layer 4 and the gallium nitride channel layer 3 by placing a p-type doped gallium nitride layer 71 between the aluminum gallium nitride layer 4 and the E-type gate conductive layer 72. This blocks the formation of the two-dimensional electron gas 2DEG, giving the E-type gate 7 the characteristics of a normally off gate. Therefore, the series connection of the normally on GaN HEMT and the normally off GaN HEMT constitutes a monolithic integrated gallium nitride stacked transistor with normally off characteristics. Since this first embodiment does not have a fluorine ion implantation region, the crystal structure of the transistor will not be destroyed by high-energy ions. Compared with existing integrated gallium nitride stacked transistors that form the E-type gate with a fluorine ion implantation region, it has better electrical characteristics, thus effectively achieving the purpose of the present invention.

[0056] Furthermore, the transistor is composed of a normally open GaN HEMT and a normally closed GaN HEMT. Compared with existing stacked transistors composed of GaN HEMT and Si MOSFET, it has advantages such as high temperature resistance, reduced packaging complexity and reduced parasitic inductance.

[0057] The above description is merely an embodiment of the present invention and should not be construed as limiting the scope of the present invention. Any simple equivalent changes and modifications made in accordance with the claims and description of the present invention shall still fall within the scope of the present invention.

Claims

1. A monolithic integrated gallium nitride stacked transistor, characterized in that... Include: substrate; A buffer layer is disposed on the substrate; A gallium nitride channel layer is disposed in the buffer layer; An aluminum gallium nitride layer is disposed in the gallium nitride channel layer; The source electrode is disposed on the aluminum gallium nitride layer; The drain electrode is disposed on the aluminum gallium nitride layer; An E-type gate is located between the source and the drain, and is disposed on the aluminum gallium nitride layer, and includes a P-type doped gallium nitride layer and an E-type gate conductive layer disposed on the P-type doped gallium nitride layer. A D-type gate, located between the source and the drain and electrically connected to the source, is disposed on the aluminum gallium nitride layer and includes a D-type gate conductive layer; and The node electrode is disposed on the aluminum gallium nitride layer and located between the E-type gate and the D-type gate, and is electrically connected to the D-type gate.

2. The monolithic integrated gallium nitride stacked transistor according to claim 1, characterized in that: The monolithic integrated gallium nitride stacked transistor further includes a dielectric layer located between the E-type gate conductive layer and the P-type doped gallium nitride layer.

3. The monolithic integrated gallium nitride stacked transistor according to claim 1, characterized in that: The monolithic integrated gallium nitride stacked transistor also includes a dielectric layer located between the D-type gate conductive layer and the aluminum gallium nitride layer.

4. The monolithic integrated gallium nitride stacked transistor according to claim 1, characterized in that: The monolithic integrated gallium nitride stacked transistor further includes a dielectric layer located between the E-type gate conductive layer and the P-type doped gallium nitride layer, and between the D-type gate conductive layer and the aluminum gallium nitride layer.

5. The monolithic integrated gallium nitride stacked transistor according to claim 1, characterized in that: The source electrode is embedded in the aluminum gallium nitride layer and the gallium nitride channel layer.

6. The monolithic integrated gallium nitride stacked transistor according to claim 1, characterized in that: The drain is embedded in the aluminum gallium nitride layer and the gallium nitride channel layer.

7. The monolithic integrated gallium nitride stacked transistor according to claim 1, characterized in that: It also includes a source field plate, which is spaced apart on the side of the D-type gate away from the substrate and electrically connected to the source.

8. The monolithic integrated gallium nitride stacked transistor according to claim 1, characterized in that: The substrate is selected from one of the following: silicon substrate, silicon carbide substrate, sapphire substrate, and insulated silicon substrate.

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