A method for reducing native defects in silicon wafers used in integrated circuits

Abstract

This application relates to a method for reducing native defects in silicon wafers used in integrated circuits. It utilizes the dual coupling effect of high-frequency eddy current temperature control and a DC electric field on the carrier regularization in the silicon wafer to fully dissolve native defects and promote their directional and uniform diffusion, resulting in a uniform distribution of native defect nucleation sites at high temperatures. During the cooling process, a rapid cooling method is used to control the nucleation size of native defects and restrict their aggregation and diffusion under the action of the DC electric field, thereby achieving the goal of reducing the size of native defects in the silicon wafer and promoting uniform distribution, meeting the requirements of advanced integrated circuit manufacturing processes.

Description

Technical Field

[0001] This invention belongs to the field of silicon wafer manufacturing technology for integrated circuits, and relates to a method for reducing native defects in silicon wafers for integrated circuits. Specifically, it relates to a method for reducing the size of native defects in silicon wafers and homogenizing them by utilizing the dual coupling effect of high-frequency coil heating and electric field during the manufacturing process of large-size single-crystal silicon wafers for integrated circuits. Background Technology

[0002] As the feature size of semiconductor devices continues to shrink, the crystal perfection of silicon wafers is subject to increasingly stringent requirements. Native defects in silicon wafers, especially crystal native particles (COP) and bulk microdefects (BMD) caused by oxygen precipitation, have become key factors restricting device performance and yield.

[0003] During the crystal growth process of single-crystal silicon for integrated circuits, due to the temperature difference between the outer and inner layers of the crystal, the temperature inside the crystal is higher than that outside. This makes it easier for interstitial atoms to form inside the crystal and for vacancies to form on the outer layer. These vacancies accumulate to form vacancy clusters. With further cooling and shrinkage, these vacancy clusters evolve into crystal native particles (COPs). In subsequent silicon wafer heat treatment, interstitial oxygen and vacancies synergistically form oxygen precipitates and bulk microdefects (BMDs). Although their macroscopic morphologies and distributions differ, their root cause lies in the oversaturation and aggregation of intrinsic point defects (such as vacancies and interstitial oxygen) introduced during crystal growth. COPs are essentially vacancy clusters existing on the surface / near the surface, directly leading to gate oxide integrity failure; BMDs are precipitated clusters of supersaturated oxygen within the bulk, whose uneven distribution induces leakage current and affects carrier lifetime.

[0004] To improve silicon wafer quality, the industry commonly employs high-temperature thermal annealing technology. However, while traditional furnace tube annealing can partially repair defects, it often has two drawbacks: prolonged high temperatures may promote further oxygen precipitation, exacerbating BMD (Body Defects), and the elimination of COP (Coefficient of Oxidation) is not thorough enough. For example, the silicon wafer and annealing method disclosed in patent announcement number CN105297140B involves annealing the silicon wafer in a non-oxidizing atmosphere and under an applied electric field for at least 2 hours at a constant temperature of not less than 1200°C and not more than 1300°C. This method processes the silicon wafer at a temperature not less than 1200°C and not more than 1300°C. At this temperature, the atomic diffusion rate is slow, and smaller, unstable primary defects will dissolve, but larger, stable primary defects dissolve very slowly or not at all, and a long holding time is required to see limited effects, resulting in high overall costs.

[0005] Therefore, there is an urgent need for a silicon wafer processing method that can effectively dissolve large-size native defects, homogenize native defects, reduce the aggregation of defect nucleation points, and thus reduce the size of native defects in silicon wafers and promote their uniform distribution. Summary of the Invention

[0006] The purpose of this invention is to provide a method for reducing native defects in silicon wafers used in integrated circuits. This method has a good dissolution effect on large-size native defects and can homogenize native defects, reduce the degree of clustering of defect nucleation points, thereby reducing the size of native defects in silicon wafers and promoting uniform distribution, thus meeting the increasingly stringent requirements of advanced processes for silicon wafer quality.

[0007] To achieve the above objectives, the basic solution of the present invention provides a method for reducing native defects in silicon wafers used in integrated circuits, comprising the following steps:

[0008] S1: High-frequency coil heating: The silicon wafer is placed in the thermal field and heated to a temperature range of 1280℃-1320℃ and maintained thereon; the thermal field is composed of a planar spiral heating coil covering the surface of the silicon wafer, with the coil plane parallel to the surface of the silicon wafer; the planar spiral heating coil uses high-frequency alternating current, and the frequency is adjusted according to temperature changes during the heating process.

[0009] S2: Apply an electric field: At the heat preservation temperature, apply an electric field to the silicon wafer, monitor the DC current value I in the silicon wafer, and control the initial current value to be I0. When the rate of change of DC current I is less than a1, it indicates that the silicon wafer has been homogenized.

[0010] S3: Cooling and removing the electric field: After the silicon wafer is kept warm, the silicon wafer is cooled down rapidly. During this process, the DC current value I of the silicon wafer is continuously monitored. When the rate of change of DC current I is less than a2, the electric field is removed and the silicon wafer is cooled to room temperature.

[0011] The principle and beneficial effects of this basic scheme are as follows:

[0012] This invention utilizes the dual coupling effect of high-frequency eddy current temperature control and DC electric field on the carrier ordering in silicon wafers to fully dissolve native defects and promote their directional and uniform diffusion, resulting in a uniform distribution of native defect nucleation sites at high temperatures. During the cooling process, rapid cooling is employed to control the nucleation size of native defects and restrict their aggregation and diffusion under the influence of the DC electric field, thereby reducing the size of native defects in the silicon wafer and promoting uniform distribution. This makes the silicon wafer suitable for advanced process requirements, producing an unexpected synergistic effect. This synergistic mechanism enables this invention to achieve the full dissolution and uniform distribution of large-sized native defects, resulting in significant technical benefits. Furthermore, this invention innovatively uses "current change rate" as a real-time, online process monitoring indicator. By using real-time current monitoring for native defect uniformity and process node determination, it achieves a highly efficient and precise technique for reducing native defects.

[0013] Compared with the silicon wafer and annealing method in the existing technology CN105297140B, this solution utilizes high-frequency eddy current temperature control and a DC electric field to process the silicon wafer. High-frequency AC power is used to supply power to the planar spiral heating coil, enabling rapid and uniform heating of the silicon wafer. Within the temperature range of 1280℃-1320℃, the native defects in the silicon wafer become highly unstable and can be effectively dissolved. Furthermore, the diffusion rate of atoms in silicon is extremely fast, making the decomposition and annihilation of native defects very rapid. The self-diffusion coefficient of silicon atoms and the diffusion ability of point defects such as oxygen and vacancies increase exponentially. COP can be almost completely and rapidly eliminated, and the dissolution products of BMD are directionally dispersed and rapidly moved away from the original interface, forcing the nucleation sites of native defects to achieve a highly uniform redistribution within the silicon wafer, achieving... The goal of reducing the size of native defects in silicon wafers and promoting uniform distribution has yielded unexpected technical results. Introducing the current change rate as a real-time monitoring indicator, real-time current monitoring is used to determine the homogenization of native defects and process nodes. When the current stabilizes (change rate less than a1), it indicates that the native defects have been homogenized. After the silicon wafer is kept at a constant temperature, it is rapidly cooled down. Combined with current monitoring (electric field removed when change rate is less than a2), the ideal state is "frozen," effectively preventing the re-nucleation and growth of defects during cooling. This locks in the processing effect, achieving a highly efficient and precise technique for reducing native defects. This avoids the over-processing or under-processing that may result from traditional processes relying on fixed time / temperature, ensuring the consistency of each silicon wafer and greatly improving the accuracy and repeatability of the process.

[0014] Optionally, the operating frequency f of the thermal field satisfies the following relationship:

[0015] (1)

[0016] In the formula, Resistivity is a function of temperature, and K is an empirical constant. The homogenization depth is μ, where μ is the permeability of the silicon wafer.

[0017] (2)

[0018] In the formula, ρ is the resistivity at room temperature, T0 is 298.15 K at room temperature, e is the natural constant, and B is the silicon material constant.

[0019] This invention has discovered through research that, during the heating process, the operating frequency of the coil needs to be adjusted accordingly based on temperature changes and matched with the homogenization depth.

[0020] Optionally, the The range of values ​​for is d / 20≤ ≤d / 10, where d is the thickness of the silicon wafer.

[0021] To achieve uniform heating of the entire silicon wafer, the homogenization depth must be increased. It is comparable to the silicon wafer thickness d. After multiple verifications, d / 20 ≤ A depth of ≤d / 10 ensures that energy can effectively penetrate into the silicon wafer core, achieving overall heating.

[0022] Optionally, the initial current value is 0.3A ≤ I0 ≤ 1.0A.

[0023] Controlling the initial current to 0.3A≤I0≤1.0A can prevent excessive current from causing local energy concentration in the silicon wafer, prevent the generation of new lattice defects, and ensure the stability of the defect control process.

[0024] Optionally, a1 ≤ 5%.

[0025] When the original defects dissolve and become homogenized, the defect distribution reaches a quasi-steady state. At this point, the change in current over time tends to level off. Setting this threshold as the process endpoint criterion means that the change in the defect structure has become very slow, and it can be considered that the target state of "homogenization" or "stabilization" has been achieved. 5% is an empirical threshold that balances process time and quality requirements.

[0026] Optionally, a2 ≤ 3%.

[0027] During rapid cooling, the nucleation size of primary defects is controlled, and their aggregation and diffusion are limited under the influence of a DC electric field to prevent the formation of harmful secondary defect clusters. As the temperature decreases, the defect reaction slows down dramatically, and the change in current also becomes increasingly slower. When a set threshold is reached, it indicates that the dynamic process of defects has been "essentially frozen." At this point, even if the electric field is removed, primary defects can no longer migrate and aggregate on a large scale to form new defects. Continuing to apply an electric field is ineffective and a waste of energy. The 3% threshold is more stringent than the 5% threshold in the heat preservation stage because defect freezing during the cooling stage is crucial to the final quality and requires higher stability confirmation.

[0028] Optionally, the silicon wafers in S1-S3 are always in a non-oxidizing atmosphere during the heating, heat preservation, and cooling processes.

[0029] Maintaining a non-oxidizing atmosphere throughout the heating, holding, and cooling process of silicon wafers prevents surface oxidation and ensures process repeatability and uniformity.

[0030] Optionally, the silicon wafer is rapidly cooled at a rate greater than 260°C / min.

[0031] A cooling rate of 260℃ / min or higher can lock in the effect of defect elimination and homogenization, prevent the re-migration and re-aggregation of eliminated defects, and ensure the treatment effect. This rate achieves the best balance between rapid freezing and thermal stress control. Attached Figure Description

[0032] Figure 1 This is a frontal schematic diagram of the planar spiral heating coil of the present invention placed on the surface of a silicon wafer. Detailed Implementation

[0033] The following detailed description illustrates the specific implementation method:

[0034] Comparative Example

[0035] Using a 12-inch P-type polished silicon wafer as the raw silicon wafer, the wafer was tested using a BMD analyzer (MO4), and the average BMD size was found to be 77nm with a density of 6.28×10⁻⁶. 7 The number of cells per cm³ is unevenly distributed, indicating that the BMD distribution is not uniform.

[0036] Example 1

[0037] Select a 12-inch P-type polished silicon wafer with the same resistivity as the comparative example, as shown in the attached figure. Figure 1 As shown, a silicon wafer is placed in a thermal field, which consists of a planar spiral heating coil covering the surface of the silicon wafer. The plane of the coil is parallel to the surface of the silicon wafer. High-frequency alternating current is used to power the planar spiral heating coil, which rapidly and uniformly heats the silicon wafer, thus homogenizing the depth of heat. The heating frequency was adjusted according to temperature changes during the heating process (d / 15) to raise the silicon wafer to a processing temperature of 1295℃ and then hold it at that temperature. A unidirectional DC electric field was applied to the silicon wafer, and the DC current value I in the silicon wafer was monitored. The initial current value I0 was controlled at 1A. When the rate of change of DC current I was less than 5%, it indicated that the original defects of the silicon wafer had been homogenized. The silicon wafer was held at that temperature for another 1 minute to allow the silicon wafer crystal structure to reach a new and more stable thermodynamic equilibrium state, thereby "locking in" the homogenization of the original defects. During this process, the intensity of the thermal field was controlled to maintain the temperature of the silicon wafer at 1295℃. After the silicon wafer was held at that temperature, it was rapidly cooled at a rate of 260℃ / min. During this process, the DC current value I of the silicon wafer was continuously monitored. When the rate of change of DC current I was less than 3%, the electric field was removed, and the silicon wafer was further cooled to room temperature. The silicon wafer was kept in a non-oxidizing atmosphere throughout the heating, holding, and cooling processes.

[0038] After the silicon wafer was cooled to room temperature, it was tested using a BMD analyzer (MO4). The average BMD size was found to be 70 nm, a 9.09% reduction compared to the comparative example, and the BMD density was 2.76 × 10⁻⁶. 8 pcs / cm 3 The value is 4.39 times the scale value, which proves that the dissolution of large-sized BMDs reduces their size, thus increasing the density of small-sized BMDs; the uniform distribution of the mapping plot proves that the BMD distribution has been homogenized.

[0039] Example 2

[0040] A 12-inch P-type polished silicon wafer with the same resistivity as the comparative example was selected. In this embodiment, the silicon wafer's holding temperature was 1280℃, and the homogenization depth was... The value is d / 20; when applying an electric field to the silicon wafer during the heat preservation stage, the initial current value I0 is controlled to be 0.3A. When the rate of change of the DC current I is less than 5%, the silicon wafer is kept warm for another 1 minute, followed by rapid cooling at a rate of 260℃ / min. When the rate of change of the DC current I is less than 3%, the electric field is removed.

[0041] After the silicon wafer was cooled to room temperature, it was tested using a BMD analyzer (MO4). The average BMD size was found to be 70 nm, a 9.09% reduction compared to the comparative example, and the BMD density was 2.76 × 10⁻⁶. 8 pcs / cm 3 It is 4.39 times the scale value. The mapping diagram is uniformly distributed, which proves that the original defects of the crystal are effectively reduced, and at the same time, a high-density uniformly distributed bulk microdefects (BMD) are formed inside.

[0042] Example 3

[0043] A 12-inch P-type polished silicon wafer with the same resistivity as the comparative example was selected. In this embodiment, the silicon wafer's holding temperature was 1320℃, and the homogenization depth was... The value is d / 10; when applying an electric field to the silicon wafer during the heat preservation stage, the initial current value I0 is controlled to be 0.3A. When the rate of change of the DC current I is less than 5%, the silicon wafer is kept warm for 1 minute, and then rapidly cooled at a rate of 300℃ / min. When the rate of change of the DC current I is less than 3%, the electric field is removed.

[0044] After the silicon wafer was cooled to room temperature, it was tested using a BMD analyzer (MO4). The average BMD size was found to be 68 nm, a reduction of 11.69% compared to the comparative example, and the BMD density was 3.01 × 10⁻⁶. 8 pcs / cm 3 It is 4.79 times the comparative value. The mapping diagram is uniformly distributed, proving that the original defects of the crystal are effectively reduced, and at the same time, a high-density uniformly distributed bulk microdefects (BMD) are formed inside.

[0045] Example 4

[0046] A 12-inch P-type polished silicon wafer with the same resistivity as the comparative example was selected. In this embodiment, the silicon wafer's holding temperature was 1280℃, and the homogenization depth was... The value is d / 20; when applying an electric field to the silicon wafer during the heat preservation stage, the initial current value I0 is controlled to be 1A. When the rate of change of the DC current I is less than 5%, the silicon wafer is kept warm for 1 minute, and then rapidly cooled at a rate of 300℃ / min. When the rate of change of the DC current I is less than 3%, the electric field is removed.

[0047] After the silicon wafer was cooled to room temperature, it was tested using a BMD analyzer (MO4). The average BMD size was found to be 71 nm, a 7.79% reduction compared to the comparative example, and the BMD density was 2.64 × 10⁻⁶. 8 pcs / cm 3 It is 4.21 times the scale value. The mapping diagram is uniformly distributed, which proves that the original defects of the crystal are effectively reduced, and at the same time, a high-density uniformly distributed bulk microdefects (BMD) are formed inside.

[0048] Example 5

[0049] A 12-inch P-type polished silicon wafer with the same resistivity as the comparative example was selected. In this embodiment, the silicon wafer's holding temperature was 1320℃, and the homogenization depth was... The value is d / 20; during the silicon wafer heat preservation stage, when an electric field is applied to the silicon wafer, the initial current value I0 is controlled to be 1A. When the rate of change of the DC current I is less than 5%, the silicon wafer is kept warm for 1 minute, and then rapid cooling is performed at a rate of 300℃ / min. When the rate of change of the DC current I is less than 3%, the electric field is removed.

[0050] After the silicon wafer was cooled to room temperature, it was tested using a BMD analyzer (MO4). The average BMD size was found to be 69 nm, a 10.39% reduction compared to the comparative example, and the BMD density was 2.88 × 10⁻⁶. 8 pcs / cm 3 It is 4.59 times the comparative value. The mapping diagram is uniformly distributed, proving that the original defects of the crystal are effectively reduced, and at the same time, a high-density uniformly distributed bulk microdefects (BMD) are formed inside.

[0051] The process parameters and results data of Examples 1-5 and the comparative examples are shown in the table below:

[0052]

[0053] Characterization data from Examples 1-5 show that, compared to the comparative examples, the silicon wafers treated by the method of this invention exhibit significantly reduced native crystal defects, while simultaneously forming a high-density, uniformly distributed bulk microdefect (BMD) within the wafer. These results demonstrate that this invention utilizes the dual coupling effect of high-frequency eddy current temperature control and DC electric field on the carrier regularization in the silicon wafer to fully dissolve native defects and promote their directional, uniform diffusion, resulting in a uniform distribution of native defect nucleation sites at high temperatures. During the cooling process, rapid cooling is employed to control the nucleation size of native defects and restrict their aggregation and diffusion under the influence of the DC electric field, thereby achieving the goal of reducing the size of native defects in the silicon wafer and promoting uniform distribution, thus meeting the requirements of advanced integrated circuit manufacturing processes.

[0054] The above descriptions are merely embodiments of the present invention, and common knowledge regarding specific structures and characteristics is not elaborated upon here. It should be noted that those skilled in the art can make various modifications and improvements without departing from the structure of the present invention, and these should also be considered within the scope of protection of the present invention. These modifications will not affect the effectiveness of the present invention or the practicality of the patent. The scope of protection claimed in this application should be determined by the content of its claims, and the specific embodiments described in the specification can be used to interpret the content of the claims.

Claims

1. A method for reducing native defects in silicon wafers used in integrated circuits, characterized in that, Includes the following steps: S1: High-frequency coil heating: The silicon wafer is placed in the thermal field and heated to a temperature range of 1280℃-1320℃ and maintained thereon; the thermal field is composed of a planar spiral heating coil covering the surface of the silicon wafer, with the coil plane parallel to the surface of the silicon wafer; the planar spiral heating coil uses high-frequency alternating current, and the frequency is adjusted according to temperature changes during the heating process. S2: Apply an electric field: At the heat preservation temperature, apply an electric field to the silicon wafer, monitor the DC current value I in the silicon wafer, and control the initial current value to be I0. When the rate of change of DC current I is less than a1, it indicates that the silicon wafer has been homogenized. S3: Cooling and removing the electric field: After the silicon wafer is kept warm, the silicon wafer is cooled down rapidly. During this process, the DC current value I of the silicon wafer is continuously monitored. When the rate of change of DC current I is less than a2, the electric field is removed and the silicon wafer is cooled to room temperature.

2. The method for reducing native defects in silicon wafers for integrated circuits according to claim 1, characterized in that: The operating frequency f of the thermal field satisfies the following relationship: (1) In the formula, Resistivity is a function of temperature, and K is an empirical constant. The homogenization depth is μ, where μ is the permeability of the silicon wafer. (2) In the formula, ρ is the resistivity at room temperature, T0 is 298.15 K at room temperature, e is the natural constant, and B is the silicon material constant.

3. The method for reducing native defects in silicon wafers for integrated circuits according to claim 2, characterized in that: The range of values ​​for is d / 20≤ ≤d / 10, where d is the thickness of the silicon wafer.

4. The method for reducing native defects in silicon wafers for integrated circuits according to claim 1, characterized in that: The initial current value is 0.3A ≤ I0 ≤ 1.0A.

5. The method for reducing native defects in silicon wafers for integrated circuits according to claim 1, characterized in that: a1≤5%.

6. The method for reducing native defects in silicon wafers for integrated circuits according to claim 1, characterized in that: The a2 ≤ 3%.

7. A method for reducing native defects in silicon wafers for integrated circuits according to claim 1, characterized in that: During the heating, heat preservation, and cooling processes of the silicon wafers in S1-S3, they are always in a non-oxidizing atmosphere.

8. The method for reducing native defects in silicon wafers for integrated circuits according to claim 1, characterized in that: The silicon wafer is rapidly cooled at a rate greater than 260°C / min.

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