A packaging structure and a method of manufacturing the same

Abstract

The application provides a packaging structure and a preparation method thereof, and relates to the technical field of semiconductor packaging. The packaging structure comprises: a first chip and a second chip which are arranged in the same layer and at intervals; a plastic package body which wraps the first chip and the second chip, the plastic package body has a first surface and a second surface which are arranged oppositely, and a pad surface of the first chip and a back surface of the second chip are exposed from the first surface; a first redistribution structure which is arranged on one side of the second surface; a second redistribution structure which is arranged on one side of the first surface and is electrically connected with the pad of the first chip; and a via structure which is arranged in the plastic package body, the via structure comprises a first hole, a first dielectric layer which is filled in the first hole, a second hole which is formed in the first dielectric layer, and a metal layer which is filled in the second hole and is electrically connected with the pad of the second chip and the first redistribution structure respectively. The packaging structure can reduce the risk of disconnection and delamination, and has high reliability.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and more specifically, to a packaging structure and its fabrication method. Background Technology

[0002] With the development of highly integrated, high-frequency, and high-speed electronic systems, packaging structures not only need to achieve multi-chip integration and high-density interconnection, but also need to consider package size, interconnect reliability, and high-frequency signal transmission performance. TMV (Through Molding Via) technology, as an important interconnection method in fan-out packaging, can form vertical interconnect channels within the plastic package, thereby achieving electrical connections between the chip and the redistribution metal layer, and therefore has good application prospects.

[0003] However, existing TMV processes typically create through-holes directly within the molding compound using laser drilling or mechanical drilling. Because the molding compound usually contains large-diameter silica particles, the resulting hole walls are relatively rough. These rough walls lead to discontinuous subsequent metal deposition and poor adhesion between the metal layer and the hole wall, easily causing reliability issues such as open circuits and delamination. Summary of the Invention

[0004] The purpose of this application is to provide a packaging structure and its fabrication method to address the shortcomings of the prior art, thereby solving the technical problem of poor metal interconnect reliability in existing TMV processes.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: One aspect of this application provides a packaging structure, including: at least one first chip and at least one second chip, the first chip and the second chip being disposed on the same layer and spaced apart, the pad surfaces of the first chip and the second chip facing opposite directions; a molding compound, the molding compound encapsulating the side and back sides of the first chip, the side sides and pad surfaces of the second chip, the molding compound having a first surface and a second surface disposed opposite to each other, the pad surfaces of the first chip and the back sides of the second chip being exposed from the first surface; a first rewiring structure disposed on one side of the second surface; a second rewiring structure disposed on one side of the first surface and electrically connected to the pads of the first chip; at least one via structure disposed within the molding compound, the via structure including a first hole, a first dielectric layer filled in the first hole, a second hole formed in the first dielectric layer and exposing the pads of the second chip, and a metal layer filled in the second hole, the metal layer being electrically connected to the pads of the second chip and the first rewiring structure respectively.

[0006] Optionally, the dielectric constant of the first dielectric layer is lower than that of the encapsulation.

[0007] Optionally, a third hole is formed on the back side of the first chip within the molding compound, and the third hole is filled with a second dielectric layer, the dielectric constant of which is lower than that of the molding compound.

[0008] Optionally, the first wiring structure includes a first wiring metal layer, a first insulating layer, and a second wiring metal layer sequentially disposed on one side of the first surface. The first insulating layer covers the first wiring metal layer, and a first window is provided on the first insulating layer to expose a portion of the first wiring metal layer. The second wiring metal layer is electrically connected to the first wiring metal layer through the first window. The second wiring structure includes a third wiring metal layer, a second insulating layer, and a fourth wiring metal layer sequentially disposed on one side of the second surface. The second insulating layer covers the third wiring metal layer, and a second window is provided on the second insulating layer to expose a portion of the third wiring metal layer. The fourth wiring metal layer is electrically connected to the third wiring metal layer through the second window.

[0009] Optionally, the first wiring structure is provided with a first external connection terminal, and the second wiring structure is provided with a second external connection terminal.

[0010] Another aspect of this application provides a method for fabricating a package structure, comprising: providing a carrier board; mounting at least one first chip with its pads facing the carrier board and at least one second chip with its back facing the carrier board at intervals on the same surface of the carrier board; molding the mounted first and second chips to form a molded body covering the first and second chips, and removing the carrier board; forming a first hole on one side of the second surface of the molded body, the first hole being located between the pads of the second chip and the second surface; filling the first hole with a dielectric material to form a first dielectric layer; forming a second hole in the first dielectric layer to expose the pads of the second chip; filling the second hole with a metal material to form a metal layer; forming a first rewiring structure electrically connected to the metal layer on one side of the second surface of the molded body, and forming a second rewiring structure electrically connected to the pads of the first chip on one side of the first surface of the molded body.

[0011] Optionally, after removing the carrier board, the method further includes: forming a third hole on one side of the second surface of the molding compound, the third hole being located between the first chip and the second surface; and filling the third hole with a dielectric material to form a second dielectric layer.

[0012] Alternatively, the dielectric constant of the dielectric material is lower than that of the encapsulation.

[0013] Optionally, forming a first rewiring structure electrically connected to a metal layer on one side of the second surface of the molding compound includes: forming a first rewiring metal layer on the second surface of the molding compound, wherein the first rewiring metal layer is electrically connected to the metal layer; forming a first insulating layer on the second surface of the molding compound, wherein the first insulating layer covers the first rewiring metal layer, and a first window is formed on the first insulating layer exposing a portion of the first rewiring metal layer; forming a second rewiring metal layer on the surface of the first insulating layer, wherein the second rewiring metal layer is electrically connected to the first rewiring metal layer through the first window; forming a second rewiring structure electrically connected to the pads of the first chip on one side of the first surface of the molding compound includes: forming a third rewiring metal layer on the first surface of the molding compound, wherein the third rewiring metal layer is electrically connected to the pads of the first chip; forming a second insulating layer on the first surface of the molding compound, wherein the second insulating layer covers the third rewiring metal layer, and a second window is formed on the second insulating layer exposing a portion of the third rewiring metal layer; forming a fourth rewiring metal layer on the surface of the second insulating layer, wherein the fourth rewiring metal layer is electrically connected to the third rewiring metal layer through the second window.

[0014] Optionally, after forming a first rewiring structure electrically connected to a metal layer on one side of the second surface of the molding compound, the method further includes: forming a first external connection terminal on the surface of the first rewiring structure opposite to the molding compound; after forming a second rewiring structure electrically connected to the pads of the first chip on one side of the first surface of the molding compound, the method further includes: forming a second external connection terminal on the surface of the second rewiring structure opposite to the molding compound.

[0015] The beneficial effects of this application include: This application provides a packaging structure, including: at least one first chip and at least one second chip, the first chip and the second chip being disposed on the same layer and spaced apart, with the pad surfaces of the first chip and the second chip facing opposite directions; a molding compound, the molding compound encapsulating the side and back sides of the first chip, the side sides and the pad surfaces of the second chip, the molding compound having a first surface and a second surface disposed opposite to each other, the pad surfaces of the first chip and the back sides of the second chip being exposed from the first surface; a first rewiring structure disposed on one side of the second surface; a second rewiring structure disposed on one side of the first surface and electrically connected to the pads of the first chip; at least one via structure disposed within the molding compound, the via structure including a first hole, a first dielectric layer filled in the first hole, a second hole formed in the first dielectric layer and exposing the pads of the second chip, and a metal layer filled in the second hole, the metal layer being electrically connected to the pads of the second chip and the first rewiring structure respectively. This encapsulation structure, by processing via structures within the molding compound, ensures that the metal layer that actually performs the conduction function is no longer directly formed in the first hole with a rough wall, but rather in the second hole with a relatively smooth wall. Therefore, it can overcome the problems of rough hole walls, discontinuous metal deposition, and poor bonding caused by large-diameter silica particles in the molding compound, reduce the risk of open circuits and delamination, and has high reliability. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the packaging structure provided in the embodiments of this application; Figure 2 A flowchart illustrating the method for fabricating the packaging structure provided in this application embodiment; Figure 3 This is one of the schematic diagrams illustrating the fabrication process of the packaging structure provided in the embodiments of this application; Figure 4 This is the second schematic diagram illustrating the fabrication process of the packaging structure provided in the embodiments of this application. Figure 5 This is the third schematic diagram illustrating the fabrication process of the packaging structure provided in the embodiments of this application; Figure 6 Fourth schematic diagram of the fabrication process of the packaging structure provided in the embodiments of this application; Figure 7 Fifth schematic diagram illustrating the fabrication process of the packaging structure provided in this application embodiment; Figure 8This is the sixth schematic diagram illustrating the fabrication process of the packaging structure provided in the embodiments of this application; Figure 9 This is the seventh schematic diagram illustrating the fabrication process of the packaging structure provided in the embodiments of this application. Figure 10 Eighth schematic diagram of the fabrication process of the packaging structure provided in the embodiments of this application; Figure 11 Schematic diagram nine illustrating the fabrication process of the packaging structure provided in this application embodiment; Figure 12 This is the tenth schematic diagram illustrating the fabrication process of the packaging structure provided in the embodiments of this application; Figure 13 Schematic diagram eleven of the packaging structure fabrication process provided in the embodiments of this application; Figure 14 12. A schematic diagram illustrating the fabrication process of the packaging structure provided in this application embodiment; Figure 15 This is 13th schematic diagram illustrating the fabrication process of the packaging structure provided in the embodiments of this application.

[0018] Icons: 10-Package structure; 11-First chip; 111-Pads of the first chip; 12-Second chip; 121-Pads of the second chip; 13-Molded package; 131-Third hole; 14-First rewiring structure; 141-First rewiring metal layer; 142-First insulating layer; 1421-First window; 143-Second rewiring metal layer; 15-Second rewiring structure; 151-Third rewiring metal layer; 152-Second insulating layer; 1521-Second window; 153-Fourth rewiring metal layer; 16-Through hole structure; 161-First hole; 162-First dielectric layer; 163-Second hole; 164-Metal layer; 17-Second dielectric layer; 18-First external connection terminal; 19-Second external connection terminal; 20-Carrier board. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. It should be noted that, unless otherwise specified, the various features in the embodiments of this application can be combined with each other, and the combined embodiments are still within the protection scope of this application.

[0021] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0022] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this application is in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0023] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0024] Please refer to Figure 1 This application provides a packaging structure 10, including: at least one first chip 11, at least one second chip 12, a molding compound 13, a first rewiring structure 14, a second rewiring structure 15, and at least one via structure 16.

[0025] Specifically, the first chip 11 and the second chip 12 are arranged on the same layer and spaced apart, that is, the first chip 11 and the second chip 12 are arranged side by side in the same horizontal plane, without overlapping or contacting each other, and are separated from each other by a certain distance. Both the first chip 11 and the second chip 12 have opposing pad surfaces and back surfaces, as well as side surfaces connecting the pad surfaces and back surfaces. The pad surface is the surface on the chip where the pads are located, and the back surface is the surface on the chip opposite to the pad surface without pads. The pad surfaces 121 of the first chip 11 and the second chip face opposite directions; for example, the pad surface 111 of the first chip faces downwards, and the pad surface 121 of the second chip faces upwards.

[0026] The first chip 11 and the second chip 12 are encapsulated and fixed by a molding compound 13, which is formed by encapsulating the first chip 11 and the second chip 12 with molding compound through a molding process. The molding compound 13 has a first surface and a second surface opposite to each other. The molding compound 13 encapsulates the side and back of the first chip 11, the side and the pad surface of the second chip 12, and the pad surface of the first chip 11 and the back of the second chip 12 are exposed from the first surface.

[0027] The first wiring structure 14 is disposed on one side of the second surface of the encapsulation body 13. The first wiring structure 14 can be attached to the second surface of the encapsulation body 13, and other hierarchical structures can also be disposed between the first wiring structure 14 and the second surface of the encapsulation body 13.

[0028] The second wiring structure 15 is disposed on one side of the first surface and is electrically connected to the pads 111 of the first chip. The second wiring structure 15 can be attached to the first surface of the molding compound 13 to achieve electrical connection with the pads 111 of the first chip; other hierarchical structures can also be disposed between the second wiring structure 15 and the first surface of the molding compound 13, and electrical connection with the pads 111 of the first chip can be achieved through the hierarchical structure.

[0029] At least one via structure 16 is provided within the molding compound 13. The via structure 16 is used to realize the electrical connection between the pads 121 of the second chip and the first rewiring structure 14. Generally speaking, the via structure 16 corresponds one-to-one with the pads 121 of the second chip, that is, one via structure 16 corresponds to one pad 121 of the second chip. If a second chip 12 has multiple pads, then the number of via structures 16 is equal to the number of its pads.

[0030] The via structure 16 includes a first hole 161, a first dielectric layer 162 filled within the first hole 161, a second hole 163 formed within the first dielectric layer 162 and exposing the pad 121 of the second chip, and a metal layer 164 filled within the second hole 163. The metal layer 164 is electrically connected to the pad 121 of the second chip and the first rewiring structure 14, respectively. It can be understood that both the first hole 161 and the second hole 163 extend along the thickness direction of the molding compound 13, with one end of each hole located on the second surface of the molding compound 13 and the other end located on the surface of the pad 121 of the second chip. The second hole 163 is located within the first hole 161, and the first dielectric layer 162 is filled between the second hole 163 and the first hole 161. Simultaneously, the second hole 163 is filled with a conductive metal layer 164.

[0031] In actual processing, a first hole 161 can be machined within the molding compound 13, followed by filling the first hole 161 with a first dielectric layer 162, then machining a second hole 163 within the first dielectric layer 162, and finally filling the second hole 163 with a metal layer 164. The wall material of the first hole 161 is the molding compound, which typically contains large-diameter silica particles, resulting in a relatively rough wall. The wall material of the second hole 163 is a dielectric material, which can be selected with smaller particle sizes, thus making the wall of the second hole 163 smoother. This combination of structure and process ensures that the metal layer 164, which actually performs the conduction function, is no longer directly formed within the rough-walled first hole 161, but rather within the relatively smooth-walled second hole 163. Therefore, it helps to overcome the problems of rough wall, discontinuous metal deposition, and poor adhesion caused by large-diameter silica particles in the molding compound, reducing the risk of open circuits and delamination, and thus improving the reliability of the packaging structure 10.

[0032] In addition, by having the pads of the first chip 11 and the second chip 12 facing opposite directions, and by setting the first rewiring structure 14 and the second rewiring structure 15 on both sides of the plastic package 13 respectively to bring out the signals of the first chip 11 and the second chip 12, it is beneficial to reduce the size of the package structure 10.

[0033] Optionally, the dielectric constant of the first dielectric layer 162 is lower than the dielectric constant of the encapsulation 13.

[0034] This configuration reduces parasitic capacitance in the conduction region, mitigates crosstalk, delay, and signal attenuation in high-frequency applications, and helps improve signal integrity.

[0035] Optionally, a third hole 131 is formed inside the molding compound 13 on the back side of the first chip 11, and a second dielectric layer 17 is filled in the third hole 131. The dielectric constant of the second dielectric layer 17 is lower than that of the molding compound 13.

[0036] The third hole 131 extends along the thickness direction of the molding compound 13, with one end located on the second surface of the molding compound 13 and the other end located on the back side of the first chip 11. The third hole 131 is filled with a second dielectric layer 17 with a dielectric constant lower than that of the molding compound 13. The provision of the second dielectric layer 17 can reduce the parasitic effect in the corresponding area of ​​the first chip 11, making the dielectric distribution of the entire package structure 10 more balanced under high-frequency conditions, further reducing the overall parasitic effect of the package structure 10, and improving the overall reliability of the package structure 10.

[0037] Optionally, the first rewiring structure 14 includes a first rewiring metal layer 141, a first insulating layer 142, and a second rewiring metal layer 143 sequentially disposed on one side of the first surface. The first insulating layer 142 covers the first rewiring metal layer 141, and a first window 1421 is provided on the first insulating layer 142 to expose a portion of the first rewiring metal layer 141. The second rewiring metal layer 143 is electrically connected to the first rewiring metal layer 141 through the first window 1421.

[0038] Specifically, one side surface of the first rewiring metal layer 141 is electrically connected to the metal layer 164 of the via structure 16, for example, by direct bonding. A first insulating layer 142 covers the other side surface and side of the first rewiring metal layer 141. A first window 1421 is provided on the first insulating layer 142, exposing the other side surface of the first rewiring metal layer 141. A second rewiring metal layer 143 covers the surface of the first insulating layer 142 facing away from the molding layer. The second rewiring metal layer 143 can be bonded to the first rewiring metal layer 141 by filling the first window 1421, thereby achieving electrical connection.

[0039] The second wiring structure 15 includes a third wiring metal layer 151, a second insulating layer 152, and a fourth wiring metal layer 153 sequentially disposed on one side of the second surface. The second insulating layer 152 encloses the third wiring metal layer 151, and a second window 1521 is provided on the second insulating layer 152 to expose a portion of the third wiring metal layer 151. The fourth wiring metal layer 153 is electrically connected to the third wiring metal layer 151 through the second window 1521.

[0040] Specifically, one side surface of the third wiring metal layer 151 is electrically connected to the pad 111 of the first chip, for example, by direct bonding. The second insulating layer 152 covers the other side surface and side of the third wiring metal layer 151. A second window 1521 is provided on the second insulating layer 152, exposing the other side surface of the third wiring metal layer 151. A fourth wiring metal layer 153 covers the surface of the second insulating layer 152 facing away from the molding compound. The fourth wiring metal layer 153 can be bonded to the third wiring metal layer 151 by filling the second window 1521, thereby achieving electrical connection.

[0041] The multilayer redistribution metal layer 164 significantly improves wiring density and wiring flexibility, enabling the signals of the first chip 11 and the second chip 12 to be redistributed and brought out on both sides of the molding compound 13. The insulating layer helps prevent interlayer short circuits and enhances circuit reliability. Furthermore, the stacking method of lower metal-insulating layer-upper metal provides a clear and easy-to-manufacture technical solution for high-density interconnects.

[0042] Optionally, the first rewiring structure 14 is provided with a first external connection terminal 18, and the second rewiring structure 15 is provided with a second external connection terminal 19.

[0043] After the double-sided redistribution structure is formed, external connection terminals, such as solder ball bumps, are further formed on the surfaces of the redistribution metal layers 164 that are finally exposed on both sides of the structure to form external interfaces suitable for subsequent package interconnection or system installation. This double-sided terminal arrangement enables the package structure 10 of this application to not only realize double-sided redistribution internally, but also to have dual-sided connection capability externally, thereby alleviating the problem of excessive concentration of traditional single-sided external interfaces, which is beneficial to shortening the signal lead-out path, improving the flexibility of interface layout and the freedom of system-level integration.

[0044] Another aspect of this application provides a method for fabricating a packaging structure, used to fabricate the packaging structure 10 as described above. Please refer to... Figure 2 The method includes: S100: Provides carrier board.

[0045] Please refer to the reference. Figure 3 The carrier 20 can be made of metal, silicon, resin, or glass. The carrier 20 must have at least one smooth surface for mounting the first chip 11 and the second chip 12.

[0046] S200: At least one first chip is mounted on the same surface of the carrier board with the pad side facing the carrier board and at least one second chip is mounted at intervals with the back side facing the carrier board.

[0047] Through a mounting process, the first chip 11 is mounted on the same surface of the carrier board 20 with its pads facing towards the carrier board 20, and the second chip 12 is mounted with its pads facing away from the carrier board 20. This is done on the upper surface of the carrier board 20, thus establishing an opposite orientation relationship between the two types of chips from the initial stage. For example, the first chip 11 is mounted onto the carrier board 20 first, and then the second chip 12 is mounted onto the carrier board 20 after the first chip 11 is mounted. When there is more than one first chip 11, two or more first chips 11 can be mounted sequentially or simultaneously. The second chip 12 is mounted in the same manner.

[0048] S300: The first and second chips after mounting are encapsulated to form a plastic package covering the first and second chips, and the carrier board is removed.

[0049] Please refer to the reference. Figure 4 and Figure 5The first chip 11 and the second chip 12 are encapsulated using a molding compound to form a molded body 13. The molding compound can be epoxy resin. After the molded body 13 is formed, the carrier board 20 is removed, exposing the first surface of the molded body 13 that was originally covered by the carrier board 20, and simultaneously exposing the pads 111 of the first chip and the back side of the second chip 12.

[0050] S400: A first hole is formed on one side of the second surface of the molding compound, the first hole being located between the pads of the second chip and the second surface.

[0051] Please refer to the reference. Figure 5 A first hole 161 is formed in the region of the molding compound 13 corresponding to the pad 121 of the second chip. The first hole 161 extends along the thickness direction of the molding compound 13, with one end located on the second surface of the molding compound 13 and the other end located on the pad 121 of the second chip, exposing the pad 121 of the second chip. The first hole 161 can be formed by mechanical drilling or laser drilling. Generally, the number of first holes 161 is equal to the number of pads 121 of the second chip and they correspond one-to-one. If a second chip 12 has multiple pads, then the number of first holes 161 equal to the number of pads is formed on the top of the second chip 12. Because there are large silicon dioxide particles in the molding compound, the hole wall of the first hole 161 is relatively rough, with a hole wall roughness of about 1μm to 50μm.

[0052] S500: Fill the first hole with dielectric material to form a first dielectric layer.

[0053] Please refer to the reference. Figure 6 A dielectric material is filled into the first hole 161 to form a first dielectric layer 162. The dielectric material can be selected from porous silica micro powder, fluorinated silica micro powder, polytetrafluoroethylene micro powder, etc.

[0054] S600: A second hole is formed within the first dielectric layer to expose the pads of the second chip.

[0055] Please refer to the reference. Figure 7 A second hole 163 is formed by secondary drilling within the first dielectric layer 162. The hole wall of the second hole 163 is smooth with a roughness of less than 100 nm. The second hole 163 extends along the thickness direction of the molding compound 13, with one end located on the second surface of the molding compound 13 and the other end located on the pad 121 of the second chip, exposing the pad 121 of the second chip. The second hole 163 can be formed by mechanical drilling or laser drilling.

[0056] S700: Fill the second hole with metallic material to form a metal layer.

[0057] Please refer to the reference. Figure 8A metal layer 164 is formed by filling the second hole 163 with a metallic material. The metallic material can be copper, aluminum, tungsten, etc. The metallic layer 164 can be formed by filling the second hole 163 with a metallic material through processes such as physical vapor deposition, electroplating, or chemical plating.

[0058] S800: A first wiring structure electrically connected to a metal layer is formed on one side of the second surface of the molding compound, and a second wiring structure electrically connected to the pads of the first chip is formed on one side of the first surface of the molding compound.

[0059] Please refer to the reference. Figure 1 The first wiring structure 14 and the second wiring structure 15 can be formed by processes such as photolithography, PVD, electroplating, and chemical plating.

[0060] Compared with existing methods that directly form holes and metallize in molding compound, the packaging structure preparation method provided in this application first processes a first hole 161 in molding compound, then fills a first dielectric layer 162, and then drills a second hole in the first dielectric layer 162 and fills it with metal. This makes the metal layer 164, which actually performs the conduction function, no longer directly formed in the first hole 161 with rough hole walls, but formed in the second hole 163 with relatively smooth hole walls. Therefore, it can significantly improve the continuity and bonding of the metal layer 164, reduce open circuits and delamination, and improve the reliability of the molding structure.

[0061] Optionally, after removing the carrier plate, the method further includes: S900: A third hole is formed on one side of the second surface of the molding compound, and the third hole is located between the first chip and the second surface.

[0062] Please refer to the reference. Figure 4 and Figure 5 After removing the carrier board 20, a third hole 131 is formed on one side of the second surface of the molding compound 13. The third hole 131 extends along the thickness direction of the molding compound 13, with one end of the third hole 131 located on the second surface of the molding compound 13 and the other end located on the back side of the first chip 11, exposing the back side of the first chip 11. The formation process of the third hole 131 can also be achieved by mechanical drilling or laser drilling.

[0063] S1000: Fill the third hole with dielectric material to form a second dielectric layer.

[0064] Please refer to the reference. Figure 6The third hole 131 is filled with dielectric material to form the second dielectric layer 17. To simplify the process and improve processing efficiency, the third hole 131 and the first hole 161 can be formed simultaneously, or the third hole 131 can be formed after the first hole 161 is formed but before the dielectric material is filled. Then, dielectric material is filled into both the first hole 161 and the third hole 131 simultaneously to form the first dielectric layer 162 and the second dielectric layer 17.

[0065] Optionally, the dielectric constant of the dielectric material is lower than that of the encapsulation 13.

[0066] A low-dielectric-constant dielectric material is introduced into the first via 161 and the third via 131 through a via-filling method to form the corresponding dielectric layers. This reduces the impact of parasitic capacitance and dielectric loss between circuits by changing the local dielectric environment above the first chip 11 and the second chip 12. Therefore, in high-frequency and high-speed applications, this reduces crosstalk, delay, and signal attenuation, improving signal integrity. Simultaneously, this low-dielectric-constant dielectric material, in conjunction with the subsequent secondary via-drilling process, provides a good foundation for forming relatively smooth via walls.

[0067] Optionally, forming a first rewiring structure electrically connected to the metal layer on one side of the second surface of the molding compound includes: S810: A first rewiring metal layer is formed on the second surface of the molding compound, wherein the first rewiring metal layer is electrically connected to the metal layer.

[0068] Please refer to Figure 9 A first rewiring metal layer 141 is formed on the second surface of the molding compound 13. The first rewiring metal layer 141 is bonded to the metal layer 164 to achieve electrical connection. The first rewiring metal layer 141 can be formed by processes such as photolithography, physical vapor deposition, electroplating, and chemical plating.

[0069] S820: A first insulating layer is formed on the second surface of the encapsulated body, wherein the first insulating layer encapsulates a first rewiring metal layer, and a first window is provided on the first insulating layer to expose a portion of the first rewiring metal layer.

[0070] Please refer to the reference. Figure 10 A first insulating layer 142 is formed on the second surface of the molding compound 13. The first insulating layer 142 covers the sides of the first redistribution metal layer 141 and the surface facing away from the molding compound 13. A first window 1421 is formed on the surface of the first insulating layer 142 facing away from the molding compound to expose the first redistribution metal layer 141. The first insulating layer 142 can be fabricated by photolithography.

[0071] S830: A second rewiring metal layer is formed on the surface of the first insulating layer, wherein the second rewiring metal layer is electrically connected to the first rewiring metal layer through a first window.

[0072] Please refer to the reference. Figure 11 A second rewiring metal layer 143 is formed on the surface of the first insulating layer 142 away from the encapsulation body 13. The second rewiring metal layer 143 fills the first window 1421 and adheres to the first rewiring metal layer 141 to achieve electrical connection.

[0073] Optionally, forming a second wiring structure on one side of the first surface of the molding compound that is electrically connected to the pads of the first chip includes: S840: A third wiring metal layer is formed on the first surface of the molding compound, wherein the third wiring metal layer is electrically connected to the pads of the first chip.

[0074] Please refer to Figure 12 A third wiring metal layer 151 is formed on the first surface of the molding compound 13. The third wiring metal layer 151 is attached to the pads 111 of the first chip to achieve electrical connection. The third wiring metal layer 151 can be formed by processes such as photolithography, physical vapor deposition, electroplating, and chemical plating.

[0075] S850: A second insulating layer is formed on the first surface of the encapsulated body, wherein the second insulating layer encapsulates a third rewiring metal layer, and a second window is provided on the second insulating layer to expose a portion of the third rewiring metal layer.

[0076] Please refer to the reference. Figure 13 A second insulating layer 152 is formed on the first surface of the molding compound 13. The second insulating layer 152 covers the sides and the surface of the third redistribution metal layer 151 away from the molding compound 13. A second window 1521 is formed on the surface of the second insulating layer 152 away from the molding compound to expose the third redistribution metal layer 151. The second insulating layer 152 can be fabricated by photolithography.

[0077] S860: A fourth wiring metal layer is formed on the surface of the second insulating layer, wherein the fourth wiring metal layer is electrically connected to the third wiring metal layer through the second window.

[0078] Please refer to the reference. Figure 14 A fourth rewiring metal layer 153 is formed on the surface of the second insulating layer 152 away from the encapsulation body 13. The fourth rewiring metal layer 153 fills the second window 1521 and adheres to the third rewiring metal layer 151 to achieve electrical connection.

[0079] By using photolithographic windowing of the insulating layer and layer-by-layer formation of the upper and lower metal layers, a high-density, multi-layered, non-interfering rewiring network can be established on both sides of the molding compound 13, making the electrical connection path between the first chip 11, the second chip 12, and the internal via structure 16 more flexible, which is conducive to achieving more signal distribution and extraction within a limited package area.

[0080] Optionally, after forming a first rewiring structure electrically connected to the metal layer on one side of the second surface of the molding compound, the method further includes: S1100: A first external connection terminal is formed on the surface of the first wiring structure away from the encapsulation.

[0081] Please refer to the reference. Figure 15 The first external connection terminal 18 can be formed with solder ball bumps on the surface of the first rewiring structure 14 away from the plastic encapsulation body 13 by electroplating or ball-planting process.

[0082] After forming a second rewiring structure 15 electrically connected to the pads 111 of the first chip on one side of the first surface of the molding compound 13, the method further includes: S1200: A second external connection terminal is formed on the surface of the second wiring structure away from the encapsulation.

[0083] Please refer to the reference. Figure 1 The second external connection terminal 19 can be formed with solder ball bumps on the surface of the second rewiring structure 15 away from the plastic encapsulation body 13 by electroplating or ball-planting process.

[0084] The double-sided terminal configuration enables the package structure 10 to not only achieve double-sided rewiring internally, but also to have double-sided connection capability externally. This alleviates the problem of overly concentrated external interfaces in traditional single-sided packaging, and helps to shorten signal lead-out paths, improve interface layout flexibility and system-level integration freedom.

[0085] Furthermore, a first external connection terminal 18 is formed on the surface of the second rewiring metal layer 143 facing away from the molding compound 13. The first external connection terminal 18 is electrically connected to the pad 121 of the second chip through the second rewiring metal layer 143, the first rewiring metal layer 141, and the metal layer 164, thereby extracting the signal from the second chip 12; a second external connection terminal 19 is formed on the surface of the fourth rewiring metal layer 153 facing away from the molding compound 13. The second external connection terminal 19 is electrically connected to the pad 111 of the first chip through the fourth rewiring metal layer 153 and the third rewiring metal layer 151, thereby extracting the signal from the first chip 11.

[0086] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple steps or multiple stages, which are not necessarily completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0087] The above description is merely an optional embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A packaging structure, characterized in that, include: At least one first chip and at least one second chip, the first chip and the second chip are arranged on the same layer and spaced apart, and the pads of the first chip and the second chip face opposite directions; A molding compound that encapsulates the side and back sides of the first chip, the side sides and pad surfaces of the second chip, the molding compound having a first surface and a second surface disposed opposite to each other, the pad surfaces of the first chip and the back sides of the second chip being exposed from the first surface; The first wiring structure is disposed on one side of the second surface; The second wiring structure is disposed on one side of the first surface and is electrically connected to the pads of the first chip; At least one via structure is disposed within the molding compound. The via structure includes a first hole, a first dielectric layer filled within the first hole, a second hole formed within the first dielectric layer and exposing the pads of the second chip, and a metal layer filled within the second hole. The metal layer is electrically connected to the pads of the second chip and the first rewiring structure, respectively.

2. The packaging structure as described in claim 1, characterized in that, The dielectric constant of the first dielectric layer is lower than that of the encapsulation.

3. The packaging structure as described in claim 1, characterized in that, A third hole is formed on the back side of the first chip within the molding compound. The third hole is filled with a second dielectric layer, the dielectric constant of which is lower than that of the molding compound.

4. The packaging structure as described in claim 1, characterized in that, The first rewiring structure includes a first rewiring metal layer, a first insulating layer and a second rewiring metal layer sequentially disposed on one side of the first surface. The first insulating layer covers the first rewiring metal layer, and a first window is provided on the first insulating layer to expose a portion of the first rewiring metal layer. The second rewiring metal layer is electrically connected to the first rewiring metal layer through the first window. The second rewiring structure includes a third rewiring metal layer, a second insulating layer, and a fourth rewiring metal layer sequentially disposed on one side of the second surface. The second insulating layer encloses the third rewiring metal layer, and a second window is provided on the second insulating layer to expose a portion of the third rewiring metal layer. The fourth rewiring metal layer is electrically connected to the third rewiring metal layer through the second window.

5. The packaging structure as described in claim 1, characterized in that, The first wiring structure is provided with a first external connection terminal, and the second wiring structure is provided with a second external connection terminal.

6. A method for preparing a packaging structure, characterized in that, include: Provide carrier board; At least one first chip is mounted on the same surface of the carrier board with the pad face facing the carrier board and at least one second chip is mounted at intervals with the back face facing the carrier board; The first chip and the second chip after mounting are encapsulated to form a molded body covering the first chip and the second chip, and the carrier board is removed; A first hole is formed on one side of the second surface of the molding compound, and the first hole is located between the pad of the second chip and the second surface; The first hole is filled with a dielectric material to form a first dielectric layer; A second hole is formed within the first dielectric layer to expose the pads of the second chip; The second hole is filled with a metallic material to form a metal layer; A first rewiring structure electrically connected to the metal layer is formed on one side of the second surface of the molding compound, and a second rewiring structure electrically connected to the pads of the first chip is formed on one side of the first surface of the molding compound.

7. The method for preparing the packaging structure as described in claim 6, characterized in that, After removing the carrier plate, the method further includes: A third hole is formed on one side of the second surface of the molding compound, and the third hole is located between the first chip and the second surface; The dielectric material is filled into the third hole to form a second dielectric layer.

8. The method for preparing the packaging structure as described in claim 6 or 7, characterized in that, The dielectric constant of the dielectric material is lower than that of the encapsulation.

9. The method for preparing the packaging structure as described in claim 7, characterized in that, The first rewiring structure, which is electrically connected to the metal layer, is formed on one side of the second surface of the molding compound, including: A first redistribution metal layer is formed on the second surface of the molding compound, wherein the first redistribution metal layer is electrically connected to the metal layer; A first insulating layer is formed on the second surface of the encapsulation, wherein the first insulating layer encapsulates the first redistribution metal layer, and a first window is provided on the first insulating layer to expose a portion of the first redistribution metal layer; A second rewiring metal layer is formed on the surface of the first insulating layer, wherein the second rewiring metal layer is electrically connected to the first rewiring metal layer through the first window; The second rewiring structure, which forms an electrical connection with the pads of the first chip on one side of the first surface of the molding compound, includes: A third wiring metal layer is formed on the first surface of the molding compound, wherein the third wiring metal layer is electrically connected to the pads of the first chip; A second insulating layer is formed on the first surface of the encapsulated body, wherein the second insulating layer encapsulates the third rewiring metal layer, and a second window is provided on the second insulating layer to expose a portion of the third rewiring metal layer; A fourth rewiring metal layer is formed on the surface of the second insulating layer, wherein the fourth rewiring metal layer is electrically connected to the third rewiring metal layer through the second window.

10. The method for preparing the packaging structure as described in claim 6, characterized in that, After forming a first rewiring structure electrically connected to the metal layer on one side of the second surface of the molding compound, the method further includes: A first external connection terminal is formed on the surface of the first rewiring structure opposite to the molding compound; After forming a second rewiring structure electrically connected to the pads of the first chip on one side of the first surface of the molding compound, the method further includes: A second external connection terminal is formed on the surface of the second rewiring structure opposite to the encapsulation.

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