Distributed intelligent wireless balance

Abstract

This invention relates to a distributed intelligent wireless balance, belonging to the field of wind tunnel balance measurement technology. It addresses the problem of intelligent measurement in wind tunnel balances. The invention features connectors installed at the center of the left and right end faces of the balance body, and strain gauge protective covers installed at the left and right ends of the balance body. The strain gauges are mounted on the balance body, located below the strain gauge protective covers. A main control module is installed in the middle of the balance body, and a circuit board protective cover is mounted on the main control module. The main control module is connected via an RS-485 bus to a vibration sensor, an angle sensor, a data acquisition module, and a temperature sensor mounted on the balance body. The vibration sensor and angle sensor are respectively located to the left and right of the main control module, the temperature sensor is located below the main control module, and the data acquisition module is located below the vibration sensor and angle sensor, respectively. This invention significantly improves the intelligence level of the balance.

Description

Technical Field

[0001] This invention belongs to the field of wind tunnel balance measurement technology, specifically relating to a distributed intelligent wireless balance. Background Technology

[0002] To meet the force measurement needs of various types of aircraft, the requirements for wind tunnel balances are gradually increasing. In recent years, with the increasing demands of multi-component force measurement tests, unsteady experiments, and dynamic simulation tests, as well as the increasing size of wind tunnels, problems such as multi-balance force measurement, interference during long-distance transmission, difficulties in transmitting test signals, and the impact of balance troubleshooting on test efficiency have become increasingly prominent. There is an urgent need for continuous advancements in balance technology to adapt to the rapid development of testing techniques.

[0003] Meanwhile, traditional wind tunnel strain balances have a single function, only capable of measuring voltage signals, which is gradually failing to keep up with the increasingly diverse types of wind tunnel tests. Therefore, improvements and enhancements are needed in their measurement functions. Summary of the Invention

[0004] The problem this invention aims to solve is to achieve intelligent measurement using a wind tunnel balance, and proposes a distributed intelligent wireless balance.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A distributed intelligent wireless balance includes a balance body, a strain gauge protective cover, strain gauges, a vibration sensor, an angle sensor, a data acquisition module, a temperature sensor, a main control module, a circuit board protective cover, and a connector.

[0007] Connectors are installed at the center of the left and right end faces of the balance body, and strain gauge protective covers are installed at the left and right ends of the balance body; the strain gauges are installed on the balance body and located below the strain gauge protective covers; the main control module is installed in the middle of the balance body, and a circuit board protective cover is installed on the main control module.

[0008] The main control module is connected to the vibration sensor, angle sensor, acquisition module, and temperature sensor installed on the balance body via an RS-485 bus. The vibration sensor and angle sensor are respectively located on the left and right sides of the main control module, the temperature sensor is located below the main control module, and the acquisition module is located below the vibration sensor and angle sensor.

[0009] Furthermore, the number of acquisition modules is 6.

[0010] Furthermore, the acquisition module consists of switches K1~K7, a filter LPF, a bridge excitation circuit, a calibration signal source, ADC1 and ADC2, an LDO, a DC / DC converter, an ARM chip, and an RS-485 interface. The acquisition module is connected to the bridge circuit.

[0011] Furthermore, the acquisition module contains four LPF filters, of which LPF1 and LPF2 are single-ended filters, and LPF3 and LPF4 are differential filters; K1, K2, K3 and K4 are two single-pole double-throw analog switches, K5 is a double-pole four-throw switch, and K6 and K7 are single-pole single-throw switches.

[0012] Furthermore, the acquisition module operates in three modes: normal operation, self-calibration, and fault diagnosis.

[0013] Furthermore, the main control module sends the real-time balance data collected by the acquisition module to the host computer at a sampling rate of 2kHz, transmitting once every 60 frames, with a transmission time of 0.8ms; the host computer then performs balance data analysis and processing.

[0014] The host computer preprocesses the received real-time balance data to remove interference signals and outputs the true balance signal. It then compares this output with the given full-scale value. When the balance signal output exceeds the full-scale output given in the balance certificate, it issues a prompt and alarm.

[0015] Furthermore, the formula for converting real-time balance data into balance stress is as follows:

[0016] ;

[0017] in, Mises stress at the critical load monitoring point, , , These are the normal stress components in three orthogonal directions. , , These are the shear stress components in the corresponding plane;

[0018] The method for preprocessing the real-time data of the balance is to perform 50Hz notch filtering, low-pass filtering and moving average filtering to remove interference signals in the original signal before calculating the load.

[0019] The beneficial effects of this invention are:

[0020] This invention discloses a distributed intelligent wireless balance that transmits signals wirelessly, reducing the use of signal cables and improving anti-interference capabilities. Based on a traditional wind tunnel strain gauge balance, this invention optimizes the design by adding distributed wireless data acquisition, processing, and transmission modules while maintaining the overall dimensions of the balance. This reduces damage to the classic balance structure and improves the balance's applicability and reliability. Compared to traditional strain gauge balances, it adds core computing and data processing functions. Based on a microchip, it can perform balance formula calculations, real-time load monitoring, and fault diagnosis, significantly enhancing the balance's intelligence. Attached Figure Description

[0021] Figure 1 This is a perspective structural diagram of a distributed intelligent wireless balance according to the present invention.

[0022] Figure 2 This is a circuit connection diagram of the data acquisition module of the present invention;

[0023] Figure 3 This is a circuit diagram illustrating the normal operating mode of the data acquisition module of this invention.

[0024] Figure 4 This is a circuit diagram illustrating the self-calibration operation mode of the acquisition module of the present invention.

[0025] Figure 5 This is a circuit diagram corresponding to the first step of the fault diagnosis operation mode of the acquisition module of the present invention;

[0026] Figure 6 This is the circuit diagram corresponding to the second step of the fault diagnosis operation mode of the acquisition module of the present invention;

[0027] Figure 7 This is a schematic diagram showing the connection relationships between temperature sensors;

[0028] Figure 8 This is a schematic diagram of the structure of a distributed intelligent wireless balance according to the present invention; In the figure, 1 is the balance body, 2 is the strain gauge protective cover, 3 is the strain gauge, 4 is the vibration sensor, 5 is the angle sensor, 6 is the acquisition module, 7 is the temperature sensor, 8 is the main control module, 9 is the circuit board protective cover, and 10 is the connector. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only for explaining the invention and are not intended to limit the invention; that is, the described specific embodiments are merely a part of the embodiments of the invention, and not all of them. The components of the specific embodiments of the invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations, and the invention may also have other embodiments.

[0030] Therefore, the following detailed description of specific embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected specific embodiments of the invention. All other specific embodiments obtained by those skilled in the art based on these specific embodiments without inventive effort are within the scope of protection of this invention.

[0031] To further understand the invention's content, features, and effects, the following specific embodiments are provided, along with accompanying drawings. Figure 1 - Appendix Figure 8 Detailed explanation is as follows:

[0032] Example 1:

[0033] A distributed intelligent wireless balance includes a balance body 1, a strain gauge protective cover 2, a strain gauge 3, a vibration sensor 4, an angle sensor 5, a data acquisition module 6, a temperature sensor 7, a main control module 8, a circuit board protective cover 9, and a connector 10.

[0034] Connectors 10 are installed at the center of the left and right end faces of the balance body 1, and strain gauge protective covers 2 are installed at the left and right ends of the balance body 1; strain gauges 3 are installed on the balance body 1 and located below the strain gauge protective covers 2; the main control module 8 is installed in the middle of the balance body 1, and a circuit board protective cover 9 is installed on the main control module 8.

[0035] The main control module 8 is connected to the vibration sensor 4, angle sensor 5, acquisition module 6, and temperature sensor 7 installed on the balance body 1 via an RS-485 bus. The vibration sensor 4 and angle sensor 5 are respectively located on the left and right sides of the main control module 8, the temperature sensor 7 is located below the main control module 8, and the acquisition module is located below the vibration sensor 4 and angle sensor 5.

[0036] Furthermore, the main control module acts as the master node in the network, while other acquisition modules act as slave nodes. The bus is arbitrated and controlled by the master node. Only when the master node notifies a slave node to upload data will the slave node occupy the bus and switch to the transmitting state to upload data; otherwise, the slave node is in the receiving state, and the bus is occupied by the master node. The main control module is also responsible for providing the acquisition modules with the 6V power supply and synchronous acquisition signals required for operation.

[0037] Furthermore, the balance body 1 is cylindrical in shape, and the number of acquisition modules 6 is 6.

[0038] Furthermore, the acquisition module 6 consists of switches K1~K7, a filter LPF, a bridge excitation circuit, a calibration signal source, ADC1 and ADC2, an LDO, a DC / DC converter, an ARM chip, and an RS-485 interface. The acquisition module is connected to the bridge circuit.

[0039] Furthermore, the acquisition module 6 contains four LPF filters, of which LPF1 and LPF2 are single-ended filters, and LPF3 and LPF4 are differential filters; K1, K2, K3 and K4 are two single-pole double-throw analog switches, K5 is a double-pole four-throw switch, and K6 and K7 are single-pole single-throw switches.

[0040] Furthermore, the resistor and capacitor of the single-ended filter are: Its cutoff frequency ;

[0041] The resistors and capacitors of the LPF3 differential filter are Its cutoff frequency ;

[0042] The resistors and capacitors of the LPF4 differential filter are Its cutoff frequency f c4 ≈229Hz;

[0043] Furthermore, the acquisition module 6 has three working modes: normal working mode, self-calibration working mode, and fault diagnosis working mode.

[0044] Furthermore, the main control module 8 sends the real-time balance data collected by the acquisition module 6 to the host computer at a sampling rate of 2kHz, transmitting once every 60 frames, with a transmission time of 0.8ms; the host computer then performs balance data analysis and processing.

[0045] The host computer preprocesses the received real-time balance data to remove interference signals and outputs the true balance signal. It then compares this output with the given full-scale value. When the balance signal output exceeds the full-scale output given in the balance certificate, it issues a prompt and alarm.

[0046] Furthermore, the formula for converting real-time balance data into balance stress is as follows:

[0047] ;

[0048] in, Mises stress at the critical load monitoring point, , , These are the normal stress components in three orthogonal directions. , , This represents the shear stress component in the corresponding plane.

[0049] Further, in the raw signal acquisition, when the first set of data is acquired in the 1ms, this data is substituted into the balance formula to calculate the real-time load of the balance, which is equivalent to obtaining a 1x6 matrix. This 1x6 matrix is ​​multiplied by several (let's assume N) 6x6 matrices (externally imported; the number of matrices may vary depending on the balance), resulting in a new 1x6 matrix. Then, the six data points in this new 1x6 matrix are used to calculate a value based on the balance stress calculation formula converted from real-time balance data. This value is compared with a set threshold (human-defined), and if it exceeds the threshold, an alarm is triggered. Data acquired at each subsequent moment is processed in this way. If 1000 sets of data are acquired within 1 second, the final result is... Each calculated value is compared with a threshold. This is equivalent to performing 1000 real-time load checks on each monitoring point (corresponding to a 6x6 matrix).

[0050] The method for preprocessing the real-time data of the balance is to perform 50Hz notch filtering, low-pass filtering and moving average filtering to remove interference signals in the original signal before calculating the load.

[0051] Table 1

[0052]

[0053] The technical specifications of the distributed intelligent wireless balance described in this embodiment are shown in Table 1.

[0054] Example 2:

[0055] The acquisition module of Example 1 is described in detail below:

[0056] The acquisition module uses the switching of K1~K7 and the cooperation of the ADC to realize fault detection of the strain circuit; the LPF filter performs low-pass filtering of the signal; the bridge excitation circuit provides a high-precision power supply with remote compensation to the bridge circuit; the calibration signal source provides a standard signal for the system's self-calibration; the ADC digitizes the analog signal to realize signal acquisition; the LDO and DC / DC converter convert the 6V power supply provided by the main control module into analog and digital power supplies to power other circuits; the ARM chip controls the ADC and communicates with the main control module; the RS-485 interface converts the ARM's TTL serial port signal into a level signal conforming to the RS-485 standard and realizes networking with the main control module.

[0057] The circuit connection relationship of the acquisition module is as follows: Figure 2 As shown:

[0058] The input terminal of K1 is connected to the negative terminal of the bridge feedback voltage, the output terminal 1 of K1 is connected to the negative terminal of the bridge excitation circuit, and the output terminal 2 of K1 is connected to LPF1. The input terminal of K2 is connected to the negative excitation signal, the output terminal 1 of K2 is connected to the ground of the bridge excitation circuit, and the output terminal 2 of K2 is connected to ground after being connected to a 2K resistor. The input terminal of K3 is connected to the positive excitation signal, the output terminal 1 of K3 is connected to the positive 5V of the bridge excitation circuit, and the output terminal 2 of K3 is connected to the AI0 terminal of ADC1. The input terminal of K4 is connected to the positive terminal of the bridge feedback voltage, the output terminal 1 of K4 is connected to the positive terminal of the bridge excitation circuit, and the output terminal 2 of K4 is connected to LPF2. The bridge excitation circuit is also connected to the 6V power supply line and ADC1. LPF1 and LPF2 are connected to ADC1. ADC1 is also connected to the LDO, DC / DC, ARM chip, and K6 and K7.

[0059] The input terminal of K6 is connected to the positive terminal of the bridge signal, and the output terminal of K6 is connected to the input terminals of LPF3, LPF4, and K5 respectively. The input terminal of K7 is connected to the negative terminal of the bridge signal, and the output terminal of K7 is connected to the input terminals of LPF3, LPF4, and K5 respectively. The first pin of output terminal 1 of K5 is connected to the AI4 input channel of ADC1, and the other pin is connected to ground through a 2k resistor. Pins 2 and 3 are connected to the calibration signal source respectively. K5 is also connected to ADC2. LPF4 is connected to ADC2. ADC2 is also connected to LDO, DC / DC, and ARM chips respectively.

[0060] Furthermore, the working method of the acquisition module 6 is explained in detail below:

[0061] Normal working mode, such as Figure 3 As shown, switches K1~K4 are connected to the corresponding terminal 1 to achieve normal power supply to the bridge circuit; K5 is connected to terminal 4, and K6 and K7 are closed to achieve normal measurement of the strain gauge bridge voltage.

[0062] Self-calibration working mode such as Figure 4 As shown, the ADC's internal self-calibration is being used. The ADC includes offset calibration and gain calibration. In self-calibration mode, K6 and K7 need to be disconnected. Offset calibration is achieved when K5 is connected to terminal 2, and gain calibration is achieved when K5 is connected to terminal 3.

[0063] When troubleshooting, such as Figure 5 and Figure 6 As shown, the enable terminal EN of the bridge excitation is invalid, causing it to malfunction. The basic principle of fault diagnosis is to measure the resistance of the bridge arms, which requires two steps to complete. The principle of the first step is as follows: Figure 5 As shown, K1~K2 are enabled, controlling K1~K4 to be connected to terminal 2, K5 to terminal 4, and K6~K7 to be closed. The ADC outputs a current of I0 through AI0, with the current flow direction indicated by the dashed line in the figure. The measurement steps are as follows:

[0064] S1. Measure the voltage V between AI1 and AI5. 15 Then the total resistance of the bridge circuit, R0 = (R1 + R4) / / (R2 + R3), is:

[0065] ;

[0066] S2. Measure the voltage V between AI1 and AI2 respectively. 12 The voltage V between AI2 and AI5 25 ,but:

[0067] ;

[0068] S3. Then measure the voltage V between AI1 and AI3 respectively. 13 The voltage value V between AI3 and AI5 35 ,but:

[0069] ;

[0070] From equations (1) to (3), we get:

[0071] ;

[0072] The principle of the second step of measurement is as follows: Figure 6As shown, the ratio of R1 to R2 is obtained by measurement, and the resistance value is calculated according to equation (4). First, the enable of K1~K2 is disabled, so that it is in a high resistance state, and the connection before and after the switch is cut off. Control K3~K4 to connect to terminal 2, K5 to terminal 1, K6~K7 to close, and the ADC outputs a current of I0 through AI4. The current flow direction is shown by the dotted line in the figure. Measure the voltage V between AI2 and AI1 respectively. 21 The voltage V between AI3 and AI1 31 ,but:

[0073] ;

[0074] Then, from equations (4) and (5), we can obtain:

[0075] ;

[0076] Then, from equations (2) and (3), we get:

[0077] .

[0078] Example 3:

[0079] In this embodiment, the bridge excitation circuit in the acquisition module of Embodiment 1 uses the ADR3650BRMZ chip, which has remote power supply compensation capability, simplifying the design work; the DC / DC uses the TPS82130 chip; the calibration signal source uses the REF35160 chip and the OPA313 chip; the RS-485 interface uses the TI THVD2450, which has IECESD protection function.

[0080] The analog-to-digital conversion (ADC1) and ADC2 sections use the TI ADS124S06. This ADC chip features two programmable current sources, selectable channel outputs, and external conversion pins for synchronous conversion. It incorporates a low-noise programmable gain amplifier (PGA), has a 24-bit sampling bit depth, and a maximum sampling frequency of 4kSPS, meeting the technical specifications. Each ADS124S06 channel consists of a data selector, PGA, a 24-bit Σ-Δ modulator, and a configurable digital filter. The PGA gain is configurable from 1, 2, 4…128. The Σ-Δ modulator oversamples the analog signal and transmits the digital signal to the digital filter module, finally sending it to the serial data interface. The built-in reference voltage source VREF is 2.5V, but an external reference voltage can also be used, set to 0.5~5V. The voltage range of the analog input channels is related to the PGA gain. The input voltage range (V) of the analog channels is:

[0081] PGA bypass: -0.05 ≤ VAINx ≤ 5.05; PGA gain Gain = 1, 2, 4, ... 16: 0.15 + V INMAX •(Gain-1)≤V AINx ≤4.85-V INMAX •(Gain-1); The gain of the PGA is Gain = 32…128: 0.15+V INMAX •15.5≤V AINx ≤4.85-V INMAX •15.5; where V INMAX =V REF / Gain.

[0082] The ADC has three operating modes: power-down mode, standby mode, and conversion mode. In power-down mode, all analog and digital circuits are powered off to reduce power consumption. Only the internal voltage reference can be configured to remain on in power-down mode to maintain fast startup. In standby mode, the ADC can be controlled to enter conversion mode via commands. Conversion mode is further divided into continuous conversion and single-transaction conversion modes. For single-transaction conversion mode, sending a START command or keeping the external START pin high initiates one conversion; after conversion, the device enters standby mode. For continuous conversion mode, sending a START command or keeping the external START pin high initiates continuous conversion; sending a STOP command or setting the external START pin low stops the conversion.

[0083] The ARM chip used is GigaDevice's GD32F103TBU6, packaged in a QFN36 package with a size of 6×6mm. An 8MHz active crystal oscillator is used as the processor's high-speed external clock, while low-speed external clock pins are not used. The reset circuit is implemented using R and C, and the startup circuit selects the ARM's program loading mode from Flash. JTAG debugging uses SW mode.

[0084] Example 4:

[0085] The temperature sensor of Example 1 is described in detail below. The temperature sensor is used to measure the temperature of the balance and is arranged in a specific location. Four sensors are arranged together, and these four sensors are connected by a single power supply and communication cable. Each sensor is distinguished by a different address. A connection diagram is shown below. Figure 7 As shown, the sensor chip is placed on a 10×10mm, 1.0mm thick circuit board. The exposed pads on the back are attached to the balance body for heat conduction. To protect the internal circuitry and isolate the external interface, the TXS0104E is selected to implement the communication interface.

[0086] Example 5:

[0087] The main control module of Embodiment 1 is described in detail below. The main control module includes: an ARM main controller, an RS-485 interface, an AD converter, a network interface and a transformer, a WIFI module, and a power supply DC / DC converter and an LDO.

[0088] The ARM master controller uses the STM32H745VIH6 chip. This master control unit consists of an ARM chip, a clock circuit, a reset circuit, and a JTAG interface. The STM32H745VIH6 is the master control chip; the clock circuit provides a stable clock for the chip; the reset circuit performs automatic power-on reset; and the JTAG interface is used for debugging the master control chip. The chip uses one SDMMC, two SPI interfaces, and two serial ports for external communication. SPI1 is used for communication with the 10M / 100M Ethernet unit, SPI3 for communication with the AD converter, USART1 for communication with the RS-485 interface, USART2 for communication with Wi-Fi, and SDMMC1 for communication with SDNAND.

[0089] The STM32H745VIH6 chip features an ARM Cortex-M7 core supporting a double-precision FPU and L1 cache. It boasts a rich set of peripheral interfaces, including USB bus, SPI bus, DMA, Ethernet, and GPIO. The system clock frequency reaches up to 480MHz. Furthermore, its internal Clock Manager (RCC) design provides greater flexibility in clock source selection. For communication peripherals that can use two different clock domains (bus interface clock or core peripheral clock), the system frequency can be changed without modifying the baud rate. The main parameters of this chip are as follows:

[0090] a) Based on the ARM Cortex-M7 core;

[0091] b) Up to 2MB of flash memory, supporting read-while-write operation;

[0092] c) Up to 1MB of on-chip RAM, 864KB of user SRAM, and 4KB of BSRAM in the backup domain;

[0093] d) Flexible external memory controllers with up to 32-bit data buses: SRAM, PSRAM, SDRAM / LPS RDRAM, NOR / NAND flash memory with clock frequencies up to 100MHz in synchronous mode.

[0094] e) The Quad-SPI memory interface is specifically designed for communication with single, dual, or Quad-SPI flash memory. It supports both single and dual data rate operation.

[0095] f) Six SPI interfaces enable communication up to 150 Mbits / s in master and slave modes, half-duplex, full-duplex, and simplex modes.

[0096] g) It has a 64MHz HSI, a 48MHz HSI, a 32kHz LSI, four 48MHz HSEs, a 32.768kHz LSE, and three PLLs in fractional mode (one for the system clock and two for the kernel clock).

[0097] When the STM32H743VIH6TR is operating normally, it offers six clock sources. These include two external oscillators: a high-speed external oscillator (supporting a frequency range of 4 to 48 MHz) and a low-speed external oscillator (32 kHz crystal), and four internal oscillators: a high-speed internal oscillator, an RC oscillator, a low-power internal oscillator, and a low-speed internal oscillator. The high-speed internal clock uses an RC oscillator, which typically has lower accuracy, with an error of around 1%, more than 10 times worse than the external high-speed oscillator. However, due to the high clock requirements of this design, an external clock is used. Specifically, OCS_IN and OSC_OUT are the high-speed and low-speed external clock pins of the main control chip, respectively. In this design, an active crystal oscillator is used as the processor's high-speed external clock; the low-speed external clock pins are not used.

[0098] The STM32H743VIH6TR offers three reset methods: power-on reset, manual reset, and software reset. Based on the project requirements, the power-on reset method is selected for the design. According to the STM32H743VIH6TR datasheet, the NRST external reset pin is active low, and the low-level duration is at least 1000ns. A resistor-capacitor (RC) reset circuit is used here to control the reset duration. Upon power-on, the capacitor charges, and the NRST pin experiences a controllable, brief low level. The duration of this low level is determined by the resistor and capacitor, calculated as: t = 1.1 × RC (fixed formula). To ensure reliable reset, a 10K resistor and a 0.1uF capacitor are selected, resulting in a calculated reset time of 1.1ms, significantly greater than the specified value of 1000ns.

[0099] To meet the requirements for measuring both voltage and current signals, the AD4112 from Analog Devices was selected as the ADC. The AD4112 is a low-power, low-noise, 24-bit analog-to-digital converter (ADC) that supports fully differential or single-ended, high-impedance bipolar inputs, ±10V voltage input, and 0mA to 20mA current input. The AD4112 also integrates key analog and digital signal conditioning modules, configuring eight individual settings for each analog input channel used. The AD4112's maximum channel scan rate is 6.21kSPS, which meets the design requirements.

[0100] 1.1.1. Network Interface Design:

[0101] The network port unit, serving as an alternative solution for communication between the balance and the data processing computer, mainly comprises an Ethernet controller, a network transformer, and network port connectors. The Ethernet controller primarily simplifies the TCP / IP protocol, reducing user design complexity and ensuring the reliability of Ethernet communication. The network transformer isolates the Ethernet controller's transmit and receive signals from network signals. The network port connector replaces traditional RJ45 network sockets, handling the connection between the network port unit and external devices.

[0102] 1.1.1.1. Ethernet Controller:

[0103] The Ethernet controller internally includes a data link layer and a physical layer, providing the foundation for a complete network protocol stack. The W5500 chip is used in the design of this Ethernet controller.

[0104] The W5500 chip is a hardwired TCP / IP embedded Ethernet controller that provides simpler Internet connectivity for embedded systems. It allows users to implement Internet connectivity in their applications using a single chip with an embedded TCP / IP stack, 10 / 100 Ethernet MAC, and PHY. Furthermore, the W5500 embeds a 32Kbyte internal memory buffer for Ethernet packet processing; Ethernet applications can be implemented simply by adding a socket program. The host chip can provide an SPI interface for communication with the W5500. The W5500's SPI supports 80MHz speed and a new, efficient SPI protocol for high-speed network communication. The W5500 also provides WOL (Wake on LAN) and power-down modes to reduce power consumption.

[0105] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0106] Although this application has been described above with reference to specific embodiments, various modifications can be made and components can be replaced with equivalents without departing from the scope of this application. In particular, as long as there is no structural conflict, the features in the specific embodiments disclosed in this application can be combined with each other in any way. The lack of an exhaustive description of these combinations in this specification is merely for the sake of brevity and resource conservation. Therefore, this application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A distributed intelligent wireless balance, characterized in that, Includes balance body (1), strain gauge protective cover (2), strain gauge (3), vibration sensor (4), angle sensor (5), acquisition module (6), temperature sensor (7), main control module (8), circuit board protective cover (9), connector (10); Connectors (10) are installed at the center of the left and right end faces of the balance body (1), and strain gauge protective covers (2) are installed at the left and right ends of the balance body (1); the strain gauge (3) is installed on the balance body (1) and located below the strain gauge protective cover (2); the main control module (8) is installed in the middle of the balance body (1), and a circuit board protective cover (9) is installed on the main control module (8). The main control module (8) is connected to the vibration sensor (4), angle sensor (5), acquisition module (6), and temperature sensor (7) installed on the balance body (1) via RS-485 bus. The vibration sensor (4) and angle sensor (5) are respectively located on the left and right sides of the main control module (8), the temperature sensor (7) is located below the main control module (8), and the acquisition module is located below the vibration sensor (4) and angle sensor (5).

2. The distributed intelligent wireless balance according to claim 1, characterized in that, The balance body (1) is cylindrical in shape, and there are 6 acquisition modules (6).

3. The distributed intelligent wireless balance according to claim 2, characterized in that, The acquisition module (6) consists of switches K1~K7, filter LPF, bridge excitation circuit, calibration signal source, ADC1 and ADC2, LDO, DC / DC, ARM chip and RS-485 interface, and the acquisition module is connected to the bridge circuit.

4. A distributed intelligent wireless balance according to claim 3, characterized in that, The acquisition module (6) contains four filters (LPFs), of which LPF1 and LPF2 are single-ended filters, and LPF3 and LPF4 are differential filters; K1, K2, K3 and K4 are two single-pole double-throw analog switches, K5 is a double-pole four-throw switch, and K6 and K7 are single-pole single-throw switches.

5. A distributed intelligent wireless balance according to claim 4, characterized in that, The acquisition module (6) has three working modes: normal working mode, self-calibration working mode, and fault diagnosis working mode.

6. A distributed intelligent wireless balance according to claim 5, characterized in that, The main control module (8) sends the real-time balance data collected by the acquisition module (6) to the host computer. The data is transmitted once every 60 frames at a sampling rate of 2kHz, and the transmission time is 0.8ms. The host computer performs balance data analysis and processing. The host computer preprocesses the received real-time balance data to remove interference signals and outputs the true balance signal. It then compares this output with the given full-scale value. When the balance signal output exceeds the full-scale output given in the balance certificate, it issues a prompt and alarm.

7. A distributed intelligent wireless balance according to claim 6, characterized in that, The formula for converting real-time balance data into balance stress is as follows: ； in, Mises stress at the critical load monitoring point, , , These are the normal stress components in three orthogonal directions. , , These are the shear stress components within the corresponding plane; The method for preprocessing the real-time data of the balance is to perform 50Hz notch filtering, low-pass filtering and moving average filtering to remove interference signals in the original signal before calculating the load.

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