An agricultural machine open multi-core controller and a resource virtualization mapping method thereof

Abstract

This invention relates to an open multi-core controller for agricultural machinery and its resource virtualization mapping method. It includes a core board module with a main control processing unit and an expansion board module consisting of input / output circuit units and a cascaded structure including at least two sub-control units. In the method, the main control processing unit generates control commands, and the sub-control units parse the control commands and control the state of electronic components in each topology multiplexing circuit according to the parsing results, thereby changing the electrical characteristics of each physical port and realizing dynamic switching of the same physical port between different operating modes. Compared with the prior art, this invention has advantages such as improved controller interface versatility, expansion flexibility, and ease of software and hardware upgrades and maintenance.

Description

Technical Field

[0001] This invention relates to the field of agricultural machinery electronic control and automation technology, and in particular to an open multi-core controller for agricultural machinery and its resource virtualization mapping method. Background Technology

[0002] With the deepening of the intelligent transformation of agriculture, the operating scenarios of agricultural robots are rapidly evolving from mechanization to automation. As the core decision-making unit of agricultural robots, the controller not only undertakes complex motion planning and autonomous decision-making tasks, but also needs to adapt to the high dynamic and high stability requirements of the unstructured agricultural environment. Against the backdrop of rapid iteration in agricultural machinery technology, developing an open controller that combines high performance and high versatility, enabling it to flexibly adapt to the complex interface requirements of various agricultural implements and to cope with low-cost replacement and upgrades of future hardware through modular design, has become a key issue that the industry urgently needs to solve.

[0003] However, existing agricultural machinery controllers generally suffer from rigid interface functions and insufficient versatility in their hardware resource configurations. Traditional controllers typically have fixed I / O interfaces designed for specific tasks (such as a single harvester or plant protection machine). When dealing with different implements or different types of sensors / actuators, it is often necessary to adjust the interface electrical characteristics through physical jumpers or even changes to the PCB board soldering. This "hard-wired" approach cannot dynamically define hardware attributes through software, resulting in low port reuse rates in multi-tasking scenarios and leading to a complex array of controller models and high maintenance costs.

[0004] Regarding controller architecture optimization, existing technologies such as those disclosed in CN120233735A, CN114115140A, CN115658569A, and CN111913822A are essentially solutions based on asymmetric multiprocessing (AMP) architecture. These solutions achieve task division between communication cores and logic cores within a single SoC chip, utilizing shared memory and hardware lock mechanisms to resolve communication interruptions. However, this approach is essentially still an on-chip coupled architecture, focusing on the logical allocation of computing power within the chip and failing to address the modular decoupling issue at the physical level of the controller. When users need to upgrade the main controller's computing power or replace it with a processor of a different architecture, the entire hardware circuit must still be redesigned, making it impossible to achieve rapid board-level hardware replacement and system integration based on a unified communication protocol.

[0005] Furthermore, most current general-purpose controllers adopt a single-core or single-board centralized structure, which has two significant drawbacks in practical applications: 1. Competition for computing resources and real-time conflicts: As agricultural robot control algorithms (such as SLAM navigation and multi-motor coordination) become increasingly complex, high-frequency low-level I / O switching tasks (such as PWM chatter control of hydraulic valves and encoder pulse capture) compete for CPU resources with complex high-level logic operations on the same chip, which can easily cause jitter in the control cycle and even lead to system crashes in severe cases. There is a lack of effective hardware-level computing resource isolation.

[0006] 2. Excessive hardware-software coupling, lacking true "software-defined hardware" capability: Low-level drivers are tightly bound to high-level application logic, resulting in poor portability. While existing technologies (such as the scheme with publication number CN118859821A) propose hardware-software separation I / O address mapping methods, they only address the static correspondence between software variable names and logical addresses (such as IEC 61131-3 addresses), failing to address the dynamic reconfiguration of physical port electrical attributes. In other words, existing technologies cannot control the switching of internal circuit topology through software instructions, thus preventing a physical pin from switching in real-time between "input mode" and "output mode," or between "analog signal acquisition" and "digital signal driving." This limitation makes it difficult for the controller to achieve rapid response through pure software configuration when facing expansions in the number of interfaces or changes in functionality.

[0007] In summary, the current system suffers from several problems, including highly coupled hardware and software architecture leading to the inability to dynamically reconfigure the electrical characteristics of physical ports, an imbalance in the allocation of computing resources between the underlying drivers and the upper-level logic operators, and a lack of truly modular decoupling and low-cost upgrade capabilities. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the existing technology and provide an open multi-core controller for agricultural machinery and its resource virtualization mapping method.

[0009] The objective of this invention can be achieved through the following technical solutions: According to one aspect of the present invention, an open multi-core controller for agricultural machinery is provided, comprising: The core board module has a main control processing unit deployed on it. The main control processing unit is used to run the agricultural machinery operation logic and generate control instructions that include I / O channel mode configuration frames and working parameter setting frames. The expansion board module is electrically connected to the core board module through a connector. The expansion board module consists of input / output circuit units and a cascaded structure including at least two sub-control units. The input / output circuit unit contains several topology multiplexing circuits and physical ports, and each topology multiplexing circuit is connected to a physical port. The sub-control unit is configured to parse control commands and control the state of electronic components in each topology multiplexing circuit according to the parsing results, thereby changing the electrical characteristics of each physical port and realizing dynamic switching of the same physical port between different working modes.

[0010] As a preferred technical solution, the main control processing unit runs a real-time operating kernel conforming to the IEC 61131-3 or IEC 61499 standard to process agricultural machinery operation logic code; the sub-control units are used to run the underlying interface drivers; the main control processing unit and the sub-control units communicate decoupledly through a resource virtualization mapping protocol.

[0011] As a preferred technical solution, the topology multiplexing circuit includes a DI / AI multiplexing circuit, a DO / DI multiplexing circuit, an FI circuit, an ADC multiplexing circuit, a DAC circuit, or a DO / DI / PWM multiplexing circuit; wherein, the ADC multiplexing circuit includes a VI / DI multiplexing circuit, a CUR / DI multiplexing circuit, and a VI / CUR multiplexing circuit.

[0012] As a preferred technical solution, the DO / DI / PWM multiplexing circuit includes an intelligent high-side switching chip, logic gate circuits, and a voltage comparator; the sub-control unit controls the logic combination of the input pins and diagnostic pins of the intelligent high-side switching chip, and combines the feedback signal of the voltage comparator to achieve switching between the following three physical modes: In PWM output mode, a pulse signal is output to the input pin; In DO output mode, output a high or low level to the input pin; In DI input mode, the input pin is set low, and the level status of the external port is read back through the diagnostic pin and voltage comparator.

[0013] As a preferred technical solution, the controller also includes a power management module, a CAN communication unit, and status indicator lights; The power management module is connected to and supplies power to the main control processing unit and the various levels of sub-control units; the CAN communication unit is deployed on the core board module to realize communication between the controller and external devices, and its communication data is directly processed by the main control processing unit. Status indicator lights are located on the core board module and expansion board module to indicate the working status of the main control processing unit, power management module and various levels of sub-control units in real time.

[0014] According to another aspect of the present invention, a resource virtualization mapping method for an open multi-core controller for agricultural machinery is provided, the method comprising: Mode configuration process: The main control processing unit of the core board module sends out the I / O channel mode configuration frame. The cascaded sub-control units in the expansion board module parse the I / O channel mode configuration frame and drive the corresponding topology multiplexing circuit to complete the virtualization mapping of the electrical characteristics of each physical port. Status transmission and monitoring process: The main control processing unit sends out working parameter setting frames. Each level of sub-control unit in the expansion board module executes the output control of the corresponding channel according to the parsing result of the working parameter setting frame, and packages the status feedback data of each physical port in a cascaded reverse order to form a data reporting frame. Finally, the data reporting frame is uploaded to the main control processing unit.

[0015] As a preferred technical solution, the mode configuration process specifically includes: The main control processing unit of the core board module runs a real-time operating system, generating and distributing I / O channel mode configuration frames containing mapping relationships between several physical port IDs and target working modes; Each level of sub-control unit in the expansion board module receives the I / O channel mode configuration frame, parses out the physical port ID belonging to its level and its corresponding target working mode, and forwards the remaining configuration information to the next level sub-control unit in cascading order; Each level of the sub-control unit controls the state of the electronic components in the corresponding topology multiplexing circuit according to the target operating mode, thereby changing the electrical characteristics of each physical port and realizing the dynamic switching of the same physical port between different operating modes.

[0016] As a preferred technical solution, the status release and monitoring process specifically includes: The main control processing unit of the core board module periodically sends out working parameter setting frames. The sub-control units at each level in the expansion board module forward the frames down in a cascaded order and execute the output control of the corresponding channel according to the working parameter setting frames. Except for the top-level sub-control unit in the cascade structure, each level of sub-control unit collects the input values ​​of each input channel and the output status of each output channel within its jurisdiction, encapsulates them into data reporting frames, and sends them to the next level of sub-control unit. The top-level sub-control unit in the cascade structure nests and packages the input values ​​and output status collected at this level with the received data reporting frames to generate a complete data reporting frame. This complete data reporting frame is then uploaded to the main control processing unit of the core board module to update the monitoring data of each physical port in the expansion board module in real time.

[0017] As a preferred technical solution, the data structures of the I / O channel mode configuration frame, the working parameter setting frame, and the data reporting frame all include: a 2-byte frame header field, a 2-byte reporting period field, an N-byte payload field, and a 1-byte sequence number field.

[0018] As a preferred technical solution, the frame header field includes five types, specifically defined as follows: The first frame header type configures the frame header for I / O channel mode; The second frame header type sets the frame header for working parameters; The first frame header type and the second frame header type are used in the communication frames sent by the main control processing unit to the sub-control unit at the top level of the cascaded structure; The third frame header type is the core board data reporting frame header, which is used in the communication frames sent from the top-level sub-control unit to the main control processing unit in the cascaded structure. The fourth frame header type is the frame header for configuring the mode within the expansion board, used in the communication frames sent from the upper-level sub-control unit to the lower-level sub-control unit within the expansion board module; The fifth frame header type is the data reporting frame header within the expansion board, used in communication frames sent from the lower-level sub-control unit to the upper-level sub-control unit within the expansion board module.

[0019] Compared with the prior art, the present invention has the following beneficial effects: 1. In this invention, not only is a separate design of the core board module and the expansion board module adopted, which conforms to the open controller design concept and realizes the optimal allocation of computing resources: the core board only runs logic code and the expansion board only runs complex circuit driving code, but also an input / output circuit unit containing several topology multiplexing circuits and physical ports is adopted. By combining the separate design of the core board module and the expansion board module with several topology multiplexing circuits, the control stability and hardware resource utilization of the controller are greatly improved. Furthermore, when using this controller, users do not need to pay attention to the writing of the underlying complex multiplexing circuit program. They only need to configure the mode of each channel on the core board module and use it directly.

[0020] As an open controller, this invention boasts excellent scalability through a discrete design combined with several topology multiplexing circuits. If subsequent upgrades to the number of controller interfaces or changes to the driver type are needed, there's no need to alter the core board's main control program and communication protocol architecture; simply reconnect the upgraded expansion board to the core board. Similarly, if the user wants to upgrade the core processor, only a new core board needs to be installed, and the communication protocol deployed within the new main control chip to continue controlling the highly multiplexed hardware circuits on the expansion board. The controller's interface versatility, expansion flexibility, and ease of software and hardware upgrades and maintenance are significantly improved.

[0021] 2. This invention utilizes multiplexed circuits with various topologies, including DI / AI, DO / DI, FI, ADC, DAC, or DO / DI / PWM, to cover the vast majority of sensor signal acquisition and actuator driving requirements in agricultural machinery operations, greatly improving the utilization and flexibility of the hardware physical interface. Through diverse multiplexed circuit designs, the controller can dynamically adapt to various types of external devices without increasing the number and size of physical ports, reducing hardware manufacturing costs and overall power consumption.

[0022] Furthermore, this invention provides a highly reliable hardware implementation scheme for port multiplexing. By utilizing a combination of intelligent high-side switches and logic gate circuits, it not only meets the power output (DO / PWM) requirements of complex actuators in agricultural machinery, but also safely switches them to input acquisition (DI) mode. Combined with the state readback mechanism of the voltage comparator, it can perform real-time closed-loop diagnosis of external port levels in various modes, effectively preventing short-circuit or overload faults in harsh agricultural machinery environments.

[0023] 3. In this invention, the controller ensures the independence and stability of power supply under the multi-core cascade architecture through the power management module; by directly deploying the CAN communication unit on the core board and processing it by the main controller, the communication delay caused by the cascade forwarding of the expansion board is eliminated, ensuring the extremely high real-time performance of the agricultural machinery vehicle bus communication; the indicator light design provides users and maintenance personnel with intuitive low-level and application-level fault diagnosis methods, making it easy to quickly locate problems.

[0024] 4. This invention achieves complete decoupling of software and hardware and hardware abstraction through a resource virtualization mapping method. By separating user logic from the underlying circuit configuration method through mode configuration and status dispatch and monitoring processes, a highly efficient custom resource virtualization mapping method is built between the core board and the expansion board. This resource virtualization mapping method alone can complete the dynamic reconfiguration of underlying electrical characteristics and real-time monitoring of interface status. Furthermore, users only need to perform a series of configurations according to the method to easily use the device, without needing to consider complex underlying configurations, significantly improving cross-platform portability. In addition, the "hierarchical distribution and nested packaged upload" mechanism effectively avoids bus conflicts when multi-level sub-controls report data, ensuring data integrity.

[0025] 5. In this invention, by defining a unified data structure for I / O channel mode configuration frames, working parameter setting frames, and data reporting frames, frame loss and out-of-order issues in complex electromagnetic interference environments of agricultural machinery are effectively prevented; and by setting frame header fields including five types, precise isolation of communication data flow is achieved, so that the interactive communication between the core board and the expansion board and the cascaded communication between the internal control units of the expansion board do not interfere with each other.

[0026] This mechanism perfectly supports the separate design of the core board and expansion board and the virtualization mapping protocol from the bottom layer of the data link, ensuring the universality and robustness of the entire protocol stack. This allows for automatic software and hardware parsing and seamless integration when the core board is replaced or the expansion board is upgraded, simply by using this standard data frame structure. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of an open multi-core controller structure for agricultural machinery according to the present invention; Figure 2 This is a hardware block diagram of an open multi-core controller for agricultural machinery in an embodiment; Figure 3 This is a communication flowchart of the resource virtualization mapping method in the embodiment. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0029] To overcome the shortcomings of rigid hardware resource configuration and tight hardware-software coupling in existing agricultural machinery controllers, this solution provides an open agricultural machinery controller based on a heterogeneous multi-core architecture (STM32 / GD32) and its dynamic virtualization mapping method for I / O resources. In terms of hardware architecture, this solution adopts a physically separated design of a core board and expansion boards. The system includes three microcontroller units (MCUs), which communicate in real time via a board-level asynchronous serial bus. The main processing MCU (GD32F470) is deployed on the core board, running a real-time runtime system conforming to the IEC 61131-3 / IEC 61499 standards, providing users with an environment for application programming, debugging, and downloading based on a PC-based general programming platform. Two coprocessor MCUs (STM32) are deployed on the expansion boards, specifically responsible for controlling the drive logic and multi-modal multiplexing circuits of all underlying electrical interfaces. When using this controller, users only need to configure the functional modes of all physical interfaces at the application layer of the core board through a standardized function library, without needing to concern themselves with underlying register operations and specific electrical switching processes, thus achieving hardware resource virtualization.

[0030] The main advantages of this solution are: 1. It achieves complete decoupling of software and hardware and hardware abstraction, separating user logic from the underlying circuit configuration method, significantly improving cross-platform portability; 2. A highly efficient custom communication mapping protocol is built between the core board and the expansion board. Dynamic reconfiguration of underlying electrical characteristics and real-time monitoring of interface status can be completed simply by following the protocol interaction instructions; 3. It adopts a modular board-to-board connection design. If it is necessary to upgrade the number of controller interfaces or change the driver type in the future, there is no need to change the main control program and communication protocol architecture of the core board. It is only necessary to reconnect the upgraded expansion board to the core board, and the core board can automatically issue the new mode configuration through the protocol. If the user wants to upgrade the core processor, it is only necessary to replace the core board and deploy the communication protocol in the new main control chip to realize the control of the hardware circuit of the expansion board, which greatly reduces the cost of system upgrade and maintenance.

[0031] Example 1 In this embodiment, an open multi-core controller for agricultural machinery is used, as follows: Figure 1 As shown, including The core board module, on which the main control processing unit is deployed, runs the IEC 61131-3 / IEC 61499 standard runtime environment. It is responsible for running all the logic code of agricultural machinery operation and communicates with the expansion board module in real time through virtualization mapping method. The main control processing unit is used to run agricultural machinery operation logic and generate control instructions containing I / O channel mode configuration frames and working parameter setting frames. The expansion board module is electrically connected to the core board module via a connector. The expansion board module includes input / output circuit units and at least two sub-control units; it is responsible for the driver operation and data processing of the underlying interface channel, and receives data from the core board module in real time and sends local data.

[0032] The input / output circuit unit contains several topology multiplexing circuits and physical ports, and each topology multiplexing circuit is connected to a physical port. The sub-control unit is configured to parse control commands and control the state of electronic components in each topology multiplexing circuit according to the parsing results, thereby changing the electrical characteristics of each physical port and realizing dynamic switching of the same physical port between different working modes.

[0033] In this embodiment, the hardware block diagram is as follows: Figure 2As shown, the main control processing unit in the core board module includes the GD32F470IGH6 chip and its basic peripheral circuitry. In the figure, the clock system and storage module are both part of the chip's basic peripheral circuitry. The GD32 runs a real-time core that conforms to the IEC61131-3 / IEC61499 international standards, which is connected to another main control chip via UART. The first sub-control unit includes the STM32F407IGT6 and its basic peripheral circuitry shown in the figure. Figure 2 In the diagram, the storage module and clock system are both basic peripheral circuits of the chip. The second sub-control unit includes the STM32F303ZET6 and its basic peripheral circuits, of which the clock system is its basic peripheral circuit. All circuits and multiplexing circuits in the diagram belong to the input / output circuit units in the expansion board module.

[0034] The core board module includes a main control processing unit; this main control processing unit is connected to the sub-control units in the expansion board module via a serial port connector. The controller also includes a power management module, which connects the main control chip and the sub-control chips to the power management module, and is responsible for supplying power to all modules.

[0035] The controller also includes indicator lights and connectors. The indicator lights are located on the expansion board module and the core board module to indicate the working status of the main control chip, the power management unit, and the various levels of sub-control chips. The connectors are used for the connection between the main control chip and the sub-control chips, the connection between two sub-control chips, and the connection between the controller as a whole and the outside. The connectors are used to power the core board and communicate with the expansion board module in real time when the core board module is connected to the expansion board module.

[0036] The core board module also includes a CAN communication unit for communication between the controller and external devices. The data is directly processed by the main control chip in the core board module. The core board module also has several test points for testing the pins of each channel of the main control chip.

[0037] In this embodiment, the sub-control unit in the expansion board module specifically includes a first sub-control unit and a second sub-control unit; the first sub-control unit includes an STM32F407IGT6 chip as the first sub-control chip, and the basic peripheral circuit of the chip; the first sub-control unit is connected to the main control processing unit through the serial port of the connector, and its other end is connected to the second sub-control unit; The second sub-control unit includes an STM32F303ZET6 main control chip, which serves as the second sub-control chip, and the basic peripheral circuitry of the chip; the second sub-control unit is connected to the first sub-control unit via a serial port of a connector.

[0038] The input / output circuit unit contains several topology multiplexing circuits and underlying electrical interfaces, and each topology multiplexing circuit is connected to a corresponding underlying electrical interface. The topology multiplexing circuit includes DI / AI multiplexing circuit (digital input / analog input multiplexing circuit), DO / DI multiplexing circuit (digital output / digital input multiplexing circuit), FI circuit (frequency input circuit), ADC multiplexing circuit (analog-to-digital conversion multiplexing circuit), DAC circuit (digital-to-analog conversion output circuit), or DO / DI / PWM multiplexing circuit (digital output / digital input / pulse width modulation output multiplexing circuit); among them, the ADC multiplexing circuit includes VI / DI multiplexing circuit (voltage input / digital input multiplexing circuit), CUR / DI multiplexing circuit (current input / digital input multiplexing circuit), and VI / CUR multiplexing circuit (voltage input / current input multiplexing).

[0039] All circuits can be controlled in terms of their operating mode and state through virtualization mapping, and their operating mode and state can be obtained. Furthermore, the operating mode of all multiplexed circuits can be changed through virtualization mapping.

[0040] In this embodiment, the first sub-control chip is connected to the DI / AI multiplexing circuit, the DO / DI multiplexing circuit, the FI circuit, the ADC multiplexing circuit, and the DAC circuit; the second sub-control chip is connected to the DO / DI / PWM multiplexing circuit.

[0041] The input / output circuit unit is the physical foundation for resource virtualization, characterized by its use of a topology multiplexing circuit structure. Taking the PWM / DO / DI multiplexing circuit as an example, this circuit consists of an intelligent high-side switch chip and its peripheral logic gates. The expansion board module's control chip controls the logic combination of the input pin (IN) and diagnostic pin (ST) of this intelligent high-side switch chip, combined with feedback from a parallel voltage comparator, to achieve switching between three physical modes: 1. PWM output mode: The MCU outputs a pulse signal with an adjustable duty cycle to the IN pin to drive the load; 2. DO Output Mode: The MCU outputs a high or low level to the IN pin to achieve switch control; 3. DI Input Mode: The MCU stops outputting (IN is set low), and the circuit detects the level status of the external port through the ST pin and the readback circuit.

[0042] The DI / AI multiplexing circuit controls the MOSFET through the control chip of the expansion board module, thereby controlling the on / off state of the pull-up resistor. When the MOSFET is on, the circuit switches to low effective digital value acquisition; when the MOSFET is off, the circuit switches to voltage acquisition mode (0-5V) or high effective digital value acquisition mode.

[0043] The operating modes of the VI / DI, VI / CUR, and CUR / DI multiplexed circuits are as follows: The VI / DI multiplexing uses a combination of a resistor divider network and a controllable pull-up circuit. In voltage mode, the pull-up circuit is disconnected by the control chip of the expansion board module, and the voltage signal after voltage division is directly acquired. In digital mode, the pull-up circuit is turned on by the control chip of the expansion board module to detect the port level status. The VI / CUR multiplexing is based on a parallel structure of a controllable MOSFET and a sampling resistor. When the MOSFET is turned off by the control chip of the expansion board module, the circuit is in a high-impedance state and the 0-5V voltage is collected. When the MOSFET is turned on by the control chip of the expansion board module, the sampling resistor is connected to convert the 4-20mA current into a voltage signal and collect it after being conditioned by the operational amplifier. CUR / DI multiplexing utilizes the aforementioned current loop characteristics, and similarly uses the expansion board module's control chip and controllable MOSFETs to achieve mode switching.

[0044] This dynamic switching based on circuit topology allows the same physical terminal to switch the working mode of the physical interface in a very short time according to the configuration frame issued by the main control chip of the core board module.

[0045] This solution employs a resource virtualization mapping method. Currently, the best-selling controllers on the market are mainly divided into various PLCs and dedicated controllers based on embedded main control chips. While the former eliminates the need to focus on specific circuit drives and register operations during programming, their upgradeability and scalability are poor. Dedicated controllers based on embedded main control chips are scalable and upgradeable, but users still need to perform complex configurations and write drivers. In this solution, however, the hardware and software layers are connected through a standard communication protocol using a resource virtualization mapping method. Users only need to perform a series of configurations according to the protocol to easily use the system.

[0046] Users can configure the modes of each circuit interface channel through a custom function library without having to consider the complex configuration of the underlying layer. If the underlying circuit structure needs to be upgraded or modified in the future, there is no need to rewrite the upper-level logic. Just configure it according to the original communication protocol to achieve in-situ replacement.

[0047] This solution adopts a separate design for the expansion board and the core board. This separate design conforms to the open controller design concept and achieves optimal allocation of computing resources. The core board only runs logic code, and the expansion board only runs circuit drive code, which greatly improves the control stability and code simplicity of the controller.

[0048] The split design concept allows users to use this controller without worrying about writing the underlying program. They only need to configure the modes of each channel on the core board and use it directly. As an open controller, it must have good scalability. The split design can solve this requirement well. If it is necessary to improve the computing power of the controller, only the core board needs to be updated, and the complex circuits on the expansion board can continue to be used directly.

[0049] Example 2 In this embodiment, a resource virtualization mapping method for an open multi-core controller for agricultural machinery is adopted, which is implemented based on a virtualization mapping system.

[0050] At the software layer, the virtualization mapping system includes the virtualization mapping task program of the main control processing unit in the core board, and also includes the virtualization mapping task programs of the first sub-control unit and the second sub-control unit in the expansion board; at the hardware layer, the controller scheme of Embodiment 1 is the same, the main control processing unit in the core board is connected to the first sub-control unit in the expansion board, and the first sub-control unit is connected to the second sub-control unit.

[0051] In the software layer, the virtualization mapping task program of the main control processing unit in the core board is responsible for configuring the operating modes of all circuits and distributing and monitoring the status of all interface channels. When programming the main control processing unit in the core board on a computer, users only need to call the custom function interface library to perform all mode configurations and status monitoring.

[0052] Figure 3 This is a communication flowchart for the resource virtualization mapping method in this scheme. The implementation process of this resource virtualization mapping method is as follows: First, when the user programs in the computer-based programming environment, they call the custom library functions dedicated to this solution to configure the mode of each channel of the controller. The input and output information of each channel is obtained as needed through the corresponding library. After the controller is powered on, the main control chips of the core board module and the expansion board module will first perform system initialization. After initialization is completed and before the program starts running, the main control chip sub-module of the core board starts sending I / O channel mode configuration frames. When the first sub-control unit in the expansion board receives the mode configuration frame sent by the core board, it will verify and parse the frame content. After parsing, it will complete the local mode configuration and forward the data. When the second sub-control unit in the expansion board receives the expansion board internal mode configuration frame forwarded by the first sub-control unit, it will parse it and perform local mode configuration. After the mode configuration is complete, the system begins operation. The main control processing unit in the core board continuously sends out working parameter setting frames. Upon receiving the working parameters, the first sub-control unit in the expansion board directly forwards the message to the second sub-control unit, then parses the working parameter frame content and updates it to each circuit channel. The second sub-control unit, upon receiving the working parameter setting frame, parses the frame content and updates it to each circuit channel. During normal system operation, the second sub-control unit in the expansion board continuously packages the on / off status of the output channel, the load current detection value of the PWM output channel, and the input value of the input channel into a data reporting frame within the expansion board and sends it to the first sub-control unit. Upon receiving the data, the first sub-control unit packages the on / off status of the output channel and the input value of the input channel into a data reporting frame and sends it to the main control chip on the core board. During normal system operation, the resource virtualization mapping program is scheduled and run as a high-priority task within each main control chip.

[0053] In this embodiment, a custom function interface library is used as an example, specifically including: In the custom function library, the `in_xxx` functions are responsible for acquiring the status of the input channels and initializing them, while the `out_xxx` functions are responsible for acquiring the status of the output channels and initializing them. The `sys_xxx` functions are responsible for reading different system states. In this embodiment, the custom functions are listed in Table 1.

[0054] Table 1 User-defined functions and their functional descriptions During the operation of the main control processing unit in the core board, the resource virtualization mapping task is scheduled and run with the highest priority, continuously updating the status of each channel. The first and second sub-control units in the expansion board both run the FreeRTOS operating system, and both contain resource virtualization mapping tasks. These tasks continuously package and send the status of each interface to the main control processing unit in the core board. This solution achieves hardware and software decoupling, mainly determined by the communication protocol in the resource virtualization mapping system. The communication protocol specifies several frame formats, and by sending different frames, the communication devices clarify the meaning of the information. The specific content of the communication protocol is as follows: All frames include a 2-byte frame header, a 2-byte reporting period, an N-byte payload (N being a positive integer from 1 to 200), and a 1-byte sequence number.

[0055] The frame header includes five types, namely: The first frame header type is an I / O channel mode configuration frame header; The second frame header type is the working parameter setting frame header; Frames with the first frame header type and the second frame header type are used by the core board main control chip to send to the first sub-control unit; The third frame header type is a data reporting frame header. This frame is used by the first sub-control unit to send data to the core board main control chip after summarizing the status of all channels. The fourth frame header type is the expansion board internal mode configuration frame header, which is used by the first sub-control chip in the expansion board to send the working mode frame to the second sub-control chip; The fifth frame header type is an internal data reporting frame of the expansion board, which is used by the second sub-control chip to send the working status of each channel to the first sub-control chip.

[0056] The 2-byte reporting period is used by both parties of the communication chip to define the effective communication period in real time; the N-byte payload is used to store the information of each channel. After the chip receives each frame of data, it extracts the payload in the frame to parse the effective information of each channel; the 1-byte sequence number is used by the receiver to determine whether packet loss occurs during communication. If communication is determined to be abnormal, an alarm program is executed, the controller debugging serial port will output an error code, all output pins of the controller will be reset, and the controller indicator light will turn into a flashing red light.

[0057] The resource virtualization mapping method of the open multi-core controller for agricultural machinery is as follows: Figure 3 As shown, this includes the mode configuration process, status delivery, and monitoring process; The mode configuration process specifically includes the following steps: 1) Power on the controller; 2) The real-time operating system of the main control chip of the controller core board module begins to run; 3) The real-time operation system of the main control processing unit sends out I / O channel mode configuration frames, which are used to send out the working modes of all channels of the controller; 4) The first sub-control chip of the expansion board module receives the circuit operating mode sent by the core board and forwards the mode configuration frame in the expansion board to the second sub-control chip; 5) After receiving the configuration frame, the first and second sub-control chips in the expansion board module parse out the channel ID and target mode. The driver calls the underlying GPIO operations, such as pulling the level of a specific pin high, thereby turning on the MOSFET and other structures in the hardware circuit, changing the impedance characteristics of the physical link, and completing the switch from mode A to mode B.

[0058] The status release and monitoring process specifically includes the following steps: 1) The main control chip of the controller core board module continuously sends out working parameter setting frames, which are used to control parameters such as the level of the digital output channel, the frequency and duty cycle of the PWM output channel, and the voltage of the DAC output channel; 2) The first sub-control chip of the expansion board module receives the working parameter setting frame sent by the core board, parses it, and forwards it to the second sub-control chip; 3) The second sub-control chip of the expansion board module continuously packages the input values ​​of each input channel and the output status of each output channel in the second sub-control unit into a second data reporting frame, and sends the second data reporting frame to the first sub-control chip; 4) In the expansion board module, the first sub-control chip continuously packages the input values ​​of each input channel, the output status of each output channel, and the second data reporting frame in the first sub-control unit into a first data reporting frame. The second data reporting frame continuously updates the input values ​​of each input channel, the circuit on / off status of each output channel, and the load current value of the PWM output channel in the expansion board to the core board.

[0059] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An open-type multi-core controller for agricultural machinery, characterized in that, include: The core board module has a main control processing unit deployed on it. The main control processing unit is used to run agricultural machinery operation logic and generate control instructions containing I / O channel mode configuration frames and working parameter setting frames. The expansion board module is electrically connected to the core board module via a connector. The expansion board module consists of input / output circuit units and a cascaded structure including at least two sub-control units. The input / output circuit unit includes several topology multiplexing circuits and physical ports, and each topology multiplexing circuit is connected to a physical port. The sub-control unit is configured to parse control commands and control the state of electronic components in each topology multiplexing circuit according to the parsing results, thereby changing the electrical characteristics of each physical port and realizing dynamic switching of the same physical port between different working modes.

2. The open multi-core controller for agricultural machinery according to claim 1, characterized in that, The main control processing unit runs a real-time operating core that conforms to the IEC 61131-3 or IEC 61499 standard, and is used to process agricultural machinery operation logic code; The sub-control unit is used to run the underlying interface driver; the main control processing unit and the sub-control unit communicate decoupled through a resource virtualization mapping protocol.

3. The open multi-core controller for agricultural machinery according to claim 1, characterized in that, The aforementioned topology multiplexing circuit includes a DI / AI multiplexing circuit, a DO / DI multiplexing circuit, a FI circuit, an ADC multiplexing circuit, a DAC circuit, or a DO / DI / PWM multiplexing circuit; wherein, the ADC multiplexing circuit includes a VI / DI multiplexing circuit, a CUR / DI multiplexing circuit, and a VI / CUR multiplexing circuit.

4. The open multi-core controller for agricultural machinery according to claim 3, characterized in that, The DO / DI / PWM multiplexing circuit includes an intelligent high-side switch chip, logic gate circuits, and a voltage comparator. The sub-control unit controls the logic combination of the input pins and diagnostic pins of the intelligent high-side switch chip, and combines this with the feedback signal from the voltage comparator to achieve switching between the following three physical modes: In PWM output mode, a pulse signal is output to the input pin; In DO output mode, output a high or low level to the input pin; In DI input mode, the input pin is set low, and the level status of the external port is read back through the diagnostic pin and voltage comparator.

5. The open multi-core controller for agricultural machinery according to claim 1, characterized in that, The controller also includes a power management module, a CAN communication unit, and status indicator lights; The power management module is connected to and supplies power to the main control processing unit and the sub-control units at each level; the CAN communication unit is deployed on the core board module to realize communication between the controller and external devices, and its communication data is directly processed by the main control processing unit. The status indicator lights are installed on the core board module and the expansion board module to indicate the working status of the main control processing unit, the power management module and the various levels of sub-control units in real time.

6. A resource virtualization mapping method for an open multi-core controller for agricultural machinery, characterized in that, The method is applied to an open multi-core controller for agricultural machinery as described in any one of claims 1-5, and the method includes: Mode configuration process: The main control processing unit of the core board module sends out the I / O channel mode configuration frame. The cascaded sub-control units in the expansion board module parse the I / O channel mode configuration frame and drive the corresponding topology multiplexing circuit to complete the virtualization mapping of the electrical characteristics of each physical port. Status sending and monitoring process: The main control processing unit sends out working parameter setting frames. Each level of sub-control unit in the expansion board module executes the output control of the corresponding channel according to the parsing result of the working parameter setting frames, and packages the status feedback data of each physical port in a cascaded reverse order to form a data reporting frame. Finally, the data reporting frame is uploaded to the main control processing unit.

7. The resource virtualization mapping method for an open multi-core controller for agricultural machinery according to claim 6, characterized in that, The mode configuration process specifically includes: The main control processing unit of the core board module runs a real-time operating system, generating and sending out the I / O channel mode configuration frame containing the mapping relationship between several physical port IDs and target working modes; Each level of sub-control unit in the expansion board module receives the I / O channel mode configuration frame, parses out the physical port ID belonging to its level and its corresponding target working mode, and forwards the remaining configuration information to the next level sub-control unit in cascading order; Each level of the sub-control unit controls the state of the electronic components in the corresponding topology multiplexing circuit according to the target working mode, thereby changing the electrical characteristics of each physical port and realizing the dynamic switching of the same physical port between different working modes.

8. The resource virtualization mapping method for an open multi-core controller for agricultural machinery according to claim 6, characterized in that, The aforementioned status issuance and monitoring process specifically includes: The main control processing unit of the core board module periodically sends out working parameter setting frames, and the sub-control units at each level in the expansion board module forward them down level by level in cascade order, and execute the output control of the corresponding channel according to the working parameter setting frames; Except for the top-level sub-control unit in the cascade structure, each level of sub-control unit collects the input values ​​of each input channel and the output status of each output channel within its jurisdiction, encapsulates them into data reporting frames, and sends them to the next level of sub-control unit. The top-level sub-control unit in the cascade structure nests and packages the input values ​​and output status collected at this level with the received data reporting frames to generate a complete data reporting frame. This complete data reporting frame is then uploaded to the main control processing unit of the core board module to update the monitoring data of each physical port in the expansion board module in real time.

9. The resource virtualization mapping method for an open multi-core controller for agricultural machinery according to claim 6, characterized in that, The data structures of the I / O channel mode configuration frame, working parameter setting frame, and data reporting frame all include: a 2-byte frame header field, a 2-byte reporting period field, an N-byte payload field, and a 1-byte sequence number field.

10. The resource virtualization mapping method for an open multi-core controller for agricultural machinery according to claim 9, characterized in that, The frame header fields include five types, specifically defined as follows: The first frame header type configures the frame header for I / O channel mode; The second frame header type sets the frame header for working parameters; The first frame header type and the second frame header type are used in the communication frames sent by the main control processing unit to the sub-control unit at the top level of the cascaded structure; The third frame header type is the core board data reporting frame header, which is used in the communication frames sent from the top-level sub-control unit to the main control processing unit in the cascaded structure. The fourth frame header type is the frame header for configuring the mode within the expansion board, used in the communication frames sent from the upper-level sub-control unit to the lower-level sub-control unit within the expansion board module; The fifth frame header type is the data reporting frame header within the expansion board, used in communication frames sent from the lower-level sub-control unit to the upper-level sub-control unit within the expansion board module.

Images