Debugging system, debugging method and medium for ai chip

Abstract

This application provides a debugging system, debugging method, and medium for AI chips. The debugging system includes: multiple first debugging distribution units, each first debugging distribution unit located within one of multiple AI cores, and includes: a first interface selection unit, comprising: a first interface for receiving a first debugging address and debugging data from a host outside the AI ​​chip; a second interface for receiving a second debugging address from an internal register of the AI ​​core, wherein the type of the second interface is different from the first interface; a first selection unit for selecting one of the first and second debugging addresses; and a first address mapping unit configured to: locate the functional module corresponding to the selected debugging address among multiple functional modules within the AI ​​core; and distribute the first debugging address and debugging data to the located functional module.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence (AI) technology, and specifically to debugging systems, debugging methods, and computer-readable storage media for AI chips. Background Technology

[0002] In recent years, the market demand for AI chips has continued to grow, especially the design and application of heterogeneous multi-core architecture AI chips have become more and more widespread, and the importance of chip debugging in the development, verification and mass production of AI chips has become increasingly prominent.

[0003] Current debugging techniques for heterogeneous multi-core AI chips generally employ dedicated debugging architectures independent of the AI ​​cores to collect and control the operational status of each AI core. These techniques typically require configuring dedicated debugging interfaces for AI cores from different manufacturers and of different types, making it difficult to establish a unified and efficient debugging mechanism. Summary of the Invention

[0004] In one aspect, embodiments of this application provide a debugging system for an AI chip, the AI ​​chip including multiple AI cores. The debugging system includes: multiple first debugging distribution units, each first debugging distribution unit located within one of the multiple AI cores, including: a first interface selection unit, including: a first interface for receiving a first debugging address and debugging data, the first debugging address and debugging data originating from a host outside the AI ​​chip; a second interface for receiving a second debugging address, the second debugging address originating from an internal register of the AI ​​core, wherein the type of the second interface is different from the first interface; a first selection unit for selecting one of the first and second debugging addresses; and a first debugging address mapping unit configured to: locate the functional module corresponding to the selected debugging address among multiple functional modules within the AI ​​core based on the selected debugging address; and distribute the first debugging address and debugging data to the located functional module.

[0005] In another aspect, embodiments of this application provide a debugging method for an AI chip, the AI ​​chip including multiple AI cores. The method includes: receiving a first debugging address and debugging data through a first interface, the first debugging address and debugging data coming from a host outside the AI ​​chip; receiving a second debugging address through a second interface, the second debugging address coming from an internal register of one of the multiple AI cores, wherein the type of the second interface is different from the first interface; selecting one of the first and second debugging addresses through a first selection unit; locating the functional module corresponding to the selected debugging address among multiple functional modules within the AI ​​core based on the selected debugging address through a first debugging address mapping unit; and distributing the first debugging address and debugging data to the located functional module.

[0006] In another aspect, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements a debugging method for an AI chip according to embodiments of this application. Attached Figure Description

[0007] The various aspects of this disclosure are best understood through the following detailed description when read in conjunction with the accompanying drawings. It should be understood that the drawings are for illustrative and descriptive purposes only and not for limiting purposes.

[0008] Figures 1-3 This is a block diagram of a debugging system for an AI chip according to an embodiment of this application.

[0009] Figure 4 This is a flowchart of a debugging method for an AI chip according to an embodiment of this application.

[0010] Figure 5 This is an application diagram of a debugging system for AI chips according to an embodiment of this application.

[0011] Figure 6 According to the embodiments of this application, regarding Figure 5 A schematic diagram of the information flow of the processing engine.

[0012] Figure 7 This is a schematic block diagram of a computing device that implements a debugging system for an AI chip according to an embodiment of this application. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not limiting.

[0014] As mentioned above, current debugging techniques for heterogeneous multi-core AI chips often require additional debugging circuitry, which significantly increases the hardware overhead and power consumption of the AI ​​chip. Furthermore, current debugging techniques also require dedicated interfaces for different AI cores, further increasing hardware design complexity and implementation costs.

[0015] In view of this, this application proposes a debugging system, debugging method and computer-readable storage medium for AI chips, which eliminates the need for additional independent debugging circuits, reduces chip area and power consumption, and is compatible with different types of interfaces, thereby improving versatility and adaptability.

[0016] Figures 1-3 This is a block diagram of a debugging system for an AI chip according to an embodiment of this application. Figure 1As shown, the AI ​​chip 101 can be a heterogeneous architecture including multiple AI cores (two cores, core 1 and core 2, are shown as an example in the figure). A debugging system 100 for an AI chip according to an embodiment of this disclosure includes: a plurality of first debugging distribution units 102, each first debugging distribution unit 102 located within one of the plurality of AI cores. Figure 1 The diagram uses core 1 as an example for illustration. The configuration of other cores can be the same as core 1, and will not be repeated here.

[0017] The first debug distribution unit 102 includes: a first interface selection unit 1021 and a first address mapping unit 1022.

[0018] The first interface selection unit 1021 includes: a first interface 10211 for receiving a first debug address and debug data, the first debug address and debug data coming from a host 103 outside the AI ​​chip; a second interface 10212 for receiving a second debug address, the second debug address coming from an internal register of the AI ​​core (e.g., the Control and Status Register CSR shown in the figure), wherein the type of the second interface is different from the first interface; and a first selection unit 10213 configured to select one of the debug addresses from the first debug address and the second debug address.

[0019] The first address mapping unit 1022 is configured to: locate the functional module corresponding to the selected debugging address among multiple functional modules within the AI ​​core (two functional modules, functional module 1 and functional module 2, are shown in the figure as examples) based on the selected debugging address; and distribute the first debugging address and debugging data to the located functional module.

[0020] According to the debugging system of this application embodiment, by setting the first debugging distribution unit in the AI ​​core, it can receive two types of debugging addresses from the host and the internal registers of the AI ​​core. It can reuse the same set of address mapping units to complete the location of functional modules in the AI ​​core and the distribution of debugging data. There is no need to configure an independent debugging circuit, which effectively reduces chip area and power consumption, and improves the compatibility and execution efficiency of heterogeneous multi-core AI chip debugging.

[0021] In some implementations, such as Figure 2 As shown, the debugging system 100 may also include a plurality of second debugging distribution units 104, each of which is located within one of the plurality of functional modules. Figure 2 The illustration uses functional module 1 as an example. The configuration of other functional modules can be the same as that of functional module 1, and will not be repeated here.

[0022] The second debugging distribution unit 104 includes: a second interface selection unit 1041 and a second address mapping unit 1042.

[0023] The second interface selection unit 1041 includes: a third interface 10411 for receiving a first debug address and debug data; a fourth interface 10412 for receiving a third debug address, the third debug address being from an internal register of a functional module (e.g., the Control and Status Register CSR shown in the figure), wherein the type of the fourth interface is different from that of the third interface; and a second selection unit 10413 configured to select one of the debug addresses from the first debug address and the third debug address.

[0024] The second address mapping unit 1042 is configured to: locate the processing engine corresponding to the selected debugging address among multiple processing engines within the functional module (two processing engines, processing engine 1 and processing engine 2, are shown as examples in the figure); and distribute the first debugging address and debugging data to the located processing engine.

[0025] By setting the second debug distribution unit within the functional module, it can receive two types of debug addresses from the first debug distribution unit and the internal registers of the functional module. The same set of address mapping units can be reused to complete the location of the processing engine and the distribution of debug data within the functional module. There is no need to configure an independent debug circuit, which effectively reduces chip area and power consumption, and improves the compatibility and execution efficiency of heterogeneous multi-core AI chip debugging.

[0026] In some implementations, such as Figure 3 As shown, the debugging system 100 may further include a third debugging distribution unit 105, located outside the AI ​​chip 101. The third debugging distribution unit 105 includes a fifth interface 1051 and a positioning unit 1052. The fifth interface 1051 is used to receive a first debugging address and debugging data from the host 103. The positioning unit 1052 is used to locate the AI ​​core among multiple AI cores based on the first debugging address (core 1 is used as an example in the figure) and to transmit the first debugging address and debugging data to the first debugging distribution unit (specifically the first interface 10211) of the located AI core. By setting the third debugging distribution unit 105, the host 103 can directly select and route a specific AI core, realizing chip-level debugging routing, avoiding interference between multiple cores, and improving the flexibility and controllability of debugging heterogeneous multi-core AI chips.

[0027] In some implementations, the first interface 10211, the third interface 10411, and the fifth interface 1051 are interfaces compliant with the Joint Test Action Group (JTAG) specification, while the second interface 10212 and the fourth interface 10412 are interfaces compliant with the RISC-V Vector Extensions (RVV) specification. Adopting standardized JTAG / RVV interfaces eliminates the need for customized interfaces for different cores, significantly improving the versatility, scalability, and debugging efficiency of heterogeneous multi-core AI chip debugging.

[0028] In some implementations, the second address mapping unit 1042 is further configured to: obtain the native state information of the located processing engine based on the address-native state information mapping table stored in the internal register (e.g., the control and status register area CSR) of the functional module, wherein the address-native state information mapping table contains the correspondence between the addresses of all processing engines in the functional module and the native state information of each processing engine; determine whether the debug address used to locate the located processing engine is a first debug address or a third debug address; and transmit the obtained native state information of the located processing engine to the first debug distribution unit 102 or the internal register of the functional module via the interfaces corresponding to the debug address used to locate the located processing engine in the third interface 10411 and the fourth interface 10412.

[0029] In some implementations, the first address mapping unit 1022 is further configured to: obtain the native state information of the located functional module based on the address-native state information mapping table stored in the internal register of the AI ​​core, wherein the address-native state information mapping table contains the correspondence between the addresses of all functional modules in the AI ​​core and the native state information of each functional module; determine whether the debug address used to locate the AI ​​core 1 is a first debug address or a second debug address; and transmit the obtained native state information of the located functional module to the third debug distribution unit 105 or the internal register of the AI ​​core via the interfaces corresponding to the debug address used to locate the AI ​​core in the first interface 10211 and the second interface 10212.

[0030] The address-native state information mapping table allows for direct and rapid matching and retrieval of native state information for the processing engine and functional modules, eliminating the need for additional queries or conversions and improving state reading efficiency. Furthermore, it automatically selects the corresponding interface for backhaul based on the debug address source, reusing existing debug loops to upload data to the host level by level, without requiring additional hardware or pins, thus saving chip area and power consumption. Native state information can be uniformly collected and transmitted in both internal and external debug modes, enabling end-to-end state monitoring and significantly improving the convenience and reliability of debugging heterogeneous multi-core AI chips.

[0031] In some implementations, the positioning unit 1052 is also configured to transmit the native state information from the first debugging distribution unit 102 to the host 103 via the fifth interface 1051.

[0032] In some implementations, the native state information of each processing engine includes operational information generated during normal operation and exception information when each processing engine malfunctions. By unifying the abnormal and normal operation information into the native state information, the exception information can be transmitted back step by step through the debugging loop. This allows for comprehensive collection of the processing engine's operational status and rapid reporting of exceptions without adding extra hardware or transmission paths, significantly improving the speed of exception location and the reliability of debugging.

[0033] The debugging system according to the embodiments of this application adopts a three-level debugging distribution unit and a dual-type interface architecture, which can realize multi-level debugging addressing from the host to the AI ​​core, functional modules and then to the processing engine. It is compatible with internal and external bidirectional debugging addresses and supports unified scheduling and flexible switching. By quickly locating the target and transmitting back running and abnormal status information through the address-native status information mapping table, there is no need to add dedicated debugging circuits, effectively reducing chip area and power consumption.

[0034] Figure 4 A flowchart illustrating a debugging method for an AI chip according to an embodiment of this disclosure is shown. Figure 4 As shown, the debugging method 400 for an AI chip according to an embodiment of the present disclosure includes steps S401-S404.

[0035] In step S401, a first debug address and debug data are received through a first interface. The first debug address and debug data come from a host outside the AI ​​chip.

[0036] At step S402, a second debug address is received through a second interface. The second debug address comes from the internal register of an AI core among multiple AI cores, and the type of the second interface is different from that of the first interface.

[0037] In step S403, a debug address is selected from the first debug address and the second debug address by the first selection unit.

[0038] In step S404, the first address mapping unit locates the functional module corresponding to the selected debugging address among multiple functional modules within the AI ​​core based on the selected debugging address, and distributes the first debugging address and debugging data to the located functional module.

[0039] The above debugging method can be provided by Figure 1 The first debug distribution unit 102 in the debug system 100 shown is executed. The first interface, the second interface, the first selection unit, and the first address mapping unit correspond to the reference. Figure 1 The first interface 10211, the second interface 10212, the first selection unit 10213, and the first address mapping unit 1022 are shown.

[0040] In some implementations, the debugging method 200 may further include: receiving a first debugging address and debugging data through a third interface; receiving a third debugging address through a fourth interface, the third debugging address being from an internal register of the functional module, wherein the type of the fourth interface is different from that of the third interface; selecting one of the debugging addresses from the first and third debugging addresses through a second selection unit; and locating the processing engine corresponding to the selected debugging address among multiple processing engines within the functional module based on the selected debugging address through a second address mapping unit; and distributing the first debugging address and debugging data to the located processing engine.

[0041] The above debugging method can be provided by Figure 2 The second debug distribution unit 104 in the debug system 100 shown is executed. The third interface, the fourth interface, the second selection unit, and the second address mapping unit correspond to the reference respectively. Figure 2 The third interface 10411, the fourth interface 10412, the second selection unit 10413, and the second address mapping unit 1042 are shown.

[0042] In some implementations, the debugging method 200 may further include: receiving a first debugging address and debugging data from the host through a fifth interface; locating a specific AI core among multiple AI cores based on the first modulation address through a positioning unit, and transmitting the first debugging address and debugging data to the first debugging distribution unit of the located AI core.

[0043] The above debugging method can be provided by Figure 3 The third debugging distribution unit 105 in the debugging system 100 shown is executed. The fifth interface and the positioning unit correspond to the reference respectively. Figure 3 The fifth interface 1051 and the positioning unit 1052 are shown.

[0044] In some implementations, the debugging method 200 may further include: obtaining the native state information of the located processing engine through a second address mapping unit based on an address-native state information mapping table stored in the internal register of the functional module, wherein the address-native state information mapping table contains the correspondence between the addresses of all processing engines in the functional module and the native state information of each processing engine; determining whether the debugging address used to locate the located processing engine is a first debugging address or a third debugging address; and transmitting the obtained native state information of the located processing engine to a first debugging distribution unit or the internal register of the functional module via the third interface and the fourth interface corresponding to the debugging address used to locate the located processing engine.

[0045] In some implementations, the debugging method 200 may further include: obtaining the native state information of the located functional module through a first address mapping unit based on an address-native state information mapping table stored in the internal register of the AI ​​core, wherein the address-native state information mapping table contains the correspondence between the addresses of all functional modules in the AI ​​core and the native state information of each functional module; determining whether the debugging address used to locate the AI ​​core is a first debugging address or a second debugging address; and transmitting the obtained native state information of the located functional module to a third debugging distribution unit or the internal register of the AI ​​core via the interface corresponding to the debugging address used to locate the AI ​​core in the first interface and the second interface.

[0046] In some implementations, the debugging method 200 may also include: transmitting the native state information from the first debugging distribution unit to the host via the fifth interface through the positioning unit.

[0047] In some implementations, the native state information of each processing engine includes the runtime information generated when each processing engine is running normally, as well as the exception information when each processing engine malfunctions.

[0048] The debugging method according to the embodiments of this application can realize multi-level debugging addressing from the host to the AI ​​core, functional modules and then to the processing engine, and is compatible with internal and external bidirectional debugging addresses, supporting unified scheduling and flexible switching. It quickly locates the target and transmits back running and abnormal status information through an address-native state information mapping table, eliminating the need for additional dedicated debugging circuits and effectively reducing chip area and power consumption.

[0049] Figure 5 This is an application diagram of a debugging system for AI chips according to an embodiment of this application. Figure 5 As shown, the AI ​​chip 101 includes, for example, four AI cores (core 0 is shown as an example in the figure). 3). Core 0 includes multiple functional modules, such as... Figure 5 As shown, there are four processing elements PE0-PE3, an inter-core communication module C2C, an instruction decoding unit (IDU), a write-back controller (WBC), and a direct data memory access module (DDMA). Core 1 Each of 3 includes multiple functional modules, such as Figure 5 As shown, four processing elements PE0 PE3, Write-back Controller Module (WBC), and Direct Data Memory Access Module (DDMA).

[0050] The debugging system 100 includes multiple first debugging distribution units 102 (exemplarily shown in the figure, which are related to core 0). The four first debugging and distribution units 102 corresponding to core 3 are located within each AI core and connected to multiple functional modules within each core. The following detailed explanation uses core 1 as an example.

[0051] The first debug distribution unit 102 receives a first debug address (i.e., debug bus address debug_bus_addr) and debug data (i.e., debug bus data debug_bus_data) through a first interface. The first debug address and debug data come from a host outside the AI ​​chip 101 (not shown in the figure). It receives a second debug address through a second interface. The second debug address comes from the Control and Status Register (CSR) of the AI ​​core 1. The type of the second interface is different from that of the first interface (e.g., the first interface is an interface conforming to the Joint Test Action Group (JTAG) specification, and the second interface is an interface conforming to the RISC-V Vector Extension (RVV) specification). It selects one of the debug addresses from the first debug address and the second debug address through a first selection unit. It locates the functional module corresponding to the selected debug address among multiple functional modules in the AI ​​core 1 based on the selected debug address (e.g., locating the processing element PE3) and distributes the first debug address and debug data to the located functional module.

[0052] The debugging system 100 also includes a plurality of second debugging distribution units 104, located within each functional module and connected to a plurality of processing engines within each functional module (the figure exemplarily shows the second debugging distribution unit 104 corresponding to the processing element PE3 and the plurality of processing engines 0 within the processing element PE3). n).

[0053] The second debug distribution unit 104 receives a first debug address (i.e., debug bus address debug_bus_addr) and debug data (i.e., debug bus data debug_bus_data) through a third interface; it receives a second debug address through a fourth interface, the second debug address being from the Control and Status Register (CSR) of the processing element PE3, wherein the type of the third interface is different from that of the fourth interface (for example, the third interface is an interface conforming to the Joint Test Action Group (JTAG) specification, and the fourth interface is an interface conforming to the RISC-V Vector Extension (RVV) specification); it selects one of the debug addresses from the first debug address and the third debug address through a second selection unit; it locates the processing engine corresponding to the selected debug address among multiple processing engines within the processing element PE3 based on the selected debug address through a second address mapping unit, and distributes the first debug address and debug data to the located processing engine.

[0054] Figure 6 According to the embodiments of this application, regarding Figure 5 A schematic diagram of the information flow in the processing engine. (Example) Figure 6The information flow 600 shown above, at the upper-layer processing element PE, the multiplexer MUX-1 receives the first address i_debug_bus_addr from the upper-layer core of the processing element and the second address i_debug_csr_addr from the control and status register CSR of the core. In the example shown in the figure, the first address, such as the debug address [20:16], is selected according to the instruction i_debug_bus_en (the most significant bit of the first address is valid, for example, it can be set to "1"), pointing to the processing element PE3.

[0055] At processing engine 0, multiplexer MUX-2 receives the first address i_debug_bus_addr from the upper-layer processing element PE and the third address i_debug_csr_addr from the status and control register (CSR) of that processing element. In the example shown in the figure, the third address, such as debug address [15:0], is selected according to the instruction i_debug_csr_en (the most significant bit of the second address is valid, for example, it can be set to "1"), pointing to processing engine 0. Processing engine 0 performs its intended functions and stores various normal operation information and exception information in registers 0. In n, native state information is provided via multiplexer MUX-3. This native state information is then provided to multiplexer MUX-4 and subsequently stored in the status and control register (CSR) of the processing element PE3. Native state information can also be provided to multiplexer MUX-5, which in turn provides it to the corresponding debug bus (debug_bus), and finally to the host via the third debug distribution unit 105. It should be understood that although in Figure 6 The native state information is provided to multiplexers MUX-4 and MUX-5 via two paths. This is for illustrative purposes only. In practice, the native state information is provided to one of multiplexers MUX-4 and MUX-5 only via the interface from which the address of the location processing engine 0 comes.

[0056] from Figure 6 As can be seen, in the debugging system of this application embodiment, each level of debugging distribution unit can be constructed using a multiplexer (MUX). For example, the second debugging distribution unit 104 can be implemented using multiplexers MUX-2 and MUX-4; the first debugging distribution unit 102 can be implemented using multiplexers MUX-1 and MUX-5. For the remaining processing engines 1 to n, their hardware architecture and debugging access process are consistent with those of the aforementioned processing engine 0, and will not be repeated.

[0057] Furthermore, multiple processing engines within the same module share the multiplexer resources corresponding to the second debugging and distribution unit; various functional modules within the same AI core share the multiplexer resources corresponding to the first debugging and distribution unit, eliminating the need to configure independent debugging selection and distribution hardware for each module and each engine.

[0058] The control system according to the embodiments of this application can complete the reception, selection, hierarchical distribution and address addressing of dual-interface debugging addresses by configuring a multiplexer, without the need for additional complex control logic, dedicated status acquisition circuits and independent debugging transmission paths; relying on the N-to-1 selection characteristic of the multiplexer, it is compatible with the address access and dynamic switching of the JTAG debugging interface and the RVV-CSR debugging interface, and reuses a unified distribution architecture and data return path. While realizing multi-mode debugging adaptation of heterogeneous AI chips, it greatly simplifies the hardware structure and reduces chip area overhead and wiring resource occupation.

[0059] According to an embodiment of this application, a computer-readable storage medium is also provided, on which a computer program is stored. When the computer program is executed by a processor, it implements the debugging method for an AI chip according to an embodiment of this application.

[0060] Figure 7 This is a schematic block diagram of a computing device implementing an embodiment of this application. For example... Figure 7 As shown, computing device 700 includes a bus 702, a processor 704, main memory 706, storage device 708, and network interface 710. Specifically, as shown, computing device 700 may include a bus 702 or other communication mechanism for transmitting information, and one or more processors 704 coupled to the bus 702 for processing information. The one or more processors 704 may include, for example, one or more general-purpose microprocessors.

[0061] like Figure 7As shown, in some implementations, computing device 700 may further include main memory 706 coupled to bus 702. Main memory 706 is used to store information and instructions executed by one or more processors 704, such as random access memory (RAM), cache, and / or other dynamic storage devices. Main memory 706 may also be used to store temporary variables or other intermediate information during the execution of instructions executed by one or more processors 704. When these instructions are stored in storage media accessible to one or more processors 704, they can cause computing device 700 to become a dedicated machine customized to perform the operations specified in the instructions. Storage device 708 may include non-volatile and / or volatile storage media. Non-volatile storage media may include, for example, optical discs or magnetic disks. Volatile storage media may include dynamic memory. Common forms of storage media may include, for example, floppy disks, hard disks, solid-state drives, magnetic tape, or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a perforated pattern, RAM, DRAM, PROM, and EPROM, FLASH-EPROM, NVRAM, any other memory chip or cartridge, or their networking versions.

[0062] like Figure 7 As shown, in some embodiments, computing device 700 may further include one or more communication interfaces or network interfaces 710 coupled to bus 702. Network interface 710 may provide bidirectional data communication coupling to one or more network links connected to one or more networks. As another example, network interface 710 may be a local area network (LAN) card to provide data communication connectivity to a LAN-compatible (or WAN component communicating with a WAN) network. Wireless links may also be implemented.

[0063] The execution of certain operations can be distributed across processors rather than residing within a single machine, but rather deployed across multiple machines. In some example embodiments, the processor or processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other example embodiments, the processor or processor-implemented engine may be distributed across multiple geographic locations.

[0064] Each of the processes, methods, and algorithms described in the preceding sections may be embodied in code modules executed by one or more computer systems or computer processors including computer hardware, and may be fully or partially automated by these code modules. The processes and algorithms may be implemented, partially or fully, in dedicated circuit systems.

[0065] When the functions disclosed herein are implemented as software functional units and sold or used as stand-alone products, they may be stored in a processor-executable, non-volatile, computer-readable storage medium. Specific technical solutions (all or part) disclosed herein, or aspects contributing to the prior art, may be embodied in the form of a software product. The software product may be stored in a storage medium and includes several instructions that cause a computing device (which may be a personal computer, server, network device, etc.) to perform all or some steps of the methods of the embodiments of this application. The storage medium may include a flash drive, portable hard disk drive, ROM, RAM, magnetic disk, optical disk, other media operable to store program code, or any combination thereof.

[0066] According to embodiments of this application, a system is provided that includes a processor and a non-transitory computer-readable storage medium storing instructions, which are executable by the processor to cause the system to perform operations corresponding to steps in any method of the embodiments disclosed above. According to embodiments of this application, a non-transitory computer-readable storage medium or computer program product storing instructions, which are executable by one or more processors to cause the one or more processors to perform operations corresponding to steps in any method of the embodiments disclosed above.

[0067] The various features and processes described above can be used independently of each other or combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure. Additionally, certain method or process blocks may be omitted in some embodiments. The methods and processes described herein are not limited to any particular order, and their associated blocks or states may be executed in other suitable orders. For example, described blocks or states may be executed in an order other than that specifically disclosed, or multiple blocks or states may be combined into a single block or state. Example blocks or states may be executed sequentially, in parallel, or in some other manner. Certain blocks or states may be added to or removed from the disclosed example embodiments. The exemplary systems and components described herein may be configured differently than described. For example, certain components may be added to, removed from, or rearranged compared to the disclosed example embodiments.

[0068] The various operations of the exemplary methods described herein can be performed at least in part by an algorithm. The algorithm may be included in program code or instructions stored in memory (e.g., the aforementioned non-transitory computer-readable storage medium). This algorithm may include a machine learning algorithm. In some embodiments, the machine learning algorithm may not explicitly turn the computer into an execution function but may learn from training data to produce a predictive model of the execution function.

[0069] The various operations of the exemplary methods described herein can be performed, at least in part, by one or more processors that are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, these processors can constitute an engine of processor implementation that operates to perform one or more of the operations or functions described herein.

[0070] Similarly, the methods described herein may be implemented at least in part by a processor, wherein one or more specific processors are instances of hardware. For example, at least some operations of the methods may be performed by one or more processors or an engine implemented by a processor. Furthermore, one or more processors may also be operable to support the execution of relevant operations in a “cloud computing” environment or as the execution of relevant operations in a “Software as a Service” (SaaS) context. For example, at least some operations may be performed by a group of computers (as an example of a machine containing processors), wherein these operations are accessible via a network (e.g., the Internet) and via one or more appropriate interfaces (e.g., application programming interfaces (APIs)).

[0071] In this specification, although individual operations of one or more methods are illustrated and described as separate operations, one or more of these individual operations may be performed simultaneously, and not necessarily in the order illustrated. Structures and functions presented as separate components in the example configurations may be implemented as composite structures or components. Similarly, structures and functions presented as single components may be implemented as single components. These and other variations, modifications, additions, and improvements fall within the scope of this document. Therefore, this specification and its drawings should be considered illustrative rather than restrictive.

[0072] As used herein, “or” is inclusive rather than exclusive unless explicitly indicated by the context. Therefore, in this document, “A, B, or C” means “A, B, A and B, A and C, B and C, or A, B, and C” unless explicitly indicated by the context. Furthermore, “and” is combined and separate unless explicitly indicated by the context. Therefore, in this document, “A and B” means “A and B, combined or separate” unless explicitly indicated by the context.

[0073] The terms “comprising” or “including” are used to indicate the presence of a subsequently claimed feature, but do not exclude the presence of other features. Unless otherwise specifically stated or otherwise understood in the context in which they are used, conditional language such as “may,” “can,” “may,” and “can” is generally intended to convey that certain embodiments include certain features, components, and / or steps that are not included in other embodiments. Therefore, this conditional language is generally not intended to imply that one or more embodiments necessarily require a certain feature, component, and / or step in any way, or that one or more embodiments must include such features, components, and / or steps.

[0074] Although the general outline of the subject matter has been described with reference to specific exemplary embodiments, various modifications and changes may be made to these embodiments without departing from the broad scope of embodiments of this disclosure. Where more than one embodiment is disclosed, these embodiments of the subject matter may be referred to individually or collectively herein as the term "invention," this is for convenience only and is not intended to automatically limit the scope of this application to any single disclosure or concept.

[0075] The embodiments illustrated herein are described in detail to enable those skilled in the art to practice the disclosed teachings. Other embodiments may be used and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. Therefore, the term "implementation" is not intended to be limiting, and the scope of the various embodiments is defined only by the appended claims and their equivalents.

Claims

1. A debugging system for an AI chip, the AI ​​chip comprising multiple AI cores, characterized in that, The debugging system includes: Multiple first debug distribution units, each located within one of the multiple AI cores, including: The first interface selection unit includes: The first interface is used to receive a first debug address and debug data, wherein the first debug address and debug data come from a host outside the AI ​​chip; A second interface is used to receive a second debug address, which originates from the internal registers of the AI ​​core, wherein the type of the second interface differs from that of the first interface; and The first selection unit is configured to select one of the debug addresses from the first debug address and the second debug address; and The first address mapping unit is configured as follows: Based on the selected debugging address, locate the functional module within the AI ​​core that corresponds to the selected debugging address; and The first debugging address and the debugging data are distributed to the located functional modules.

2. The debugging system according to claim 1, characterized in that, The debugging system further includes multiple second debugging distribution units, each of which is located within one of the multiple functional modules, including: The second interface selection unit includes: The third interface is used to receive the first debugging address and the debugging data; A fourth interface is used to receive a third debug address, which originates from the internal register of the functional module, wherein the type of the fourth interface differs from that of the third interface; and The second selection unit is configured to select one of the debug addresses from the first debug address and the third debug address; and The second address mapping unit is configured as follows: Based on the selected debug address, locate the processing engine corresponding to the selected debug address among multiple processing engines within the functional module; and The first debug address and the debug data are distributed to the located processing engine.

3. The debugging system according to claim 2, characterized in that, The debugging system also includes: A third debug distribution unit, located outside the AI ​​chip, includes: The fifth interface is used to receive the first debugging address and the debugging data from the host; The positioning unit is used to locate the AI ​​core among the plurality of AI cores based on the first debugging address, and transmit the first debugging address and the debugging data to the first debugging distribution unit of the located AI core.

4. The debugging system according to claim 3, characterized in that, The first interface, the third interface, and the fifth interface are interfaces compliant with the Joint Test Action Group (JTAG) specification, and the second interface and the fourth interface are interfaces compliant with the RISC-V Vector Extension (RVV) specification.

5. The debugging system according to claim 3, characterized in that, The second address mapping unit is also configured as follows: Based on the address-native state information mapping table stored in the internal registers of this functional module, the native state information of the located processing engine is obtained. This address-native state information mapping table contains the correspondence between the addresses of all processing engines in this functional module and the native state information of each processing engine. Determine whether the debug address used to locate the located processing engine is the first debug address or the third debug address; as well as The acquired native state information of the located processing engine is transmitted to the first debug distribution unit or the internal register of the functional module via the third interface and the fourth interface, which correspond to the debug address used to locate the located processing engine.

6. The debugging system according to claim 5, characterized in that, The first address mapping unit is further configured as follows: Based on the address-native state information mapping table stored in the internal registers of the AI ​​core, the native state information of the located functional module is obtained. The address-native state information mapping table contains the correspondence between the addresses of all functional modules in the AI ​​core and the native state information of each functional module. Determine whether the debug address used to locate the AI ​​core is the first debug address or the second debug address; as well as The acquired native state information of the located functional module is transmitted to the third debug distribution unit or the internal register of the AI ​​core via the first interface and the second interface corresponding to the debug address used to locate the AI ​​core.

7. The debugging system according to claim 6, characterized in that, The positioning unit is further configured to: The native state information from the first debug distribution unit is transmitted to the host via the fifth interface.

8. The debugging system according to claim 5, characterized in that, The native state information of each processing engine includes the running information generated when each processing engine is running normally and the abnormal information when each processing engine is running abnormally.

9. A debugging method for an AI chip, the AI ​​chip comprising multiple AI cores, characterized in that, The method includes: The first debugging address and debugging data are received through the first interface, and the first debugging address and debugging data come from a host outside the AI ​​chip; A second debug address is received through a second interface, the second debug address comes from the internal register of one of the plurality of AI cores, wherein the type of the second interface is different from the first interface; The first selection unit selects one of the debugging addresses from the first debugging address and the second debugging address; The first address mapping unit locates the functional module corresponding to the selected debugging address among multiple functional modules within the AI ​​core, and distributes the first debugging address and the debugging data to the located functional module.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the debugging method for an AI chip according to claim 9.

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