Graph neural network accelerator and device based on topology reconfiguration and dynamic early exit

Abstract

This invention discloses a graph neural network accelerator and device based on topology reconstruction and dynamic early retirement. The graph neural network accelerator includes an interconnected graph preprocessing module and an accelerator body. The graph preprocessing module includes a feature preprocessor, a pruner, a community divider, a topology optimizer, and an encoder to generate optimized graph structure data in ECSR format. The accelerator body includes an aggregation engine, a combination engine, a hierarchical storage unit, and a global configuration controller. The combination engine includes a confidence evaluation unit for evaluating node convergence confidence during graph neural network inference to support dynamic early retirement acceleration. This invention aims to address the low inference efficiency of general-purpose CPUs and GPUs due to the sparse and unstructured hybrid computing characteristics, as well as the shortcomings of existing graph neural network accelerators in topology adaptability, computational resource utilization, and model support, thereby improving the inference efficiency of graph neural network accelerators.

Description

Technical Field

[0001] This invention relates to hardware accelerator technology for graph neural networks, specifically to a graph neural network accelerator and device based on topology reconstruction and dynamic early regression. Background Technology

[0002] Graph Neural Networks (GNNs), with their powerful modeling capabilities for non-Euclidean data, have become an important tool for processing irregular graph data, demonstrating outstanding performance in fields such as recommender systems, social network mining, and biomedicine. By iteratively passing information across the graph topology, GNNs can effectively capture high-order relationships and complex attribute features between nodes. However, with the exponential growth in the scale of real-world graph data, the computational and memory overhead of GNN inference processes has also increased dramatically. Unlike traditional convolutional neural networks that process regular grid data, the inference process of GNNs includes two stages: sparse neighbor aggregation and dense feature combination. This hybrid computational mode gives GNNs powerful expressive capabilities, but the low bandwidth utilization caused by irregular memory access, the latency accumulation caused by high-dimensional feature computation, and the operator heterogeneity requirements introduced by algorithm variants cause general-purpose processors (CPUs / GPUs) to face bottlenecks when performing GNN inference. To address these challenges, existing technologies have proposed various dedicated accelerators for GNNs, including HyGCN, GCNAX, MEGA, FlowGNN, and PruneGNN. HyGCN introduced a heterogeneous dual-engine design for the first time, deploying a sparse aggregation engine and a dense combination engine respectively, and successfully decoupled memory-intensive and computation-intensive tasks through pipeline parallelism. GCNAX and MEGA focus on customized data scheduling to improve the execution efficiency of sparse operators; FlowGNN designed a general data flow architecture that flexibly adapts to various GNN variants through configurable message passing paths. In addition, PruneGNN explored a pruning framework that coordinates algorithms and hardware, and alleviated computation and memory access pressure by removing redundant connections and network weights in the graph. Although the above works have made fruitful explorations in microarchitecture design and data flow scheduling, they still have the following shortcomings when facing large-scale and variable graph data in the real world: (1) Existing works treat graph data as immutable static objects and rely on dynamic scheduling or load balancing mechanisms on the hardware side to alleviate memory access pressure. However, the efficient execution of hardware depends on regular parallelism (such as SIMD alignment), while the original graph data has natural irregularity. Existing work has failed to solve the structural mismatch between data and computing architecture, which leads to the problem of channel idleness or invalid filling when the accelerator is processing highly sparse graphs, resulting in a decrease in the effective computing power density of the accelerator. (2) Existing work generally adopts the static execution mode of "full graph-full layer", which ignores the convergence heterogeneity of nodes in feature evolution and performs feature transformation of uniform depth on all nodes. A large number of simple nodes that have become stable in the shallow layer continue to perform deep MLP transformation, resulting in invalid inference, wasting computing resources and memory access bandwidth, and reducing inference energy efficiency.(3) Most existing works are based on the computational model of classic GCN for architecture design. In order to support emerging operators such as GraphSage neighbor sampling, GIN feature fusion and GAT attention mechanism, they often rely on inefficient software simulation or complex control logic, which reduces inference performance and makes it difficult to balance efficiency and algorithm versatility under fixed function pipelines.

[0003] Graph neural networks learn low-dimensional representations of graph data through message passing mechanisms, while simultaneously capturing topological structure and node attribute information. The inference process of a typical graph neural network consists of two sequential execution phases: aggregation and combination. These two phases achieve neighborhood information propagation through multiple iterations, enabling nodes to aggregate the feature information of their k-hop neighbors. The mathematical expression for arbitrary-layer inference in a graph neural network is as follows: ; ; in, For nodes and its neighboring nodes' first The intermediate aggregated feature vector obtained by layer feature aggregation. It is an aggregate function. Represents a node In the Layer combined feature vectors; nodes For nodes The neighboring nodes; For nodes The set of neighbors; For parallel operations; For nodes The combination; Represents a node In the Combined feature vectors of layers; It is a combinatorial function. For nodes In the The combined feature vector of the layers, For nodes and its neighboring nodes' first The intermediate aggregated feature vector obtained by layer feature aggregation. For the first The trainable weight matrix of the layer. Aggregation function. It can achieve sparse neighborhood feature aggregation (such as summation, mean, max pooling, etc.) and combination functions. This is used to perform dense feature transformation through linear transformation and nonlinear activation. For partial graph neural networks, edge attributes... This will be incorporated into the aggregation process to model the relationships between nodes, at which point the formula expands to: ; in, This represents the edge-aware feature transformation function.

[0004] The aggregation phase is typically mapped to sparse matrix-dense matrix multiplication (SpMM), which, constrained by the sparsity of the graph topology, is memory-bound, with its performance bottleneck being the high latency caused by random memory access. The combination phase is typically mapped to dense matrix multiplication (GEMM) via a multilayer perceptron (MLP), exhibiting high regularity and parallelism, making it a computation-bound task. To efficiently handle this heterogeneous hybrid workload, existing mainstream dedicated accelerators (such as HyGCN and AWB-GCN) generally adopt a heterogeneous dual-engine architecture: utilizing a dedicated sparse aggregation engine to handle irregular message passing, and combining it with dense computing engines such as systolic arrays to handle regular feature transformations. This embodiment's research is also based on this dual-engine architecture, further exploring its potential through hardware and software co-optimization.

[0005] Although mainstream graph neural network models all follow the general computational framework of "aggregation-composition," they differ in their specific execution logic and computational modes. For example, GraphSage introduces a neighbor sampling mechanism, transforming static graph processing into dynamic local subgraph construction, which places higher demands on the hardware's random memory access capabilities and sampling logic. GIN enhances the computational overhead of edge feature fusion by introducing nonlinear transformations of central node features. GAT, on the other hand, assigns dynamic weights to each edge through a self-attention mechanism, introducing complex transcendental function operations and more frequent intermediate result memory accesses. These differences in execution logic and computational modes lead to computational resource mismatch and control logic redundancy in traditional fixed pipeline architectures when handling different variants. For example, an addition tree optimized for GCN will generate a large number of idle operators when processing the attention weight multiplication of GAT. Therefore, hardware accelerators must be highly flexible and dynamically configure the execution path according to the computational primitives of different algorithms.

[0006] Graph neural network inference is a hybrid workload consisting of alternating memory-intensive aggregation and computationally intensive operations. Existing dedicated accelerators have alleviated the execution bottleneck between the two types of operations to some extent through customized microarchitectures and flexible data flow scheduling. However, the hardware design has not fully exploited the characteristics of graph data, mainly in the following three aspects: (1) The memory-intensive nature of graph neural network inference limits its performance to memory bandwidth. Structured pruning can reduce the total memory access, but it exacerbates the irregularity of the graph topology: the different number of neighboring nodes makes it difficult to maintain regular data parallelism in lockstep execution architectures such as SIMD or systolic arrays. To meet hardware synchronization constraints, existing designs generally use zero-filled aligned variable-length neighbor lists, causing a large number of computing units to idle on meaningless zero values. Experimental results show that on real graph datasets such as Reddit, more than 40% of the computation cycles are consumed by such invalid operations, reducing the effective computing power density of the accelerator. This reflects a structural mismatch between the inherent sparsity of graph data and the hardware's requirement for regular parallelism. Existing accelerators lack a topology representation mechanism that can actively adapt to the hardware execution model while maintaining memory access efficiency. (2) Existing graph neural network accelerators generally adopt the static execution mode of "full graph - full layer", ignoring the convergence heterogeneity of nodes in the feature transformation process. Experimental results show that on typical datasets, the feature vectors of about 60% of nodes tend to be stable after shallow aggregation. Continuing to perform deep feature transformation on them can only bring marginal accuracy gains, but consume a lot of computation and memory resources. Introducing an early termination mechanism is a way to eliminate redundant computation, but directly applying it to the GNN architecture will destroy the data dependency chain required for message passing. If the convergence node terminates processing early, its neighbors will encounter data interruption due to the lack of effective feature input when aggregating in subsequent layers, which will destroy the semantic integrity of the model. Therefore, it is necessary to design a mechanism that can reduce redundant computation and maintain data dependency at the logical level to achieve efficient inference. (3) The evolution of graph neural network models has produced diverse computational characteristics: GraphSage introduces random neighbor sampling, breaking the static adjacency access mode; GIN requires the fusion of edge features and node features, introducing multi-source data dependency; GAT, through dynamic attention weight calculation, produces nonlinear normalization and irregular memory access. These operations differ from the sparse matrix-vector multiplication of classic GCNs in their computational patterns, memory access behavior, and data dependencies. However, existing accelerators are generally based on GCNs and lack hardware support for these models. This results in low hardware execution efficiency when processing variants of graph neural networks such as GraphSage, GIN, and GAT, making it difficult to simultaneously optimize algorithmic diversity and inference performance. Therefore, a hardware design is needed that can cover mainstream graph neural network variants without sacrificing execution efficiency. In summary, existing graph neural network accelerators still have room for optimization in terms of topology adaptability, computational resource utilization, and model support. Summary of the Invention

[0007] The technical problem to be solved by this invention is to provide a graph neural network accelerator and device based on topology reconstruction and dynamic early termination, addressing the aforementioned problems of the prior art. This invention aims to solve the problem that the sparse and unstructured hybrid computing characteristics lead to low inference efficiency of general-purpose processors such as CPUs and GPUs, and the shortcomings of existing graph neural network accelerators in terms of topology adaptability, computing resource utilization and model support, thereby improving the inference efficiency of graph neural network accelerators.

[0008] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A graph neural network accelerator based on topology reconstruction and dynamic early retirement includes an interconnected graph preprocessing module and an accelerator body. The graph preprocessing module is used to reshape the original sparse graph structure data through semantically aware alignment pruning and hardware-aware topology enhancement before feeding it into the accelerator body to accelerate the execution of the original sparse graph structure data. The graph preprocessing module includes: The feature preprocessor is used to perform a linear transformation on the initial features of each node in the original sparse graph structure data using the parameters of the first layer of the graph neural network to obtain preprocessed features. The pruning tool is used to calculate the address distance between the two nodes corresponding to each edge in the original sparse graph structure data and the similarity between the preprocessed features. The edges are then filtered based on the threshold of address distance and similarity between preprocessed features to obtain a set of filtered edges. The community divider is used to divide the nodes into communities using a preset community detection algorithm, based on the filtered edge set and the original sparse graph structure data node set. The topology optimizer performs sharding operations on a set of communities, with each community corresponding to an ECSR shard; for each ECSR shard, it iterates through each node within it. And filter candidate nodes that meet the following conditions. (1) Node With nodes Belonging to the same community; (2) Node With nodes Currently not adjacent; (3) Nodes With nodes The similarity between the preprocessed features is greater than a preset threshold; for each slice, traverse each node within it. And in all its candidate nodes Select the candidate nodes with the highest similarity of preprocessed features. Multiple candidate nodes selected respectively With nodes Establish edges between the filtered edges and add them to the supplementary edge set; merge the filtered edge set and the supplementary edge set to obtain the final edge set; The encoder is used to encode the optimized graph structure data, which consists of the final set of edges and the set of nodes of the original sparse graph structure data, into ECSR format and enable the expansion degree digital segment to obtain optimized graph structure data in ECSR format. The accelerator body includes an aggregation engine and a combination engine. The combination engine includes a confidence evaluation unit for evaluating the convergence confidence of nodes during the inference process of the graph neural network, and a node is identified as an early termination node when its convergence confidence is greater than or equal to a preset confidence threshold.

[0009] Optionally, the feature preprocessor uses the parameters of the first layer of the graph neural network to perform a linear transformation on the initial features of the nodes to obtain the function expression of the preprocessed features: ; in, For nodes Preprocessing features, and These represent the weights and biases in the parameters of the first layer of the graph neural network. For nodes The original characteristics.

[0010] Optionally, the function expression for the pruning tool to filter edges based on address distance and a threshold of similarity between preprocessed features is as follows: and ; in, For nodes and nodes Cosine similarity between preprocessed features The threshold for cosine similarity. and They are nodes and nodes Preprocessing features, and They are nodes and nodes address, This is the address span threshold.

[0011] Optionally, the accelerator body further includes a hierarchical storage unit and a global configuration controller. The aggregation engine is used to perform sparse neighbor aggregation calculations for graph neural networks, including a SIMD processor array. The combination engine is used to perform node feature transformations and nonlinear mappings for graph neural networks, including a systolic array. The hierarchical storage unit includes a high-bandwidth memory, a weight buffer, a feature buffer, an edge buffer, a combination buffer, and an aggregation buffer. The weight buffer and feature buffer are respectively connected to the high-bandwidth memory to obtain the weights and features stored in the high-bandwidth memory. The output of the combination engine is connected to the aggregation engine through the combination buffer to output the calculation results of the combination engine to the aggregation engine after passing through the combination buffer. The high-bandwidth memory is connected to the aggregation engine through the edge buffer to provide edge data to the aggregation engine. The output of the aggregation engine is connected to the high-bandwidth memory through the aggregation buffer to write the results of sparse neighbor aggregation calculations back to the high-bandwidth memory through the aggregation buffer. The global configuration controller is used to provide the aggregation engine and combination engine with the allocation of computing tasks and the scheduling of system resources.

[0012] Optionally, for any node The confidence assessment unit performs node convergence confidence assessment, which includes: obtaining node... The output feature vector of the combination stage, calculated in the combination engine, is mapped to the probability space by approximate softmax for each dimension of the output feature vector of the combination stage: ; in, For graph neural networks The layer outputs the i-th dimension feature in the feature vector during the combination stage. Feature representation after mapping to probability space for The ReLU activation results A constant used to prevent the denominator from being zero. for The ReLU activation results For graph neural networks In the layer combination stage, the j-th dimension of the output feature vector is selected; in the feature representation after mapping each dimension of the output feature vector to the probability space, the maximum value is selected as the node. In the graph neural network Convergence confidence of the layer If any node In the graph neural network Convergence confidence of the layer Greater than or equal to the preset confidence threshold Then determine the node Convergence, node For early termination nodes, node The combined stage outputs feature vectors The features are frozen; the hierarchical storage unit includes a freeze buffer for storing frozen features. The input of the freeze buffer is connected to the combination engine, and the output is connected to the aggregation engine to output the frozen features calculated by the combination engine to the aggregation engine. The function expression for the aggregation engine to perform sparse neighbor aggregation calculation of the graph neural network is: ; in, For nodes The aggregation results For nodes The set of neighboring nodes Size, For nodes In the graph neural network The layer combination stage outputs feature vectors. For nodes The set of neighboring nodes Early retirement node The weighting coefficients, Early departure node In the graph neural network The layer combination stage outputs feature vectors. , Early departure node The early termination layer index, and the conditions for the aggregation engine to trigger early termination are: ; in, For nodes In the graph neural network The early termination status of a layer, with values ​​of 1 and 0 indicating whether early termination is performed; For nodes In the graph neural network Convergence confidence of the layer For graph neural networks The convergence confidence threshold of the layer, "for or logic, For nodes In the graph neural network The set of neighboring nodes that have retired early Size, The threshold for the proportion of neighbors leaving early.

[0013] Optionally, the freeze buffer includes multiple storage blocks, each storage block having an independent cache to support parallel access; the freeze buffer and the combination buffer are connected to the aggregation engine through a multiplexer to select one of the frozen features calculated by the combination engine and the ordinary features stored in the combination buffer to output to the aggregation engine.

[0014] Optionally, the aggregation engine includes a sampling processing unit for randomly selecting k neighboring nodes from optimized graph structure data in ECSR format and generating an index for access by the aggregation engine. The sampling processing unit includes a sampling controller, a pseudo-random number generator, and an out-of-order memory access controller. The sampling controller specifies the number of samples for the pseudo-random number generator via a configuration signal. The pseudo-random number generator employs a linear feedback shift register and is used when the degree of a node is greater than or equal to the number of layers in the graph neural network. The sampling index for the set of neighboring nodes is randomly assigned at any time; the out-of-order memory access controller is used to convert the out-of-order sampling index generated by the pseudo-random number generator into an ordered address within the ECSR fragment.

[0015] Optionally, the aggregation engine includes an edge feature processing unit for fusing and transforming edge features and node features. The edge feature processing unit consists of an edge weight multiplier and a feature fusion unit. The edge weight multiplier uses a 16-bit fixed-point multiplier to support element-wise multiplication of edge features and node features. The feature fusion unit is used to support additive fusion of node features and edge features, and outputs the fused feature vector for use by the aggregation engine.

[0016] Optionally, the aggregation engine includes an attention processing unit for calculating attention coefficients between nodes and performing weighted aggregation. The attention processing unit includes a feature input and mapping module, a score calculation module, an aggregation and normalization module, a weighted aggregation and multi-head output module, and a multi-head connector. The feature input and mapping module maps the input features and weights to a low-dimensional space through a fully connected layer. The score calculation module maps the concatenated input features to an attention score through a fully connected layer. The aggregation and normalization module normalizes the attention score to attention coefficients using an approximate softmax calculation. The weighted aggregation and multi-head output module multiplies the attention coefficients with the original features using multiple multipliers and then sums the multiplication results using a summation tree to obtain the aggregated features of each attention head. The multi-head connector connects the aggregated features of each attention head to obtain the final aggregated node feature vector.

[0017] A computer device includes a microprocessor and an accelerator interconnected, the accelerator being the graph neural network accelerator based on topology reconstruction and dynamic early regression.

[0018] Compared with existing technologies, the present invention mainly achieves the following beneficial effects: The graph neural network accelerator of the present invention includes an interconnected graph preprocessing module and an accelerator body. The graph preprocessing module is used to reshape the original sparse graph structure data through semantically aware alignment pruning and hardware-aware topology enhancement, and then feed it into the accelerator body to achieve accelerated execution of the original sparse graph structure data. The graph preprocessing module includes a feature preprocessor, a pruner, a community divider, a sharding module, a sharding filtering module, an edge-filling module, a merging module, and an encoder to generate optimized graph structure data in ECSR format. The present invention solves the memory access mismatch problem by normalizing the data flow through hardware-aware topology reconstruction. While ensuring model accuracy, it removes noisy edges with low semantic contribution and supplements local edges under HBM page constraints based on SIMD alignment principles. This enhances memory access locality at the topology level and improves the effective utilization of computing units. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of the graph neural network accelerator in an embodiment of the present invention.

[0020] Figure 2 This is a schematic diagram of the sampling processing unit in an embodiment of the present invention.

[0021] Figure 3 This is a schematic diagram of the attention processing unit in an embodiment of the present invention.

[0022] Figure 4 The results show the speedup comparison between ReE-GNN, GCN, and GIN in this embodiment of the invention.

[0023] Figure 5 The results show the speedup comparison between ReE-GNN, GraphSage, and GAT in this embodiment of the invention.

[0024] Figure 6 This presents the experimental results comparing the reduction of DRAM accesses between ReE-GNN and GCN / GIN in this embodiment of the invention.

[0025] Figure 7 This presents the experimental results comparing the reduction of DRAM access between ReE-GNN and GraphSage and GAT in this embodiment of the invention.

[0026] Figure 8 The diagram shows the ablation experiment results of the acceleration ratio in the embodiments of the present invention, where (a) is the ablation experiment result on the Cora dataset, (b) is the ablation experiment result on the Citeseer dataset, (c) is the ablation experiment result on the PubMed dataset, and (d) is the ablation experiment result on the Reddit dataset.

[0027] Figure 9 The diagram shows the ablation experiment results of reducing DRAM access times in the embodiments of the present invention, where (a) is the ablation experiment result on the Cora dataset, (b) is the ablation experiment result on the Citeseer dataset, (c) is the ablation experiment result on the PubMed dataset, and (d) is the ablation experiment result on the Reddit dataset.

[0028] Figure 10 The above describes the optimization effect of topology reconstruction on the RAW collision rate and the combined buffer hit rate in the aggregation stage in this embodiment of the invention, where (a) is the optimization effect on the RAW collision rate and (b) is the optimization effect on the combined buffer hit rate. Detailed Implementation

[0029] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0030] like Figure 1 As shown, this embodiment of the graph neural network accelerator based on topology reconstruction and dynamic early retirement includes an interconnected graph preprocessing module and an accelerator body. The graph preprocessing module is used to reshape the original sparse graph structure data through semantically aware alignment pruning and hardware-aware topology enhancement before feeding it into the accelerator body to achieve accelerated execution of the original sparse graph structure data. The original sparse graph structure data can be represented as: ,in For a set of nodes, The graph structure data can be accelerated as needed, such as when classifying papers. The nodes in the graph structure data are papers, and the edges are the reference relationships between the nodes. The attributes of the nodes may include the keywords of the papers. The graph neural network accelerator based on topology reconstruction and dynamic early termination in this embodiment can be used to accelerate the propagation of the graph structure data of the graph neural network to extract features. Finally, a classifier is used to obtain the classification results of the papers, such as classifying the papers into different subject areas.

[0031] The graph preprocessing module, as the front-end processing part of the accelerator, transforms unstructured raw graph data into a high-throughput regularized computational flow, which can be implemented using FPGA or software as needed. To address the structural mismatch between unstructured graph data and highly parallel computing architectures and improve the effective computing power density of the accelerator, the graph preprocessing module reshapes the raw sparse graph data into regularized dense blocks adapted to the hardware parallel granularity through two stages: semantically aware alignment pruning and hardware-aware regularization filling. Specifically, the graph preprocessing module includes: Feature preprocessor for raw sparse graph structure data For each node in the graph neural network, the initial features of the node are linearly transformed using the parameters of the first layer to obtain preprocessed features; Pruners are used to prune the set of edges in the original sparse graph structure data. Each edge The algorithm calculates the address distance between the two nodes corresponding to the edge and the similarity between the preprocessed features. It then filters the edges based on a threshold set for both address distance and preprocessed feature similarity, resulting in a filtered edge set. ; Community divider, used for filtering edge sets and the node set of the original sparse graph structure data. A preset community detection algorithm is used to divide nodes into communities to obtain a community set; The topology optimizer performs sharding operations on a set of communities, with each community corresponding to an ECSR shard. Each shard can correspond to a page mapping unit in hardware storage, enhancing locality during graph data access. For each ECSR shard, it iterates through each node within it. And filter candidate nodes that meet the following conditions. (1) Node With nodes Belonging to the same community; (2) Node With nodes Currently not adjacent; (3) Nodes With nodes The similarity between the preprocessed features is greater than a preset threshold; for each slice, traverse each node within it. And in all its candidate nodes Select the candidate nodes with the highest similarity of preprocessed features. Multiple candidate nodes selected respectively With nodes Establish edges between them, and add the established edges to the supplementary edge set. ; Set the filter edges Supplementary edge set Merging them yields the final set of edges. : ; An encoder is used to convert the final set of edges. The node set of the original sparse graph structure data Optimized graph structure data Perform ECSR encoding and enable extended number segments to obtain optimized graph structure data in ECSR format. This allows for the transformation of irregular graphs into regular workloads through hardware-aware topology reconstruction, thereby optimizing memory access locality. The accelerator body includes an aggregation engine and a combination engine. The combination engine includes a confidence evaluation unit for evaluating the convergence confidence of nodes during the inference process of the graph neural network, and a node is identified as an early termination node when its convergence confidence is greater than or equal to a preset confidence threshold.

[0032] To improve the discriminative power of feature vectors and avoid redundant computations during optimization, the weights of the first layer of a GNN are used to preprocess the initial features. In this embodiment, the feature preprocessor uses the parameters of the first layer of the graph neural network to perform a linear transformation on the initial features of the nodes to obtain the preprocessed features. The functional expression is as follows: ; in, For nodes Preprocessing features, and These represent the weights and biases in the parameters of the first layer of the graph neural network. For nodes The original characteristics.

[0033] To address the load imbalance caused by the power-law distribution of graph topology, this embodiment first prunes the original graph structure. Unlike traditional random discarding strategies, this embodiment introduces semantic relevance scoring as the pruning criterion, preserving topological information to the greatest extent while reducing computational load. The function expression for the pruner to filter edges based on address distance and a threshold of similarity between preprocessed features is as follows: and ; in, For nodes and nodes Cosine similarity between preprocessed features The threshold for cosine similarity. and They are nodes and nodes Preprocessing features, and They are nodes and nodes address, The address span threshold is: ; in, and They are nodes and The initial feature vector (before inter-layer propagation in GNN). This represents the L2 norm. To accommodate the differences in feature distribution across different datasets, a dynamic threshold is used for pruning instead of a fixed value. The threshold is calculated as follows: ; in, and These are the mean and standard deviation of the cosine similarity of all edges in the original graph, respectively. This strategy can ensure that the pruning ratio is stable at 30% to 40%, reducing the number of edges while minimizing the loss of accuracy.

[0034] Furthermore, due to the fixed parallel width of the hardware execution unit, the residual edges after pruning or the original sparse nodes often cannot fill the slots in the computation pipeline, resulting in idle computing resources. To further improve the computing power density and suppress the oversmoothing phenomenon in deep GNNs, this embodiment designs a hardware-aware regularization filling mechanism, which regularizes the load by introducing locally high-value edges. To avoid frequent HBM page switching caused by random edge addition, this embodiment first establishes memory access distance constraints. Based on HBM page alignment, an address span threshold is defined. To avoid potential cross-page access: ; in, This is the HBM page size (1KB in this example). This refers to the storage width of a single node's feature vector. This is achieved by limiting the address deviation of the node index to no more than an address span threshold. To ensure that all neighbor nodes pointed to by newly added edges are stored in the current physical page or adjacent buffer, memory access overhead is limited to a single page activation. Under the premise of satisfying memory access distance constraints, the Louvain algorithm is first used to perform topological clustering to identify closely related local communities. Then, the identified communities are mapped to Enhanced Compacted Sparse Row (ECSR) shards to ensure that logically related nodes are stored contiguously in the DRAM physical space. Based on the standard CSR format, the ECSR format reduces adjacency list storage overhead by performing differential encoding and variable byte encoding on column pointers, and provides an address alignment basis for subsequent regularized memory accesses. This embodiment focuses on mining higher-order implicit associations in the graph structure. Specifically, for nodes within the same community and ECSR shard, this embodiment uses their two-hop neighbors as the core candidate pool. If a two-hop neighbor's semantic similarity score with the source node meets a threshold, and there is no physical connection between them, i.e.: and ; in, (Ensure that the supplementary edges have high semantic value). node and The edge between, For the semantically pruned graph, it is introduced as a high-value fill edge. This strategy enhances the model's global context awareness by establishing long-range dependencies using local idle slots within the community, without compromising memory access locality. To balance model accuracy and hardware overhead, the maximum number of fill edges per node is 3. To avoid cross-page overhead caused by introducing remote edges, this embodiment adopts a data copy localization strategy, physically copying the feature vectors of selected neighbors to the end of the adjacent data block of the source node. This design transforms the originally discrete random memory access into efficient streaming sequential reading, suppressing model oversmoothing while ensuring that hardware execution efficiency is not affected by topological complexity. Finally, hardware-aware regularization not only enriches the global context by utilizing the implicit associations of multi-hop neighbors, but also elevates the originally discrete sparse computation to regularized vectorized execution by filling idle computation slots.

[0035] like Figure 1As shown, in this embodiment, the accelerator body also includes a hierarchical storage unit and a global configuration controller. The aggregation engine is used to perform sparse neighbor aggregation calculations of the graph neural network, including a SIMD processor array; the combination engine is used to perform node feature transformations and nonlinear mappings of the graph neural network, including a systolic array; the hierarchical storage unit includes a high-bandwidth memory (HBM), a weight buffer, a feature buffer, an edge buffer, a combination buffer, and an aggregation buffer. The weight buffer and feature buffer are respectively connected to the high-bandwidth memory to obtain the weights and features stored in the high-bandwidth memory. The output of the combination engine is connected to the aggregation engine through the combination buffer to output the calculation results of the combination engine to the aggregation engine after passing through the combination buffer. The high-bandwidth memory is connected to the aggregation engine through the edge buffer to provide edge data to the aggregation engine; the output of the aggregation engine is connected to the high-bandwidth memory through the aggregation buffer to write the results of the sparse neighbor aggregation calculations back to the high-bandwidth memory through the aggregation buffer; the global configuration controller is used to allocate computing tasks and schedule system resources for the aggregation engine and the combination engine. The bandwidth memory (HBM) stores the original graph data, the optimized graph data, and the model weights. The on-chip buffer, consisting of the weight buffer, feature buffer, edge buffer, combination buffer, and aggregation buffer, uses a ping-pong mechanism to hide the bandwidth memory access latency and ensure that the computing unit maintains high utilization.

[0036] After several layers of transformation, the semantic information of a node becomes sufficiently stable, and subsequent deep computations will not significantly alter its decision-making outcome; therefore, the node can be considered converged. That is, if the node... In the Layer combination stage output features ,satisfy: ; Then the node is considered In the Layer convergence, where For the feature change threshold, This represents the L2 norm.

[0037] Since the feature vectors of converged nodes possess inter-class discriminative power in the classification space, the maximum value (confidence) of their softmax output will be significantly higher than that of non-converged nodes. This embodiment employs a lightweight softmax algorithm combined with the maximum confidence evaluation criterion to avoid complex computations and additional training overhead. Let the output feature vector of the combined stage be: ; Where d is the feature dimension.

[0038] like Figure 1 As shown, in this embodiment, the ensemble engine includes a confidence evaluation unit for evaluating the convergence confidence of nodes during the inference process of the graph neural network, for any node. The confidence assessment unit performs node convergence confidence assessment, which includes: obtaining node... The output feature vector of the combination stage, calculated in the combination engine, is mapped to the probability space by approximate softmax for each dimension of the output feature vector of the combination stage: ; in, For graph neural networks The layer outputs the i-th dimension feature in the feature vector during the combination stage. Feature representation after mapping to probability space for The ReLU activation results A constant used to prevent the denominator from being zero. for The ReLU activation results For graph neural networks The j-th dimension of the output feature vector in the layer combination stage; this approximate softmax does not require exponential operation and full normalization, and can reflect the inter-class discrimination of the feature through linear transformation only, and the confidence correlation coefficient with the full softmax is ≥0.95.

[0039] In the combination stage, the maximum value of each feature dimension in the output feature vector after mapping to the probability space is selected as the node. In the graph neural network Convergence confidence of the layer ,Right now: ; If any node In the graph neural network Convergence confidence of the layer Greater than or equal to the preset confidence threshold (Configurable by software), then determine the node. Convergence, node For early termination nodes, node The combined stage outputs feature vectors This is a frozen feature. Assume that when a node's features converge, the feature component corresponding to its true class is significantly larger than the feature components corresponding to the other classes, i.e.: ; in, Represents a node The true category index. After normalization, we can approximate it as follows: ; Therefore, the convergence confidence of the node is: ; Conversely, for nodes that have not yet converged, the feature components corresponding to each category are usually quite similar, without exhibiting a clear dominant component. In this case, the normalized output is approximately uniformly distributed, i.e.: ; Therefore: ; in, This represents the feature dimension or the number of categories. Therefore, a confidence threshold can be set. It effectively distinguishes between converged nodes and non-converged nodes, with a low probability of misjudgment.

[0040] like Figure 1 As shown, in this embodiment, the hierarchical storage unit includes a freeze buffer for storing frozen features. The input end of the freeze buffer is connected to the combination engine and the output end is connected to the aggregation engine to output the frozen features calculated by the combination engine to the aggregation engine. The freeze buffer caches the static features of early-retrieval nodes with high priority, which can improve the feature access efficiency in the aggregation stage.

[0041] To ensure semantic integrity during the inference process, the accelerator must save the converged feature vector of a converged node while skipping its subsequent computational pipeline. This ensures data supply to neighboring nodes during the later aggregation phase. Since the features of a converged node are sufficiently stable, subsequent nonlinear transformations have low marginal contributions to semantic enhancement, and freezing them will not affect inference accuracy. Therefore, if the node... In the If a layer triggers early termination, its feature vector remains unchanged in all subsequent layers, that is: ; in, For nodes In the The feature vector of the layer.

[0042] Set nodes The set of neighbor nodes is This includes nodes that have already left early. (Frozen features) ) and nodes that did not leave early (Dynamic characteristics) ). No. layer( The aggregated output of ) is: ; in, ( (for the early departure layer of node x). Let v be an aggregation function (summation, mean, etc.). Since node v has converged, it satisfies... Substituting into the aggregate function, we get: ; in, This refers to aggregation error. Aggregation error is related to the feature change threshold. Positive correlation, and When the feature changes threshold Small enough (e.g.) When the aggregation error is... This is negligible and will not affect the feature representation of neighboring nodes. To standardize the aggregation call of frozen features, a freeze operator is defined. Using a hybrid aggregation logic that describes both static and dynamic features, the function expression for the aggregation engine to perform sparse neighbor aggregation calculations in a graph neural network is as follows: ; in, For nodes The aggregation results For nodes The set of neighboring nodes Size, For nodes In the graph neural network The layer combination stage outputs feature vectors. For nodes The set of neighboring nodes Early retirement node The weighting coefficients, Early departure node In the graph neural network The layer combination stage outputs feature vectors. , Early departure node Early retirement layer index, Defined by the GCN model, such as the normalization coefficient, this operator retains the logic of GCN aggregation while also... It has been adapted to the call of the freeze feature.

[0043] The semantic attributes of GNN nodes exhibit community consistency, with nodes within the same community showing similar convergence trends. Therefore, when a node's majority of neighbors have prematurely terminated, the node's semantic information is sufficiently stable, potentially triggering premature termination. Thus, in this embodiment, the condition for the aggregation engine to trigger premature termination is: ; in, For nodes In the graph neural network The early termination status of a layer, with values ​​of 1 and 0 indicating whether early termination is performed; For nodes In the graph neural network Convergence confidence of the layer For graph neural networks The convergence confidence threshold of the layer, "for or logic, For nodes In the graph neural network The set of neighboring nodes that have retired early Size, This sets a threshold for the early departure rate of neighbors (default 0.7, set based on community consensus theory). The early departure status of neighboring nodes reflects the overall convergence trend of the community. Even if a node's own confidence level does not reach the threshold, convergence can still be determined based on community consensus, further increasing the early departure rate without increasing accuracy loss. Through the above dynamic node-level early departure mechanism, confidence assessment is used to allow nodes to leave early to reduce computational load, and a dedicated cache is used to maintain the feature data of early-leaking nodes, achieving on-demand allocation of computing resources.

[0044] In this embodiment, the frozen buffer includes multiple storage blocks, each with an independent cache to support parallel access. The frozen buffer and the combined buffer are connected to the aggregation engine via a multiplexer to select one of the frozen features calculated by the combined engine and the ordinary features stored in the combined buffer for output to the aggregation engine. To address the storage and access requirements of static features in the dynamic node-level early termination mechanism, the storage hierarchy design is optimized, a frozen buffer is added, and the feature selection logic of the aggregation engine is extended to achieve dynamic switching between static and dynamic features. The frozen buffer is a dedicated SRAM for storing the static features of early-terminating nodes. It adopts a block storage design with a total capacity of 2MB, corresponding to ECSR shards. Each shard corresponds to a 256KB cache, supporting parallel access. It is set to the highest priority (higher than the combined buffer), and when neighboring nodes are aggregated, the features of early-terminating nodes are read from the frozen buffer first, avoiding the replacement overhead of dynamic feature cache. Writing adopts a "one-time freeze" strategy; after a node triggers early termination, its features are directly written to the corresponding block. Reading adopts an "address index + shard mapping" mechanism, quickly locating the cache block through the node ID. The freeze buffer employs the LRU algorithm, replacing long-unaccessed static features only when the cache is full, ensuring a high cache hit rate for frequently reused features. To support mixed reading of static and dynamic features, the feature access path of the aggregation engine is expanded by adding a 2-to-1 multiplexer and selection control logic. A selection signal `selv` is generated based on the early-retreat flag in the node status register array, and the input to either the freeze buffer or the combined buffer is selected according to this signal. The selection logic runs in parallel with the SIMD computation unit pipeline of the aggregation engine, without adding additional latency; feature reading employs a double-buffering mechanism to ensure a bubble-free pipeline. When the target node feature is not found in the freeze buffer, the system automatically switches to the combined buffer to read the dynamic feature and triggers a cache update, avoiding data access errors.

[0045] like Figure 1 and Figure 2 As shown, the aggregation engine includes a sampling processing unit for randomly selecting k neighboring nodes from optimized graph structure data in ECSR format and generating an index for the aggregation engine to access. The sampling processing unit includes a sampling controller, a pseudo-random number generator, and an out-of-order memory access controller. The sampling controller is used to specify the number of samples for the pseudo-random number generator via a configuration signal. The pseudo-random number generator uses a linear feedback shift register and is used when the degree of a node is greater than or equal to the number of layers in the graph neural network. Randomly specify the sampling index for the neighbor node set at a certain time; the out-of-order memory access controller is used to convert the out-of-order sampling index generated by the pseudo-random number generator into the sequential address within the ECSR shard. The sampling processing unit is designed for the neighbor random sampling requirement of GraphSage, randomly selects k neighbor nodes from the adjacency list in ECSR format, and generates indexes for the aggregation engine to access. The pseudo-random number generator adopts the LFSR (Linear Feedback Shift Register) architecture, supports 16-bit random number output, and the period is greater than or equal to 2 16 -1, meeting the requirements of sampling randomness; the sampling controller supports configurable sampling numbers k = 4 / 8 / 16, specifies the target sampling number through the configuration signal, and the controller dynamically adjusts the sampling strategy according to the node degree (randomly select when the degree ≥ k, and sample all when the degree < k); the out-of-order memory access controller solves the conflict between the out-of-order access of the sampling index and the sequential streaming read of the ECSR format, converts the out-of-order sampling index into the sequential address within the ECSR shard, and ensures the utilization rate of the memory access bandwidth.

[0046] As Figure 1 shown, the aggregation engine includes an edge feature processing unit for fusing and transforming edge features and node features. The edge feature processing unit consists of an edge weight multiplier and a feature fuser. The edge weight multiplier adopts a 16-bit fixed-point multiplier to support the element-wise multiplication of edge features and node features; the feature fuser is used to support the additive fusion of node features and edge features, and outputs the fused feature vector for the aggregation engine to use. The edge feature processing unit is designed for the edge feature embedding requirement of GIN, fuses and transforms edge features and node features. The edge weight multiplier adopts a 16-bit fixed-point multiplier, supports the element-wise multiplication of edge features and node features, and meets the real-time fusion requirement; the feature fuser supports the additive fusion of node features and edge features, and outputs the fused feature vector for the aggregation engine to use.

[0047] As Figure 1 and Figure 3As shown, the aggregation engine includes an attention processing unit for calculating attention coefficients between nodes and performing weighted aggregation. This attention processing unit comprises a feature input and mapping module, a score calculation module, an aggregation and normalization module, a weighted aggregation and multi-head output module, and a multi-head connector. The feature input and mapping module maps input features and weights to a low-dimensional space through a fully connected layer. The score calculation module concatenates the input features and maps them to attention scores through a fully connected layer. The aggregation and normalization module normalizes the attention scores to attention coefficients using an approximate softmax calculation. The weighted aggregation and multi-head output module multiplies the attention coefficients with the original features using multiple multipliers and then sums the results using a summation tree to obtain the aggregated features of each attention head. The multi-head connector connects the aggregated features of each attention head to obtain the final aggregated node feature vector. The attention processing unit is designed to meet the attention weight calculation requirements of GAT, calculating attention coefficients between nodes and performing weighted aggregation. It consists of an attention weight calculator, a softmax unit, and a weighted aggregator. The attention weight calculator has two built-in fully connected layers (FC1+FC2). FC1 maps node features to a low-dimensional space, and FC2 outputs attention scores, supporting multi-head attention (configurable with 2 / 4 / 8 heads). The softmax unit uses approximate softmax calculation to normalize the attention scores. The weighted aggregator multiplies the normalized attention coefficients with the node features and outputs an aggregated node feature vector.

[0048] In this embodiment, the aggregation engine is responsible for sparse neighbor aggregation calculations in the graph neural network. It integrates a 32×16 SIMD processor array, a feature selection unit, and multi-variant heterogeneous processing units (sampling processing unit, edge feature processing unit, and attention processing unit). The aggregation engine also includes a decoder and a scheduler. The decoder is used to decode the input data (edges, nodes), and the scheduler is used to schedule aggregation tasks on the aggregation engine. Each SIMD unit has a built-in adder, divider, and comparator. In specific aggregation modes, inactive logic units will be placed in a power-off state to reduce static power consumption. To adapt to the node-level early termination mechanism, the feature selection unit can dynamically switch between the combination buffer and the frozen buffer based on the node status flag, ensuring the correctness of multi-model aggregation. The aggregation engine can dynamically adjust the hardware path through configuration information to support multiple variants: GCN / GIN enables the adder tree to perform Sum / Mean reduction, GraphSAGE activates the comparator chain to perform Max-pooling aggregation, and GAT, in conjunction with a dedicated attention processing unit, processes weighted summation, supporting real-time injection of edge features. The mode switching of the aggregation function is completed during the inter-layer pipeline pause, without affecting the pipeline throughput.

[0049] The ensemble engine efficiently handles node feature transformations and nonlinear mapping tasks in graph neural networks. Based on a systolic array architecture, it achieves general support for multiple GNN paradigms through reconfigurable data flow management and arithmetic logic enhancement. The ensemble engine employs weight-resident data flow, preloading weights into the processing unit, allowing feature vectors to flow within the array. This reduces redundant weight access, improving the energy efficiency of linear transformations. The aggregation engine not only supports multilayer perceptron (MLP) operations for GCN, GAT, and GraphSAGE, but also adapts to the feature reshaping needs of different model depths and dimensions through dynamic configuration logic. For models like GIN involving multiple hidden layers and high-complexity MLP aggregation, the ensemble engine expands the addition tree to 4 levels by configuring signals to improve the parallelism of high-dimensional transformations; while when processing low-level transformations like GCN, the addition tree can be folded to 3 levels, effectively reducing computational latency by shortening the logical path. The ensemble engine incorporates dedicated activation function units that can be switched instantly according to configuration instructions to meet the nonlinear mapping needs of different models. Finally, the combined engine integrates a convergence confidence evaluation unit, which provides convergence status criteria for the dynamic node-level early termination mechanism by real-time monitoring of the numerical offset after feature transformation, and outputs the transformed feature vector and its corresponding confidence index in real time.

[0050] The global configuration controller is responsible for allocating computational tasks and dynamically scheduling system resources. It supports configuration parsing for different graph neural network variants, configuring topology reconstruction parameters, and configuring dynamic node-level early termination thresholds. Simultaneously, it monitors the operational status of each module, especially performing synchronous flow control between the sparse aggregation engine and the dense combination engine to minimize pipeline bubbles caused by data dependencies. The controller monitors the status and feature convergence of each computing unit in real time, ensuring that the system maintains high-performance output while always operating within its optimal efficiency range based on real-time feedback of early termination signals.

[0051] This embodiment of the graph neural network accelerator based on topology reconstruction and dynamic early termination (ReE-GNN) adopts a hardware-software co-pipeline based on the "combination-aggregation" sequence, and hides off-chip access latency through double buffering and task overlap mechanism. The entire execution process is divided into the following five stages: (1) Graph preprocessing and topology optimization stage. The system loads the original graph data and model weights from HBM to the on-chip storage unit. The software-level preprocessing engine completes graph reconstruction and task reordering, generates hardware-aware normalized task sequences and distributes them to the hardware scheduler to minimize on-chip RAW conflicts and improve data locality. (2) Combination engine feature transformation and confidence evaluation stage. The global configuration controller parses the model configuration and the combination engine switches to the corresponding mode. Node features flow into the systolic array in vector form, and are transformed with static weights using MLP to output feature vectors. The confidence evaluation unit calculates the node confidence in real time and compares it with the threshold: if the threshold is reached, the node is marked as "exited" and the feature is written to the frozen cache for reuse in subsequent layers; otherwise, it is marked as "active" and the feature is written back to the feature buffer to enter the next iteration. (3) Neighbor aggregation stage of the aggregation engine. The aggregation engine reads the early exit node features from the frozen cache first according to the marking of the node status register array, and reads the active node features from the feature buffer when it misses. According to different model configurations, the aggregation engine calls the corresponding heterogeneous processing unit (sampling processing unit, edge feature fusion unit or attention processing unit) to perform aggregation operation and outputs the intermediate aggregated features to the aggregation buffer. (4) Inter-layer switching and configuration update stage. After the current layer is calculated, the global configuration controller updates the threshold of the next layer, and the on-chip buffer starts ping-pong switching: the data of the current buffer block is written back to HBM or passed to the next layer, and the other buffer block preloads subsequent data to hide the access delay. (5) Final result output stage. After the L-layer iteration is completed, the final feature vector is written back to HBM from the feature buffer via DMA, and the end-to-end inference process ends.

[0052] To verify the effectiveness of the ReE-GNN accelerator based on topology reconstruction and dynamic early retirement (ReE-GNN) in this embodiment, six datasets—Cora, Citeseer, Pubmed, Dblp, Nell, and Reddit—were used to evaluate the architecture of this embodiment on four graph neural network models: GCN, GIN, GAT, and GraphSage. To evaluate the performance of the ReE-GNN accelerator, this embodiment was compared with four advanced accelerators: HyGCN, GCNAX, MEGA, and DCSR-GCN. This embodiment implemented a cycle-accurate simulator in C++ to simulate the behavior of the accelerator, thereby obtaining the number of execution cycles for performance evaluation. Given the configuration differences between the various accelerators—for example, the buffer size in HyGCN is 24MB, and the systolic array in HyGCN is 32×128—for a fair comparison, the same computational unit configuration was set for HyGCN when performing performance comparisons. For GCNAX, which uses a unified computational unit, the area of ​​its computational units was ensured to be comparable to the total area of ​​the processing units in DCSR-GCN. For MEGA, an unquantized design portion is used. This embodiment implements DCSR-GCN using Verilog and performs logic synthesis on Xilinx Vivado 2023.1 using the 1GHz Versal ACAP 7nm proprietary process library to obtain the area and power consumption of the processing unit. For the SRAM-based on-chip buffer, this embodiment uses CACTI-7.0 to model the area and power consumption. This embodiment uses HBM1.0 with a bandwidth of 256GB / s as DRAM and uses DRAMSIM3 to model off-chip access and estimate the energy consumption of accessing DRAM. This embodiment compares the speedup of the ReE-GNN graph neural network accelerator with topology reconstruction and dynamic early retirement on six datasets: Cora, Citeseer, Pubmed, Dblp, Nell, and Reddit. Figure 4 and Figure 5 As shown.

[0053] from Figure 4 and Figure 5As can be seen, the graph neural network accelerator based on topology reconstruction and dynamic early termination (ReE-GNN) in this embodiment achieves speedups of up to 35.7x, 9.8x, 7.5x, and 4.6x compared to HyGCN, GCNAX, MEGA, and DCSR-GCN, respectively. ReE-GNN shows better acceleration performance on the Nell, Reddit, and PubMed datasets. Nell's average node degree is only 3.83, its adjacency list is highly sparse, and its node IDs exhibit strong local clustering, enabling the hardware-aware topology reconstruction mechanism to effectively improve the in-page access ratio. Simultaneously, the Nell dataset has a feature dimension as high as 61278, and the dynamic node-level early termination mechanism causes 38% of nodes to exit prematurely at shallow layers, significantly reducing redundant computation in the combination stage. Furthermore, the vectorization processing of the vector systolic array fully leverages the parallel computation advantages of long feature vectors. The Reddit and PubMed datasets also possess high feature dimensions or strong locality, thus achieving similar speedup gains. On the Cora and Citeseer datasets, ReCE-GNN's acceleration performance is moderate. These two datasets have moderate feature dimensions and low node degrees. The memory access optimization brought by topology reconstruction and the computational reduction of the early termination mechanism can be effectively converted into performance gains. However, due to the small size of the datasets, the overall acceleration is lower than that of the three large-scale datasets mentioned above. On the Dblp dataset, the acceleration performance is relatively lower than other datasets. This dataset has a high average node degree (5.97) and relatively dense connections. On the one hand, it weakens the compression benefits of the ECSR format and the normalization effect of topology reconstruction. On the other hand, it increases the complexity of neighbor-aware decision-making in the early termination mechanism. At the same time, its feature dimension (1639) is at a moderate level, and the parallel computing advantage of the vector systolic array is not fully released. Moreover, the dense connections make it difficult to avoid RAW conflicts in the aggregation stage, which affects pipeline efficiency.

[0054] This embodiment compares the DRAM access counts of the topology reconstruction and dynamic early retirement graph neural network accelerator (ReE-GNN) with those of benchmark accelerators on six datasets: Cora, Citesier, Pubmed, Dblp, Nell, and Reddit. Figure 6 and Figure 7 As shown. From Figure 6 and Figure 7As can be seen, the graph neural network accelerator based on topology reconstruction and dynamic early termination (ReE-GNN) in this embodiment achieves memory access reductions of up to 42.3 times, 6.7 times, 5.9 times, and 3.8 times respectively compared to HyGCN, GCNAX, MEGA, and DCSR-GCN. The memory access reduction is most significant on the Reddit, Nell, and PubMed datasets. Reddit has a large node scale (233,000 nodes) and dense edge count (115 million edges). Hardware-aware topology reconstruction, through community partitioning and adding edges within shards, reduces cross-page accesses by 74%. Simultaneously, the dynamic node-level early termination mechanism causes 45% of nodes to trigger early termination, and their feature vectors are frozen in a dedicated on-chip cache. Access to these nodes during the aggregation phase is completed through a high-priority cache, avoiding repeated HBM reads. The Nell and PubMed datasets also have high feature dimensionality or strong sparsity, and the memory access optimization effect is similar to that of Reddit. On the Cora and Citeseer datasets, the memory access optimization effect is moderate. These two datasets have low node degrees (2-3), sparse adjacency lists, and low raw memory access overhead, limiting the compression space for topology reconstruction. However, their feature dimensions are high (Cora: 1433, Citeseer: 3703). While the early-retirement mechanism can reduce some computation, the memory access savings from feature freezing are limited by the dataset size, resulting in a lower overall memory access reduction compared to large-scale datasets. On the Dblp dataset, the memory access optimization is relatively low. This dataset has a high average node degree (5.97) and relatively dense connections, weakening the normalization effect of topology reconstruction and increasing the complexity of neighbor-aware decision-making in the early-retirement mechanism. Its feature dimension (1639) is at a medium level, and the cache hit rate of the frozen buffer is close to saturation, making it difficult to achieve further memory access savings through feature freezing. Furthermore, the dense connections lead to a certain degree of RAW conflicts during the aggregation stage, impacting memory access efficiency.

[0055] To quantify the independent contributions of hardware-aware graph topology reconstruction, dynamic node-level early termination mechanism, and multi-variant heterogeneous processing units, ablation experiments were conducted under unified hardware resource constraints in this embodiment. Four representative datasets—Cora, Citeseer, PubMed, and Reddit—were selected for the experiment. The classic GNN accelerator HyGCN was used as the baseline architecture. Hardware-aware graph topology reconstruction (introducing HFTR), dynamic node-level early termination mechanism (introducing CEE), and a dedicated GNN operator (introducing DGO, i.e., the complete ReE-GNN) were sequentially superimposed. The ablation experiment results are as follows: Figure 8 and Figure 9 As shown.

[0056] like Figure 8As shown, on the Reddit dataset, the speedup after introducing HFTR is approximately 3.0x (represented as 3.0× in the figure). This is attributed to its semantic pruning and hardware-guided edge addition, which increases the in-page access ratio from 62% to 84%, reducing cross-page memory access latency and RAW conflict rate. On the Citeseer dataset, the benefits of introducing HFTR are relatively small due to the low node degree and unclear community structure. The speedup is further improved by adding CEE on top of HFTR. On the PubMed dataset, introducing CEE increases the speedup from 3.5x to 8.2x. This is attributed to its high feature dimension (500), which causes many nodes to converge at shallow layers. Early termination prunes approximately 35% of redundant computation, while the introduction of a freeze buffer avoids repeated memory accesses of static features. On the Cora dataset, introducing CEE contributes approximately 2.1x of additional speedup, which is roughly consistent with the node convergence ratio. Finally, after adding DGO (i.e., the complete ReE-GNN), the speedup reaches its highest value on all datasets. On the Reddit dataset, introducing DGO increased the speedup from 15.0x to 30.2x, thanks to the hardware-native support of the reconfigurable data path for operations such as sampling and edge fusion, eliminating the additional overhead of software simulation. On the Citeseer dataset, the final speedup was 14.8x, lower than Reddit, but still better than existing work.

[0057] like Figure 9 As shown, HFTR reduces DRAM access counts by an average of 2.5 times through ECSR compression and cross-page edge filtering. On the Reddit dataset, HFTR reduces memory access counts to 10.8 times the baseline, primarily due to the reduction in adjacency list storage size. CEE utilizes a frozen buffer to cache static features, ensuring that accesses to early-retrieval node features during the aggregation phase are performed entirely on-chip, avoiding redundant HBM reads. On the PubMed dataset, CEE further reduces memory access counts to 18.3 times the baseline, directly related to the early-retrieval rate and feature dimension. On Cora, CEE contributes approximately 1.4 times the additional reduction. DGO optimizes the sampling access pattern through an out-of-order memory access controller and retains intermediate data for operations such as edge feature fusion on-chip, ultimately reducing ReE-GNN's DRAM access counts by an average of 18.5 times compared to HyGCN. On the Reddit dataset, the memory access count reduction reaches a maximum of 25.4 times.

[0058] Considering that HFTR has the most direct impact on memory access locality, this embodiment further analyzes the impact of topology reconstruction on memory access performance from two dimensions: cache hit rate and RAW conflict rate. The optimization effect of topology reconstruction on RAW conflict rate and composite buffer hit rate during the aggregation phase is as follows: Figure 10As shown, "original" refers to the basic classical GNN accelerator HyGCN; "semantic pruning" is based on "original" with the addition of the pruner of the graph preprocessing module in this embodiment. (a) shows the optimization effect of RAW collision rate, and (b) shows the optimization effect of combined buffer hit rate. Figure 10 The results show that on the Nell dataset, semantic pruning reduces invalid edges by 35% and the RAW conflict rate from 28% to 19%. Hardware-aware edge addition further reduces the conflict rate to 17%, a cumulative reduction of 40%. Edge addition is limited to the same ECSR shard, avoiding the risk of cross-shard edge conflicts. Furthermore, two-stage reordering improves the scheduling efficiency of the optimized graph. Regarding cache hit rate, pruning reduces feature access to redundant edges, increasing the hit rate of the combined buffer from 62% to 78%. Edge addition enhances feature reuse within the community, further increasing the hit rate to 84%, a cumulative improvement of 35%. This is because supplementary edges within the same shard make neighboring node features more easily accessed consecutively, reducing cache replacement frequency. In addition, the impact of graph structure reshaping varies across different datasets: the RAW conflict rate on the Reddit dataset is reduced by 38%, and the cache hit rate is improved by 32%, while the Dblp dataset, due to its dense connections, only sees a 25% reduction in conflict rate and a 20% improvement in hit rate, but this is still significantly better than the unoptimized baseline architecture.

[0059] In summary, addressing the bottlenecks of existing GNN accelerators in graph topology adaptability, computational resource utilization, and model support, this embodiment of a graph neural network accelerator based on topology reconstruction and dynamic early termination (ReE-GNN) executes a hardware-aware topology optimization strategy through a graph preprocessing module. Through a two-stage operation of semantically aware pruning and hardware-aware regularization and filling, the graph structure is reshaped while preserving semantic information, maximizing the proportion of in-page accesses and reducing memory access conflicts. This embodiment's accelerator integrates a dynamic node-level early termination mechanism, focusing on node-level convergence determination during the composition phase. It employs convergence confidence evaluation and feature freezing strategies to avoid aggregation dependency conflicts while removing invalid computations and improving computational resource utilization. Finally, this embodiment's device includes a multi-variant heterogeneous processing unit, flexibly supporting mainstream GNN models such as GraphSage, GIN, and GAT while maintaining optimal GCN inference efficiency. Experimental results show that ReE-GNN achieves up to 35.7x, 9.8x, 7.5x and 4.6x performance speedup compared to HyGCN, GCNAX, MEGA and DCSR-GCN on six datasets (Cora, Citeseer, Pubmed, Dblp, Nell, and Reddit) and four GNN models, respectively, and up to 42.3x, 6.7x, 5.9x and 3.8x reduction in DRAM memory accesses, with accuracy loss controlled within 3%.

[0060] In addition, this embodiment also provides a computer device including a microprocessor and an accelerator interconnected, wherein the accelerator is the graph neural network accelerator based on topology reconstruction and dynamic early regression.

[0061] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A graph neural network accelerator based on topology reconstruction and dynamic early retirement, characterized in that, It includes an interconnected graph preprocessing module and an accelerator body. The graph preprocessing module is used to reshape the original sparse graph structure data through semantically aware alignment pruning and hardware-aware topology enhancement and send it into the accelerator body to achieve accelerated execution of the original sparse graph structure data. The graph preprocessing module includes: The feature preprocessor is used to perform a linear transformation on the initial features of each node in the original sparse graph structure data using the parameters of the first layer of the graph neural network to obtain preprocessed features. The pruning tool is used to calculate the address distance between the two nodes corresponding to each edge in the original sparse graph structure data and the similarity between the preprocessed features. The edges are then filtered based on the threshold of address distance and similarity between preprocessed features to obtain a set of filtered edges. The community divider is used to divide the nodes into communities using a preset community detection algorithm, based on the filtered edge set and the original sparse graph structure data node set. The topology optimizer performs sharding operations on a set of communities, with each community corresponding to an ECSR shard; for each ECSR shard, it iterates through each node within it. And filter candidate nodes that meet the following conditions. (1) Node With nodes Belonging to the same community; (2) Node With nodes Currently not adjacent; (3) Nodes With nodes The similarity between the preprocessed features is greater than a preset threshold; for each slice, traverse each node within it. And in all its candidate nodes Select the candidate nodes with the highest similarity of preprocessed features. Multiple candidate nodes selected respectively With nodes Establish edges between the filtered edges and add them to the supplementary edge set; merge the filtered edge set and the supplementary edge set to obtain the final edge set; The encoder is used to encode the optimized graph structure data, which consists of the final set of edges and the set of nodes of the original sparse graph structure data, into ECSR format and enable the expansion degree digital segment to obtain optimized graph structure data in ECSR format. The accelerator body includes an aggregation engine and a combination engine. The combination engine includes a confidence evaluation unit for evaluating the convergence confidence of nodes during the inference process of the graph neural network, and a node is identified as an early termination node when its convergence confidence is greater than or equal to a preset confidence threshold.

2. The graph neural network accelerator based on topology reconstruction and dynamic early retirement according to claim 1, characterized in that, The feature preprocessor uses the parameters of the first layer of the graph neural network to perform a linear transformation on the initial features of the nodes to obtain the preprocessed features. The functional expression is as follows: ； in, For nodes Preprocessing features, and These represent the weights and biases in the parameters of the first layer of the graph neural network. For nodes The original characteristics.

3. The graph neural network accelerator based on topology reconstruction and dynamic early retirement according to claim 1, characterized in that, The function expression for the pruning tool to filter edges based on a threshold of address distance and similarity between preprocessed features is as follows: and ; in, For nodes and nodes Cosine similarity between preprocessed features The threshold for cosine similarity. and They are nodes and nodes Preprocessing features, and They are nodes and nodes address, This is the address span threshold.

4. The graph neural network accelerator based on topology reconstruction and dynamic early retirement according to claim 1, characterized in that, The accelerator body also includes a hierarchical storage unit and a global configuration controller. The aggregation engine is used to perform sparse neighbor aggregation calculations for graph neural networks, including a SIMD processor array. The combination engine is used to perform node feature transformations and nonlinear mappings for graph neural networks, including a systolic array. The hierarchical storage unit includes a high-bandwidth memory, a weight buffer, a feature buffer, an edge buffer, a combination buffer, and an aggregation buffer. The weight buffer and feature buffer are respectively connected to the high-bandwidth memory to obtain the weights and features stored in the high-bandwidth memory. The output of the combination engine is connected to the aggregation engine through the combination buffer to output the calculation results of the combination engine to the aggregation engine after passing through the combination buffer. The high-bandwidth memory is connected to the aggregation engine through the edge buffer to provide edge data to the aggregation engine. The output of the aggregation engine is connected to the high-bandwidth memory through the aggregation buffer to write the results of sparse neighbor aggregation calculations back to the high-bandwidth memory through the aggregation buffer. The global configuration controller is used to allocate computing tasks and schedule system resources for the aggregation engine and the combination engine.

5. The graph neural network accelerator based on topology reconstruction and dynamic early retirement according to claim 4, characterized in that, For any node The confidence assessment unit performs node convergence confidence assessment, which includes: obtaining node... The output feature vector of the combination stage, calculated in the combination engine, is mapped to the probability space by approximate softmax for each dimension of the output feature vector of the combination stage: ； in, For graph neural networks The layer outputs the i-th dimension feature in the feature vector during the combination stage. Feature representation after mapping to probability space for The ReLU activation results A constant used to prevent the denominator from being zero. for The ReLU activation results For graph neural networks In the layer combination stage, the j-th dimension of the output feature vector is selected; in the feature representation after mapping each dimension of the output feature vector to the probability space, the maximum value is selected as the node. In the graph neural network Convergence confidence of the layer If any node In the graph neural network Convergence confidence of the layer Greater than or equal to the preset confidence threshold Then determine the node Convergence, node For early termination nodes, node The combined stage outputs feature vectors The features are frozen; the hierarchical storage unit includes a freeze buffer for storing frozen features. The input of the freeze buffer is connected to the combination engine, and the output is connected to the aggregation engine to output the frozen features calculated by the combination engine to the aggregation engine. The function expression for the aggregation engine to perform sparse neighbor aggregation calculation of the graph neural network is: ； in, For nodes The aggregation results For nodes The set of neighboring nodes Size, For nodes In the graph neural network The layer combination stage outputs feature vectors. For nodes The set of neighboring nodes Early retirement node The weighting coefficients, Early departure node In the graph neural network The layer combination stage outputs feature vectors. , Early departure node The early termination layer index, and the conditions for the aggregation engine to trigger early termination are: ； in, For nodes In the graph neural network The early termination status of a layer, with values ​​of 1 and 0 indicating whether early termination is performed; For nodes In the graph neural network Convergence confidence of the layer For graph neural networks The convergence confidence threshold of the layer, "for or logic, For nodes In the graph neural network The set of neighboring nodes that have retired early Size, The threshold for the proportion of neighbors leaving early.

6. The graph neural network accelerator based on topology reconstruction and dynamic early retirement according to claim 5, characterized in that, The frozen buffer includes multiple storage blocks, each with an independent cache to support parallel access; the frozen buffer and the combined buffer are connected to the aggregation engine through a multiplexer to select one of the frozen features calculated by the combined engine and the ordinary features stored in the combined buffer to output to the aggregation engine.

7. The graph neural network accelerator based on topology reconstruction and dynamic early retirement according to claim 4, characterized in that, The aggregation engine includes a sampling processing unit for randomly selecting k neighboring nodes from optimized graph structure data in ECSR format and generating an index for the aggregation engine to access. The sampling processing unit includes a sampling controller, a pseudo-random number generator, and an out-of-order memory access controller. The sampling controller specifies the number of samples for the pseudo-random number generator via a configuration signal. The pseudo-random number generator uses a linear feedback shift register and is used when the degree of a node is greater than or equal to the number of layers in the graph neural network. The sampling index for the set of neighboring nodes is randomly assigned at any time; the out-of-order memory access controller is used to convert the out-of-order sampling index generated by the pseudo-random number generator into an ordered address within the ECSR fragment.

8. The graph neural network accelerator based on topology reconstruction and dynamic early retirement according to claim 4, characterized in that, The aggregation engine includes an edge feature processing unit for fusing and transforming edge features and node features. The edge feature processing unit consists of an edge weight multiplier and a feature fusion unit. The edge weight multiplier uses a 16-bit fixed-point multiplier to support element-wise multiplication of edge features and node features. The feature fusion unit is used to support additive fusion of node features and edge features, and outputs the fused feature vector for use by the aggregation engine.

9. The graph neural network accelerator based on topology reconstruction and dynamic early retirement according to claim 4, characterized in that, The aggregation engine includes an attention processing unit for calculating attention coefficients between nodes and performing weighted aggregation. The attention processing unit includes a feature input and mapping module, a score calculation module, an aggregation and normalization module, a weighted aggregation and multi-head output module, and a multi-head connector. The feature input and mapping module maps input features and weights to a low-dimensional space through a fully connected layer. The score calculation module concatenates the input features and maps them to attention scores through a fully connected layer. The aggregation and normalization module normalizes the attention scores to attention coefficients using an approximate softmax calculation. The weighted aggregation and multi-head output module multiplies the attention coefficients with the original features using multiple multipliers and then sums the results using a summation tree to obtain the aggregated features of each attention head. The multi-head connector connects the aggregated features of each attention head to obtain the final aggregated node feature vector.

10. A computer device comprising a microprocessor and an accelerator interconnected, characterized in that, The accelerator is the graph neural network accelerator based on topology reconstruction and dynamic early termination as described in any one of claims 1 to 9.

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