Vertical cavity surface emitting laser and method of manufacturing the same

Abstract

This invention provides a vertical-cavity surface-emitting laser (VCSEL) and its manufacturing method. The VCSEL includes: a substrate; an epitaxial structure comprising an N-type DBR layer, an active layer, an oxide confinement layer, and a P-type DBR layer stacked on the substrate from bottom to top, wherein the unoxidized region of the oxide confinement layer defines the emission port of the VCSEL; a first insulating dielectric layer formed on the epitaxial structure; an N-interconnect formed between the substrate and the epitaxial structure, wherein the N-interconnect partially overlaps with the emission port in a direction perpendicular to the top surface of the substrate, and an N-electrode electrically leads upward from the top surface of the N-interconnect to the top surface of the first insulating dielectric layer; and a P-interconnect and / or a P-electrode formed on the top surface of the first insulating dielectric layer, wherein the P-interconnect and / or the P-electrode penetrates the first insulating dielectric layer to be electrically connected to the P-type DBR layer, and the P-interconnect and the P-electrode are electrically connected. The technical solution of this invention reduces the distance between the centers of adjacent light-emitting units, thereby increasing the photocurrent density and improving the power.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a vertical cavity surface-emitting laser and its manufacturing method. Background Technology

[0002] A two-dimensional addressable vertical-cavity surface-emitting laser (VCSEL) contains an array of multiple light-emitting units. Each light-emitting unit contains an array of multiple light-emitting ports. N-electrodes and N-interconnects are arranged around the light-emitting ports, resulting in a large distance (i.e., pitch) between the centers of two adjacent light-emitting units, which in turn leads to a low photocurrent density and low power. Summary of the Invention

[0003] The purpose of this invention is to provide a vertical cavity surface-emitting laser and its manufacturing method, which reduces the distance between the centers of adjacent light-emitting units, thereby increasing the photocurrent density and power.

[0004] To achieve the above objectives, the present invention provides a vertical-cavity surface-emitting laser, comprising:

[0005] Base;

[0006] The epitaxial structure includes an N-type DBR layer, an active layer, an oxide confinement layer, and a P-type DBR layer stacked from bottom to top on the substrate, wherein the unoxidized region of the oxide confinement layer defines the output port of the vertical cavity surface-emitting laser.

[0007] A first insulating dielectric layer is formed on the epitaxial structure;

[0008] N-interconnects and N-electrodes, wherein the N-interconnects are formed between the substrate and the epitaxial structure, the N-interconnects partially overlap with the light outlet in a direction perpendicular to the top surface of the substrate, and the N-electrodes are electrically led upward from the top surface of the N-interconnects to the top surface of the first insulating dielectric layer;

[0009] P interconnects and P electrodes are formed on the top surface of the first insulating dielectric layer, and the P interconnects and / or the P electrodes penetrate the first insulating dielectric layer to be electrically connected to the P-type DBR layer, and the P interconnects are electrically connected to the P electrodes.

[0010] Optionally, the substrate includes a first substrate and a bonding layer stacked from bottom to top.

[0011] Optionally, the first substrate is made of silicon.

[0012] Optionally, the epitaxial structure further includes an N-type epitaxial layer formed between the substrate and the N-type DBR layer.

[0013] Optionally, the epitaxial structure further includes a capping layer formed between the P-type DBR layer and the first insulating dielectric layer.

[0014] Optionally, the vertical-cavity surface-emitting laser further includes:

[0015] A first annular via penetrates the P-type DBR layer, the oxide confinement layer, and the active layer and enters the N-type DBR layer. A portion of the oxide confinement layer on the sidewall of the first via is an oxidized region. The N-interconnect and the P-interconnect partially overlap with the first via in a direction perpendicular to the top surface of the substrate.

[0016] A second insulating dielectric layer fills the first through-hole.

[0017] Optionally, the vertical-cavity surface-emitting laser further includes:

[0018] A second annular through-hole surrounds the first through-hole and penetrates the epitaxial structure. A portion of the oxide confinement layer on the sidewall of the second through-hole is an oxidized region. The P electrode partially overlaps with the second through-hole in a direction perpendicular to the top surface of the substrate.

[0019] The third insulating dielectric layer fills the second through-hole.

[0020] Optionally, the vertical-cavity surface-emitting laser further includes:

[0021] A passivation layer covers the first insulating dielectric layer and the P interconnect, and extends to a portion of the top surface of the N electrode and a portion of the top surface of the P electrode.

[0022] The present invention also provides a method for manufacturing a vertical-cavity surface-emitting laser, comprising:

[0023] An epitaxial structure is formed on a substrate, and an N-interconnect is formed between the substrate and the epitaxial structure. The epitaxial structure includes an N-type DBR layer, an active layer, an oxide confinement layer, and a P-type DBR layer stacked from bottom to top. The unoxidized region of the oxide confinement layer defines the exit port of the vertical cavity surface emitter laser. The N-interconnect partially overlaps with the exit port in a direction perpendicular to the top surface of the substrate.

[0024] A first insulating dielectric layer is formed on the epitaxial structure;

[0025] An N-electrode, a P-interconnect, and a P-electrode are formed. The N-electrode is electrically led upward from the top surface of the N-interconnect to the top surface of the first insulating dielectric layer. The P-interconnect and the P-electrode are formed on the top surface of the first insulating dielectric layer, and the P-interconnect and / or the P-electrode penetrates the first insulating dielectric layer to be electrically connected to the P-type DBR layer. The P-interconnect is electrically connected to the P-electrode.

[0026] Optionally, the steps of forming the epitaxial structure on the substrate and forming the N-interconnect include:

[0027] A second substrate is provided, on which a P-type DBR layer, a confinement layer, an active layer and an N-type DBR layer are formed in a bottom-to-top stacked manner;

[0028] N-interconnects are formed on a portion of the N-type DBR layer;

[0029] A second bonding layer is formed on the N-type DBR layer and the N interconnect;

[0030] A first substrate is provided, and a first bonding layer is formed on the first substrate;

[0031] The side of the second bonding layer away from the second substrate is bonded to the side of the first bonding layer away from the first substrate;

[0032] Peel off the second substrate;

[0033] A first via is formed that penetrates the P-type DBR layer, the confinement layer, and the active layer and enters the N-type DBR layer. The first via is annular.

[0034] A portion of the confinement layer on the sidewall of the first via is oxidized to form an oxide layer. The remaining confinement layer and the oxide layer after oxidation constitute an oxide confinement layer. The N interconnect and the P interconnect partially overlap with the first via in a direction perpendicular to the top surface of the substrate.

[0035] Optionally, the first substrate is made of silicon, and the second substrate is made of GaAs.

[0036] Optionally, the method for manufacturing the vertical-cavity surface-emitting laser further includes:

[0037] A second through hole is formed around and surrounds the first through hole, and the second through hole penetrates the epitaxial structure;

[0038] The limiting layer on the sidewall of the second via is oxidized, and the P electrode partially overlaps with the second via in a direction perpendicular to the top surface of the substrate.

[0039] Optionally, the method for manufacturing the vertical-cavity surface-emitting laser further includes:

[0040] A second insulating dielectric layer is filled in the first through hole, and a third insulating dielectric layer is filled in the second through hole.

[0041] Optionally, the method for manufacturing the vertical-cavity surface-emitting laser further includes:

[0042] A passivation layer is formed to cover the first insulating dielectric layer and the P interconnect, and extends to a portion of the top surface of the N electrode and a portion of the top surface of the P electrode.

[0043] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0044] 1. The vertical-cavity surface-emitting laser of the present invention comprises: a substrate; an epitaxial structure including an N-type DBR layer, an active layer, an oxide confinement layer, and a P-type DBR layer stacked from bottom to top on the substrate, wherein the unoxidized region of the oxide confinement layer defines the light emission port of the vertical-cavity surface-emitting laser; a first insulating dielectric layer formed on the epitaxial structure; an N-interconnect and an N-electrode, wherein the N-interconnect is formed between the substrate and the epitaxial structure, the N-interconnect partially overlaps with the light emission port in a direction perpendicular to the top surface of the substrate, and the N-electrode is electrically led upward from the top surface of the N-interconnect to the top surface of the first insulating dielectric layer; and a P-interconnect and a P-electrode formed on the top surface of the first insulating dielectric layer, wherein the P-interconnect and / or the P-electrode penetrates the first insulating dielectric layer to be electrically connected to the P-type DBR layer, and the P-interconnect is electrically connected to the P-electrode. This reduces the distance between the centers of adjacent light-emitting units, thereby increasing the photocurrent density and improving the power.

[0045] 2. The method for manufacturing a vertical-cavity surface-emitting laser (VCSEL) of the present invention includes: forming an epitaxial structure on a substrate; forming an N-interconnect between the substrate and the epitaxial structure; the epitaxial structure comprising an N-type DBR layer, an active layer, an oxide confinement layer, and a P-type DBR layer stacked from bottom to top; the unoxidized region of the oxide confinement layer defining the light exit port of the VCSEL; the N-interconnect partially overlapping the light exit port in a direction perpendicular to the top surface of the substrate; forming a first insulating dielectric layer on the epitaxial structure; forming an N-electrode, a P-interconnect, and a P-electrode; the N-electrode being electrically led upwards from the top surface of the N-interconnect to the top surface of the first insulating dielectric layer; the P-interconnect and the P-electrode being formed on the top surface of the first insulating dielectric layer; and the P-interconnect and / or the P-electrode penetrating the first insulating dielectric layer to be electrically connected to the P-type DBR layer; the P-interconnect being electrically connected to the P-electrode. This reduces the distance between the centers of adjacent light-emitting units, thereby increasing the photocurrent density and power. Attached Figure Description

[0046] Figure 1 This is a top view schematic diagram of a vertical cavity surface-emitting laser according to an embodiment of the present invention;

[0047] Figure 2 This is a cross-sectional schematic diagram of a vertical cavity surface-emitting laser according to an embodiment of the present invention;

[0048] Figure 3 This is a flowchart of a method for manufacturing a vertical cavity surface-emitting laser according to an embodiment of the present invention.

[0049] Among them, the appendix Figures 1-3 The annotations in the attached figures are explained as follows:

[0050] 101-First substrate; 102-Bonding layer; 121-N-type epitaxial layer; 122-N-type DBR layer; 123-Active layer; 1241-Confinement layer; 1242-Oxide layer; 125-P-type DBR layer; 126-Capping layer; 13-First insulating dielectric layer; 141-First via; 142-Second via; 143-Third via; 151-First insulating layer; 152-Second insulating layer; 153-Third insulating layer; 154-Fourth insulating layer; 161-N interconnect; 162-N electrode; 171-P interconnect; 172-P electrode; 18-Passivation layer; L1-Light emission port. Detailed Implementation

[0051] To make the objectives, advantages, and features of the present invention clearer, the vertical-cavity surface-emitting laser and its manufacturing method proposed in this invention will be described in further detail below. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0052] An embodiment of the present invention provides a vertical-cavity surface-emitting laser (VCSEL), comprising: a substrate; an epitaxial structure including an N-type DBR layer, an active layer, an oxide confinement layer, and a P-type DBR layer stacked from bottom to top on the substrate, wherein an unoxidized region of the oxide confinement layer defines the output port of the VCSEL; a first insulating dielectric layer formed on the epitaxial structure; an N-interconnect and an N-electrode, wherein the N-interconnect is formed between the substrate and the epitaxial structure, the N-interconnect partially overlaps with the output port in a direction perpendicular to the top surface of the substrate, and the N-electrode is electrically led upward from the top surface of the N-interconnect to the top surface of the first insulating dielectric layer; and a P-interconnect and a P-electrode formed on the top surface of the first insulating dielectric layer, wherein the P-interconnect and / or the P-electrode penetrates the first insulating dielectric layer to be electrically connected to the P-type DBR layer, and the P-interconnect is electrically connected to the P-electrode.

[0053] See below. Figure 1 and Figure 2The vertical-cavity surface-emitting laser of this embodiment will be described in more detail, wherein, Figure 2 The A1 region in the text is Figure 1 A cross-sectional view along the AA' direction. Figure 2 The B1 region is Figure 1 A cross-sectional view along the BB' direction. Figure 2 The C1 region is Figure 1 A cross-sectional view along the CC' direction; it should be noted that, in Figure 1 In order to clearly illustrate the wiring location of N interconnect 161, P interconnect 171, which is located outside the area of ​​the optical output port L1, is shown below N interconnect 161.

[0054] The substrate includes a first substrate 101 and a bonding layer 102 stacked from bottom to top.

[0055] In one embodiment, the material of the first substrate 101 has better heat dissipation properties than GaAs, thereby improving heat dissipation efficiency, reducing power consumption, and increasing power output. For example, the material of the first substrate 101 can be silicon, silicon carbide, or copper tungsten alloy (CuW), etc.

[0056] In one embodiment, the bonding layer 102 is made of silicon oxide.

[0057] In one embodiment, the bonding layer 102 includes a first bonding layer and a second bonding layer stacked from bottom to top.

[0058] The epitaxial structure includes an N-type DBR layer 122, an active layer 123, an oxide confinement layer, and a P-type DBR layer 125 stacked from bottom to top on the substrate. The unoxidized region of the oxide confinement layer defines the output port L1 of the vertical cavity surface emitter laser.

[0059] The oxidation confinement layer includes a confinement layer 1241 and an oxide layer 1242. The confinement layer 1241 is an unoxidized region, and the oxide layer 1242 is an oxidized region. The oxidized region is annular and surrounds the unoxidized region.

[0060] In one embodiment, the confinement layer 1241 is an aluminum compound layer, and the oxide layer 1242 is an aluminum oxide compound layer. The aluminum compound layer is, for example, AlGaAs.

[0061] In one embodiment, the epitaxial structure further includes an N-type epitaxial layer 121 formed between the substrate and the N-type DBR layer 122. The N-type epitaxial layer 121 serves as an ohmic contact to reduce contact resistance.

[0062] In one embodiment, the epitaxial structure further includes a capping layer 126 formed on the P-type DBR layer 125.

[0063] The N-type epitaxial layer 121 and the N-type DBR layer 122 are doped with N-type materials, and the P-type DBR layer 125 and the capping layer 126 are doped with P-type materials. The N-type dopant can be at least one of elements such as Si, Ge, and Sn, and the P-type dopant can be at least one of elements such as C, Mg, Zn, Ca, Sr, and Ba.

[0064] The N-type epitaxial layer 121, the N-type DBR layer 122, the P-type DBR layer 125, and the capping layer 126 are heavily doped.

[0065] The active layer 123 may include multiple pairs of quantum well composite layers, and the quantum well composite layers may include alternating barriers and potential wells.

[0066] The N-type epitaxial layer 121 and the N-type DBR layer 122 can be made of at least one of AlGaAs, GaN, AlGaN, GaAs, AlGaInP, and SiC; the active layer 123 can be made of at least one of AlN, GaN, AlGaN, InGaN, AlInGaN, GaAs, AlGaInP, and SiC; the P-type DBR layer 125 can be made of at least one of AlGaAs, GaN, AlGaN, BAlN, GaAs, AlGaInP, and SiC; and the capping layer 126 can be made of at least one of GaAs, InGaAs, GaN, AlGaN, InGaN, and InGaAsN.

[0067] A first insulating dielectric layer 13 is formed on the epitaxial structure.

[0068] The first insulating dielectric layer 13 may include a single-layer structure or a structure of at least two stacked layers.

[0069] The capping layer 126 is formed between the P-type DBR layer 125 and the first insulating dielectric layer 13.

[0070] In one embodiment, the vertical-cavity surface-emitting laser further includes:

[0071] An annular first through-hole 141 penetrates the P-type DBR layer 125, the oxide confinement layer, and the active layer 123 and enters the N-type DBR layer 122. A portion of the oxide confinement layer on the sidewall of the first through-hole 141 is an oxidized region. The first through-hole 141 also penetrates the first insulating dielectric layer 13 and the capping layer 126.

[0072] The second insulating dielectric layer fills the first through-hole 141.

[0073] In one embodiment, the vertical-cavity surface-emitting laser further includes:

[0074] An annular second through-hole 142 surrounds the first through-hole 141 and penetrates the epitaxial structure. A portion of the oxide limiting layer on the sidewall of the second through-hole 142 is an oxidized region. The second through-hole 142 also penetrates the first insulating dielectric layer 13 and the capping layer 126.

[0075] The third insulating dielectric layer fills the second through-hole 142.

[0076] In one embodiment, the second via 142 may include a first sub-via and a second sub-via. The first sub-via penetrates the first insulating dielectric layer 13, the capping layer 126, the P-type DBR layer 125, the oxide confinement layer, and the active layer 123, and enters the N-type DBR layer 122. The second sub-via extends downward from the bottom wall of the first sub-via, penetrating the N-type DBR layer 122 and the N-type epitaxial layer 121. The width of the first sub-via is greater than the width of the second sub-via. The depth of the first sub-via may be the same as the depth of the first via 141.

[0077] In one embodiment, the second insulating dielectric layer includes a first insulating layer 151 and a third insulating layer 153, wherein the first insulating layer 151 is formed on the inner wall of the first through hole 141, and the third insulating layer 153 fills the first through hole 141.

[0078] In one embodiment, the third insulating dielectric layer includes a second insulating layer 152 and a third insulating layer 153, wherein the second insulating layer 152 is formed on the inner wall of the second through hole 142, and the third insulating layer 153 fills the second through hole 142.

[0079] N-interconnect 161 is electrically connected to N-electrode 162. N-interconnect 161 is formed between the substrate and the epitaxial structure. N-interconnect 161 partially overlaps with the light exit port L1 in a direction perpendicular to the top surface of the substrate. N-electrode 162 is electrically led upwards from the top surface of N-interconnect 161 to the top surface of the first insulating dielectric layer 13. N-interconnect 161 is electrically connected to the N-type epitaxial layer 121 and the N-type DBR layer 122.

[0080] In one embodiment, the vertical cavity surface emitter laser further includes a third via 143 that penetrates the first insulating dielectric layer 13 and the epitaxial structure to expose a portion of the N interconnect 161. A fourth insulating layer 154 is formed on the sidewall of the third via 143. The N electrode 162 fills the third via 143 and extends to the first insulating dielectric layer 13 surrounding the third via 143.

[0081] P-interconnect 171 and P-electrode 172 are formed on the top surface of the first insulating dielectric layer 13, and the P-interconnect 171 and / or the P-electrode 172 penetrate the first insulating dielectric layer 13 to be electrically connected to the P-type DBR layer 125. The P-interconnect 171 and the P-electrode 172 are electrically connected. The P-interconnect 171 and / or the P-electrode 172 also penetrate the capping layer 126.

[0082] In one embodiment, the first insulating dielectric layer 13 is formed on the capping layer 126 surrounding the first through hole 141, the second through hole 142 and the third through hole 143.

[0083] In one embodiment, the first insulating dielectric layer 13, the first insulating layer 151, the second insulating layer 152, and the fourth insulating layer 154 may include a single sub-insulating layer or at least two stacked sub-insulating layers. The material of the sub-insulating layer may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0084] The material of the third insulating layer 153 may include organic insulating materials, such as polyimide.

[0085] In one embodiment, the vertical-cavity surface-emitting laser includes a plurality of light-emitting units arranged in an array, each light-emitting unit including a plurality of light-emitting ports L1 arranged in an array. The third insulating dielectric layer in the second via 142 serves as an isolation structure to isolate adjacent light-emitting units. The N-interconnect 161 and the P-interconnect 171 are arranged in the region of the light-emitting unit. The N-electrode 162 and the P-electrode 172 are located around the light-emitting unit (i.e., around the second via 142). The N-interconnect 161 extends to the third via 142. The periphery of the second through-hole 142 is electrically connected to the N electrode 162. The P interconnect 171 extends to the periphery of the second through-hole 142, or the P electrode 172 extends to the light-emitting unit region, such that the P interconnect 171 is electrically connected to the P electrode 172. The N interconnect 161, the P interconnect 171, and the first through-hole 141 partially overlap in a direction perpendicular to the top surface of the substrate. The P interconnect 171 or the P electrode 172 and the second through-hole 142 partially overlap in a direction perpendicular to the top surface of the substrate.

[0086] exist Figure 1 In the illustrated embodiment, three light-emitting units are arranged along the first direction X, and four light-emitting units are arranged along the second direction Y. That is, the vertical cavity surface-emitting laser includes an array of three light-emitting units. 4 = 12 light-emitting units, each of which includes 3 arrayed units. 2 = 6 light-emitting ports L1 (i.e., 3 light-emitting ports L1 arranged along the first direction X and 2 light-emitting ports L1 arranged along the second direction Y); adjacent light-emitting units arranged along the first direction X are isolated by the third insulating dielectric layer in the second through-hole 142, while adjacent light-emitting units arranged along the second direction Y are not isolated by the third insulating dielectric layer in the second through-hole 142; each light-emitting unit area is provided with multiple N interconnect lines 161, with multiple N interconnect lines 161 extending in the first direction X spaced apart along the second direction Y, and multiple N interconnect lines 161 extending in the second direction Y spaced apart along the first direction X; both the N interconnect lines 161 extending in the first direction X and the N interconnect lines 161 extending in the second direction Y extend below the light-emitting ports L1 and below the first through-hole 141; the multiple N interconnect lines 161 extending in the first direction X and the multiple N interconnect lines 161 extending in the second direction Y intersect and are relatively close to each other. The intersection is located below the light outlet L1; the N interconnects 161 extending in the first direction X of adjacent light-emitting unit regions are not connected, while the N interconnects 161 extending in the second direction Y of adjacent light-emitting unit regions are connected. The N interconnects 161 extending in the second direction Y also extend to the periphery of the second through-hole 142, so that the N interconnects 161 extending in the second direction Y are electrically connected to the N electrode 162 on the periphery of the second through-hole 142; each light-emitting unit region is provided with a P interconnect 171, which is located on the periphery of the light outlet L1. The P interconnects 171 of adjacent light-emitting unit regions arranged in the first direction X are connected, while the P interconnects 171 of adjacent light-emitting unit regions arranged in the second direction Y are not connected. The P electrode 172 extends from above the second through-hole 142 to the periphery of the second through-hole 142, and the P interconnects 171 extending in the first direction X are connected to the P electrode 172. Wherein, the first direction X is perpendicular to the second direction Y.

[0087] It should be noted that, although Figure 2 The A1 region in the text is Figure 1 A schematic cross-sectional view along the AA' direction, however, Figure 2 The A1 area in the diagram represents Figure 1 The structure in the first direction X contains only one light-emitting unit (i.e. Figure 2 The second through hole 142 on the right side and the P electrode 172 on the right side correspond to... Figure 1 (The cross-section at the DD' position in the middle).

[0088] The vertical-cavity surface-emitting laser further includes a passivation layer 18 covering the first insulating dielectric layer 13 and the P-interconnect 171, wherein the passivation layer 18 extends to a portion of the top surface of the N-electrode 162 and a portion of the top surface of the P-electrode 172. The exposed portions of the top surfaces of the N-electrode 162 and the P-electrode 172 by the passivation layer 18 are used for subsequent testing or wire bonding.

[0089] As can be seen from the above, the vertical cavity surface-emitting laser provided by the present invention includes an epitaxial structure comprising an N-type DBR layer, an active layer, an oxide confinement layer, and a P-type DBR layer stacked on the substrate from bottom to top. The unoxidized region of the oxide confinement layer defines the light emission port of the vertical cavity surface-emitting laser. The N interconnect is formed between the substrate and the epitaxial structure. The N interconnect partially overlaps with the light emission port in a direction perpendicular to the top surface of the substrate. The N electrode is electrically led upward from the top surface of the N interconnect to the top surface of the first insulating dielectric layer. That is, the N interconnect is arranged below the region of the light emission port. Part of the N interconnect and the light emission port share the area of ​​the substrate, which reduces the distance between adjacent light emission ports, thereby reducing the area of ​​the light-emitting unit and the distance (i.e., pitch) between the centers of adjacent light-emitting units, thus increasing the photocurrent density and improving the power.

[0090] One embodiment of the present invention provides a method for manufacturing a vertical-cavity surface-emitting laser, see reference. Figure 3 , Figure 3 This is a flowchart of a method for manufacturing a vertical-cavity surface-emitting laser according to an embodiment of the present invention, the method comprising:

[0091] Step S1: Form an epitaxial structure on a substrate and form an N-interconnect between the substrate and the epitaxial structure. The epitaxial structure includes an N-type DBR layer, an active layer, an oxide confinement layer, and a P-type DBR layer stacked from bottom to top. The unoxidized region of the oxide confinement layer defines the exit port of the vertical cavity surface emitter laser. The N-interconnect partially overlaps with the exit port in a direction perpendicular to the top surface of the substrate.

[0092] Step S2: Form a first insulating dielectric layer on the epitaxial structure;

[0093] Step S3: Form an N electrode, a P interconnect, and a P electrode. The N electrode is electrically led upward from the top surface of the N interconnect to the top surface of the first insulating dielectric layer. The P interconnect and the P electrode are formed on the top surface of the first insulating dielectric layer, and the P interconnect and / or the P electrode penetrate the first insulating dielectric layer to be electrically connected to the P-type DBR layer. The P interconnect is electrically connected to the P electrode.

[0094] See below. Figure 1 and Figure 2 The manufacturing method of the vertical cavity surface-emitting laser provided in this embodiment is described in more detail.

[0095] According to step S1, an epitaxial structure is formed on the substrate, and an N-interconnect 161 is formed between the substrate and the epitaxial structure. The epitaxial structure includes an N-type DBR layer 122, an active layer 123, an oxide confinement layer, and a P-type DBR layer 125 stacked from bottom to top. The unoxidized region of the oxide confinement layer defines the output port L1 of the vertical cavity surface emitter laser. The N-interconnect 161 and the output port L1 partially overlap in a direction perpendicular to the top surface of the substrate.

[0096] In one embodiment, the steps of forming an epitaxial structure on a substrate and forming an N-interconnect 161 include:

[0097] A second substrate (not shown) is provided, on which a P-type DBR layer 125, a confinement layer 1241, an active layer 123 and an N-type DBR layer 122 are formed from bottom to top.

[0098] N-interconnects 161 are formed on a portion of the N-type DBR layer 122;

[0099] A second bonding layer is formed on the N-type DBR layer 122 and the N-interconnect 161;

[0100] A first substrate 101 is provided, and a first bonding layer is formed on the first substrate 101;

[0101] The side of the second bonding layer away from the second substrate is bonded to the side of the first bonding layer away from the first substrate 101; wherein, the first bonding layer and the second bonding layer after bonding constitute the bonding layer 102;

[0102] Peel off the second substrate;

[0103] A first via 141 is formed that penetrates the P-type DBR layer 125, the confinement layer 1241 and the active layer 123 and enters the N-type DBR layer 122. The first via 141 is annular.

[0104] The portion of the limiting layer 1241 on the sidewall of the first through hole 141 is oxidized to form an oxide layer 1242.

[0105] After oxidizing a portion of the limiting layer 1241 on the sidewall of the first via 141, the method for manufacturing the vertical cavity surface-emitting laser further includes filling the first via 141 with a second insulating dielectric layer.

[0106] In one embodiment, a sacrificial layer (not shown) and a capping layer 126 are further formed between the second substrate and the P-type DBR layer 125, the sacrificial layer being closer to the second substrate than the capping layer 126; the sacrificial layer is also removed after the second substrate is stripped. The sacrificial layer serves as a buffer layer between the second substrate and the capping layer 126, and the first via 141 also penetrates the capping layer 126.

[0107] In one embodiment, before forming the N-interconnect 161, an N-type epitaxial layer 121 is also formed on the N-type DBR layer 122, such that the N-interconnect 161 is formed on a portion of the N-type epitaxial layer 121.

[0108] In one embodiment, the material of the first substrate 101 has better heat dissipation properties than the material of the second substrate, thereby improving heat dissipation efficiency, reducing power consumption, and increasing power output. For example, the material of the first substrate 101 may be silicon, silicon carbide, or copper tungsten alloy (CuW), and the material of the second substrate may be GaAs.

[0109] In one embodiment, the bonding layer 102 is made of silicon oxide.

[0110] The oxidation confinement layer includes a confinement layer 1241 and an oxide layer 1242 remaining after oxidation. The remaining confinement layer 1241 is an unoxidized region, and the oxide layer 1242 is an oxidized region. The oxidized region is annular, surrounding the unoxidized region.

[0111] In one embodiment, the limiting layer 1241 is an aluminum compound layer, and the oxide layer 1242 is an aluminum oxide compound layer. The aluminum compound layer is, for example, AlGaAs, which is oxidized to form Al2O3.

[0112] The N-type epitaxial layer 121 and the N-type DBR layer 122 are doped with N-type materials, and the P-type DBR layer 125 and the capping layer 126 are doped with P-type materials. The N-type dopant can be at least one of elements such as Si, Ge, and Sn, and the P-type dopant can be at least one of elements such as C, Mg, Zn, Ca, Sr, and Ba.

[0113] The N-type epitaxial layer 121, the N-type DBR layer 122, the P-type DBR layer 125, and the capping layer 126 are heavily doped.

[0114] The active layer 123 may include multiple pairs of quantum well composite layers, and the quantum well composite layers may include alternating barriers and potential wells.

[0115] The N-type epitaxial layer 121 and the N-type DBR layer 122 can be made of at least one of AlGaAs, GaN, AlGaN, GaAs, AlGaInP, and SiC; the active layer 123 can be made of at least one of AlN, GaN, AlGaN, InGaN, AlInGaN, GaAs, AlGaInP, and SiC; the P-type DBR layer 125 can be made of at least one of AlGaAs, GaN, AlGaN, BAlN, GaAs, AlGaInP, and SiC; and the capping layer 126 can be made of at least one of GaAs, InGaAs, GaN, AlGaN, InGaN, and InGaAsN.

[0116] In one embodiment, prior to forming the first via 141, the capping layer 126 may be etched to form a plurality of openings exposing a portion of the top surface of the P-type DBR layer 125, which are subsequently filled by the first insulating dielectric layer 13 and / or the second insulating dielectric layer.

[0117] According to step S2, a first insulating dielectric layer 13 is formed on the epitaxial structure.

[0118] The first insulating dielectric layer 13 may include a single-layer structure or a structure of at least two stacked layers.

[0119] According to step S3, an N-electrode 162, a P-interconnect 171, and a P-electrode 172 are formed. The N-electrode 162 is electrically led upwards from the top surface of the N-interconnect 161 to the top surface of the first insulating dielectric layer 13. The P-interconnect 171 and the P-electrode 172 are formed on the top surface of the first insulating dielectric layer 13, and the P-interconnect 171 and / or the P-electrode 172 penetrate the first insulating dielectric layer 13 to be electrically connected to the P-type DBR layer 125. The P-interconnect 171 is electrically connected to the P-electrode 172. The N-interconnect 161 is electrically connected to the N-type epitaxial layer 121 and the N-type DBR layer 122.

[0120] In one embodiment, the method for manufacturing the vertical-cavity surface-emitting laser further includes:

[0121] A second through hole 142 is formed around and surrounds the first through hole 141, and the second through hole 142 penetrates the epitaxial structure;

[0122] The portion of the limiting layer 1241 on the sidewall of the second through hole 142 is oxidized to form an oxide layer 1242.

[0123] After oxidizing a portion of the limiting layer 1241 on the sidewall of the second via 142, the method for manufacturing the vertical cavity surface-emitting laser further includes filling the second via 142 with a third insulating dielectric layer.

[0124] In one embodiment, the second via 142 may include a first sub-via and a second sub-via. The first sub-via penetrates the cap layer 126, the P-type DBR layer 125, the confinement layer 1241, and the active layer 123, and enters the N-type DBR layer 122. The second sub-via extends downward from the bottom wall of the first sub-via, penetrating the N-type DBR layer 122 and the N-type epitaxial layer 121. The width of the first sub-via is greater than the width of the second sub-via. The first sub-via may be formed simultaneously with the first via 141, and the depth of the first sub-via may be the same as the depth of the first via 141. Simultaneously, portions of the confinement layer 1241 on the sidewalls of both the first sub-via and the first via 141 are oxidized.

[0125] In one embodiment, the second insulating dielectric layer includes a first insulating layer 151 and a third insulating layer 153, wherein the first insulating layer 151 is formed on the inner wall of the first through hole 141, and the third insulating layer 153 fills the first through hole 141.

[0126] In one embodiment, the third insulating dielectric layer includes a second insulating layer 152 and a third insulating layer 153, wherein the second insulating layer 152 is formed on the inner wall of the second through hole 142, and the third insulating layer 153 fills the second through hole 142.

[0127] Before forming the N-electrode 162, the method for manufacturing the vertical-cavity surface-emitting laser further includes: forming a third via 143 penetrating the first insulating dielectric layer 13 and the epitaxial structure to expose a portion of the N-interconnect 161; forming a fourth insulating layer 154 on the inner wall of the third via 143; and etching away the fourth insulating layer 154 from the bottom wall of the third via 143. The N-electrode 162 fills the third via 143 and extends to the first insulating dielectric layer 13 surrounding the third via 143.

[0128] In one embodiment, the first insulating dielectric layer 13 is formed on the capping layer 126 surrounding the first through hole 141, the second through hole 142 and the third through hole 143.

[0129] In one embodiment, the first insulating dielectric layer 13, the first insulating layer 151, the second insulating layer 152, and the fourth insulating layer 154 may include a single sub-insulating layer or at least two stacked sub-insulating layers. The material of the sub-insulating layer may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0130] The material of the third insulating layer 153 may include organic insulating materials, such as polyimide.

[0131] In one embodiment, the step of forming the first insulating dielectric layer 13, the first insulating layer 151, the second insulating layer 152, the third insulating layer 153, and the fourth insulating layer 154 may include: after oxidizing a portion of the limiting layer 1241 on the sidewalls of the first sub-via and the first via 141, forming a first sub-insulating layer on the inner walls of the first sub-via and the first via 141 and on the top surface of the capping layer 126; and etching the first sub-insulating layer, the N-type DBR layer 122, and the N-type epitaxial layer 121 on the bottom wall of the first sub-via to form the second sub-via. Subsequently, a second sub-insulating layer is formed on the inner wall of the first through hole 141 and the second through hole 142 and on the top surface of the first sub-insulating layer on the periphery; the third insulating layer 153 is filled in the first through hole 141 and the second through hole 142; after etching the second sub-insulating layer, the first sub-insulating layer and the epitaxial structure on the periphery of the first through hole 141 and the second through hole 142 to form the third through hole 143, a third sub-insulating layer is formed on the inner wall of the third through hole 143 and on the top surface of the second sub-insulating layer on the periphery, and the third sub-insulating layer on the bottom wall of the third through hole 143 is etched away. The first insulating dielectric layer 13 may include the first sub-insulating layer, the second sub-insulating layer, and the third sub-insulating layer stacked on the top surface of the capping layer 126; or, when etching away the third sub-insulating layer on the bottom wall of the third via 143, the third sub-insulating layer on the top surface of the capping layer 126 may be etched away simultaneously, such that the first insulating dielectric layer 13 includes the first sub-insulating layer and the second sub-insulating layer; the first insulating layer 151 may include the first sub-insulating layer and the second sub-insulating layer located on the inner wall of the first via 141; the second insulating layer 152 may include the first sub-insulating layer and the second sub-insulating layer located on the inner wall of the second via 142; the fourth insulating layer 154 may include the third sub-insulating layer located on the side wall of the third via 143.

[0132] In one embodiment, since the first insulating dielectric layer 13 and / or the second insulating dielectric layer fill the opening, after etching away the fourth insulating layer 154 on the bottom wall of the third via 143, the first insulating dielectric layer 13 and / or the second insulating dielectric layer in the opening are also etched away, so that the P interconnect 171 and / or the P electrode 172 subsequently filled in the opening can be electrically connected to the P-type DBR layer 125.

[0133] In one embodiment, the N electrode 162, the P interconnect 171, and the P electrode 172 are formed by forming a metal layer in the third via 143, the opening, and the first insulating dielectric layer, and by etching the metal layer.

[0134] In one embodiment, the vertical-cavity surface-emitting laser includes a plurality of light-emitting units arranged in an array, each light-emitting unit including a plurality of light-emitting ports L1 arranged in an array. The third insulating dielectric layer in the second via 142 serves as an isolation structure to isolate adjacent light-emitting units. The N-interconnect 161 and the P-interconnect 171 are arranged in the region of the light-emitting unit. The N-electrode 162 and the P-electrode 172 are located around the light-emitting unit (i.e., around the second via 142). The N-interconnect 161 extends to the third via 142. The periphery of the second through-hole 142 is electrically connected to the N electrode 162. The P interconnect 171 extends to the periphery of the second through-hole 142, or the P electrode 172 extends to the light-emitting unit region, such that the P interconnect 171 is electrically connected to the P electrode 172. The N interconnect 161, the P interconnect 171, and the first through-hole 141 partially overlap in a direction perpendicular to the top surface of the substrate. The P interconnect 171 or the P electrode 172 and the second through-hole 142 partially overlap in a direction perpendicular to the top surface of the substrate.

[0135] exist Figure 1 In the illustrated embodiment, three light-emitting units are arranged along the first direction X, and four light-emitting units are arranged along the second direction Y. That is, the vertical cavity surface-emitting laser includes an array of three light-emitting units. 4 = 12 light-emitting units, each of which includes 3 arrayed units. 2 = 6 light-emitting ports L1 (i.e., 3 light-emitting ports L1 arranged along the first direction X and 2 light-emitting ports L1 arranged along the second direction Y); adjacent light-emitting units arranged along the first direction X are isolated by the third insulating dielectric layer in the second through-hole 142, while adjacent light-emitting units arranged along the second direction Y are not isolated by the third insulating dielectric layer in the second through-hole 142; each light-emitting unit area is provided with multiple N interconnect lines 161, with multiple N interconnect lines 161 extending in the first direction X spaced apart along the second direction Y, and multiple N interconnect lines 161 extending in the second direction Y spaced apart along the first direction X; both the N interconnect lines 161 extending in the first direction X and the N interconnect lines 161 extending in the second direction Y extend below the light-emitting ports L1 and below the first through-hole 141; the multiple N interconnect lines 161 extending in the first direction X and the multiple N interconnect lines 161 extending in the second direction Y intersect and are relatively close to each other. The intersection is located below the light outlet L1; the N interconnects 161 extending in the first direction X of adjacent light-emitting unit regions are not connected, while the N interconnects 161 extending in the second direction Y of adjacent light-emitting unit regions are connected. The N interconnects 161 extending in the second direction Y also extend to the periphery of the second through-hole 142, so that the N interconnects 161 extending in the second direction Y are electrically connected to the N electrode 162 on the periphery of the second through-hole 142; each light-emitting unit region is provided with a P interconnect 171, which is located on the periphery of the light outlet L1. The P interconnects 171 of adjacent light-emitting unit regions arranged in the first direction X are connected, while the P interconnects 171 of adjacent light-emitting unit regions arranged in the second direction Y are not connected. The P electrode 172 extends from above the second through-hole 142 to the periphery of the second through-hole 142, and the P interconnects 171 extending in the first direction X are connected to the P electrode 172. Wherein, the first direction X is perpendicular to the second direction Y.

[0136] It should be noted that, although Figure 2 The A1 region in the text is Figure 1 A schematic cross-sectional view along the AA' direction, however, Figure 2 The A1 area in the diagram represents Figure 1 The structure in the first direction X contains only one light-emitting unit (i.e. Figure 2 The second through hole 142 on the right side and the P electrode 172 on the right side correspond to... Figure 1 (The cross-section at the DD' position in the middle).

[0137] The method for manufacturing the vertical cavity surface-emitting laser further includes: forming a passivation layer 18 covering the first insulating dielectric layer 13 and the P interconnect 171, and extending to a portion of the top surface of the N electrode 162 and a portion of the top surface of the P electrode 172. The portion of the top surface of the N electrode 162 and the portion of the top surface of the P electrode 172 exposed by the passivation layer 18 is used for subsequent testing or wire bonding, etc.

[0138] As can be seen from the above, the manufacturing method of the vertical cavity surface-emitting laser provided by the present invention involves forming an epitaxial structure on a substrate and forming an N-interconnect between the substrate and the epitaxial structure. The epitaxial structure includes an N-type DBR layer, an active layer, an oxide confinement layer, and a P-type DBR layer stacked from bottom to top. The unoxidized area of ​​the oxide confinement layer defines the light emission port of the vertical cavity surface-emitting laser. The N-interconnect partially overlaps with the light emission port in a direction perpendicular to the top surface of the substrate. The N-electrode is electrically led upward from the top surface of the N-interconnect to the top surface of the first insulating dielectric layer. That is, the N-interconnect is arranged below the area of ​​the light emission port. Part of the N-interconnect and the light emission port share the area of ​​the substrate, thereby reducing the distance between adjacent light emission ports, which in turn reduces the area of ​​the light-emitting unit and the distance (i.e., pitch) between the centers of adjacent light-emitting units, thereby increasing the photocurrent density and improving the power.

[0139] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A vertical-cavity surface-emitting laser, characterized in that, include: Base; The epitaxial structure includes an N-type DBR layer, an active layer, an oxide confinement layer, and a P-type DBR layer stacked from bottom to top on the substrate, wherein the unoxidized region of the oxide confinement layer defines the output port of the vertical cavity surface-emitting laser. A first insulating dielectric layer is formed on the epitaxial structure; N-interconnects and N-electrodes, wherein the N-interconnects are formed between the substrate and the epitaxial structure, the N-interconnects partially overlap with the light outlet in a direction perpendicular to the top surface of the substrate, and the N-electrodes are electrically led upward from the top surface of the N-interconnects to the top surface of the first insulating dielectric layer; P interconnects and P electrodes are formed on the top surface of the first insulating dielectric layer, and the P interconnects and / or the P electrodes penetrate the first insulating dielectric layer to be electrically connected to the P-type DBR layer, and the P interconnects are electrically connected to the P electrodes.

2. The vertical-cavity surface-emitting laser as described in claim 1, characterized in that, The substrate comprises a first substrate and a bonding layer stacked from bottom to top.

3. The vertical-cavity surface-emitting laser as described in claim 2, characterized in that, The first substrate is made of silicon.

4. The vertical-cavity surface-emitting laser as described in claim 1, characterized in that, The epitaxial structure further includes an N-type epitaxial layer formed between the substrate and the N-type DBR layer.

5. The vertical-cavity surface-emitting laser as described in claim 1, characterized in that, The epitaxial structure also includes a capping layer formed between the P-type DBR layer and the first insulating dielectric layer.

6. The vertical-cavity surface-emitting laser as described in claim 1, characterized in that, The vertical-cavity surface-emitting laser also includes: A first annular via penetrates the P-type DBR layer, the oxide confinement layer, and the active layer and enters the N-type DBR layer. A portion of the oxide confinement layer on the sidewall of the first via is an oxidized region. The N-interconnect and the P-interconnect partially overlap with the first via in a direction perpendicular to the top surface of the substrate. A second insulating dielectric layer fills the first through-hole.

7. The vertical-cavity surface-emitting laser as described in claim 6, characterized in that, The vertical-cavity surface-emitting laser also includes: A second annular through-hole surrounds the first through-hole and penetrates the epitaxial structure. A portion of the oxide confinement layer on the sidewall of the second through-hole is an oxidized region. The P electrode partially overlaps with the second through-hole in a direction perpendicular to the top surface of the substrate. The third insulating dielectric layer fills the second through-hole.

8. The vertical-cavity surface-emitting laser as described in claim 1, characterized in that, The vertical-cavity surface-emitting laser also includes: A passivation layer covers the first insulating dielectric layer and the P interconnect, and extends to a portion of the top surface of the N electrode and a portion of the top surface of the P electrode.

9. A method for manufacturing a vertical-cavity surface-emitting laser, characterized in that, include: An epitaxial structure is formed on a substrate, and an N-interconnect is formed between the substrate and the epitaxial structure. The epitaxial structure includes an N-type DBR layer, an active layer, an oxide confinement layer, and a P-type DBR layer stacked from bottom to top. The unoxidized region of the oxide confinement layer defines the exit port of the vertical cavity surface emitter laser. The N-interconnect partially overlaps with the exit port in a direction perpendicular to the top surface of the substrate. A first insulating dielectric layer is formed on the epitaxial structure; An N-electrode, a P-interconnect, and a P-electrode are formed. The N-electrode is electrically led upward from the top surface of the N-interconnect to the top surface of the first insulating dielectric layer. The P-interconnect and the P-electrode are formed on the top surface of the first insulating dielectric layer, and the P-interconnect and / or the P-electrode penetrates the first insulating dielectric layer to be electrically connected to the P-type DBR layer. The P-interconnect is electrically connected to the P-electrode.

10. The method for manufacturing a vertical-cavity surface-emitting laser as described in claim 9, characterized in that, The steps of forming an epitaxial structure on a substrate and forming N-interconnects include: A second substrate is provided, on which a P-type DBR layer, a confinement layer, an active layer and an N-type DBR layer are formed in a bottom-to-top stacked manner; N-interconnects are formed on a portion of the N-type DBR layer; A second bonding layer is formed on the N-type DBR layer and the N interconnect; A first substrate is provided, and a first bonding layer is formed on the first substrate; The side of the second bonding layer away from the second substrate is bonded to the side of the first bonding layer away from the first substrate; Peel off the second substrate; A first via is formed that penetrates the P-type DBR layer, the confinement layer, and the active layer and enters the N-type DBR layer. The first via is annular. A portion of the confinement layer on the sidewall of the first via is oxidized to form an oxide layer. The remaining confinement layer and the oxide layer after oxidation constitute an oxide confinement layer. The N interconnect and the P interconnect partially overlap with the first via in a direction perpendicular to the top surface of the substrate.

11. The method for manufacturing a vertical-cavity surface-emitting laser as described in claim 10, characterized in that, The first substrate is made of silicon, and the second substrate is made of GaAs.

12. The method for manufacturing a vertical-cavity surface-emitting laser as described in claim 10, characterized in that, The manufacturing method of the vertical-cavity surface-emitting laser further includes: A second through hole is formed around and surrounds the first through hole, and the second through hole penetrates the epitaxial structure; The limiting layer on the sidewall of the second via is oxidized, and the P electrode partially overlaps with the second via in a direction perpendicular to the top surface of the substrate.

13. The method for manufacturing a vertical-cavity surface-emitting laser as described in claim 12, characterized in that, The manufacturing method of the vertical-cavity surface-emitting laser further includes: A second insulating dielectric layer is filled in the first through hole, and a third insulating dielectric layer is filled in the second through hole.

14. The method for manufacturing a vertical-cavity surface-emitting laser as described in claim 9, characterized in that, The manufacturing method of the vertical-cavity surface-emitting laser further includes: A passivation layer is formed to cover the first insulating dielectric layer and the P interconnect, and extends to a portion of the top surface of the N electrode and a portion of the top surface of the P electrode.

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