A quasi-synchronous optimal PWM control method, device and system for a five-level ANPC inverter

Abstract

This invention discloses a quasi-synchronous optimal PWM control method, device, and system for a five-level ANPC inverter. The method first establishes constraints for selecting the switching mode sequence for quasi-synchronous optimal pulse width modulation operation. Within a limited prediction range, candidate switching mode sequences are searched based on predefined constraints and pre-optimized pulse modes, and the three-phase floating capacitor voltage and midpoint voltage are predicted accordingly. The switching mode sequence with optimal capacitor voltage balance performance is selected by minimizing the cost function. Furthermore, a fixed weighting factor setting can lead to capacitor voltage imbalance, causing interruption of the inverter's quasi-synchronous optimal PWM operation. Therefore, an online weighting factor adjustment method is designed to achieve active coordinated control of the capacitor voltage. This invention ensures that the inverter can effectively balance the capacitor voltage with the minimum switching frequency, achieving quasi-synchronous optimal PWM operation of the five-level ANPC inverter.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, and in particular relates to a quasi-synchronous optimal PWM control method, device, and system for a five-level ANPC inverter. Background Technology

[0002] Compared to traditional three-level inverters, five-level inverters offer significant advantages such as lower device voltage stress, superior output waveform quality, and lower harmonic distortion, making them one of the core topologies for medium- and high-voltage, high-power applications. Among them, the five-level active neutral-point clamp (5L-ANPC) inverter, through optimized topology, overcomes the inherent defects of traditional neutral-point clamp inverters (neutral-point voltage drift) and flying-capacitor inverters (numerous capacitors and difficult voltage balancing), effectively reducing system cost and control complexity. It has broad application prospects in medium- and high-voltage frequency converters, new energy grid-connected converters, and other fields.

[0003] In medium- and high-voltage applications, the thermal losses of power devices severely limit the switching frequency of inverters, typically requiring them to operate at low switching frequencies (hundreds of hertz). Synchronous Optimal Pulse Width Modulation (SOP), also known as Optimal Pulse Modes (OPPs), is a key technology for achieving high-performance inverter operation at low switching frequencies. Its core principle is to optimize the switching angle and voltage level structure to suppress specific harmonics to the maximum extent possible while meeting output voltage amplitude requirements, thereby reducing total harmonic distortion (THD) and switching losses, and ensuring the system's steady-state performance.

[0004] However, the 5L-ANPC inverter has four critical internal capacitor voltages that require precise control: the midpoint voltage (NP-V) formed by the upper and lower capacitors of the DC bus, and the flying capacitor voltage (FC-V) of the three-phase branches. These capacitor voltages must be stabilized at preset reference values ​​(NP-V reference value is 0V, FC-V reference value is 1 / 4 of the DC bus voltage), otherwise it will lead to inverter output voltage distortion, uneven voltage stress on components, and even damage to power devices. Existing capacitor voltage balance control technology mainly has the following technical defects:

[0005] 1) Existing technologies achieve capacitor voltage balance by switching redundant switching modes, but additional switching mode switching will lead to a significant increase in switching frequency, which will not only increase switching losses, but also reduce the safety margin of power devices, conflicting with the requirements for low switching frequency operation.

[0006] 2) Random switching of redundant switching modes will disrupt the inherent synchronization characteristics between the switching frequency and the fundamental frequency of SOP technology, causing the inverter to fail to achieve SOP operation and deteriorating the harmonic suppression effect.

[0007] 3) In traditional model predictive control (MPC), the weighting factor of the cost function is often set to a fixed value or the hysteresis width is determined by trial and error. This makes it difficult to adapt to dynamic changes in operating conditions such as modulation index and fundamental frequency, which can easily lead to capacitor voltage imbalance and thus disrupt the quasi-SOP operating state.

[0008] 4) Existing predictive control methods mostly employ short prediction time domains or complex optimization algorithms, which have high computational overhead and are difficult to deploy on ordinary industrial-grade DSP hardware platforms. Instead, they require the use of high-performance chips such as FPGAs, which limits their engineering practicality and increases costs.

[0009] Therefore, there is an urgent need for a 5L-ANPC inverter control method that balances precise capacitor voltage balance, near-SOP operating characteristics, and engineering feasibility, in order to solve the technical pain points of existing technologies such as excessively high switching frequency, poor frequency synchronization, weak adaptability of weighting factors, and high computational overhead. Summary of the Invention

[0010] The purpose of this invention is to propose a quasi-synchronous optimal PWM control method, device, and system for a five-level ANPC inverter, to solve the conflict between capacitor voltage balance regulation and quasi-synchronous optimal pulse width modulation operation when using synchronous optimal PWM (SOP) control in existing 5L-ANPC inverters. This invention achieves high-precision internal capacitor voltage balance at the lowest switching frequency while ensuring quasi-synchronous optimal pulse width modulation operation of the inverter, reducing switching losses, and improving system stability and engineering practicality.

[0011] This invention provides the following technical solution:

[0012] In a first aspect, the present invention provides a quasi-synchronous optimal PWM control method for a five-level ANPC inverter, the method comprising:

[0013] Based on the quasi-synchronous optimized pulse width modulation operation constraints, within a preset finite prediction time domain, a candidate switching mode sequence is obtained by combining the inverter's switching state topology screening; the constraints include minimum switching action constraints between adjacent switching modes and switching mode transition constraints during adjacent rolling cycles.

[0014] A current extrapolation model is constructed using the second-order Taylor expansion method. Based on the phase current sampling values ​​at the current and the two previous time points, the phase current changes corresponding to each candidate switching mode sequence in the prediction time domain are predicted.

[0015] A prediction model for the midpoint voltage and the flying capacitor voltage is constructed. By combining the current mapping relationship and phase current change of the candidate switching mode sequence, the predicted values ​​of the midpoint voltage and the three-phase flying capacitor voltage of each candidate switching mode sequence are obtained.

[0016] A multi-objective cost function containing a capacitor voltage balance error term is constructed. The weighting factor is adjusted online based on the current capacitor voltage prediction error. The optimal switching mode sequence is selected from the candidate switching mode sequence by minimizing the cost function.

[0017] Based on the switching pulse signal corresponding to the optimal switching mode sequence, the five-level ANPC inverter is driven to operate, achieving quasi-synchronous optimal pulse width modulation under capacitor voltage balance.

[0018] In one implementation, the minimum switching action constraint for adjacent switching modes is as follows: when switching between adjacent switching modes, only power devices in Cell2 or Cell3 are allowed to switch, and Cell1 is only switched when the voltage polarity is reversed, ensuring that the switching action between adjacent switching modes is minimized; wherein Cell2 corresponds to the flying capacitor C in the bridge arm. f Connected S a3 , Power devices, Cell3 corresponds to the S on the output side of the bridge arm. a4 , Power devices; Cell1 corresponds to the S on the DC bus side of the bridge arm. a1 , S a2 , Power devices;

[0019] The transition constraint of the switching mode during adjacent rolling cycles is as follows: if the voltage level at the end of the previous cycle is the same as the voltage level at the beginning of the current cycle, then the first element of the current candidate switching mode sequence is the same as the switching mode at the end of the previous cycle; otherwise, the transition path between the switching mode at the end of the previous cycle and the switching mode at the beginning of the current cycle is limited by the minimum switching action constraint of adjacent switching modes, so as to avoid additional switching actions when cycles are connected.

[0020] In one implementation, the prediction time domain is set to π / 6, which is 1 / 12 of the fundamental period of the five-level ANPC inverter.

[0021] In one implementation, the step of filtering the candidate switch pattern sequence further includes:

[0022] An optimal pulse mode lookup table is pre-constructed. The lookup table stores the optimal switching angle and voltage level structure in the range of modulation index m = 0.3 to 1.27. The optimization objective is to suppress the 6n±1st harmonic, where n∈N* and N* represents the set of positive integers.

[0023] Candidate switch state sequences are obtained by using lookup tables and quasi-synchronous optimized pulse width modulation operation constraints.

[0024] In one implementation, the step of filtering the candidate switch pattern sequence includes:

[0025] The voltage level structure is obtained from the optimal pulse pattern lookup table based on the modulation index;

[0026] Based on the minimum switching action constraint of adjacent switching modes, the minimum switching action path of adjacent switching modes is traversed to initially screen feasible sequences for a single cycle.

[0027] By combining the switching mode transition constraints during adjacent rolling cycles with the switching mode at the end of the previous cycle, a second screening is conducted to obtain the final candidate sequence set.

[0028] In one implementation, the multi-objective cost function is:

[0029]

[0030] in, For a multi-objective cost function, This is the midpoint voltage balance weighting factor. The normalized squared error of the midpoint voltage. For the midpoint voltage prediction deviation, This is the total voltage of the DC bus. For the first Phase-flying capacitor voltage balance weighting factor, Corresponding to phases A, B, and C respectively. The normalized squared error of the three-phase flying capacitor voltage is given. For the first Predicted value of phase-flying capacitor voltage;

[0031] In one implementation, the online adjustment of the weighting factors is as follows:

[0032] ,

[0033] in, For the midpoint voltage prediction error, For the present time

[0034] Midpoint voltage sampling deviation, This is the midpoint voltage increment caused by the optimal sequence in the previous control cycle. To account for the prediction error of the flying capacitor voltage, For the present The first moment Phase-flying capacitor voltage sampling value, The first result caused by the optimal sequence of the previous control cycle Phase-flying capacitor voltage increment, The sum of errors, and .

[0035] In one embodiment, the method further includes:

[0036] It adopts a dual-CPU parallel architecture, with high-frequency tasks sampling and outputting switching signals in real time, and low-frequency tasks performing candidate sequence screening, model prediction and optimal sequence selection, to achieve engineering deployment.

[0037] Secondly, the present invention provides a quasi-synchronous optimal PWM control device for a five-level ANPC inverter, the device comprising:

[0038] The signal acquisition module is used to acquire sampled values ​​of phase current, neutral point voltage, and flying capacitor voltage of the five-level ANPC inverter.

[0039] The sequence filtering module is used to obtain a sequence of candidate switching modes based on quasi-synchronous optimized pulse width modulation operation constraints within a preset finite prediction time domain, combined with the inverter's switching state topology. The constraints include minimum switching action constraints between adjacent switching modes and transition constraints between switching modes during adjacent rolling cycles.

[0040] The current prediction module is used to construct a current extrapolation model using the second-order Taylor expansion method. Based on the phase current sampling values ​​of the current and the previous two time points, it predicts the phase current changes corresponding to each candidate switching mode sequence in the prediction time domain.

[0041] The voltage prediction module is used to construct prediction models for the midpoint voltage and the flying capacitor voltage. By combining the current mapping relationship and phase current changes of the candidate switching mode sequence, the predicted values ​​of the midpoint voltage and the three-phase flying capacitor voltage of each candidate switching mode sequence are obtained.

[0042] The optimal sequence selection module is used to construct a multi-objective cost function that includes a capacitor voltage balance error term, adjust the weighting factor online based on the current capacitor voltage prediction error, and select the optimal switching mode sequence from the candidate switching mode sequences by minimizing the cost function.

[0043] The drive control module is used to drive the five-level ANPC inverter to operate according to the switching pulse signal corresponding to the optimal switching mode sequence, so as to achieve quasi-synchronous optimal pulse width modulation under capacitor voltage balance.

[0044] Thirdly, the present invention provides a five-level ANPC inverter quasi-synchronous optimal PWM control system, the system comprising the above-mentioned five-level ANPC inverter quasi-synchronous optimal PWM control device.

[0045] Beneficial effects of this invention:

[0046] 1. By synchronizing the device switching frequency with the fundamental frequency, switching losses are significantly reduced; at the same time, the harmonic suppression advantage of the quasi-synchronous optimal PWM technology is retained, resulting in low output current harmonic distortion rate and excellent steady-state performance.

[0047] 2. The DC bus midpoint voltage remains stable near the reference value with small ripple amplitude; the three-phase flying capacitor voltage remains stable at the target reference value with controllable ripple range, covering the full modulation index operating range, thus completely solving the problem of capacitor voltage imbalance inside the multi-level inverter.

[0048] 3. When the modulation index changes abruptly, the fundamental frequency switches, or the voltage level structure changes, the output voltage does not jump abnormally, the internal capacitor voltage does not become unstable, the dynamic adjustment response is rapid, and it can quickly adapt to complex operating conditions.

[0049] 4. When the intermediate voltage or the voltage of the flying capacitor deviates significantly, it can quickly recover to the normal operating range in a short time, effectively resisting interference from non-ideal factors such as power grid fluctuations and load changes, and the system has high operational stability.

[0050] 5. It adopts a finite prediction time domain and parallel processing architecture, with controllable computational load. It can be deployed on conventional industrial-grade digital signal processing platforms. The execution time of both high-frequency and low-frequency tasks meets the real-time control requirements. It does not rely on high-performance hardware platforms and has good engineering feasibility. Attached Figure Description

[0051] The accompanying drawings, as part of this invention, are provided to further illustrate the invention. The illustrative embodiments and descriptions of the invention are used to explain the invention, but do not constitute an undue limitation thereof. Clearly, the drawings described below are merely some embodiments, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0052] Figure 1 This is a schematic diagram of the main circuit topology of a five-level active midpoint clamp inverter.

[0053] Figure 2 This is a flowchart of a quasi-synchronous optimal PWM control method for a five-level ANPC inverter provided in one embodiment of the present invention;

[0054] Figure 3 This is a diagram showing the permissible switching relationship of a single-phase switching mode provided in one embodiment of the present invention.

[0055] Figure 4 This is a steady-state experimental result provided in one embodiment of the present invention; wherein... Figure 4 In the middle (a), phase voltage and phase current are represented; Figure 4 In the middle (b), the voltage at the midpoint and the voltage of the floating capacitor are respectively. Figure 4 (c) represents the optimal switching mode and driving signal; Figure 4 In the middle (d), the phase current FFT is represented.

[0056] Figure 5This is a second steady-state experimental result provided in one embodiment of the present invention; wherein... Figure 5 In the middle (a), phase voltage and phase current are represented; Figure 5 In the middle (b), the voltage at the midpoint and the voltage of the floating capacitor are respectively. Figure 5 (c) represents the optimal switching mode and driving signal; Figure 5 In the middle (d), the phase current FFT is represented.

[0057] Figure 6 This is the third steady-state experimental result provided in one embodiment of the present invention; wherein... Figure 6 In the middle (a), phase voltage and phase current are represented; Figure 6 In the middle (b), the voltage at the midpoint and the voltage of the floating capacitor are respectively. Figure 6 (c) represents the optimal switching mode and driving signal; Figure 6 In the middle (d), the phase current FFT is represented.

[0058] Figure 7 This is the fourth steady-state experimental result provided in one embodiment of the present invention; wherein... Figure 7 In the middle (a), phase voltage and phase current are represented; Figure 7 In the middle (b), the voltage at the midpoint and the voltage of the floating capacitor are respectively. Figure 7 (c) Optimal switching mode and drive signal; Figure 7 In the middle (d), the phase current FFT is represented.

[0059] Figure 8 This is a dynamic experimental result provided in one embodiment of the present invention; wherein... Figure 8 In the middle (a), phase voltage and phase current are represented; Figure 8 In the middle (b), the voltage at the midpoint and the voltage of the floating capacitor are respectively.

[0060] Figure 9 This is the second dynamic experimental result provided in one embodiment of the present invention; Figure 9 In the middle (a), phase voltage and phase current are represented; Figure 9 In the middle (b), the voltage at the midpoint and the voltage of the floating capacitor are respectively.

[0061] Figure 10 This is the third dynamic experimental result provided in one embodiment of the present invention;

[0062] Figure 11 The fourth dynamic experimental result provided in one embodiment of the present invention;

[0063] Figure 12 This is an experimental waveform diagram of the switching frequency trajectory provided in one embodiment of the present invention;

[0064] Figure 13 The optimal switching angle provided in one embodiment of the present invention Figure showing the results of voltage level structure optimization.

[0065] It should be noted that these accompanying drawings and textual descriptions are not intended to limit the scope of the invention in any way, but rather to illustrate the concept of the invention to those skilled in the art by referring to specific embodiments. Detailed Implementation

[0066] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0067] To address the conflict between capacitor voltage balance regulation and quasi-SOP operation in existing 5L-ANPC inverters using Synchronous Optimal PWM (SOP) control, which includes issues such as increased switching frequency due to additional switching mode switching, asynchrony between the fundamental frequency and switching frequency, poor adaptability of fixed weighting factor settings, and high computational overhead for predictive control making it difficult to implement in engineering, this invention proposes an OSMS-MPC control strategy based on Optimal Pulse Mode (OPP) to optimize the selection of the switching mode sequence within a finite prediction time domain. The five-level ANPC inverter topology is referenced... Figure 1 As shown.

[0068] One embodiment of the present invention illustrates a quasi-synchronous optimal PWM control method for a five-level ANPC inverter, such as... Figure 2 As shown, the method includes:

[0069] Step S100: Based on the quasi-synchronous optimized pulse width modulation operation constraints, within the preset finite prediction time domain, candidate switching mode sequences are obtained by combining the inverter's switching state topology screening.

[0070] To ensure minimum switching frequency and frequency synchronization, two types of strict constraints are designed to screen candidate switching mode sequences and limit the switching mode transition logic. The constraints include minimum switching action constraints for adjacent switching modes and switching mode transition constraints during adjacent rolling cycles.

[0071] Furthermore, the minimum switching action constraint for adjacent switching modes is as follows: when switching between adjacent switching modes, only power devices in Cell2 or Cell3 are allowed to switch, and Cell1 is only switched when the voltage polarity is reversed, ensuring that the switching actions between adjacent switching modes are minimized. The switching mode transition constraint during adjacent rolling cycles is as follows: if the voltage level at the end of the previous cycle is the same as the voltage level at the beginning of the current cycle, then the first element of the current candidate switching mode sequence is the same as the switching mode at the end of the previous cycle; otherwise, the minimum switching action constraint for adjacent switching modes limits the transition path between the switching mode at the end of the previous cycle and the switching mode at the beginning of the current cycle, avoiding additional switching actions during cycle transitions.

[0072] Specifically, refer to Figure 1As shown, Cell2 corresponds to the flying capacitor C in the bridge arm. f Connected S a3 , Power devices, Cell3 corresponds to the S on the output side of the bridge arm. a4 , Power devices; Cell1 corresponds to the S on the DC bus side of the bridge arm. a1 , S a2 , Power devices. The minimum switching action constraint for adjacent switching modes is (Constraint I): Clearly define the allowed switching path for single-phase signal mode, allowing switching of Cell2 (corresponding to switch S) only during transitions between adjacent voltage levels. x3 ) or Cell3 (corresponding switch S) x4 Power devices; Cell1 (corresponding to switch S) x1 S x2 Devices switch only when the voltage polarity reverses (i.e., the voltage level switches from the positive range to the negative range or vice versa). This constraint ensures minimal switching action during adjacent switching mode transitions, avoiding unnecessary switching losses. For example, when the voltage level switches from 0 to +1, if level 0 is M4, it indicates that the previous voltage level transitioned from +1, there is no voltage waveform polarity reversal, and only a single switching action of Cell2 or Cell3 is allowed, without involving the switching of Cell1 device; if level 0 is M3, it indicates that the previous voltage level transitioned from -1, that is, the voltage waveform undergoes polarity reversal, and only a single switching action of Cell1 and Cell2 or Cell3 is allowed. Switching mode transition constraint during adjacent rolling cycles (Constraint II): ensures minimum switching action between adjacent rolling control cycles. If the last voltage level of the previous control cycle is the same as the first voltage level of the current cycle, then the first switching mode of the current candidate switching mode sequence must be exactly the same as the last switching mode of the previous cycle to avoid extra switching actions during cycle transitions; if the voltage levels are different, then constraint I limits the transition path between the last switching mode of the previous cycle and the first switching mode of the current cycle to ensure minimal switching actions. Figure 3 The switching mode transitions shown are indicated by arrows, with arrows representing possible transitions. Referring to Table 1, the permissible switching mode transitions for S... x3 and S x4 Each switching mode transition only activates once; for S x1 and S x2 An action will only occur when the voltage level crosses from 0.

[0073] Table 1 Switching Modes and Switching Signals

[0074] Furthermore, the prediction time domain is set to π / 6, which is 1 / 12 of the fundamental period of the five-level ANPC inverter.

[0075] Specifically, to balance control performance and computational overhead, the prediction time domain is strictly set to π / 6 (i.e., 1 / 12 of the fundamental frequency period). The core basis for this time domain selection is that the optimal pulse mode of the 5L-ANPC inverter has quarter-cycle symmetry, and the π / 6 time domain can completely cover the continuous range of a single voltage level, while avoiding a surge in computational load due to an excessively long time domain. During the control process, the optimal switching mode sequence is updated every π / 6 electrical angle (approximately 1.67ms at a fundamental frequency of 50Hz). The pulse modes of the other two phases are derived through the symmetry of the pulse mode of a single-phase cycle, significantly reducing computational complexity and ensuring that the algorithm can be deployed on a common industrial-grade DSP platform.

[0076] In an optional embodiment, the process further includes:

[0077] An optimal pulse mode lookup table is pre-constructed. The lookup table stores the optimal switching angle and voltage level structure in the range of modulation index m = 0.3 to 1.27. The optimization objective is to suppress the 6n±1st harmonic, where n∈N* and N* represents the set of positive integers.

[0078] Candidate switch state sequences are obtained by using lookup tables and quasi-synchronous optimized pulse width modulation operation constraints.

[0079] To ensure the harmonic suppression effect of quasi-SOP operation, an OPP lookup table covering the entire modulation index range (0.3-1.27) is pre-constructed.

[0080] The pulse number p (the number of switching cycles in a quarter of the voltage waveform period) is set. In a specific embodiment, p=7 to balance harmonic suppression and switching losses. When p=7, there are 8 possible voltage level structures, and their voltage level changes within 1 / 4 of the fundamental period can be expressed as:

[0081]

[0082] With the goal of suppressing 6n±1 (n∈N*) harmonics, the objective function is constructed as follows:

[0083]

[0084] in, The switching angle vector. The symbol for voltage level change. The minimum interval between adjacent switch angles. The maximum harmonic order;

[0085] In this embodiment of the application, the step of screening candidate switch pattern sequences includes:

[0086] Step S110: Obtain the voltage level structure from the optimal pulse mode lookup table based on the modulation index.

[0087] Step S120: Traverse the minimum switching action path of adjacent switching modes according to the minimum switching action constraint of adjacent switching modes, and initially screen the feasible sequence for a single cycle.

[0088] Step S130: Combining the switching mode transition constraints during adjacent rolling cycles with the switching mode at the end of the previous cycle, a second screening is performed to obtain the final candidate sequence set.

[0089] Specifically, based on the two types of quasi-SOP constraints in the design, the candidate switching mode sequence with the minimum switching action is obtained through the following steps. Based on the current modulation index m, the corresponding voltage level structure (such as {0,1,0}, {0,1,2,1,0}, etc.) is obtained from the pre-optimized optimal pulse mode (OPP) lookup table (LUT).

[0090] For each voltage level structure, according to constraint I, traverse all transition paths that satisfy the minimum switching action of adjacent switching modes, such as... Figure 3 As shown, the feasible switching mode sequence within a single cycle was initially obtained through screening.

[0091] Based on constraint II, the initial selection of switching mode sequences is further filtered according to the final voltage level and final switching mode of the previous cycle: if the final voltage level of the previous cycle is the same as the first voltage level of the current cycle, the sequence whose first switching mode is the same as the final switching mode of the previous cycle is retained; otherwise, the sequence that satisfies the conversion logic of constraint I is retained.

[0092] The final set of candidate switching mode sequences is output, with the size of the set controlled between 8 and 16 groups to balance optimization effect and computational efficiency. For example, the candidate switching mode sequences corresponding to the voltage level structure {0,1,0} include 8 sets of sequences such as {M4,M5,M3}, {M3,M5,M4}, and {M4,M6,M3}.

[0093] Step S200: Construct a current extrapolation model using the second-order Taylor expansion method. Based on the phase current sampling values ​​at the current and the previous two time points, predict the phase current changes corresponding to each candidate switching mode sequence in the prediction time domain.

[0094] Accurate current extrapolation and capacitor voltage prediction models are constructed to provide a reliable basis for cost function evaluation. A second-order Taylor expansion method is used to accurately estimate the phase current in each switching angle interval within the prediction time domain.

[0095] Based on the sampled current values ​​at the current moment and the two moments before, and considering the rate of change and acceleration of change of current, the estimated phase current values ​​at each predicted moment are derived.

[0096] Furthermore, the expression for the estimated phase current of phase a in the current extrapolation model is as follows:

[0097]

[0098] in, This is the current phase current sample value. , These are the sampled values ​​from the previous two time points. The fundamental frequency, To control the cycle, The electrical angle difference between the target time and the current time.

[0099] The same logic applies to b and c.

[0100] Step S300: Construct prediction models for the midpoint voltage and the flying capacitor voltage, and combine the current mapping relationship and phase current changes of the candidate switching mode sequences to obtain the predicted values ​​of the midpoint voltage and the three-phase flying capacitor voltage for each candidate switching mode sequence.

[0101] Mapping model of midpoint current, floating capacitor current and phase current corresponding to switching mode:

[0102]

[0103]

[0104] Midpoint voltage (NP-V) prediction model: Based on the volt-ampere characteristics of midpoint current and capacitance, and combined with the current mapping relationship corresponding to the switching mode, the midpoint voltage change in the prediction time domain is derived.

[0105] Furthermore, the expression for the midpoint voltage prediction model is as follows:

[0106]

[0107]

[0108] in, The sampling error of the midpoint voltage at the current moment. This represents the change in midpoint voltage caused by the current cycle's candidate switching mode sequence. This represents the change in midpoint voltage caused by the optimal switching mode sequence in the previous cycle. This is the DC bus capacitance value. , , This is the midpoint current mapping matrix corresponding to each phase switching mode. , , These represent the electrical angle widths of the switching angle intervals for phases A, B, and C, respectively. , , The predicted current sequences are for phases A, B, and C, respectively.

[0109] Flying capacitor voltage (FC-V) prediction model: Similarly, based on the charging and discharging characteristics of the flying capacitor and the current control logic of the switching mode, the predicted value of the three-phase flying capacitor voltage is derived.

[0110] Furthermore, taking phase a as an example, and similarly for phases b and c, the expression for the flying capacitor voltage prediction model is:

[0111]

[0112]

[0113] in, This is the sampled value of the current flying capacitor voltage. This represents the change in fly-through capacitor voltage caused by the current candidate switching mode sequence. This represents the change in the flyover capacitor voltage caused by the optimal switching mode sequence in the previous cycle. For the flying capacitance value, This is the overflying capacitor current mapping matrix corresponding to the a-phase switching mode. The electrical angle width of each switching angle interval of phase a. This represents the estimated phase current of phase a corresponding to the electrical angle width of each switching angle interval.

[0114] Step S400: Construct a multi-objective cost function that includes a capacitor voltage balance error term, adjust the weighting factor online based on the current capacitor voltage prediction error, and select the optimal switching mode sequence from the candidate switching mode sequence by minimizing the cost function.

[0115] A multi-objective cost function that takes into account both the midpoint voltage balance and the three-phase flying capacitor voltage balance is constructed, and an online weighting factor adjustment mechanism is designed to ensure dynamic matching of control priorities under different operating conditions.

[0116] Furthermore, the multi-objective cost function is:

[0117]

[0118] Among them, among them, For a multi-objective cost function, This is the midpoint voltage balance weighting factor. The normalized squared error of the midpoint voltage. For the midpoint voltage prediction deviation, This represents the total DC bus voltage. Normalization can eliminate the impact of voltage amplitude on cost assessment. For the first The phase-flying capacitor voltage balance weighting factor, the sum of the weights satisfies . Corresponding to phases A, B, and C respectively. The reference value is set as the normalized squared error of the three-phase flying capacitor voltage. It matches the level output logic of the 5L-ANPC inverter. For the first Predicted value of phase-flying capacitor voltage.

[0119] Online weighting factor adjustment mechanism: Based on the prediction error of the internal capacitor voltage at the current moment, the weights are dynamically allocated to ensure that the capacitor voltage with the larger deviation is corrected first when there is voltage imbalance.

[0120] Furthermore, the online adjustment method for the weighting factors is as follows:

[0121] ,

[0122] in, For the midpoint voltage prediction error, For the present time

[0123] Midpoint voltage sampling deviation, This is the midpoint voltage increment caused by the optimal sequence in the previous control cycle. To account for the prediction error of the flying capacitor voltage, For the present The first moment Phase-flying capacitor voltage sampling value, The first result caused by the optimal sequence of the previous control cycle Phase-flying capacitor voltage increment, The sum of errors, and .

[0124] Preferably, weights are dynamically allocated: , And limited This ensures the rationality and stability of weight allocation.

[0125] Step S500: Drive the five-level ANPC inverter to operate according to the switching pulse signal corresponding to the optimal switching mode sequence, so as to achieve quasi-synchronous optimal pulse width modulation under capacitor voltage balance.

[0126] In an optional embodiment, the quasi-synchronous optimal PWM control method for a five-level ANPC inverter further includes:

[0127] Step S600: Adopting a dual-CPU parallel architecture, the high-frequency task samples in real time and outputs switching signals, while the low-frequency task performs candidate sequence screening, model prediction, and optimal sequence selection to achieve engineering deployment.

[0128] To reduce computational overhead and enable engineered deployment, the OSMS-MPC strategy is split into high-frequency real-time tasks and low-frequency optimization tasks, which are deployed on industrial-grade DSP platforms with dual-CPU architecture (such as TIF28377D) and achieve inter-core data interaction through inter-process communication (IPC).

[0129] a. High-frequency real-time task (deployed on CPU1), the specific implementation process is as follows:

[0130] The midpoint voltage is sampled with a control period of 50 μs. Three-phase flying capacitor voltage and three-phase current The electrical angle is calculated in real time, and the trigger signal status is determined. If the trigger signal is true, the modulation index m and the optimal switching mode sequence are updated, and the low-frequency optimization task is called in parallel; otherwise, the optimal switching mode sequence of the previous cycle is used. The OPP switching angle corresponding to the current electrical angle is obtained through a LUT. The switching mode index of each phase is determined by comparing it with the carrier signal. Based on the optimal switching mode sequence and index, the switching signals of each phase are obtained from the switching state table. The output is then sent to the power device drive circuit. The single execution time of the task is 19.05μs, which meets the real-time control requirements.

[0131] b. Low-frequency optimization task (deployed on CPU2), the specific implementation process is as follows:

[0132] A trigger signal is detected using a trigger period of π / 6 electrical angle (approximately 1.67ms at a fundamental frequency of 50Hz). Upon triggering, the optimization process is initiated. The modulation index m, internal voltage sample values, phase current sample values, and the optimal switching mode sequence from the previous cycle are read from CPU1. The voltage level structure and switching angle of the corresponding OPP are obtained from the LUT. The candidate switching mode sequence screening process is executed to obtain the set of candidate switching mode sequences for the current period. Based on the current extrapolation model, the predicted current sequence corresponding to each candidate sequence is calculated. Combined with the voltage prediction model, the predicted midpoint voltage value corresponding to each candidate sequence is calculated. Predicted value of flying capacitor voltage The weighting factors under the current operating conditions are calculated through an online weighting factor adjustment mechanism. and The cost function value J of each candidate sequence is calculated, and the sequence with the smallest J is selected as the optimal switching mode sequence. The optimal switching mode sequence is then transferred to CPU1 for execution of the next π / 6 cycle high-frequency task. The average execution time of the task is 260μs, and the maximum execution time does not exceed 302μs, ensuring that optimization is completed within the trigger cycle.

[0133] Within the modulation index m = 0.3 to 1.27, the above optimization problem is solved with a step size of 0.025 to obtain the optimal switching angle corresponding to each modulation index. With voltage level structure, such as Figure 13 As shown.

[0134] In one specific embodiment, the experimental parameters are shown in Table 2. The specific implementation of the present invention is based on the 5L-ANPC inverter experimental platform.

[0135] Table 2

[0136]

[0137] The specific experimental procedure is as follows:

[0138] I. System Initialization

[0139] (1) After powering on, initialize the DSP core register, ADC sampling module, PWM output module and IPC communication module to ensure that each hardware module works normally.

[0140] (2) Load the pre-optimized OPP lookup table (LUT), which stores the optimal switching angles corresponding to modulation index m = 0.3-1.27 and step size 0.01. With voltage level structure.

[0141] (3) Set the initial operating parameters: fundamental frequency f=50Hz, modulation index m=0.5, reference value of neutral point voltage 0V, reference value of three-phase flying capacitor voltage 50V, number of pulses p=7;

[0142] (4) Initialize the switch mode sequence buffer and set the initial switch mode to M3 (voltage level 0, corresponding to switch states Sx3=1, Sx4=1).

[0143] II. High-frequency real-time task execution (CPU1), which is executed in a loop with a period of 50μs, and the steps are as follows:

[0144] (1) Synchronously sample the midpoint voltage through the ADC module Three-phase flying capacitor voltage and three-phase current .

[0145] (2) Calculate the current electrical angle in real time based on the fundamental frequency f and the system running time. .

[0146] (3) When the electrical angle When the value is an integer multiple of π / 6 (i.e., at times 0, π / 6, π / 3, π / 2, etc.), the trigger signal is set to true, the modulation index m is updated (if there is an external instruction), and the optimal switching mode sequence transmitted by CPU2 is read via IPC. Otherwise, the trigger signal is set to false, and the optimal switching mode sequence of the previous cycle is used.

[0147] (4) Based on the current modulation index m and electrical angle Retrieve the corresponding switching angle from the OPP lookup table. .

[0148] (5) Adjust the switch angle Convert to the corresponding time interval, compare with the carrier signal, and determine the switching mode index of each equivalent time point. .

[0149] (6) Based on the optimal switching mode sequence (x=a,b,c) and the switch status table (Table I) are used to generate the switch signals for each phase. It is then output to the drive circuit via the PWM module.

[0150] (7) The sampled internal voltage and phase current data are transmitted to CPU2 via IPC for use in low-frequency optimization tasks.

[0151] III. Low-frequency optimization task execution (CPU2), with a trigger cycle of π / 6 electrical angle, executes the following steps after triggering:

[0152] (1) Receive the modulation index m and midpoint voltage transmitted by CPU1 via IPC. Three-phase flying capacitor voltage Three-phase phase current and the optimal switching mode sequence of the previous cycle .

[0153] (2) Based on the modulation index m, read the corresponding voltage level structure from the OPP lookup table. (e.g., when m=0.5, l1={0,1,0,1,0,1,0,1}) and the switching angle .

[0154] (3) For the voltage level structure of each phase, according to constraint I, traverse the adjacent switching mode conversion paths to obtain a preliminary selection of feasible switching mode sequences for a single cycle; combine constraint II with the switching mode at the end of the previous cycle. The final set of candidate switch mode sequences (8 sequences per phase) is obtained through secondary screening.

[0155] (4) Based on the sequence of each candidate switching mode,

[0156] Combination and ,

[0157] Calculate the midpoint current mapping symbol sequence Symbol sequence mapped to flying capacitor current .

[0158] (5) Based on the second-order Taylor expansion current extrapolation model, input the current sample values ​​of the current and the previous two time moments, and calculate the predicted current sequence corresponding to each candidate switching mode sequence. .

[0159] (6) Combine the voltage prediction model with the input of the predicted current sequence, symbol sequence and switching angle range. Calculate the predicted midpoint voltage value for each candidate sequence. Predicted value of flying capacitor voltage .

[0160] (7) Calculate the midpoint voltage error With the three-phase flying capacitor voltage error Dynamically allocate weight factors and .

[0161] (8) Calculate the cost function value J of each candidate sequence, and select the sequence with the smallest J as the optimal switching mode sequence for the current period. .

[0162] (9) Transmit the optimal switching mode sequence to CPU1 via IPC and cache it for later use.

[0163] IV. Adaptive Adjustment for Operating Conditions: When system operating conditions change (such as modulation index adjustment, fundamental frequency switching, load mutation, or internal voltage imbalance), the following adaptive adjustments are performed:

[0164] (1) Update the OPP lookup table index in real time, re-filter the candidate switch mode sequence, and dynamically adjust the weighting factor according to the voltage error under the new operating conditions.

[0165] (2) By quickly identifying load changes through current sampling values, the acceleration coefficient of the current extrapolation model is optimized to ensure the accuracy of current prediction. At the same time, the voltage balance weight factor is increased to suppress capacitor voltage fluctuations.

[0166] (3) Automatically detect the voltage deviation of the flying capacitor and the midpoint voltage, adaptively adjust the weighting factor of the corresponding voltage, and prioritize the switching mode sequence that can quickly correct the voltage deviation to shorten the imbalance correction time.

[0167] Figure 4 This is the first result of the steady-state experiment, in which... Figure 4 In the middle (a), phase voltage and phase current are represented; Figure 4 In the middle (b), the voltage at the midpoint and the voltage of the floating capacitor are respectively. Figure 4 (c) represents the optimal switching mode and driving signal; Figure 4 In the middle (d), the phase current FFT (m=0.5, f=50Hz, level structure l1) is: Cell2 / 3 switching frequency 350Hz. Figure 5 This is the second result of the steady-state experiment, in which... Figure 5 In the middle (a), phase voltage and phase current are represented; Figure 5 In the middle (b), the voltage at the midpoint and the voltage of the floating capacitor are respectively. Figure 5 (c) represents the optimal switching mode and driving signal; Figure 5 In the middle (d), the phase current FFT (m=0.5, f=25Hz, level structure l1) is: Cell2 / 3 switching frequency 175Hz. Figure 6 This is the third result of the steady-state experiment, in which... Figure 6 In the middle (a), phase voltage and phase current are represented; Figure 6 In the middle (b), the voltage at the midpoint and the voltage of the floating capacitor are respectively. Figure 6 (c) represents the optimal switching mode and driving signal; Figure 6 In the middle (d), the phase current FFT (m=0.9, f=50Hz, level structure l6) is: Cell2 / 3 switching frequency 350Hz. Figure 7 The fourth result of the steady-state experiment is as follows: Figure 7 In the middle (a), phase voltage and phase current are represented; Figure 7 In the middle (b), the voltage at the midpoint and the voltage of the floating capacitor are respectively. Figure 7 (c) Optimal switching mode and drive signal; Figure 7 In the middle (d), the phase current FFT is (m=1.2, f=50Hz, level structure l7): Cell2 / 3 switching frequency is 350Hz. m is the modulation index, and f is the fundamental frequency.

[0168] Figures 4 to 7Experimental waveforms were presented using the proposed method with p=7 under the following conditions: modulation degree 0.5 / fundamental frequency 50Hz, modulation degree 0.5 / fundamental frequency 50Hz, modulation degree 0.9 / fundamental frequency 50Hz, and modulation degree 1.2 / fundamental frequency 50Hz. Steady-state experimental results show that the switching frequency of the device in Cell1 is synchronized with the fundamental frequency, and the number of switching cycles of the devices in Cell2 and Cell3 fluctuates around p within one fundamental frequency cycle (the maximum number of switching cycles does not exceed ±2), achieving quasi-synchronous operation. Based on achieving quasi-synchronous operation, the harmonic optimization characteristics of OPP are guaranteed, and the balanced control effect of capacitor voltage is maintained.

[0169] Figure 8 This is the first result of the dynamic experiment, in which... Figure 8 In the middle (a), phase voltage and phase current are represented; Figure 8 In (b), the voltage is the midpoint voltage and the voltage of the floating capacitor (m=0.5→0.9, f=50Hz, l1→l6): there is no voltage jump across the level. Figure 9 This is the second result of the dynamic experiment. Figure 9 In the middle (a), phase voltage and phase current are represented; Figure 9 In (b), the voltage at the midpoint and the voltage of the floating capacitor (m=1.2→0.5, f=50Hz, l7→l1) show no instability in the voltage of the flying capacitor and the voltage at the midpoint.

[0170] Figure 8 and Figure 9 The algorithm performance under working condition images is demonstrated when the proposed method is used. When the modulation or fundamental frequency changes abruptly, the proposed strategy can quickly respond to achieve target value tracking, while the balance of capacitor voltage is guaranteed, without abnormal fluctuations or instability.

[0171] Figure 10 and Figure 11 The proposed strategy was verified to have the ability to actively control the capacitor voltage. When the midpoint voltage or the floating capacitor voltage has become unstable, applying the proposed algorithm can restore the capacitor voltage to balance in a short time.

[0172] Figure 12 The switching frequencies of Cell2 and Cell3 devices were statistically analyzed at different fundamental frequencies using the proposed algorithm. Compared with the ideal synchronous modulation switching frequency, the switching frequency of the inverter using the proposed algorithm always fluctuates slightly around its baseline, indicating that quasi-synchronous operation has been achieved.

[0173] Within the modulation index m = 0.3 to 1.27, the above optimization problem is solved with a step size of 0.025 to obtain the optimal switching angle corresponding to each modulation index. With voltage level structure, such as Figure 13 As shown.

[0174] The following is an embodiment of the five-level ANPC inverter quasi-synchronous optimal PWM control device of the present invention, which can be used to execute the five-level ANPC inverter quasi-synchronous optimal PWM control method embodiment of the present invention. For details not disclosed in the embodiment of the five-level ANPC inverter quasi-synchronous optimal PWM control device of the present invention, please refer to the five-level ANPC inverter quasi-synchronous optimal PWM control method embodiment of the present invention.

[0175] An exemplary embodiment of the present invention provides a quasi-synchronous optimal PWM control device for a five-level ANPC inverter, the device comprising:

[0176] The signal acquisition module is used to acquire sampled values ​​of phase current, neutral point voltage, and flying capacitor voltage of the five-level ANPC inverter.

[0177] The sequence filtering module is used to obtain a sequence of candidate switching modes based on quasi-synchronous optimized pulse width modulation operation constraints within a preset finite prediction time domain, combined with the inverter's switching state topology. The constraints include minimum switching action constraints between adjacent switching modes and transition constraints between switching modes during adjacent rolling cycles.

[0178] The current prediction module is used to construct a current extrapolation model using the second-order Taylor expansion method. Based on the phase current sampling values ​​of the current and the previous two time points, it predicts the phase current changes corresponding to each candidate switching mode sequence in the prediction time domain.

[0179] The voltage prediction module is used to construct prediction models for the midpoint voltage and the flying capacitor voltage. By combining the current mapping relationship and phase current changes of the candidate switching mode sequence, the predicted values ​​of the midpoint voltage and the three-phase flying capacitor voltage of each candidate switching mode sequence are obtained.

[0180] The optimal sequence selection module is used to construct a multi-objective cost function that includes a capacitor voltage balance error term, adjust the weighting factor online based on the current capacitor voltage prediction error, and select the optimal switching mode sequence from the candidate switching mode sequences by minimizing the cost function.

[0181] The drive control module is used to drive the five-level ANPC inverter to operate according to the switching pulse signal corresponding to the optimal switching mode sequence, so as to achieve quasi-synchronous optimal pulse width modulation under capacitor voltage balance.

[0182] It should be noted that the five-level ANPC inverter quasi-synchronous optimal PWM control device provided in the above embodiments is only illustrated by the division of the above functional modules when executing the five-level ANPC inverter quasi-synchronous optimal PWM control method. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the five-level ANPC inverter quasi-synchronous optimal PWM control device and the five-level ANPC inverter quasi-synchronous optimal PWM control method embodiments belong to the same concept, and the implementation process is detailed in the five-level ANPC inverter quasi-synchronous optimal PWM control method embodiments, which will not be repeated here.

[0183] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0184] An exemplary embodiment of the present invention provides a five-level ANPC inverter quasi-synchronous optimal PWM control system, which is a five-level ANPC inverter quasi-synchronous optimal PWM control device.

[0185] It should be noted that the quasi-synchronous optimal PWM control device based on the five-level ANPC inverter refers to the above embodiment, and will not be repeated here.

[0186] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A quasi-synchronous optimal PWM control method for a five-level ANPC inverter, characterized in that: The method includes: Based on the quasi-synchronous optimized pulse width modulation operation constraints, within a preset finite prediction time domain, a candidate switching mode sequence is obtained by combining the inverter's switching state topology screening; the constraints include minimum switching action constraints between adjacent switching modes and switching mode transition constraints during adjacent rolling cycles. A current extrapolation model is constructed using the second-order Taylor expansion method. Based on the phase current sampling values ​​at the current and the two previous time points, the phase current changes corresponding to each candidate switching mode sequence in the prediction time domain are predicted. A prediction model for the midpoint voltage and the flying capacitor voltage is constructed. By combining the current mapping relationship and phase current change of the candidate switching mode sequence, the predicted values ​​of the midpoint voltage and the three-phase flying capacitor voltage of each candidate switching mode sequence are obtained. A multi-objective cost function containing a capacitor voltage balance error term is constructed. The weighting factor is adjusted online based on the current capacitor voltage prediction error. The optimal switching mode sequence is selected from the candidate switching mode sequence by minimizing the cost function. Based on the switching pulse signal corresponding to the optimal switching mode sequence, the five-level ANPC inverter is driven to operate, achieving quasi-synchronous optimal pulse width modulation under capacitor voltage balance.

2. The quasi-synchronous optimal PWM control method for a five-level ANPC inverter according to claim 1, characterized in that: The minimum switching action constraint for adjacent switching modes is as follows: when switching between adjacent switching modes, only power devices in Cell2 or Cell3 are allowed to switch, and Cell1 is only switched when the voltage polarity is reversed, ensuring that the switching action between adjacent switching modes is minimized; where Cell2 corresponds to the flying capacitor C in the bridge arm. f Connected S a3 , Power devices, Cell3 corresponds to the S on the output side of the bridge arm. a4 , Power devices; Cell1 corresponds to the S on the DC bus side of the bridge arm. a1 , S a2 , Power devices; The transition constraint of the switching mode during adjacent rolling cycles is as follows: if the voltage level at the end of the previous cycle is the same as the voltage level at the beginning of the current cycle, then the first element of the current candidate switching mode sequence is the same as the switching mode at the end of the previous cycle; otherwise, the transition path between the switching mode at the end of the previous cycle and the switching mode at the beginning of the current cycle is limited by the minimum switching action constraint of adjacent switching modes, so as to avoid additional switching actions when cycles are connected.

3. The quasi-synchronous optimal PWM control method for a five-level ANPC inverter according to claim 1, characterized in that: The prediction time domain is set to π / 6, which is 1 / 12 of the fundamental period of the five-level ANPC inverter.

4. The quasi-synchronous optimal PWM control method for a five-level ANPC inverter according to claim 1, characterized in that: The step of screening candidate switch pattern sequences also includes: An optimal pulse mode lookup table is pre-constructed. The lookup table stores the optimal switching angle and voltage level structure in the range of modulation index m = 0.3 to 1.

27. The optimization objective is to suppress the 6n±1st harmonic, where n∈N* and N* represents the set of positive integers. Candidate switch state sequences are obtained by using lookup tables and quasi-synchronous optimized pulse width modulation operation constraints.

5. The quasi-synchronous optimal PWM control method for a five-level ANPC inverter according to claim 4, characterized in that: The step of filtering candidate switch pattern sequences includes: The voltage level structure is obtained from the optimal pulse pattern lookup table based on the modulation index; Based on the minimum switching action constraint of adjacent switching modes, the minimum switching action path of adjacent switching modes is traversed to initially screen feasible sequences for a single cycle. By combining the switching mode transition constraints during adjacent rolling cycles with the switching mode at the end of the previous cycle, a second screening is conducted to obtain the final candidate sequence set.

6. The quasi-synchronous optimal PWM control method for a five-level ANPC inverter according to claim 1, characterized in that: The multi-objective cost function is: ， in, For a multi-objective cost function, This is the midpoint voltage balance weighting factor. The normalized squared error of the midpoint voltage. For the midpoint voltage prediction deviation, This is the total voltage of the DC bus. For the first Phase-flying capacitor voltage balance weighting factor, Corresponding to phases A, B, and C respectively. The normalized squared error of the three-phase flying capacitor voltage is given. For the first Predicted value of phase-flying capacitor voltage.

7. The quasi-synchronous optimal PWM control method for a five-level ANPC inverter according to claim 6, characterized in that: The online adjustment method for weighting factors is as follows: ， ， in, For the midpoint voltage prediction error, For the present Midpoint voltage sampling deviation at time t. This is the midpoint voltage increment caused by the optimal sequence in the previous control cycle. To account for the prediction error of the flying capacitor voltage, For the present The first moment Phase-flying capacitor voltage sampling value, The first result caused by the optimal sequence of the previous control cycle Phase-flying capacitor voltage increment, The sum of errors, and .

8. The quasi-synchronous optimal PWM control method for a five-level ANPC inverter according to claim 1, characterized in that: The method further includes: It adopts a dual-CPU parallel architecture, with high-frequency tasks sampling and outputting switching signals in real time, and low-frequency tasks performing candidate sequence screening, model prediction and optimal sequence selection, to achieve engineering deployment.

9. A quasi-synchronous optimal PWM control device for a five-level ANPC inverter, characterized in that: The device includes: The signal acquisition module is used to acquire sampled values ​​of phase current, neutral point voltage, and flying capacitor voltage of the five-level ANPC inverter. The sequence filtering module is used to obtain a sequence of candidate switching modes based on quasi-synchronous optimized pulse width modulation operation constraints within a preset finite prediction time domain, combined with the inverter's switching state topology. The constraints include minimum switching action constraints between adjacent switching modes and transition constraints between switching modes during adjacent rolling cycles. The current prediction module is used to construct a current extrapolation model using the second-order Taylor expansion method. Based on the phase current sampling values ​​of the current and the previous two time points, it predicts the phase current changes corresponding to each candidate switching mode sequence in the prediction time domain. The voltage prediction module is used to construct prediction models for the midpoint voltage and the flying capacitor voltage. By combining the current mapping relationship and phase current changes of the candidate switching mode sequence, the predicted values ​​of the midpoint voltage and the three-phase flying capacitor voltage of each candidate switching mode sequence are obtained. The optimal sequence selection module is used to construct a multi-objective cost function that includes a capacitor voltage balance error term, adjust the weighting factor online based on the current capacitor voltage prediction error, and select the optimal switching mode sequence from the candidate switching mode sequences by minimizing the cost function. The drive control module is used to drive the five-level ANPC inverter to operate according to the switching pulse signal corresponding to the optimal switching mode sequence, so as to achieve quasi-synchronous optimal pulse width modulation under capacitor voltage balance.

10. A quasi-synchronous optimal PWM control system for a five-level ANPC inverter, characterized in that: The system includes the five-level ANPC inverter quasi-synchronous optimal PWM control device as described in claim 9.

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