A single-inductor three-output dc-dc boost converter

Abstract

The application discloses a single-inductor three-output DC boost converter, which comprises a DC boost main module provided with an inductor and a main power tube, and the voltage output end of the DC boost main module is connected with three output branches provided with branch power switch tubes, and the converter further comprises a main power tube control module, a front-end detection module, a clock signal generation module and a branch charging control module, the main power tube control module is used for controlling the main power tube to be periodically turned on and turned off; in a switching cycle of the main power tube, the main power tube control module firstly controls the main power tube to be turned on to charge the inductor and then turned off after the charging is completed, and then detection and charging logic control is performed on each output branch according to a preset branch control priority order; the converter has the advantages that dynamic pulse cross-cycle modulation is realized, output voltage fluctuation caused by untimely adjustment is effectively avoided, and the stability of the output voltage is remarkably improved.

Description

Technical Field

[0001] This invention relates to a switching power supply converter, and more particularly to a single-inductor, three-output DC-DC boost converter. Background Technology

[0002] As wireless IoT systems become increasingly complex, power management systems need to effectively provide multiple power supplies to various modules. Single-input multiple-output (SIMO) DC-DC converters are favored for their simple design, high power density, and excellent scalability. However, in low-energy environments, due to energy scarcity, the power harvested by the front-end energy harvesting circuit is only a few hundred microwatts or even tens of microwatts, and the output voltage of the front-end energy harvesting circuit is only a few hundred microvolts. Furthermore, if power needs to be supplied to three or more devices, a single-inductor multiple-output (SIMO) DC-DC boost converter is required to boost the input voltage and provide the necessary power to multiple loads. Because multiple loads need to be powered simultaneously, if the voltage difference between the loads is too large, unstable output voltage or even shutdown can easily occur.

[0003] To address the problems caused by load imbalance, researchers have made numerous efforts. Currently, the mainstream approach is a hybrid modulation method using PWM (Pulse-Width Modulation) and PSM (Pulse Skip Modulation). PWM modulation stabilizes the output voltage by adjusting the number of skipped cycles. However, both methods rely on load detection to determine whether to enter the PSM modulation stage, with a fixed number of skipped cycles pre-set. This can lead to redundancy or insufficient skipped cycles, severely impacting output voltage stability. Subsequent researchers added a stepped skipped cycle count to address this issue, but this still doesn't solve the problem at its root. Detecting load conditions and pre-setting multiple skipped cycles require additional circuitry, increasing overall circuit complexity. Furthermore, because the method requires load detection before entering the PSM modulation stage (i.e., only entering the stage after an unbalanced load has been identified), it exhibits a lag. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a single-inductor three-output DC boost converter that realizes dynamic pulse cross-cycle modulation, which effectively avoids output voltage fluctuations caused by untimely adjustment and significantly improves the stability of output voltage.

[0005] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows: a single-inductor three-output DC-DC boost converter, including a DC-DC boost main module with an inductor and a main power transistor, wherein the voltage output terminal of the DC-DC boost main module is connected in parallel with three output branches with branch power switching transistors, and further includes a main power transistor control module, a front-end detection module, a clock signal generation module and a branch charging control module. The main power transistor control module is used to control the main power transistor to periodically turn on and off; within one switching cycle of the main power transistor, the main power transistor control module first controls the main power transistor to turn on to charge the inductor and then turns it off after charging is completed, and then performs detection and charging logic control on each of the output branches according to a preset branch control priority order;

[0006] Specifically, for the output branch with the highest current control priority, if the front-end detection module detects that the load sampling voltage of the output branch is lower than a preset valley reference voltage, the clock signal generation module and the branch charging control module cooperate to control the power switch of the output branch to turn on to start charging. When the front-end detection module detects that the load sampling voltage of the output branch reaches a preset peak reference voltage, it controls the power switch of the output branch to turn off to stop charging, and then executes the detection and charging logic control of the next priority output branch. If the front-end detection module detects that the load sampling voltage of the output branch with the highest current control priority is higher than a preset valley reference voltage, the clock signal generation module and the branch charging control module cooperate to control the power switch of the output branch to remain off to skip charging, and directly executes the detection and charging logic control of the next priority output branch. After the detection and charging logic control of the three output branches is executed in sequence, the main power transistor control module controls the main power transistor to turn on again to start the next switching cycle of the main power transistor.

[0007] Compared with existing technologies, the advantages of this invention are that it uses a front-end detection module to detect the load sampling voltage of each output branch in real time, and the clock signal generation module and the branch charging control module cooperate to control the charging according to a preset branch control priority order, thus realizing dynamic pulse cross-cycle modulation. In each switching cycle, the system only charges the branches whose load sampling voltage is lower than the corresponding valley reference voltage, while skipping the charging of branches whose load sampling voltage is higher than the valley reference voltage. The number of skipped cycles is dynamically determined by the real-time state of the load sampling voltage of each branch, which completely solves the problem of redundant or insufficient skipped cycles in the traditional fixed-cycle skipping method. At the same time, this invention adopts a real-time detection and real-time decision-making mechanism. In each switching cycle, it generates the corresponding clock enable signal and controls the charging action in real time according to the actual state of the load sampling voltage of each output branch. There is no system adjustment lag caused by the pre-setting of the number of skipped cycles or the detection of the load condition before judgment in the traditional PWM / PSM hybrid modulation method, which effectively avoids output voltage fluctuations and significantly improves the stability of the output voltage.

[0008] Furthermore, the present invention achieves the above-mentioned dynamic pulse cross-cycle modulation function only through the coordinated operation of the main power transistor control module, the front-end detection module, the clock signal generation module, and the branch charging control module. It does not require additional mode selection circuits, oscillators, or other complex control circuits. The circuit structure is simple, the design complexity is low, and it has good scalability and integration advantages.

[0009] Preferably, within one switching cycle of the main power transistor, the main power transistor control module first controls the main power transistor to turn on to charge the inductor and then turns it off after charging is completed, entering the energy distribution stage; in the energy distribution stage, detection and charging logic control is performed on each of the output branches according to a preset branch control priority order, and the specific control logic of the detection and charging logic control is as follows:

[0010] First, a charging decision is made for the output branch with the highest current branch control priority: When processing this output branch, the clock signal generation module generates a valid clock enable signal only if the front-end detection module detects that the load sampling voltage of this output branch is lower than the preset valley reference voltage corresponding to this output branch; otherwise, the clock signal generation module generates an invalid clock enable signal. When the branch charging control module receives a valid clock enable signal, it controls the power switch of this output branch to turn on to start charging until the front-end detection module detects that the load sampling voltage of this output branch reaches the preset peak reference voltage. Then, the branch charging control module controls the power switch of this output branch to turn off to stop charging. If the branch charging control module receives an invalid clock enable signal, it does not trigger the charging action for this output branch, and the power switch of this output branch remains off, thus skipping the charging of this output branch.

[0011] According to this control logic, the subsequent two output branches are processed sequentially based on their control priority. After processing all three output branches, the main power transistor control module controls the main power transistor to turn on again, starting the next switching cycle. Within each switching cycle, the system performs a dynamic control process of valley-triggered charging and peak-stop charging for the branches according to priority, providing a basic framework for subsequent circuits to achieve dynamic cross-cycle modulation.

[0012] Preferably, the three output branches are defined as the first output branch, the second output branch, and the third output branch in order of branch control priority, and the front-end detection module includes a first branch detection submodule and a second branch detection submodule.

[0013] The first branch detection submodule is used to acquire the first branch load sampling voltage of the first output branch, and generate a first peak detection signal and a first valley detection signal corresponding to the first output branch; the first peak detection signal is used to indicate whether the first branch load sampling voltage of the first output branch reaches a preset first peak reference voltage, and the first valley detection signal is used to indicate whether the first branch load sampling voltage of the first output branch is lower than a preset first valley reference voltage.

[0014] The second branch detection submodule is used to acquire the second branch load sampling voltage of the second output branch, and generate a second peak detection signal and a second valley detection signal corresponding to the second output branch. The second peak detection signal is used to indicate whether the second branch load sampling voltage of the second output branch reaches a preset second peak reference voltage, and the second valley detection signal is used to indicate whether the second branch load sampling voltage of the second output branch is lower than a preset second valley reference voltage. The three output branches are defined as first, second, and third output branches according to priority, and corresponding peak and valley detection signals are set, laying the signal foundation for subsequent circuits to accurately distinguish the state of each branch and achieve independent control.

[0015] Preferably, the first branch detection submodule includes a first peak comparator, a first valley comparator, and a first branch load voltage sampling module. The first branch load voltage sampling module is used to generate a corresponding first branch load sampling voltage based on the load voltage of the first output branch. The positive input terminal of the first peak comparator is used to receive the first branch load sampling voltage, and the negative input terminal of the first peak comparator is used to connect to a preset first peak reference voltage. The output terminal of the first peak comparator outputs the first peak detection signal. The positive input terminal of the first valley comparator is used to receive the first branch load sampling voltage, and the negative input terminal of the first valley comparator is used to connect to a preset first valley reference voltage. The output terminal of the first valley comparator outputs the first valley detection signal through a first inverter.

[0016] The second branch detection submodule includes a second peak comparator, a second valley comparator, and a second branch load voltage sampling module. The second branch load voltage sampling module generates a corresponding second branch load sampling voltage based on the load voltage of the second output branch. The positive input of the second peak comparator receives the second branch load sampling voltage, and the negative input is connected to a preset second peak reference voltage. The output of the second peak comparator outputs the second peak detection signal. The positive input of the second valley comparator receives the second branch load sampling voltage, and the negative input is connected to a preset second valley reference voltage. The output of the second valley comparator outputs the second valley detection signal via a second inverter. By employing a structure combining a peak comparator and a valley comparator with an inverter, peak and valley detection signals for the first and second branches are generated respectively, achieving accurate detection of the branch voltage window.

[0017] Preferably, the clock signal generation module includes a first clock signal generation submodule and a second clock signal generation submodule. The first clock signal generation submodule includes a first D flip-flop and a two-input AND gate. The second clock signal generation submodule includes a second D flip-flop, a third D flip-flop, a 2-to-1 data selector, and a four-input AND gate. The data input terminal and asynchronous reset terminal of the first D flip-flop respectively receive the first valley detection signal. The clock input terminal of the first D flip-flop receives the main power transistor switching control signal generated by the main power transistor control module. The non-inverting output terminal of the first D flip-flop outputs a first latch signal. The first input terminal of the two-input AND gate receives the first latch signal. The second input terminal of the two-input AND gate receives the inverted signal of the main power transistor switching control signal. The output terminal of the two-input AND gate outputs a first clock enable signal.

[0018] The branch charging control module includes a first branch switch control module and a second branch switch control module. The first branch switch control module includes a fifth D flip-flop, and the second branch switch control module includes a sixth D flip-flop. The data input terminal of the fifth D flip-flop receives the first peak detection signal through a fourth inverter. The clock input terminal of the fifth D flip-flop receives the first clock enable signal. The asynchronous reset terminal of the fifth D flip-flop receives the inverted signal of the first peak detection signal. The inverted output terminal of the fifth D flip-flop outputs a first branch switch control signal for controlling the first power switch transistor of the first output branch.

[0019] The data input terminal of the second D flip-flop receives the first valley detection signal, the asynchronous reset terminal of the second D flip-flop receives a high-level signal, the clock input terminal of the second D flip-flop receives the main power transistor switch control signal, and the non-inverting output terminal of the second D flip-flop outputs a second latch signal; the selection terminal of the 2-to-1 data selector receives the second latch signal, the first data input terminal of the 2-to-1 data selector receives the first branch switch control signal, the second data input terminal of the 2-to-1 data selector receives the inverted signal of the main power transistor switch control signal, and the output terminal of the 2-to-1 data selector is connected to a third... The inverter is connected to the clock input of the third D flip-flop; the data input and asynchronous reset of the third D flip-flop respectively receive the second valley detection signal, and the positive output of the third D flip-flop outputs the third latch signal; the first input of the four-input AND gate receives the inverted output signal of the first D flip-flop, the second input of the four-input AND gate receives the third latch signal, the third input of the four-input AND gate receives the inverted signal of the main power transistor switch control signal, the fourth input of the four-input AND gate receives the first branch switch control signal, and the output of the four-input AND gate outputs the second clock enable signal;

[0020] The data input terminal of the sixth D flip-flop receives the second peak detection signal through the fifth inverter. The clock input terminal of the sixth D flip-flop receives the second clock enable signal. The asynchronous reset terminal of the sixth D flip-flop receives the inverted signal of the second peak detection signal. The inverted output terminal of the sixth D flip-flop outputs a second branch switching control signal for controlling the second power switch of the second output branch. Through a sequential logic circuit structure composed of D flip-flops, AND gates, and selectors, strict priority control and dynamic skip logic are achieved, ensuring that energy is only allocated to branches with voltages below the valley value in each cycle, avoiding unnecessary charging.

[0021] Preferably, it also includes a stability control module, the front-end detection module further includes a third branch load voltage sampling module, the third branch load voltage sampling module is used to generate a corresponding third branch load sampling voltage according to the load voltage of the third output branch, the clock signal generation module further includes a third clock signal generation submodule, and the branch charging control module further includes a third branch switch control module.

[0022] The stability control module generates a system status signal based on the combined state of the sampled voltage of the third branch load and the inductor current. The third clock signal generation submodule and the third branch switch control module control the charging process of the third output branch based on the system status signal: when the system status signal is valid, the third clock signal generation submodule allows the generation of a valid third clock enable signal, and the third branch switch control module controls the third power switch of the third output branch to turn on for charging based on the valid third clock enable signal; when the system status signal is invalid, the third clock signal generation submodule prohibits the generation of a valid third clock enable signal, or during charging, the third branch switch control module forcibly turns off the third power switch of the third output branch to stop charging. By introducing a stability control module to generate a system status signal based on the third branch voltage and inductor current state, a stability control scheme is added on top of dynamic modulation, effectively solving the oscillation problem that may be caused by voltage and current phase differences in a single-inductor three-output DC-DC boost converter.

[0023] Preferably, the stability control module includes a multi-input comparator, a low-pass filter, an inductor current peak comparator, and an inductor current valley comparator. The main power transistor control module includes an inductor current sampling resistor. One end of the inductor current sampling resistor is connected to the output terminal of the inductor and is used to acquire the inductor current sampling signal. The other end of the inductor current sampling resistor is grounded. The input terminal of the low-pass filter is connected to one end of the inductor current sampling resistor. The output terminal of the low-pass filter outputs the DC component of the inductor current sampling signal.

[0024] The positive input terminal of the inductor current peak comparator is connected to one end of the inductor current sampling resistor, the negative input terminal of the inductor current peak comparator is used to connect to a preset inductor peak current reference voltage, and the output terminal of the inductor current peak comparator outputs an inductor current peak detection signal.

[0025] The negative input terminal of the inductor current valley comparator is connected to one end of the inductor current sampling resistor, the positive input terminal of the inductor current valley comparator is used to connect to a preset inductor valley current reference voltage, and the output terminal of the inductor current valley comparator outputs an inductor current valley detection signal.

[0026] The multi-input comparator includes a first positive input terminal, a second positive input terminal, a first negative input terminal, and a second negative input terminal. The first positive input terminal is used to connect to a preset reference voltage of the third output branch. The second positive input terminal is connected to the output terminal of the low-pass filter. The first negative input terminal receives the sampled voltage of the third branch load. The second negative input terminal is connected to one end of the inductor current sampling resistor. The output terminal of the multi-input comparator outputs the system status signal. Through the inductor current sampling resistor, low-pass filter, inductor current peak comparator, inductor current valley comparator, and multi-input comparator, accurate sampling of the inductor current and the composite generation of the system status signal are achieved, providing an accurate input signal for stability control.

[0027] Preferably, the third clock signal generation submodule is a five-input AND gate. The first input of the five-input AND gate receives the inverted output signal of the first D flip-flop, the second input of the five-input AND gate receives the inverted output signal of the second D flip-flop, the third input of the five-input AND gate receives the inverted signal of the main power transistor switch control signal, the fourth input of the five-input AND gate receives the first branch switch control signal, the fifth input of the five-input AND gate receives the second branch switch control signal, and the output of the five-input AND gate outputs the third clock enable signal.

[0028] The third branch switch control module includes a seventh D flip-flop, a sixth inverter, and a third NOR gate. The data input terminal of the seventh D flip-flop is connected to the output terminal of the multi-input comparator through the sixth inverter. The clock input terminal of the seventh D flip-flop receives the third clock enable signal. The asynchronous reset terminal of the seventh D flip-flop is connected to the output terminal of the third NOR gate. The inverted output terminal of the seventh D flip-flop outputs a third branch switch control signal for controlling the third power switch transistor of the third output branch.

[0029] The first input of the third NOR gate is connected to the output of the multi-input comparator, and the second input of the third NOR gate is connected to the output of the inductor current valley comparator. A five-input AND gate is used to generate the third clock enable signal, and combined with the seventh D flip-flop, NOR gate, and other circuits, the charging and forced shutdown of the third branch are precisely controlled under the dual constraints of priority order and stability.

[0030] Preferably, the system status signal is also used to control the charging process of the first output branch and the second output branch;

[0031] The first branch switch control module further includes a first NOR gate, the first input terminal of which receives the first peak detection signal, the second input terminal of which is connected to the output terminal of the multi-input comparator, and the output terminal of which is connected to the asynchronous reset terminal of the fifth D flip-flop.

[0032] The second branch switch control module further includes a second NOR gate. The first input of the second NOR gate receives the second peak detection signal, the second input of the second NOR gate is connected to the output of the multi-input comparator, and the output of the second NOR gate is connected to the asynchronous reset terminal of the sixth D flip-flop. By connecting the system status signal to the asynchronous reset terminals of the first and second branch flip-flops through the NOR gate, global stability control of all output branches in the overall circuit is achieved, significantly improving the response capability and reliability of the single-inductor three-output DC-DC boost converter under transient conditions.

[0033] Preferably, the main power transistor control module further includes a fourth D flip-flop and a seventh inverter; the data input and asynchronous reset terminals of the fourth D flip-flop are both connected to the output of the inductor current peak comparator via the seventh inverter; the clock input of the fourth D flip-flop is connected to the output of the multi-input comparator; the non-inverting output of the fourth D flip-flop outputs the main power transistor switching control signal; and the inverting output of the fourth D flip-flop outputs the inverted signal of the main power transistor switching control signal. Through the fourth D flip-flop and the seventh inverter, the main power transistor switching control signal is generated with the system state signal as the periodic starting point and the peak current as the turn-off criterion, providing a stable and reliable operating rhythm for the entire single-inductor three-output DC-DC boost converter. Attached Figure Description

[0034] Figure 1 This is a circuit block diagram of Embodiment 1 of the present invention;

[0035] Figure 2 This is a schematic diagram of the main circuit structure of the present invention;

[0036] Figure 3 This is a partial circuit structure diagram of the front-end detection module in Embodiment 1 of the present invention;

[0037] Figure 4 This is a partial circuit diagram of the clock signal generation module in Embodiment 1 of the present invention;

[0038] Figure 5 This is a circuit block diagram of Embodiment 2 of the present invention;

[0039] Figure 6This is a partial circuit diagram of the stability control module in Embodiment 2 of the present invention;

[0040] Figure 7 This is a circuit diagram of the third clock signal generation submodule in Embodiment 2 of the present invention;

[0041] Figure 8 This is a circuit diagram of the branch charging control module in Embodiment 2 of the present invention;

[0042] Figure 9 This is a partial circuit structure diagram of the main power transistor control module in Embodiment 2 of the present invention. Detailed Implementation

[0043] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0044] Example 1: As Figures 1-4 As shown, a single-inductor, three-output DC-DC boost converter includes a DC-DC boost main module S1 with an inductor L and a main power transistor MN1. The voltage output terminal of the DC-DC boost main module S1 is connected to three output branches with branch power switches. It also includes a main power transistor control module S2, a front-end detection module S3, a clock signal generation module S4, and a branch charging control module S5. The main power transistor control module S2 is used to control the main power transistor MN1 to periodically turn on and off. During one switching cycle of the main power transistor MN1, the main power transistor control module S2 first controls the main power transistor MN1 to turn on to charge the inductor L and then turns it off after charging is completed. Subsequently, it performs detection and charging logic control on each output branch according to a preset branch control priority order.

[0045] For the output branch with the highest control priority, if the front-end detection module S3 detects that the load sampling voltage of this output branch is lower than the preset valley reference voltage, the clock signal generation module S4 and the branch charging control module S5 cooperate to control the power switch of this output branch to turn on to start charging. When the front-end detection module S3 detects that the load sampling voltage of this output branch reaches the preset peak reference voltage, it controls the power switch of this output branch to turn off to stop charging, and then executes the detection and charging logic control of the next priority output branch. If the front-end detection module S3 detects that the load sampling voltage of the output branch with the highest control priority is higher than the preset valley reference voltage, the clock signal generation module S4 and the branch charging control module S5 cooperate to control the power switch of this output branch to remain off to skip charging, and directly executes the detection and charging logic control of the next priority output branch. After the detection and charging logic control of the three output branches are executed in sequence, the main power transistor control module S2 controls the main power transistor MN1 to turn on again, and starts the next switching cycle of the main power transistor MN1.

[0046] During one switching cycle of the main power transistor MN1, the main power transistor control module S2 first controls the main power transistor MN1 to conduct to charge the inductor L and then turns it off after charging is completed, entering the energy distribution stage. In the energy distribution stage, the detection and charging logic control is performed on each output branch according to the preset branch control priority order. The specific control logic of the detection and charging logic control is as follows:

[0047] First, a charging decision is made for the output branch with the highest control priority: When processing this output branch, the clock signal generation module S4 generates a valid clock enable signal only if the front-end detection module S3 detects that the load sampling voltage of this output branch is lower than the preset valley reference voltage corresponding to this output branch; otherwise, the clock signal generation module S4 generates an invalid clock enable signal. When the branch charging control module S5 receives a valid clock enable signal, it controls the power switch of this output branch to turn on to start charging until the front-end detection module S3 detects that the load sampling voltage of this output branch reaches the preset peak reference voltage. Then, the branch charging control module S5 controls the power switch of this output branch to turn off to stop charging. If the branch charging control module S5 receives an invalid clock enable signal, it does not trigger the charging action for this output branch, and the power switch of this output branch remains in the off state, thus skipping the charging of this output branch.

[0048] According to this control logic, the two subsequent output branches are processed sequentially based on the branch control priority order. Finally, after completing the processing of all three output branches, the main power transistor control module S2 controls the main power transistor MN1 to turn on again and start the next switching cycle.

[0049] The three output branches are defined as the first output branch Z1, the second output branch Z2 and the third output branch Z3 according to the branch control priority. The front-end detection module S3 includes the first branch detection submodule and the second branch detection submodule.

[0050] The first branch detection submodule is used to acquire the first branch load sampling voltage Vofb1 of the first output branch Z1, and generate a first peak detection signal V1 and a first valley detection signal P1 corresponding to the first output branch Z1. The first peak detection signal V1 is used to indicate whether the first branch load sampling voltage Vofb1 of the first output branch Z1 reaches the preset first peak reference voltage Vref1_high, and the first valley detection signal P1 is used to indicate whether the first branch load sampling voltage Vofb1 of the first output branch Z1 is lower than the preset first valley reference voltage Vref1_low.

[0051] The second branch detection submodule is used to acquire the second branch load sampling voltage Vofb2 of the second output branch Z2, and generate a second peak detection signal V2 and a second valley detection signal P2 corresponding to the second output branch Z2. The second peak detection signal V2 is used to indicate whether the second branch load sampling voltage Vofb2 of the second output branch Z2 reaches the preset second peak reference voltage Vref2_high, and the second valley detection signal P2 is used to indicate whether the second branch load sampling voltage Vofb2 of the second output branch Z2 is lower than the preset second valley reference voltage Vref2_low.

[0052] The first branch detection submodule includes a first peak comparator COMP1, a first valley comparator COMP2, and a first branch load voltage sampling module. The first branch load voltage sampling module generates a corresponding first branch load sampling voltage Vofb1 based on the load voltage Vo1 of the first output branch Z1. Specifically, the first branch load voltage sampling module consists of two first branch sampling resistors Rf1a and Rf1b connected in series between the source and ground of the first power switch MP1. The connection point of these two first branch sampling resistors Rf1a and Rf1b outputs the first branch load sampling voltage Vofb1. The first peak comparator COMP1... The positive input terminal is used to receive the first branch load sampling voltage Vofb1. The negative input terminal of the first peak comparator COMP1 is used to connect to the preset first peak reference voltage Vref1_high. The output terminal of the first peak comparator COMP1 outputs the first peak detection signal V1. The positive input terminal of the first valley comparator COMP2 is used to receive the first branch load sampling voltage Vofb1. The negative input terminal of the first valley comparator COMP2 is used to connect to the preset first valley reference voltage Vref1_low. The output terminal of the first valley comparator COMP2 outputs the first valley detection signal P1 through the first inverter INV1.

[0053] The second branch detection submodule includes a second peak comparator COMP3, a second valley comparator COMP4, and a second branch load voltage sampling module. The second branch load voltage sampling module generates a corresponding second branch load sampling voltage Vofb2 based on the load voltage Vo2 of the second output branch Z2. Specifically, the second branch load voltage sampling module consists of two second branch sampling resistors Rf2a and Rf2b connected in series between the source and ground of the second power switch MP1. The connection point of these two second branch sampling resistors Rf2a and Rf2b outputs the second branch load sampling voltage Vofb2. The second peak comparator COMP3... The positive input terminal of the second peak comparator COMP3 is used to receive the sampled voltage Vofb2 of the second branch load. The negative input terminal of the second peak comparator COMP3 is used to connect to the preset second peak reference voltage Vref2_high. The output terminal of the second peak comparator COMP3 outputs the second peak detection signal V2. The positive input terminal of the second valley comparator COMP4 is used to receive the sampled voltage Vofb2 of the second branch load. The negative input terminal of the second valley comparator COMP4 is used to connect to the preset second valley reference voltage Vref2_low. The output terminal of the second valley comparator COMP4 outputs the second valley detection signal P2 through the second inverter INV2.

[0054] The clock signal generation module S4 includes a first clock signal generation submodule and a second clock signal generation submodule. The first clock signal generation submodule includes a first D flip-flop D1 and a two-input AND gate AND1. The second clock signal generation submodule includes a second D flip-flop D2, a third D flip-flop D3, a two-to-one data selector MUX2_1, and a four-input AND gate AND2. The data input terminal and the asynchronous reset terminal of the first D flip-flop D1 respectively receive a first valley detection signal P1. The clock input terminal of the first D flip-flop D1 receives the main power transistor switching control signal SFV generated by the main power transistor control module S2. The non-inverting output terminal of the first D flip-flop D1 outputs a first latch signal P1V. The first input terminal of the two-input AND gate AND1 receives the first latch signal P1V. The second input terminal of the two-input AND gate AND1 receives the inverted signal SFVN of the main power transistor switching control signal. The output terminal of the two-input AND gate AND1 outputs a first clock enable signal CP1.

[0055] The branch charging control module S5 includes a first branch switch control module and a second branch switch control module. The first branch switch control module includes a fifth D flip-flop D5, and the second branch switch control module includes a sixth D flip-flop D6. The data input terminal of the fifth D flip-flop D5 receives a first peak detection signal V1 through a fourth inverter INV4. The clock input terminal of the fifth D flip-flop D5 receives a first clock enable signal CP1. The asynchronous reset terminal of the fifth D flip-flop D5 receives the inverted signal of the first peak detection signal. The inverted output terminal of the fifth D flip-flop D5 outputs a first branch switch control signal S1V for controlling the first power switch MP1 of the first output branch Z1.

[0056] The data input terminal of the second D flip-flop D2 receives the first valley detection signal P1. The asynchronous reset terminal of the second D flip-flop D2 receives a high-level signal provided by an external power supply voltage. The clock input terminal of the second D flip-flop D2 receives the main power transistor switch control signal SFV. The non-inverting output terminal of the second D flip-flop D2 outputs the second latch signal. The selection terminal of the 2-to-1 data selector MUX2_1 receives the second latch signal. The first data input terminal of the 2-to-1 data selector MUX2_1 receives the first branch switch control signal S1V. The second data input terminal of the 2-to-1 data selector MUX2_1 receives the inverted signal SFVN of the main power transistor switch control signal. The output terminal of the 2-to-1 data selector MUX2_1 is connected to the first... The three inverters INV3 are connected to the clock input of the third D flip-flop D3; the data input and asynchronous reset input of the third D flip-flop D3 respectively receive the second valley detection signal P2, and the non-inverting output of the third D flip-flop D3 outputs the third latch signal P2V; the first input of the four-input AND gate AND2 receives the inverted output signal P1VN of the first D flip-flop D1, the second input of the four-input AND gate AND2 receives the third latch signal P2V, the third input of the four-input AND gate AND2 receives the inverted signal SFVN of the main power transistor switch control signal, the fourth input of the four-input AND gate AND2 receives the first branch switch control signal S1V, and the output of the four-input AND gate AND2 outputs the second clock enable signal CP2.

[0057] The data input terminal of the sixth D flip-flop D6 receives the second peak detection signal V2 through the fifth inverter INV5. The clock input terminal of the sixth D flip-flop D6 receives the second clock enable signal CP2. The asynchronous reset terminal of the sixth D flip-flop D6 receives the inverted signal of the second peak detection signal. The inverted output terminal of the sixth D flip-flop D6 outputs the second branch switch control signal S2V for controlling the second power switch MP2 of the second output branch Z2.

[0058] The core working principle of this embodiment is as follows:

[0059] In this embodiment, during operation, the main power transistor control module S2 generates a main power transistor switching control signal SFV to control the main power transistor MN1 to periodically turn on and off. In each switching cycle, the main power transistor MN1 first turns on to charge the inductor L, and after charging, it turns off and enters the energy distribution stage. During the energy distribution stage, the system processes the three output branches sequentially according to a preset branch control priority order. The front-end detection module S3 obtains the load sampling voltage Vofb1 of the first output branch Z1 and the load sampling voltage Vofb2 of the second output branch Z2 through the first branch detection submodule and the second branch detection submodule, respectively, and generates corresponding first peak detection signal V1, first valley detection signal P1, second peak detection signal V2, and second valley detection signal P2. The clock signal generation module S4 generates a first clock enable signal CP1 and a second clock enable signal CP2 based on these signals and the main power transistor switching control signal SFV. The branch charging control module S5 controls the power switching transistors of the corresponding output branches to turn on or off based on the received clock enable signal. Specifically... Specifically, for the first output branch Z1, when the first valley detection signal P1 is valid, the first clock enable signal CP1 is valid, triggering the fifth D flip-flop D5 to output the first branch switch control signal S1V, causing the first power switch MP1 to conduct and charge until the first peak detection signal V1 is valid and then turned off; if the first valley detection signal P1 is invalid, the first output branch Z1 is skipped; for the second output branch Z2, its charging decision must be made after the first output branch Z1 has been processed, and the validity of the second clock enable signal CP2 is determined by the first D flip-flop D5. The inverted output signal P1VN of flip-flop D1, the third latch signal P2V, the inverted signal SFVN of the main power transistor switch control signal, and the first branch switch control signal S1V jointly determine that when the second clock enable signal CP2 is valid, the sixth D flip-flop D6 outputs the second branch switch control signal S2V according to the state of the second peak detection signal V2, controlling the second power switch MP2 to charge or skip; after all three output branches have been processed, the main power transistor control module S2 turns on the main power transistor MN1 again to start the next switching cycle.

[0060] The beneficial effects of Example 1 are as follows:

[0061] This embodiment achieves dynamic pulse cross-cycle modulation through the aforementioned circuit structure and operating logic. Within each switching cycle, the system only charges output branches whose load sampling voltage is lower than the corresponding valley reference voltage, while skipping charging output branches whose voltage is higher than the valley reference voltage. The number of skipped cycles is dynamically determined by the real-time state of the load sampling voltage of each branch, completely solving the problem of redundant or insufficient skipped cycles in traditional fixed-cycle skipping methods. Simultaneously, this embodiment employs a real-time detection and decision-making mechanism, instantly generating corresponding clock enable signals based on the actual state of the load sampling voltage of each output branch within each switching cycle. The charging control method avoids the system adjustment lag caused by pre-setting the number of skipped cycles or detecting the load condition before making a judgment, which is common in traditional PWM / PSM hybrid modulation methods. This effectively avoids output voltage fluctuations and significantly improves output voltage stability. In addition, this embodiment achieves the above-mentioned dynamic pulse cross-cycle modulation function through the coordinated work of the main power transistor control module S2, the front-end detection module S3, the clock signal generation module S4, and the branch charging control module S5. No additional mode selection circuit, oscillator, or other complex control circuits are required. The circuit structure is simple, the design complexity is low, and it has good scalability and integration advantages.

[0062] Example 2: Figures 5-9As shown, the rest is the same as in Embodiment 1, except that it also includes a stability control module S6, and the front-end detection module S3 also includes a third branch load voltage sampling module. The third branch load voltage sampling module is used to generate a corresponding third branch load sampling voltage Vofb3 based on the load voltage Vo3 of the third output branch Z3. The third branch load voltage sampling module consists of two third branch sampling resistors Rf3a and Rf3b connected in series between the output terminal and the ground terminal of the third output branch Z3. The connection point of the two third branch sampling resistors Rf3a and Rf3b outputs the third branch load sampling voltage Vofb3. The clock signal generation module S4 also includes a third clock signal generation submodule, and the branch charging control module S5 also includes a third branch switch control module. The stability control module S6 is used to generate a third branch load sampling voltage Vofb3 based on the load voltage Vo3 of the third output branch Z3. The system status signal V3 is generated by combining the state of the third branch load sampling voltage Vofb3 with the inductor current state. The third clock signal generation submodule and the third branch switch control module control the charging process of the third output branch Z3 according to the system status signal V3: when the system status signal V3 is valid, the third clock signal generation submodule allows the generation of a valid third clock enable signal CP3, and the third branch switch control module controls the third power switch MP3 of the third output branch Z3 to be turned on for charging according to the valid third clock enable signal CP3; when the system status signal V3 is invalid, the third clock signal generation submodule prohibits the generation of a valid third clock enable signal CP3, or the third branch switch control module forcibly turns off the third power switch MP3 of the third output branch Z3 to stop charging during the charging process.

[0063] The stability control module S6 includes a multi-input comparator COMP7, a low-pass filter LPF, an inductor current peak comparator COMP5, and an inductor current valley comparator COMP6. The main power transistor control module S2 includes an inductor current sampling resistor R. One end of the inductor current sampling resistor R is connected to the output terminal of the inductor L and is used to acquire the inductor current sampling signal Vsen. The other end of the inductor current sampling resistor R is grounded. The input terminal of the low-pass filter LPF is connected to one end of the inductor current sampling resistor R. The output terminal of the low-pass filter LPF outputs the DC component Vsen_DC of the inductor current sampling signal.

[0064] The positive input terminal of the inductor current peak comparator COMP5 is connected to one end of the inductor current sampling resistor R. The negative input terminal of the inductor current peak comparator COMP5 is used to connect to the preset inductor peak current reference voltage Vilpeak. The output terminal of the inductor current peak comparator COMP5 outputs the inductor current peak detection signal V4. The negative input terminal of the inductor current valley comparator COMP6 is connected to one end of the inductor current sampling resistor R. The positive input terminal of the inductor current valley comparator COMP6 is used to connect to the preset inductor valley current reference voltage Vilvalley. The output terminal of the inductor current valley comparator COMP6 outputs the inductor current valley detection signal V5.

[0065] The multi-input comparator COMP7 includes a first positive input terminal, a second positive input terminal, a first negative input terminal, and a second negative input terminal. The first positive input terminal of the multi-input comparator COMP7 is used to connect to the preset reference voltage Vref3 of the third output branch Z3. The second positive input terminal of the multi-input comparator COMP7 is connected to the output terminal of the low-pass filter LPF. The first negative input terminal of the multi-input comparator COMP7 is used to receive the load sampling voltage Vofb3 of the third branch. The second negative input terminal of the multi-input comparator COMP7 is connected to one end of the inductor current sampling resistor R. The output terminal of the multi-input comparator COMP7 outputs the system status signal V3.

[0066] The third clock signal generation submodule is a five-input AND gate AND3. The first input of AND gate AND3 receives the inverted output signal P1VN of the first D flip-flop D1; the second input receives the inverted output signal P2VN of the second D flip-flop D2; the third input receives the inverted signal SFVN of the main power transistor switch control signal; the fourth input receives the first branch switch control signal S1V; the fifth input receives the second branch switch control signal S2V; and the output of AND gate AND3 outputs the third clock enable signal CP3. The third branch switch control module includes the seventh D flip-flop D7, the sixth... The data input terminals of inverter INV6 and the third NOR gate NOR3, and the seventh D flip-flop D7 are connected to the output terminal of multi-input comparator COMP7 via the sixth inverter INV6. The clock input terminal of the seventh D flip-flop D7 receives the third clock enable signal CP3. The asynchronous reset terminal of the seventh D flip-flop D7 is connected to the output terminal of the third NOR gate NOR3. The inverted output terminal of the seventh D flip-flop D7 outputs the third branch switch control signal S3V for controlling the third power switch MP3 of the third output branch Z3. The first input terminal of the third NOR gate NOR3 is connected to the output terminal of multi-input comparator COMP7, and the second input terminal of the third NOR gate NOR3 is connected to the output terminal of inductor current valley comparator COMP6.

[0067] The system status signal V3 is also used to control the charging process of the first output branch Z1 and the second output branch Z2;

[0068] The first branch switch control module also includes a first NOR gate NOR1, whose first input receives a first peak detection signal V1, whose second input is connected to the output of a multi-input comparator COMP7, and whose output is connected to the asynchronous reset terminal of a fifth D flip-flop D5; the second branch switch control module also includes a second NOR gate NOR2, whose first input receives a second peak detection signal V2, whose second input is connected to the output of a multi-input comparator COMP7, and whose output is connected to the asynchronous reset terminal of a sixth D flip-flop D6.

[0069] The main power transistor control module S2 also includes a fourth D flip-flop D4 and a seventh inverter INV7. The data input and asynchronous reset terminals of the fourth D flip-flop D4 are connected to the output of the inductor current peak comparator COMP5 through the seventh inverter INV7. The clock input of the fourth D flip-flop D4 is connected to the output of the multi-input comparator COMP7. The non-inverting output of the fourth D flip-flop D4 outputs the main power transistor switching control signal SFV, and the inverting output of the fourth D flip-flop D4 outputs the inverted signal SFVN of the main power transistor switching control signal.

[0070] The working principle of Example 2 is as follows:

[0071] This second embodiment adds a stability control module S6 based on the first embodiment and improves the control circuit of the third output branch Z3. The stability control module S6 obtains the inductor current sampling signal Vsen through the inductor current sampling resistor R. One path of the inductor current sampling signal Vsen is filtered by a low-pass filter LPF to extract its DC component Vsen_DC, and the other path is sent to the inductor current peak comparator COMP5 and the inductor current valley comparator COMP6. They are compared with the preset inductor peak current reference voltage Vilpeak and inductor valley current reference voltage Vilvalley, respectively, to generate the inductor current peak detection signal V4 and the inductor current valley detection signal V5. The multi-input comparator COMP7 performs a composite comparison of the reference reference voltage Vref3 of the third output branch Z3, the load sampling voltage Vofb3 of the third branch, the inductor current sampling signal Vsen and its DC component Vsen_DC, and outputs the system status signal V3.

[0072] The system status signal V3 is connected to the third clock signal generation submodule and the third branch switch control module. The third clock signal generation submodule is a five-input AND gate AND3, whose output generates a third clock enable signal CP3. The condition for the third clock enable signal CP3 to be valid is that the inverted output signal P1VN of the first D flip-flop D1, the inverted output signal P2VN of the second D flip-flop D2, the inverted signal SFVN of the main power transistor switch control signal, the first branch switch control signal S1V, and the second branch switch control signal S2V are all high simultaneously, that is, the first two output branches have been processed and The system is in the energy distribution phase. Under the triggering of the third clock enable signal CP3, the seventh D flip-flop D7 in the third branch switch control module outputs the third branch switch control signal S3V according to the system status signal V3 after being inverted by the sixth inverter INV6, controlling the third power switch MP3 to conduct and charge. At the same time, the third NOR gate NOR3 performs a NOR operation on the system status signal V3 and the inductor current valley detection signal V5. Its output is connected to the asynchronous reset terminal of the seventh D flip-flop D7, which can forcibly turn off the third power switch MP3 when the system status signal V3 is invalid or the inductor current is too low.

[0073] The system status signal V3 is further extended to the control of the first two output branches. The first NOR gate NOR1 performs a NOR operation on the first peak detection signal V1 and the system status signal V3, and its output is connected to the asynchronous reset terminal of the fifth D flip-flop D5. The second NOR gate NOR2 performs a NOR operation on the second peak detection signal V2 and the system status signal V3, and its output is connected to the asynchronous reset terminal of the sixth D flip-flop D6. When the system status signal V3 is invalid, the fifth D flip-flop D5 and the sixth D flip-flop D6 can be forcibly reset, and the first power switch MP1 or the second power switch MP2 can be immediately turned off.

[0074] The fourth D flip-flop D4 in the main power transistor control module S2 uses the system status signal V3 as its clock. Its data input terminal and asynchronous reset terminal are both connected to the inductor current peak detection signal V4 through the seventh inverter INV7, ensuring that each switching cycle starts when the system status signal V3 is valid, and turns off the main power transistor MN1 in time when the inductor current reaches its peak value, outputting the main power transistor switching control signal SFV and its inverted signal SFVN.

[0075] The beneficial effects of Example 2 are as follows:

[0076] This second embodiment effectively solves the system oscillation problem that may be caused by the phase asynchrony between the output voltage and inductor current in a single-inductor three-output DC-DC boost converter by introducing a system status signal V3, significantly improving the stability of the converter over a wide load range. The system status signal V3, as a global control signal, not only directly controls the charging start / stop and forced shutdown of the third output branch Z3, but also intervenes in the charging process of the first two branches in real time through NOR gates, immediately stopping the charging of all branches when the system is unstable, achieving millisecond-level emergency interruption protection. Simultaneously, the system status signal V3 serves as the clock for the fourth D flip-flop D4, ensuring that the start of each switching cycle occurs in a stable system state, avoiding voltage fluctuations caused by forced charging in an unstable state. This solution adds only a few circuits to the first embodiment, achieving stability control of the entire circuit while maintaining a simple circuit structure, demonstrating good practical value and scalability.

[0077] Table 1 below compares the single-inductor three-output DC-DC boost converter proposed in Embodiment 2 with current research on single-inductor multi-output modulation methods. Scheme 1 is the technical solution proposed by H.-J. Choi et al., entitled "An Ultra-Low Power Soft-Switching Self-Oscillating SIMO Converter for Implantable Stimulation Systems," with the corresponding Chinese title "Ultra-Low Power Soft-Switching Self-Oscillating Single-Inductor Multi-Output Converter for Implantable Stimulation Systems." Scheme 2 is the technical solution proposed by Y. Jiang et al., entitled "Output Control Techniques for Dual-Frequency SIMO Buck Converters," with the corresponding Chinese title "Output Control Technology for Dual-Frequency Single-Inductor Multi-Output Buck Converters." Scheme 3 is the technical solution proposed by Dong Yi, Bu Gang, and Dong Weihua, entitled "A Low-Intermodulation Single-Inductor Three-Output Boost DC-DC Converter." Scheme 4 is the technical solution proposed by Zhang Liwen, entitled "Design of a Wide Load Range High-Efficiency Single-Inductor Dual-Output DC-DC Converter."

[0078] Table 1

[0079]

[0080] As shown in Table 1, although Schemes 1 to 4 reduce the degree of skipped cycle redundancy or insufficiency through some technical means, they still cannot eliminate the problem. Schemes 1 and 4 require the addition of additional circuits, such as oscillators and mode selection circuits, which increases circuit complexity and power consumption, and reduces the scalability of branches. The different input and output stages of Scheme 2 make it more difficult to add branches; Scheme 3, although relatively simple to implement and highly scalable, still suffers from the problem of skipped cycle redundancy or insufficiency. In contrast, this second embodiment completely solves the problem of skipped cycle redundancy or insufficiency without reducing the scalability of branches or adding additional circuits, through dynamic PSM technology.

Claims

1. A single-inductor, three-output DC-DC boost converter, comprising a DC-DC boost main module with an inductor and a main power transistor, wherein the voltage output terminal of the DC-DC boost main module is connected in parallel to three output branches with branch power switching transistors, characterized in that... It also includes a main power transistor control module, a front-end detection module, a clock signal generation module, and a branch charging control module. The main power transistor control module is used to control the main power transistor to periodically turn on and off. During one switching cycle of the main power transistor, the main power transistor control module first controls the main power transistor to turn on to charge the inductor and then turns it off after charging is completed. Subsequently, it performs detection and charging logic control on each output branch according to the preset branch control priority order. Specifically, for the output branch with the highest current control priority, if the front-end detection module detects that the load sampling voltage of the output branch is lower than a preset valley reference voltage, the clock signal generation module and the branch charging control module cooperate to control the power switch of the output branch to turn on to start charging. When the front-end detection module detects that the load sampling voltage of the output branch reaches a preset peak reference voltage, it controls the power switch of the output branch to turn off to stop charging, and then executes the detection and charging logic control of the next priority output branch. If the front-end detection module detects that the load sampling voltage of the output branch with the highest current control priority is higher than a preset valley reference voltage, the clock signal generation module and the branch charging control module cooperate to control the power switch of the output branch to remain off to skip charging, and directly executes the detection and charging logic control of the next priority output branch. After the detection and charging logic control of the three output branches is executed in sequence, the main power transistor control module controls the main power transistor to turn on again to start the next switching cycle of the main power transistor.

2. The single-inductor three-output DC-DC boost converter according to claim 1, characterized in that... During one switching cycle of the main power transistor, the main power transistor control module first controls the main power transistor to turn on to charge the inductor and then turns it off after charging is completed, entering the energy distribution stage. In the energy distribution stage, detection and charging logic control is performed on each output branch according to a preset branch control priority order. The specific control logic of the detection and charging logic control is as follows: First, a charging decision is made for the output branch with the highest control priority: When processing the output branch, the clock signal generation module generates a valid clock enable signal if and only if the front-end detection module detects that the load sampling voltage of the output branch is lower than the preset valley reference voltage corresponding to the output branch; otherwise, the clock signal generation module generates an invalid clock enable signal. When the branch charging control module receives a valid clock enable signal, it controls the power switch of the output branch to turn on and start charging. Charging continues until the front-end detection module detects that the load sampling voltage of the output branch has reached a preset peak reference voltage. At this point, the branch charging control module controls the power switch of the output branch to turn off to stop charging. If the branch charging control module receives an invalid clock enable signal, it does not trigger the charging action for the output branch, and the power switch of the output branch remains off, thus skipping the charging of the output branch. According to this control logic, the two subsequent output branches are processed sequentially based on the branch control priority order. Finally, after completing the processing of all three output branches, the main power transistor control module controls the main power transistor to turn on again and start the next switching cycle.

3. A single-inductor, three-output DC-DC boost converter according to claim 2, characterized in that... The three output branches are defined as the first output branch, the second output branch, and the third output branch in order of branch control priority. The front-end detection module includes the first branch detection submodule and the second branch detection submodule. The first branch detection submodule is used to acquire the first branch load sampling voltage of the first output branch, and generate a first peak detection signal and a first valley detection signal corresponding to the first output branch; the first peak detection signal is used to indicate whether the first branch load sampling voltage of the first output branch reaches a preset first peak reference voltage, and the first valley detection signal is used to indicate whether the first branch load sampling voltage of the first output branch is lower than a preset first valley reference voltage. The second branch detection submodule is used to acquire the second branch load sampling voltage of the second output branch and generate a second peak detection signal and a second valley detection signal corresponding to the second output branch. The second peak detection signal is used to indicate whether the second branch load sampling voltage of the second output branch reaches a preset second peak reference voltage, and the second valley detection signal is used to indicate whether the second branch load sampling voltage of the second output branch is lower than a preset second valley reference voltage.

4. A single-inductor, three-output DC-DC boost converter according to claim 3, characterized in that... The first branch detection submodule includes a first peak comparator, a first valley comparator, and a first branch load voltage sampling module. The first branch load voltage sampling module generates a corresponding first branch load sampling voltage based on the load voltage of the first output branch. The positive input of the first peak comparator receives the first branch load sampling voltage, and the negative input is connected to a preset first peak reference voltage. The output of the first peak comparator outputs the first peak detection signal. The positive input of the first valley comparator receives the first branch load sampling voltage, and the negative input is connected to a preset first valley reference voltage. The output of the first valley comparator outputs the first valley detection signal through a first inverter. The second branch detection submodule includes a second peak comparator, a second valley comparator, and a second branch load voltage sampling module. The second branch load voltage sampling module generates a corresponding second branch load sampling voltage based on the load voltage of the second output branch. The positive input of the second peak comparator receives the second branch load sampling voltage, and the negative input is connected to a preset second peak reference voltage. The output of the second peak comparator outputs the second peak detection signal. The positive input of the second valley comparator receives the second branch load sampling voltage, and the negative input is connected to a preset second valley reference voltage. The output of the second valley comparator outputs the second valley detection signal via a second inverter.

5. A single-inductor, three-output DC-DC boost converter according to claim 4, characterized in that... The clock signal generation module includes a first clock signal generation submodule and a second clock signal generation submodule. The first clock signal generation submodule includes a first D flip-flop and a two-input AND gate. The second clock signal generation submodule includes a second D flip-flop, a third D flip-flop, a 2-to-1 data selector, and a four-input AND gate. The data input terminal and asynchronous reset terminal of the first D flip-flop respectively receive the first valley detection signal. The clock input terminal of the first D flip-flop receives the main power transistor switching control signal generated by the main power transistor control module. The non-inverting output terminal of the first D flip-flop outputs a first latch signal. The first input terminal of the two-input AND gate receives the first latch signal. The second input terminal of the two-input AND gate receives the inverted signal of the main power transistor switching control signal. The output terminal of the two-input AND gate outputs a first clock enable signal. The branch charging control module includes a first branch switch control module and a second branch switch control module. The first branch switch control module includes a fifth D flip-flop, and the second branch switch control module includes a sixth D flip-flop. The data input terminal of the fifth D flip-flop receives the first peak detection signal through a fourth inverter. The clock input terminal of the fifth D flip-flop receives the first clock enable signal. The asynchronous reset terminal of the fifth D flip-flop receives the inverted signal of the first peak detection signal. The inverted output terminal of the fifth D flip-flop outputs a first branch switch control signal for controlling the first power switch transistor of the first output branch. The data input terminal of the second D flip-flop receives the first valley detection signal, the asynchronous reset terminal of the second D flip-flop receives a high-level signal, the clock input terminal of the second D flip-flop receives the main power transistor switch control signal, and the non-inverting output terminal of the second D flip-flop outputs a second latch signal; the selection terminal of the 2-to-1 data selector receives the second latch signal, the first data input terminal of the 2-to-1 data selector receives the first branch switch control signal, the second data input terminal of the 2-to-1 data selector receives the inverted signal of the main power transistor switch control signal, and the output terminal of the 2-to-1 data selector is connected to a third... The inverter is connected to the clock input of the third D flip-flop; the data input and asynchronous reset of the third D flip-flop respectively receive the second valley detection signal, and the positive output of the third D flip-flop outputs the third latch signal; the first input of the four-input AND gate receives the inverted output signal of the first D flip-flop, the second input of the four-input AND gate receives the third latch signal, the third input of the four-input AND gate receives the inverted signal of the main power transistor switch control signal, the fourth input of the four-input AND gate receives the first branch switch control signal, and the output of the four-input AND gate outputs the second clock enable signal; The data input terminal of the sixth D flip-flop receives the second peak detection signal through the fifth inverter, the clock input terminal of the sixth D flip-flop receives the second clock enable signal, the asynchronous reset terminal of the sixth D flip-flop receives the inverted signal of the second peak detection signal, and the inverted output terminal of the sixth D flip-flop outputs a second branch switch control signal for controlling the second power switch of the second output branch.

6. A single-inductor, three-output DC-DC boost converter according to claim 5, characterized in that... It also includes a stability control module, and the front-end detection module further includes a third branch load voltage sampling module. The third branch load voltage sampling module is used to generate a corresponding third branch load sampling voltage based on the load voltage of the third output branch. The clock signal generation module further includes a third clock signal generation submodule, and the branch charging control module further includes a third branch switch control module. The stability control module is used to generate a system status signal based on the combined state of the sampled voltage of the third branch load and the state of the inductor current. The third clock signal generation submodule and the third branch switch control module control the charging process of the third output branch according to the system status signal: when the system status signal is valid, the third clock signal generation submodule allows the generation of a valid third clock enable signal, and the third branch switch control module controls the third power switch of the third output branch to be turned on for charging according to the valid third clock enable signal; when the system status signal is invalid, the third clock signal generation submodule prohibits the generation of a valid third clock enable signal, or during the charging process, the third branch switch control module forcibly turns off the third power switch of the third output branch to stop charging.

7. A single-inductor, three-output DC-DC boost converter according to claim 6, characterized in that... The stability control module includes a multi-input comparator, a low-pass filter, an inductor current peak comparator, and an inductor current valley comparator. The main power transistor control module includes an inductor current sampling resistor. One end of the inductor current sampling resistor is connected to the output terminal of the inductor and is used to acquire the inductor current sampling signal. The other end of the inductor current sampling resistor is grounded. The input terminal of the low-pass filter is connected to one end of the inductor current sampling resistor. The output terminal of the low-pass filter outputs the DC component of the inductor current sampling signal. The positive input terminal of the inductor current peak comparator is connected to one end of the inductor current sampling resistor, the negative input terminal of the inductor current peak comparator is used to connect to a preset inductor peak current reference voltage, and the output terminal of the inductor current peak comparator outputs an inductor current peak detection signal. The negative input terminal of the inductor current valley comparator is connected to one end of the inductor current sampling resistor, the positive input terminal of the inductor current valley comparator is used to connect to a preset inductor valley current reference voltage, and the output terminal of the inductor current valley comparator outputs an inductor current valley detection signal. The multi-input comparator includes a first positive input terminal, a second positive input terminal, a first negative input terminal, and a second negative input terminal. The first positive input terminal of the multi-input comparator is used to connect to a preset reference voltage of the third output branch. The second positive input terminal of the multi-input comparator is connected to the output terminal of the low-pass filter. The first negative input terminal of the multi-input comparator is used to receive the sampled voltage of the third branch load. The second negative input terminal of the multi-input comparator is connected to one end of the inductor current sampling resistor. The output terminal of the multi-input comparator outputs the system status signal.

8. A single-inductor, three-output DC-DC boost converter according to claim 7, characterized in that... The third clock signal generation submodule is a five-input AND gate. The first input of the five-input AND gate receives the inverted output signal of the first D flip-flop, the second input of the five-input AND gate receives the inverted output signal of the second D flip-flop, the third input of the five-input AND gate receives the inverted signal of the main power transistor switch control signal, the fourth input of the five-input AND gate receives the first branch switch control signal, the fifth input of the five-input AND gate receives the second branch switch control signal, and the output of the five-input AND gate outputs the third clock enable signal. The third branch switch control module includes a seventh D flip-flop, a sixth inverter, and a third NOR gate. The data input terminal of the seventh D flip-flop is connected to the output terminal of the multi-input comparator through the sixth inverter. The clock input terminal of the seventh D flip-flop receives the third clock enable signal. The asynchronous reset terminal of the seventh D flip-flop is connected to the output terminal of the third NOR gate. The inverted output terminal of the seventh D flip-flop outputs a third branch switch control signal for controlling the third power switch transistor of the third output branch. The first input terminal of the third NOR gate is connected to the output terminal of the multi-input comparator, and the second input terminal of the third NOR gate is connected to the output terminal of the inductor current valley comparator.

9. A single-inductor, three-output DC-DC boost converter according to claim 8, characterized in that... The system status signal is also used to control the charging process of the first output branch and the second output branch; The first branch switch control module further includes a first NOR gate, the first input terminal of which receives the first peak detection signal, the second input terminal of which is connected to the output terminal of the multi-input comparator, and the output terminal of which is connected to the asynchronous reset terminal of the fifth D flip-flop. The second branch switch control module further includes a second NOR gate, the first input terminal of which receives the second peak detection signal, the second input terminal of which is connected to the output terminal of the multi-input comparator, and the output terminal of which is connected to the asynchronous reset terminal of the sixth D flip-flop.

10. A single-inductor, three-output DC-DC boost converter according to claim 8 or 9, characterized in that... The main power transistor control module further includes a fourth D flip-flop and a seventh inverter; the data input terminal and asynchronous reset terminal of the fourth D flip-flop are both connected to the output terminal of the inductor current peak comparator through the seventh inverter; the clock input terminal of the fourth D flip-flop is connected to the output terminal of the multi-input comparator; the non-inverting output terminal of the fourth D flip-flop outputs the main power transistor switching control signal; and the inverting output terminal of the fourth D flip-flop outputs the inverted signal of the main power transistor switching control signal.

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