Polar amplifier with dynamic duty cycle

Abstract

This disclosure provides a polar coordinate amplifier with a dynamic duty cycle. The electronic device may include a wireless circuit having a polar coordinate power amplifier. The gate terminal of a transistor in the PMOS portion of the amplifier may receive a first local oscillator (LO) signal. The gate terminal of a transistor in the NMOS portion of the amplifier may receive a second LO signal. A tunable clock generator may generate the first and second LO signals based on binary control signals received from a physical layer (PHY) controller. The PHY controller may supply the binary control signals to weighted / enabled transistors in the inverter group of the tunable clock generator to dynamically adjust the duty cycle ratio between the first and second LO signals over time. The PHY controller may perform this adjustment over time based on the characteristics of the radio frequency signal in a manner that optimizes the linearity and power consumption of the amplifier, even when the characteristics change.

Description

[0001] This application claims priority to U.S. Patent Application No. 19 / 016,212, filed January 10, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates in general to electronic devices, including electronic devices having wireless circuitry. Background Technology

[0003] Electronic devices may possess wireless communication capabilities. Electronic devices with wireless communication capabilities have wireless circuitry, which includes one or more antennas. The wireless transceiver circuitry within the wireless circuitry uses the antennas to transmit and receive radio frequency signals.

[0004] The radio frequency (RF) signal transmitted by the antenna can be fed through one or more power amplifiers configured to amplify the low-power analog signal into a higher-power signal more suitable for long-distance transmission over the air. Providing a power amplifier with sufficient performance levels can be challenging. For example, if not carefully managed, the power amplifier may exhibit insufficient dynamic range and linearity, which could limit the RF performance of the wireless circuitry. Summary of the Invention

[0005] An electronic device may include a wireless circuit. The wireless circuit may include a transmission path. The transmission path may include a polar power amplifier that outputs a radio frequency (RF) signal. The amplifier may include a p-channel metal-oxide-semiconductor (PMOS) portion and an n-channel metal-oxide-semiconductor (NMOS) portion. The PMOS portion may receive a power supply voltage that carries amplitude modulation of the RF signal. The gate terminals of some transistors in the PMOS portion of the amplifier may receive a first local oscillator (LO) signal. The gate terminals of some transistors in the NMOS portion of the amplifier may receive a second LO signal. The first LO signal and the second LO signal may carry phase modulation of the RF signal.

[0006] A tunable clock generator can generate the first LO signal and the second LO signal based on an oscillation signal received from a physical layer (PHY) controller and an M-bit binary control signal. For example, the tunable clock generator may include a first set of M complementary metal-oxide-semiconductor (CMOS) inverters that generate the first LO signal with a first duty cycle, and may include a second set of M CMOS inverters that generate the second LO signal with a second duty cycle. The first duty cycle and the second duty cycle define the duty cycle ratio between the first LO signal and the second LO signal.

[0007] The PHY controller may have knowledge of one or more characteristics of the RF signal to be transmitted by the amplifier. The PHY controller may supply corresponding bits of the M-bit binary control signal to the weighted / enable transistors in each of the M CMOS inverters in the first group and in each of the M CMOS inverters in the second group. The M-bit binary control signal may dynamically control the first and second groups to adjust the duty cycle ratio between the first LO signal and the second LO signal over time. The PHY controller may perform this adjustment based on one or more characteristics of the RF signal in a way that optimizes the linearity and power consumption of the amplifier over time, even when these characteristics change. For example, when the RF signal is at a low power level and / or exhibits a peak-to-average power ratio (PAPR), the LO signal may be provided as an overlapped signal, and when the RF signal is at a high power level and / or exhibits a low PAPR, the LO signal may be provided as a non-overlapping signal.

[0008] One aspect of this disclosure provides a wireless circuit. The wireless circuit may include a tunable clock generator configured to generate a first local oscillator (LO) signal and a second LO signal, the tunable clock generator being configured to adjust the duty cycle ratio between the first LO signal and the second LO signal over time. The wireless circuit may include an amplifier configured to output a radio frequency (RF) signal, wherein the first LO signal and the second LO signal deliver a phase modulation of the RF signal. The amplifier may include a first power input receiving a power supply voltage that delivers an amplitude modulation of the RF signal. The amplifier may include a second power input receiving a reference voltage. The amplifier may include a p-type transistor coupled to the first power input and having a gate terminal configured to receive the first LO signal. The amplifier may include an n-type transistor coupled to the second power input and having a gate terminal configured to receive the second LO signal.

[0009] One aspect of this disclosure provides a method for transmitting a radio frequency (RF) signal. The amplifier may include supplying a power supply voltage to a power input terminal of the amplifier, wherein the power supply voltage carries amplitude modulation of the RF signal. The method may include providing a first LO signal to a p-channel metal-oxide-semiconductor (PMOS) portion of the amplifier and a second LO signal to an n-channel metal-oxide-semiconductor (NMOS) portion of the amplifier using a local oscillator (LO) generator, wherein the first LO signal and the second LO signal carry phase modulation of the RF signal. The method may include using one or more processors to control the LO generator to adjust the duty cycle ratio between the first LO signal and the second LO signal based on characteristics of the RF signal.

[0010] One aspect of this disclosure provides a wireless circuit. The wireless circuit may include a polar coordinate amplifier configured to output a radio frequency (RF) signal. The wireless circuit may include a clock circuit configured to supply a first local oscillator (LO) signal and a second LO signal to the polar coordinate amplifier, wherein the first LO signal and the second LO signal transmit phase modulation of the RF signal. The wireless circuit may include one or more processors configured to control the clock circuit to switch between supplying the first LO signal and the second LO signal as overlapping signals to the polar coordinate amplifier and supplying the first LO signal and the second LO signal as non-overlapping signals to the polar coordinate amplifier based on one or more characteristics of the RF signal. Attached Figure Description

[0011] Figure 1 These are illustrations of exemplary electronic devices, including wireless circuits, based on some implementation schemes.

[0012] Figure 2 This is a diagram of an exemplary wireless circuit including a radio frequency amplifier, based on some implementation schemes.

[0013] Figure 3 This is a diagram of an exemplary transmitting circuit including a polar coordinate amplifier, based on some implementation schemes.

[0014] Figure 4 and Figure 5 This is a circuit diagram of an exemplary polar coordinate amplifier with dynamic duty cycle according to some implementation schemes.

[0015] Figure 6 This is a circuit diagram of an exemplary dynamic duty cycle generator for a polar coordinate amplifier, based on some implementation schemes.

[0016] Figure 7 This is a state diagram illustrating the exemplary operating modes of a polar coordinate amplifier with dynamic duty cycle, based on some implementation schemes.

[0017] Figure 8 This is a flowchart illustrating the exemplary operations involved in transmitting radio frequency signals using a polar coordinate amplifier with a dynamic duty cycle.

[0018] Figure 9 This is an example of how dynamically adjusting the duty cycle of the clock signal provided to the polar coordinate amplifier according to some implementation schemes can reduce the amplitude modulation to phase modulation (AMPM) distortion of the amplifier.

[0019] Figure 10This is a graph illustrating how dynamically adjusting the duty cycle of the clock signal provided to the polar coordinate amplifier according to some implementation schemes can reduce the adjacent channel leakage ratio (ACLR) of the polar coordinate amplifier. Detailed Implementation

[0020] Figure 1 The electronic device 10 may be: a computing device, such as a laptop computer, desktop computer, computer monitor containing an embedded computer, tablet computer, cellular phone, media player, or other handheld or portable electronic device; a smaller device, such as a wristwatch, a wristband, a headset or handset, a device embedded in glasses, goggles, a helmet; or other equipment worn on the user's head (e.g., an augmented, virtual, or mixed reality head-mounted display device); or another wearable or micro device, a television, a computer monitor without an embedded computer, a gaming device, a navigation device, an embedded system (such as a system in which electronic equipment with a display is installed in a kiosk or a car), a voice-controlled speaker connected to the wireless Internet, a home entertainment device, a remote control device, a game controller, a peripheral user input device, a wireless base station or access point, equipment that enables the functionality of two or more of these devices; or other electronic equipment.

[0021] like Figure 1 As shown in the functional block diagram, device 10 may include components located on or within an electronic device housing, such as housing 12. Housing 12 (sometimes referred to as a shell) may be formed of plastic, glass, ceramic, fiber composite material, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or combinations of these materials. In some embodiments, housing 12 may be partially or entirely formed of dielectric or other low-conductivity materials (e.g., glass, ceramic, plastic, sapphire, etc.). In other embodiments, housing 12, or at least some of the structures constituting housing 12, may be formed of metallic elements.

[0022] Device 10 may include control circuitry 14. Control circuitry 14 may include storage devices, such as storage device circuitry 16. Storage device circuitry 16 may include hard disk drive storage devices, non-volatile memory (e.g., flash memory configured to form a solid-state drive or other electrically programmable read-only memory), volatile memory (e.g., static random access memory or dynamic random access memory), etc. Storage device circuitry 16 may include storage devices integrated within device 10, and / or removable storage media.

[0023] Control circuitry 14 may include processing circuitry, such as processing circuitry 18. Processing circuitry 18 may be used to control the operation of device 10. Processing circuitry 18 may include one or more processors, such as a microprocessor, microcontroller, digital signal processor, host processor, baseband processor integrated circuit, application-specific integrated circuit, central processing unit (CPU), graphics processing unit (GPU), etc. Control circuitry 14 may be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code for performing operations in device 10 may be stored on storage device circuitry 16 (e.g., storage device circuitry 16 may include a non-transitory (tangible) computer-readable storage medium storing software code). This software code may sometimes be referred to as program instructions, software, data, commands, or code. The software code stored on storage device circuitry 16 may be executed by processing circuitry 18.

[0024] Control circuitry 14 can be used to run software on device 10, such as satellite navigation applications, internet browsing applications, Voice over Internet Protocol (VoIP) telephone calling applications, email applications, media playback applications, operating system functions, etc. To support interaction with external equipment, control circuitry 14 can be used to implement communication protocols. Communication protocols that can be implemented using control circuitry 14 include Internet Protocol, Wireless Local Area Network (WLAN) protocols (e.g., IEEE 802.11 protocol—sometimes referred to as Wi-Fi). ® ), such as Bluetooth ® Protocols such as those used for other short-range wireless communication links, including wireless personal area network (WPAN) protocols, IEEE 802.11ad protocols (e.g., ultra-wideband protocols), cellular phone protocols (e.g., 3G protocols, 4G (LTE) protocols, 3GPP fifth-generation (5G) new radio (NR) protocols, sixth-generation (6G) protocols, sub-THz protocols, THz protocols, etc.), antenna diversity protocols, satellite navigation system protocols (e.g., Global Positioning System (GPS) protocols, Global Navigation Satellite System (GLONASS) protocols, etc.), satellite communication (SATCOM) protocols, antenna-based spatial ranging protocols, optical communication protocols, or any other desired communication protocols. Each communication protocol may be associated with a corresponding radio access technology (RAT), which specifies the physical connection method used to implement the protocol.

[0025] Device 10 may include input-output circuitry 20. Input-output circuitry 20 may include input-output devices 22. Input-output devices 22 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output devices 22 may include user interface devices, data port devices, and other input-output components. For example, input-output devices 22 may include touch sensors, displays (e.g., touch-sensitive displays and / or force-sensitive displays), light-emitting components such as displays without touch sensor capability, buttons (mechanical, capacitive, optical, etc.), scroll wheels, touchpads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses for detecting motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), etc. In some configurations, keyboards, headphones, displays, pointing devices such as touchpads, mice and joysticks, and other input-output devices may be coupled to device 10 via wired or wireless connections (e.g., some of the input-output devices 22 may be peripherals coupled to the main processing unit or other parts of device 10 via wired or wireless links).

[0026] Input-output circuitry 20 may include wireless circuitry 24 to support or perform radio frequency (RF) signal transmission and / or reception of device 10. Wireless circuitry 24 may be used for wireless communication. Wireless communication performed by wireless circuitry 24 may include or involve wireless data communication (e.g., where wireless data is carried by RF signals transmitted bidirectionally or unidirectionally between wireless circuitry 24 and other communication equipment), RF signal transmission, RF signal reception, and / or radio-based spatial ranging / sensing (e.g., radio detection and ranging (radar) operation, short-range object detection such as object detection based on near-field RF signals, etc.). RF signals transmitted by wireless circuitry 24 may include or carry wireless data (e.g., organized into frames, packets, symbols, datagrams, etc.), radar or other spatial ranging waveforms, continuous wave signals, chirped signals, control signals, management signals, reference signals, beacon signals, tones, pulses / pulses, waveforms associated with one or more communication protocols, and / or any other RF waveforms or signals. Wireless circuit 24 is sometimes referred to herein as wireless communications circuitry 24, wireless communication circuitry 24, communication circuit 24, or simply circuit 24. Wireless circuit 24 may include one or more antennas. Wireless circuit 24 may also include baseband processor circuitry, transceiver circuitry, amplifier circuitry, filter circuitry, switching circuitry, radio frequency transmission lines, and / or any other circuitry for transmitting and / or receiving radio frequency signals using antennas. Some or all components of wireless circuit 24 may be disposed on, mounted to, communicatively coupled to, and / or integrated within the same substrate (e.g., printed circuit board, semiconductor substrate, chip, integrated circuit (IC), IC package, etc.), or distributed between two or more substrates (e.g., printed circuit board, semiconductor substrate, chip, IC, IC package, etc.).

[0027] Wireless circuit 24 can transmit and / or receive radio frequency signals within the corresponding frequency band of a radio frequency (sometimes referred to herein as a communication band or simply a "band"). The frequency band processed by wireless circuit 24 may include wireless local area network (WLAN) bands (e.g., Wi-Fi). ® (IEEE 802.11) or other WLAN communication bands such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), Wi-Fi ® 6E band (e.g., 5925MHz to 7125MHz), Wi-Fi ® 7-band and / or other Wi-Fi ®Frequency bands (e.g., 1875MHz to 5160MHz); Wireless Personal Area Network (WPAN) bands such as 2.4GHz Bluetooth. ® Frequency bands or other WPAN communication bands; cellular phone bands (e.g., bands from approximately 600 MHz to approximately 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) band below 10 GHz, 5G New Radio Frequency Range 2 (FR2) band between 20 GHz and 60 GHz, etc.); other centimeter or millimeter wave bands between 10 GHz and 100 GHz; sub-THz bands between approximately 100 GHz and 10 THz (e.g., 6G bands); near field communication (NFC) bands (e.g., 13.56 MHz); satellite navigation bands (e.g., GPS bands from 1565 MHz to 1610 MHz, Global Navigation Satellite System (GLONASS) bands, BeiDou Navigation Satellite System (BDS) bands, etc.); ultra-wideband (UWB) bands operating under the IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols; satellite communication (satcom) bands (e.g., IEEE...). C-band (4-8GHz), S-band (2-4GHz), L-band (1-2GHz), X-band (8-12GHz), W-band (75-110GHz), V-band (40-75GHz), K-band (18-27GHz), K a Frequency band (26.5-40GHz), K u Frequency bands (12-18GHz, etc.); unlicensed frequency bands; communication frequency bands under the 3GPP wireless communication standard family; communication frequency bands under the IEEE 802.XX standard family; and / or any other desired frequency bands of interest.

[0028] Figure 2 This is a diagram showing exemplary components within wireless circuit 24. For example... Figure 2 As shown, wireless circuitry 24 may include a processor such as processor 26, radio frequency (RF) transceiver circuitry such as RF transceiver 28, RF front-end circuitry such as RF front-end module (FEM) 40, and antenna 42. Processor 26 may be a baseband processor, application processor, general-purpose processor, microprocessor, microcontroller, digital signal processor, host processor, dedicated signal processing hardware, or other type of processor. Processor 26 may be coupled to transceiver 28 via path 34. Transceiver 28 may be coupled to antenna 42 via RF transmission line path 36. RF front-end module 40 may be disposed on RF transmission line path 36 between transceiver 28 and antenna 42.

[0029] exist Figure 2In the example, for clarity, wireless circuit 24 is illustrated as including only a single processor 26, a single transceiver 28, a single front-end module 40, and a single antenna 42. Generally, wireless circuit 24 may include any desired number of processors 26, any desired number of transceivers 28, any desired number of front-end modules 40, and any desired number of antennas 42. Each processor 26 may be coupled to one or more transceivers 28 via a corresponding path 34. Each transceiver 28 may include transmitter circuitry 30 configured to output uplink signals to antenna 42, may include receiver circuitry 32 configured to receive downlink signals from antenna 42, and may be coupled to one or more antennas 42 via a corresponding RF transmit line path 36. Each RF transmit line path 36 may have a corresponding front-end module 40 disposed thereon. If desired, two or more front-end modules 40 may be disposed on the same RF transmit line path 36. If desired, one or more RF transmit line paths 36 in wireless circuit 24 may be implemented without any front-end modules disposed thereon.

[0030] The RF transmit line path 36 may be coupled to an antenna feed section on the antenna 42. The antenna feed section may, for example, include a positive antenna feed terminal and a ground antenna feed terminal. The RF transmit line path 36 may have a positive transmit line signal path coupled to a positive antenna feed terminal on the antenna 42. The RF transmit line path 36 may also have a ground transmit line signal path coupled to a ground antenna feed terminal on the antenna 42. This example is illustrative, and in general, the antenna 42 may be fed using any desired antenna feeding scheme. If desired, the antenna 42 may have multiple antenna feed sections coupled to one or more RF transmit line paths 36.

[0031] RF transmission path 36 may include a means for communication with device 10 ( Figure 1 The transmitting lines in device 10 route the radio frequency antenna signals within the device. The transmitting lines in device 10 may include coaxial cables, microstrip transmitting lines, stripline transmitting lines, edge-coupled microstrip transmitting lines, edge-coupled stripline transmitting lines, and transmitting lines formed by combinations of these types of transmitting lines. The transmitting lines in device 10 (such as the transmitting lines in radio frequency transmitting line path 36) may be integrated into rigid and / or flexible printed circuit boards.

[0032] During wireless transmission, processor 26 can provide a transmit signal (e.g., a digital or baseband signal) to transceiver 28 via path 34. Transceiver 28 may also include circuitry for converting the transmit (baseband) signal received from processor 26. For example, transceiver circuitry 28 may include mixer circuitry for up-converting (or modulating) the transmit (baseband) signal to radio frequency before transmission via antenna 42. The processor 26 communicates with transceiver 28 in this manner. Figure 2 The examples are illustrative. Generally, transceiver 28 can communicate with a baseband processor, application processor, general-purpose processor, microcontroller, microprocessor, or one or more processors within circuit 18. Transceiver circuit 28 may also include digital-to-analog converter (DAC) circuitry and / or analog-to-digital converter (ADC) circuitry for converting signals between the digital and analog domains. Transceiver 28 can transmit radio frequency (RF) signals via transmitter (TX) 30 through RF transmission line path 36 and front-end module 40 via antenna 42. Antenna 42 can transmit the RF signal to external wireless equipment by radiating the RF signal into free space.

[0033] During wireless reception, antenna 42 can receive radio frequency (RF) signals from external wireless equipment. The received RF signals can be transmitted to transceiver 28 via RF transmission path 36 and front-end module 40. Transceiver 28 may include circuitry, such as receiver (RX) 32, for receiving signals from front-end module 40 and for converting the received RF signals into corresponding baseband signals. For example, transceiver 28 may include mixer circuitry for down-converting (or demodulating) the received RF signals to baseband frequencies before transmitting the received signals via path 34 to processor 26.

[0034] Front-end module (FEM) 40 may include radio frequency front-end circuitry that operates on radio frequency signals transmitted (transmitted and / or received) via radio frequency transmission line path 36. For example, FEM 40 may include front-end module (FEM) components such as radio frequency filter circuitry 44 (e.g., low-pass filter, high-pass filter, notch filter, band-pass filter, multiplexing circuitry, duplexer circuitry, dual-signal circuitry, triplexer circuitry, etc.), switching circuitry 46 (e.g., one or more radio frequency switches), radio frequency amplifier circuitry 48 (e.g., one or more power amplifiers 50 and / or one or more low-noise amplifier circuitry 52), signal attenuators, impedance matching circuitry (e.g., circuitry that helps match the impedance of antenna 42 with the impedance of radio frequency transmission line 36), antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and / or switches that adjust the frequency response of antenna 42), radio frequency coupler circuitry, charge pump circuitry, power management circuitry, digital control and interface circuitry, and / or any other desired circuitry that operates on the radio frequency signals transmitted and / or received by antenna 42. Each of the front-end module components can be mounted on a common (shared) substrate, such as a rigid printed circuit board substrate or a flexible printed circuit board substrate. If desired, the various front-end module components can also be integrated into a single integrated circuit chip. If desired, amplifier circuit 48 and / or other components in front-end 40 (such as filter circuit 44) can also be implemented as part of transceiver circuit 28.

[0035] Filter circuit 44, switching circuit 46, amplifier circuit 48, and other circuits may be disposed along RF transmission line path 36, may be incorporated into FEM 40, and / or may be incorporated into antenna 42 (e.g., to support antenna tuning, to support operation in a desired frequency band, etc.). These components (sometimes referred to herein as antenna tuning components) may be adjusted (e.g., using control circuit 14) to adjust the frequency response and wireless performance of antenna 42 over time.

[0036] Transceiver 28 may be separate from front-end module 40. For example, transceiver 28 may be formed on another substrate such as the main logic board of device 10, a rigid printed circuit board, or a flexible printed circuit that is not part of front-end module 40. Although for clarity, in Figure 1In the example, control circuitry 14 is shown separate from wireless circuitry 24, but wireless circuitry 24 may include processing circuitry and / or storage circuitry, the processing circuitry forming part of processing circuitry 18, and the storage circuitry forming part of storage circuitry 16 of control circuitry 14 (e.g., portions of control circuitry 14 may be implemented on wireless circuitry 24). As an example, portions of processor 26 and / or transceiver 28 (e.g., a host processor on transceiver 28) may form part of control circuitry 14. Control circuitry 14 (e.g., portions of control circuitry 14 formed on processor 26, portions of control circuitry 14 formed on transceiver 28, and / or portions of control circuitry 14 separate from wireless circuitry 24) may provide control signals (e.g., via one or more control paths in device 10) to control the operation of front-end module 40.

[0037] Transceiver 28 may include a frequency band for processing WLAN communication (e.g., Wi-Fi). ® (IEEE 802.11) or other WLAN communication bands such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), Wi-Fi ® 6E band (e.g., 5925MHz to 7125MHz) and / or other Wi-Fi ® Wireless LAN transceiver circuitry covering a frequency band (e.g., 1875MHz to 5160MHz); handling 2.4GHz Bluetooth. ® Wireless personal area network transceiver circuits for frequency bands or other WPAN communication bands; cellular phone transceiver circuits that process cellular phone frequency bands (e.g., bands from approximately 600 MHz to approximately 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) band below 10 GHz, 5G New Radio Frequency Range 2 (FR2) band between 20 GHz and 60 GHz, 6G bands above 100 GHz, etc.); near field communication (NFC) transceiver circuits that process near field communication frequency bands (e.g., 13.56 MHz); satellite navigation receiver circuits that process satellite navigation frequency bands (e.g., GPS band from 1565 MHz to 1610 MHz, Global Navigation Satellite System (GLONASS) band, BeiDou Navigation Satellite System (BDS) band, etc.); and circuits that use IEEE... Ultra-wideband (UWB) transceiver circuitry for handling communications using the 802.15.4 protocol and / or other ultra-wideband communication protocols; and / or any other desired radio frequency transceiver circuitry for covering any other desired communication frequency band of interest.

[0038] Wireless circuit 24 may include one or more antennas, such as antenna 42. Antenna 42 can be formed using any desired antenna structure. For example, antenna 42 may be an antenna with a resonant element, formed from a loop antenna structure, patch antenna structure, inverted F-shaped antenna structure, slot antenna structure, planar inverted F-shaped antenna structure, helical antenna structure, monopole antenna, dipole, a combination of these designs, etc. Two or more antennas 42 may be arranged in one or more phased antenna arrays (e.g., for transmitting radio frequency signals at millimeter-wave frequencies). Parasitic elements may be included in antenna 42 to adjust antenna performance. Antenna 42 may be provided with a conductive cavity that supports the antenna resonant element of antenna 42 (e.g., antenna 42 may be a cavity-backed antenna, such as a cavity-backed slot antenna).

[0039] As described above, the front-end module 40 may include one or more power amplifiers (PAs) 50 in the transmit (uplink) path. The power amplifiers 50 (sometimes referred to as RF power amplifiers, transmit amplifiers, or amplifiers) may be configured to amplify the RF signal without altering its shape, format, or modulation. For example, amplifiers 50 may be used to provide 10dB gain, 20dB gain, 10dB-20dB gain, less than 20dB gain, more than 20dB gain, or other suitable amounts of gain.

[0040] Figure 3 This is a diagram illustrating an exemplary transmission path 58 of wireless circuit 24. Transmission path 58 is sometimes referred to herein as transmission chain 58 or transmission circuit 58. (Example...) Figure 3 As shown, wireless circuit 24 may include processing circuitry such as one or more processors 26, converter circuitry such as converter circuitry 54, radio frequency amplifier circuitry such as radio frequency amplifier 50 (e.g., power amplifier), and an antenna 42 configured to radiate the radio frequency signal output by amplifier 50. Additional components (not shown) may also be provided at different locations along the transmission path 58 if desired.

[0041] Amplifier 50 can be set on FEM 40 or Figure 2 In the transceiver circuit 28. Processor 26 may represent one or more processors, such as a baseband processor, application processor, digital signal processor, microcontroller, microprocessor, central processing unit (CPU), programmable device, combination of these circuits and / or Figure 1 One or more processors are included within circuit 18. Processor 26 may be configured to generate a digital baseband signal Dbb (e.g., a digital data bit stream at baseband). Signal Dbb is sometimes referred to as a digital signal or a transmit signal. As an example, signal Dbb generated by processor 26 may include in-phase (I) and quadrature-phase (Q) signals, radius and phase signals, vector inputs, or other digitally decoded signals.

[0042] In the specific implementation described herein as an example, amplifier 50 is implemented as a polar power amplifier (PA). Therefore, amplifier 50 is sometimes referred to herein as polar PA 50, polar RF amplifier 50, or simply polar amplifier 50. For example, a polar amplifier can be scaled more easily during the fabrication / manufacturing of wireless circuit 24 than a non-polar amplifier architecture. Implementing amplifier 50 as a polar amplifier also allows the transmission circuit 58 to be implemented without an additional / dedicated mixer for up-converting the signal to RF (e.g., because amplifier 50 uses a local oscillator signal to drive the amplifier output as an amplified signal at RF, which is then used as the RF signal RFSIG).

[0043] When implemented as a polar coordinate amplifier, amplifier 50 may include a first power supply voltage terminal or input, such as power supply input 68 (sometimes referred to herein as power supply terminal 68, power input terminal 68, bias terminal 68, or bias input terminal 68). Amplifier 50 may also include a second power supply input, such as a reference voltage input 71 (sometimes referred to herein as power supply terminal 71, reference terminal 71, reference input terminal 71, bias input terminal 71, bias terminal 71, ground input terminal 71, or ground terminal 71). Reference voltage input 71 may receive a reference potential, such as reference voltage 66 (e.g., ground voltage, VSS, or another reference potential). For example, reference voltage input 71 and power supply input 68 may form a power supply voltage rail for amplifier 50.

[0044] Amplifier 50 may also include a clock terminal or input, different from the power supply input 68 and the reference voltage input 71, such as a local oscillator (LO) input 70 (sometimes referred to herein as LO terminal 70, LO input terminal 70, clock input terminal 70, or clock input terminal 70). Amplifier 50 may receive a clock signal, such as a local oscillator signal, at its LO input 70. In a specific implementation described herein by way of example, the clock signal may include a differential LO signal pair comprising a first (positive) LO signal LOP and a second (negative) LO signal LON. Amplifier 50 may receive a power supply voltage, such as a power supply voltage VDD, at its power supply input 68. Amplifier 50 may use the local oscillator signals LOP and LON and the power supply voltage VDD to generate an radio frequency signal RFSIG (e.g., without using up-conversion or mixer circuitry separate from amplifier 50).

[0045] The input of converter circuit 54 is communicatively coupled to the output of processor 26. Converter circuit 54 may have a first output communicatively coupled to the LO input 70 of amplifier 50 via signal path 60. Converter circuit 54 may also have a second output communicatively coupled to the power input 68 of amplifier 50 via signal path 62. Signal path 60 is sometimes referred to herein as phase signal path 60. Signal path 62 is sometimes referred to herein as amplitude signal path 62.

[0046] The converter circuit 54 may include signal conversion circuitry, such as a digital-to-analog converter (DAC) circuit and a Cartesian-to-polar coordinate converter circuit. As an example, the Cartesian-to-polar coordinate converter circuit may be implemented using one or more digital signal processors within the converter circuit 54. The Cartesian-to-polar coordinate converter circuit can convert the signal Dbb from a single signal in Cartesian coordinates into two distinct signals in polar coordinates. The two signals in polar coordinates may include an amplitude signal (waveform) A(t) and a corresponding phase signal (waveform) θ(t).

[0047] The amplitude signal A(t) represents the amplitude of the signal Dbb and the associated radio frequency signal output by amplifier 50 at time t. The phase signal θ(t) represents the phase of the signal Dbb and the associated radio frequency signal output by amplifier 50 at the same time t. For example, the DAC circuit in converter circuit 54 may include a first DAC (e.g., a first set of one or more DAC units) that converts the amplitude signal A(t) from the digital domain to the analog domain and may include a second DAC (e.g., a second set of one or more DAC units) that converts the phase signal θ(t) from the digital domain to the analog domain. Converter circuit 54 may output the amplitude signal A(t) to signal path 62 (in the analog domain). Converter circuit 54 may simultaneously output the phase signal θ(t) to signal path 60 (in the analog domain).

[0048] If desired, wireless circuit 24 may include amplifier circuitry, such as an envelope amplifier 64 disposed on signal path 62 between converter circuitry 54 and amplifier 50. Envelope amplifier 64 may amplify (scale) the amplitude signal A(t) to generate a supply voltage VDD provided to amplifier 50 (e.g., the supply voltage VDD may vary according to the amplitude signal A(t) over time, or equivalently, the amplitude signal A(t) may represent the supply voltage VDD before scaling by envelope amplifier 64). If desired, envelope amplifier 64 may be replaced by any desired supply voltage generation circuitry (e.g., power integrated circuit, power management unit, low dropout (LDO) regulator, envelope tracking integrated circuit, etc.) that generates the supply voltage VDD based on the amplitude signal A(t) (e.g., by scaling or otherwise processing the amplitude signal A(t)). Alternatively, envelope amplifier 64 may be omitted, and the supply voltage VDD may be formed by the amplitude signal A(t) without scaling or amplification. Generally speaking, the power supply voltage VDD can be a voltage waveform that encodes or carries the amplitude information (modulation) of the radio frequency signal RFSIG to be output by amplifier 50 (e.g., represented by the amplitude signal A(t)). The power supply input 68 is sometimes referred to herein as the amplitude modulation (AM) input of amplifier 50.

[0049] Wireless circuit 24 may include clock circuitry, such as an LO generator 56 disposed on signal path 60 between converter circuit 54 and amplifier 50. LO generator 56 may generate local oscillator signals LOP and LON provided to the LO input 70 of amplifier 50 based on a phase signal θ(t). (E.g., the local oscillator signals LOP and LON may encode phase information (modulation) of the radio frequency signal RFSIG to be output by amplifier 50.) For example, LO generator 56 may include synthesizers, signal generators, oscillator circuitry (e.g., crystal oscillator, voltage-controlled oscillator (VCO), etc.), loop circuitry (e.g., one or more phase-locked loops, frequency-locked loops, etc.), inverter circuitry, and / or any other desired circuitry that converts the phase signal θ(t) into local oscillator signals LOP and LON. More generally, the local oscillator signals LOP and LON may be any desired oscillation or periodic clock signal used to drive amplifier 50 using phase modulation from the output of converter circuit 54 (e.g., phase modulation of the radio frequency signal RFSIG to be transmitted). Phase modulation (coding) performed by amplifier 50 under the control of local oscillator signals LOP and LON (e.g., based on phase signal θ(t)) and / or amplitude modulation (coding) performed by amplifier 50 under the control of power supply voltage VDD (e.g., based on amplitude signal A(t)) can collectively represent the radio data carried by signal Dbb and radio frequency signal RFSIG (e.g., converter circuit 54 can convert the radio data in signal Dbb (such as baseband data representing symbol streams, packets, frames, datagrams, etc.) into time-varying amplitude modulation carried by amplitude signal A(t) and time-varying phase modulation carried by phase signal θ(t).

[0050] During signal transmission, local oscillator signals LOP and LON drive amplifier 50, while simultaneously powering amplifier 50 with the corresponding voltage waveform of the power supply voltage VDD. This allows amplifier 50 to output an amplified radio frequency (RF) signal RFSIG in the corresponding frequency band at its output. The RF signal RFSIG may have a phase (as a function of time) controlled by the local oscillator signals LOP and LON and the phase signal θ(t). The RF signal RFSIG may have a corresponding magnitude or amplitude (as a function of time) controlled by the power supply voltage VDD and the amplitude signal A(t). Antenna 42 radiates the RF signal RFSIG.

[0051] In the specific implementation described herein as an example, local oscillator signals LOP and LON may be provided to amplifier 50 with a dynamically adjustable duty cycle (e.g., amplifier 50 may use a dynamic duty cycle to generate radio frequency signal RFSIG). Figure 4 and Figure 5This is a circuit diagram illustrating an example of how local oscillator signals LOP and LON can be provided to amplifier 50 with a dynamically adjustable duty cycle.

[0052] like Figure 4 As shown, amplifier 50 can be a complementary metal-oxide-semiconductor (CMOS) amplifier with an amplifier core comprising an array of p-channel metal-oxide-semiconductor (PMOS) transistors 92P and an array of n-channel metal-oxide-semiconductor (NMOS) transistors 92N. Transistor 92P is sometimes referred to herein as a PMOS transistor 92P or a p-type transistor 92P. Transistor 92N is sometimes referred to herein as an NMOS transistor 92N or an n-type transistor 92N.

[0053] PMOS transistor 92P may be used, for example, to form one or more PMOS common-source stages of amplifier 50 (e.g., PMOS transistor 92P may be a PMOS common-source transistor). NMOS transistor 92N may be used, for example, to form one or more NMOS common-source stages of amplifier 50 (e.g., NMOS transistor 92N may be an NMOS common-source transistor). The PMOS common-source stage and the NMOS common-source stage may be coupled in series between the power supply input terminal 68 and the reference voltage input terminal 71 of amplifier 50. For example, amplifier 50 may also include one or more common-source and common-gate stages (e.g., PMOS common-source and common-gate stages and NMOS common-source and common-gate stages) coupled in series between the PMOS common-source stage and the NMOS common-source stage (e.g., PMOS common-source stage, PMOS common-source and common-gate stage, NMOS common-source and common-gate stage and NMOS common-source stage may be coupled in series between the power supply input terminal 68 and the reference voltage input terminal 71). Amplifier 50 may have an RF output coupled between a PMOS cascode stage and an NMOS cascode stage (e.g., between the PMOS and NMOS portions of amplifier 50). The RF output may be communicatively coupled to antenna 42. Figure 3 During signal transmission, amplifier 50 can output an RF signal RFSIG at its RF output terminal. Figure 3 ).

[0054] The signal path 60 coupled to the LO input 70 of amplifier 50 may include a first (e.g., positive) signal line 60P and a second (e.g., negative) signal line 60N. The LO input 70 may include a first clock terminal, such as the LO input terminal 70P (e.g., for clocking the PMOS portion of amplifier 50 using a local oscillator signal LOP), and may include a second clock terminal, such as the LO input terminal 70N (e.g., for clocking the NMOS portion of amplifier 50 using a local oscillator signal LON). Signal line 60P may be coupled to the LO input terminal 70P. Signal line 60N may be coupled to the LO input terminal 70N. The gate terminal of transistor 92P may be communicatively coupled to the LO input terminal 70P and therefore communicatively coupled to signal line 60P. The gate terminal of transistor 92N may be communicatively coupled to the LO input terminal 70N and therefore communicatively coupled to signal line 60N.

[0055] When referring to the current-conducting terminals of a metal-oxide-semiconductor (MOS) transistor, the terms "source" and "drain" are sometimes used interchangeably. Therefore, the source and drain terminals are sometimes referred to as "source-drain" terminals (e.g., a transistor having a gate terminal, a first source-drain terminal, and a second source-drain terminal). A PMOS transistor 92P may each have a corresponding first source-drain terminal (e.g., a source terminal) communicatively coupled to the power input 68 for receiving the power supply voltage VDD. A PMOS transistor 92P may each have a corresponding second source-drain terminal (e.g., a drain terminal) communicatively coupled to the reference voltage input 71 via an NMOS transistor 92N, a cascode stage, and / or other circuitry in the amplifier 50. An NMOS transistor 92N may each have a corresponding first source-drain terminal (e.g., a source terminal) communicatively coupled to the reference voltage input 71 for receiving the reference voltage 71. Each of the NMOS transistors 92N may have a corresponding second source-drain terminal (e.g., a drain terminal) communicatively coupled to the power input terminal 68 via the PMOS transistor 92P, the cascode stage, and / or other circuitry in the amplifier 50.

[0056] During signal transmission, the gate terminal of PMOS transistor 92P can receive the local oscillator signal LOP via LO input terminal 70P. The gate terminal of NMOS transistor 92N can receive the local oscillator signal LON via LO input terminal 70N. The LO input terminal 70 of amplifier 50 is sometimes also referred to herein as the phase modulation (PM) input terminal of amplifier 50. The local oscillator signal LOP can drive the gate terminal of PMOS transistor 92P to selectively activate or deactivate the transistor (e.g., to induce or stop current flow between the source and drain terminals of the transistor). The local oscillator signal LON can drive the gate terminal of NMOS transistor 92N to selectively activate or deactivate the transistor (e.g., to induce or stop current flow between the source and drain terminals of the transistor). The cascode stage (not shown) and the common-source stage in amplifier 50 can drive the output voltage to the RF output terminal of amplifier 50.

[0057] The term "activation" in this document refers to or is defined as the action of placing the switch in a "conducting" or low-impedance state, such that the two terminals of the switch are electrically connected to conduct current. Activating a switch may sometimes be referred to as turning on or closing a switch. The term "deactivation" in this document refers to or is defined as the action of placing the switch in a "de-off" or high-impedance state, such that the two terminals of the switch / transistor are electrically disconnected with minimal leakage current. Deactivating a switch may sometimes be referred to as turning off or opening a switch. The voltage generated at the RF output of amplifier 50 can form the RF signal RFSIG ( Figure 3 ), which can exhibit time-varying phase modulation as given by the local oscillator signals LOP and LON (e.g., based on Figure 3 The phase signal θ(t) can exhibit time-varying amplitude modulation as given by the supply voltage VDD. Phase and / or amplitude modulation can carry or encode the signal Dbb ( Figure 3 Wireless data.

[0058] The transmitting circuit 58 may include physical layer (PHY) control circuitry such as a PHY controller 72, amplitude modulation (AM) digital-to-analog converter (DAC) circuitry such as an AMDAC 74, and an LDO regulator 76 for providing a power supply voltage VDD to the power input 68 of the amplifier 50. For example, the PHY controller 72 and / or the AMDAC 74 may form the converter circuit 54. Figure 3 It is part of the PHY controller 72. If needed, the PHY controller 72 can form part of the processor 26. Figure 3 (or part of other PHY layer processing / control circuitry in device 10.) The LDO regulator 76 may, for example, be formed as part of... Figure 3This is part of the envelope amplifier 64. This example is illustrative and not limiting, and in general, the transmitting circuit 58 may include any desired circuitry for providing the power supply voltage VDD, which delivers amplitude modulation of the radio frequency signal RFSIG to the amplifier 50.

[0059] During signal transmission, the PHY controller 72 can receive the signal Dbb ( Figure 3 Information about the signal Dbb and / or the radio frequency signal RFSIG to be transmitted by amplifier 50. PHY controller 72 can provide a digital amplitude modulation signal to AMDAC 74. AMDAC 74 can convert the digital amplitude modulation signal into an amplitude signal A(t). LDO regulator 76 can generate the power supply voltage VDD based on the amplitude signal A(t).

[0060] In some specific implementations, static (non-tunable and non-dynamic) clock generators (e.g., in...) Figure 3 The LO generator 56 is used to generate local oscillator signals LOP and LON provided to amplifier 50. The static clock generator includes one or more static chains of inverters, NAND gates, NOR gates, and / or other non-tunable circuitry. The static clock generator generates the local oscillator signal LOP with a first fixed (static) duty cycle and the local oscillator signal LON with a second fixed (static) duty cycle. Although the second duty cycle may differ from the first duty cycle (e.g., the local oscillator signals may not overlap), the first and second duty cycles remain fixed (constant) over time. This allows amplifier 50 to clock with a non-ideal duty cycle ratio between the local oscillator signal LON and the local oscillator signal LOP, given the current transmission characteristics of the RF signal RFSIG, which itself may change over time (e.g., as the type or content of the data packets to be transmitted changes over time). Because in this example the clock generator is non-tunable and the local oscillator signals LOP and LON do not have adjustable duty cycle ratios, the duty cycle ratio cannot be tuned to provide an improved performance level to amplifier 50 even if the characteristics of the RF signal RFSIG change over time. For example, this could reduce one or more wireless performance metrics (key performance indicators characterizing the performance of amplifier 50, such as error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR)).

[0061] To mitigate these issues, amplifier 50 can be dynamically clocked using local oscillator signals LOP and LON, which are provided with dynamically adjustable duty cycles over time. For example... Figure 5As shown, the transmitting circuit 58 may include an adjustable (tunable) local oscillator signal generation circuit, such as a tunable duty cycle generator 80. The tunable duty cycle generator 80 may, for example, be configured as... Figure 3 This is part of the LO generator 56. The tunable duty cycle generator 80 may have a first (e.g., positive) output terminal coupled to signal line 60P. The tunable duty cycle generator 80 may have a second (e.g., negative) output terminal coupled to signal line 60N. The tunable duty cycle generator 80 can generate a local oscillator signal LOP with a first dynamic duty cycle and can output the local oscillator signal LOP to signal line 60P via its first output terminal. The tunable duty cycle generator 80 can generate a local oscillator signal LON with a second dynamic duty cycle and can output the local oscillator signal LON to signal line 60N via its first output terminal. The tunable duty cycle generator 80 can generate the local oscillator signals LOP and LON based on corresponding oscillation signals OSC (e.g., reference oscillator signal, clock signal, crystal oscillator signal, local oscillator signal, etc.).

[0062] The PHY controller 72 can provide a digital control signal CTRL (e.g., a multi-bit binary inverter enable signal EN) to the tunable duty cycle generator 80 via control path 78. The control signal CTRL can set or configure the tunable duty cycle generator 80 to generate a local oscillator signal LOP with a specific duty cycle, and can control the duty cycle generator 80 to change, tune, or adjust the duty cycle of the local oscillator signal LOP over time based on one or more characteristics of the radio frequency signal RFSIG to be transmitted by the amplifier 50 (e.g., based on data packets to be carried by the radio frequency signal RFSIG). The control signal CTRL can also set or configure the tunable duty cycle generator 80 to generate a local oscillator signal LON with a specific duty cycle, and can control the duty cycle generator 80 to change, tune, or adjust the duty cycle of the local oscillator signal LON over time based on one or more characteristics of the radio frequency signal RFSIG to be transmitted by the amplifier 50 (e.g., based on data packets to be carried by the radio frequency signal RFSIG).

[0063] If desired, the transmitting circuit 58 may include a first clock driver 86P (e.g., one or more amplifiers) disposed on signal line 60P between the tunable duty cycle generator 80 and amplifier 50. If desired, the transmitting circuit 58 may include a capacitor 88P (e.g., one or more capacitors and / or distributed capacitors coupled in series and / or parallel between clock driver 86P and LO input terminal 70P) between clock driver 86P and amplifier 50 on signal line 60P. Similarly, if desired, the transmitting circuit 58 may include a second clock driver 86N (e.g., one or more amplifiers) disposed on signal line 60N between the tunable duty cycle generator 80 and amplifier 50. If desired, the transmitting circuit 58 may include a capacitor 88N (e.g., one or more capacitors and / or distributed capacitors coupled in series and / or parallel between clock driver 86N and LO input terminal 70N) between clock driver 86N and amplifier 50 on signal line 60N. Clock drivers 86P and 86N may amplify the local oscillator signals LOP and LON to a desired signal level suitable for driving amplifier 50, respectively. Capacitors 88P and 88N can be used, for example, as high-pass filters to block the DC components of the local oscillator signals LOP and LON, which can help protect transistors 92P and 92N (e.g., help ensure that the local oscillator signals LOP and LON are always on or off).

[0064] Figure 4 The operation of amplifier 50 during a first time period is illustrated, wherein tunable duty cycle generator 80 provides amplifier 50 with local oscillator signals LOP and LON as overlapping local oscillator signals. Local oscillator signals LOP and LON are referred to herein as and defined as “overlapping” local oscillator signals when the duty cycle of local oscillator signal LOP (and its equivalent PMOS transistor 92P) is equal to the duty cycle of local oscillator signal LON (and its equivalent NMOS transistor 92N), such that local oscillator signals LOP and LON exhibit a duty cycle ratio DCRA equal to one (e.g., where the duty cycle ratio (DCR) of local oscillator signals LOP / LON is given by the ratio of the duty cycle of local oscillator signal LOP to the duty cycle of local oscillator signal LON, and vice versa). Furthermore, when generated as overlapping local oscillator signals, the rising edge of each pulse or peak of local oscillator signal LOP (e.g., at...) Figure 4 The curve 82 shows time T1) at which the rising edge of each pulse or peak of the local oscillator signal LON is time-dependent (e.g., at such time). Figure 4The falling edge of each pulse or peak of the local oscillator signal LOP (e.g., at time T1 as shown in curve 84) is aligned with the falling edge of each pulse or peak of the local oscillator signal LON (e.g., at time T2 as shown in curve 82) in time. Figure 4 The curve 84 (at time T2) is aligned. In other words, when the tunable duty cycle generator 80 outputs local oscillator signals LOP and LON as overlapping signals with a duty cycle ratio DCRA equal to one, the pulse in the local oscillator signal LOP can be simultaneous with the pulse in the local oscillator signal LON.

[0065] Providing the local oscillator signals LOP and LON as overlapping local oscillator signals to amplifier 50 can optimize the performance of amplifier 50 for certain types of RFSIG signals, but may cause amplifier 50 to consume excessive power for other types of RFSIG signals. Consider an example where the RFSIG signal will be transmitted at a relatively low output power level while carrying one or more radio data packets with a relatively high peak-to-average power ratio (PAPR). This might be the case, for example, when transmitting the RFSIG signal using certain types of modulation and decoding schemes such as 16-QAM modulation. Figure 4 Curve 90 illustrates an exemplary voltage waveform of the power supply voltage VDD in this type of scenario (e.g., amplitude modulation of the RF signal RFSIG).

[0066] As shown by curve 90, the supply voltage VDD can exhibit a relatively low peak voltage V2 (e.g., 0.8V, 0.6V-1.2V, 0.8V-1.2V, 0.8V-1V, etc.) corresponding to a relatively low output power level of the RF signal RFSIG (e.g., when the supply voltage VDD is supplied to amplifier 50 at voltage V2, amplifier 50 can output an RF signal RFSIG with a relatively low peak output power level). A high PAPR of the RF signal can cause a certain supply voltage VDD to be supplied to amplifier 50 at a relatively low voltage (e.g., less than a threshold V1 (e.g., 0.2V, 0.5V, etc.)). However, if not careful, biasing amplifier 50 with a voltage less than the threshold V1 can cause amplifier 50 to exhibit reduced linearity (e.g., when receiving a supply voltage VDD less than the threshold V1, amplifier 50 can operate in a region of reduced linearity). Using overlapping local oscillator signals LOP and LON (e.g., with a duty cycle ratio DCRA=1, as shown in curves 82 and 84) to drive the gate terminals of transistors 92P / 92N can help improve the linearity of amplifier 50. Therefore, when the RF signal to be transmitted by amplifier 50 exhibits a waveform of this type (see, for example, curve 90) carrying amplitude modulation given by the supply voltage VDD falling below a threshold V1, PHY controller 72 can control tunable duty cycle generator 80 to send the local oscillator signals LOP and LON as overlapping local oscillator signals to amplifier 50. This can be used to mitigate the reduction in linearity of amplifier 50 caused by the supply voltage VDD falling below the threshold V1. For example, when the RF signal RFSIG is at 8MHz and transmitted using a 16-QAM modulation scheme, clocking amplifier 50 using overlapping local oscillator signals LOP / LON can reduce the ACLR of amplifier 50 by up to 11-12 dB, while also increasing the EVM by up to 6-7 dB.

[0067] On the other hand, when transmitting other types of radio frequency signals (RFSIG), clocking amplifier 50 using overlapping local oscillator signals LOP and LON may reduce the efficiency of amplifier 50. For example, when the RFSIG signal is to be transmitted at a relatively high output power level and / or a relatively low PAPR, driving amplifier 50 with overlapping local oscillator signals LOP and LON may cause amplifier 50 to consume excessive power without the risk of falling into the nonlinear region. PHY controller 72 can be used to dynamically adjust the tunable duty cycle generator 80 in a way that balances the linearity of amplifier 50 with the efficiency of amplifier 50 (causing the tunable duty cycle generator 80 to adjust or tune the duty cycle ratio between the local oscillator signals LOP and LON) (e.g., optimizing efficiency and linearity given the specific characteristics of the RFSIG signal being transmitted).

[0068] Figure 5 Another example is illustrated, in which the PHY controller 72 controls the tunable duty cycle generator 80 to generate local oscillator signals LOP and LON as non-overlapping local oscillator signals during a second time period. Local oscillator signals LOP and LON are referred to herein as and defined as “non-overlapping” local oscillator signals when the duty cycle of the local oscillator signal LOP (and its equivalent PMOS transistor 92P) differs from the duty cycle of the local oscillator signal LON (and its equivalent NMOS transistor 92N), such that the local oscillator signals LOP and LON exhibit a second duty cycle ratio DCRB that is not equal to one.

[0069] When the local oscillator signals LOP and LON are non-overlapping local oscillator signals, the width of each pulse of the local oscillator signal LON may differ from the width of the corresponding pulse of the local oscillator signal LOP, and / or the width of each minimum value of the local oscillator signal LON may differ from the width of the corresponding minimum value of the local oscillator signal LOP. Furthermore, the rising edge of each pulse of the local oscillator signal LON may occur at a different time than the rising edge of each pulse of the local oscillator signal LOP, and / or the falling edge of each pulse of the local oscillator signal LON may occur at a different time than the falling edge of each pulse of the local oscillator signal LOP. For example, as shown in curve 98, the rising edge of the local oscillator signal LON may occur at time T1, which is after time T and before time T2, and the falling edge of the local oscillator signal LON may occur at time T2', which is after time T1' and before time T2.

[0070] When the waveform of the RF signal RFSIG does not additionally require amplifier 50 to be biased by a supply voltage VDD below a threshold V1, using non-overlapping local oscillator signals LOP and LON to drive amplifier 50 in this way can help improve the efficiency of amplifier 50. Consider an example where the RF signal RFSIG will be transmitted at a relatively high output power level while carrying one or more wireless data packets with a relatively low PAPR. Figure 5 Curve 94 illustrates an exemplary voltage waveform of the power supply voltage VDD in this type of scenario.

[0071] As shown in curve 94, the supply voltage VDD can exhibit a relatively high peak voltage V3 > V2 (e.g., 1.6V, 1V-2V, 1.2V-1.8V, etc.) corresponding to a relatively high output power level for the RF signal RFSIG (e.g., when the supply voltage VDD is supplied to amplifier 50 at voltage V3, amplifier 50 can output an RF signal RFSIG with a relatively high peak output power level). Because the RF signal exhibits a low PAPR in this example, the supply voltage VDD will not drop below the threshold V1. Therefore, it is not necessary to use overlapping local oscillator signals LOP and LON (e.g., ...). Figure 4 (As shown) clock-controlled linearity improvements are applied to amplifier 50, and a local oscillator signal is provided as a non-overlapping local oscillator signal (e.g.) Figure 5 (As shown) This can lead to a reduction in power consumption and an improvement in the efficiency of amplifier 50.

[0072] In this example, the local oscillator signal LOP may be pulsed high for 53% of the period of the oscillation signal OSC (e.g., a reference oscillator signal used to form or generate the local oscillator signal) received by the tunable duty cycle generator 80, while the local oscillator signal LON may be pulsed high for 47% of the period of the local oscillator signal OSC. In this example, the duty cycle ratio DCRB may be given by a ratio 53 / 47, which is not equal to one (e.g., because...). Figure 5 The local oscillator signals LOP and LON do not overlap. For example, this can help reduce the power consumption of amplifier 50 by up to 6-7% compared to using overlapping local oscillator signals to drive amplifier 50. On the other hand, in Figure 4 In the example, when the local oscillator signals LOP and LON are output as overlapping local oscillator signals, the local oscillator signals LOP and LON are each pulsed high for 50% of the period of the oscillation signal OSC, corresponding to a duty cycle DCRA=50 / 50=1.

[0073] Figure 4 and Figure 5The example illustrates only two duty cycle ratios for the local oscillator signals LOP and LON, corresponding to two different operating modes of amplifier 50 (e.g., a low-power / high PAPR mode where the local oscillator signal is provided with a duty cycle ratio DCRA=1, and a high-power / low PAPR mode where the local oscillator signal is provided with a first duty cycle DCRB not equal to one). This is illustrative and not limiting. In general, PHY controller 72 can control tunable duty cycle generator 80 to switch between a set of N different duty cycle ratios for the local oscillator signals LOP and LON, each duty cycle ratio corresponding to a different operating mode among the N different operating modes of amplifier 50. Each duty cycle ratio and operating mode can correspond to an optimal balance of linearity and efficiency of amplifier 50 under different corresponding combinations of the characteristics of the RF signal RFSIG transmitted by amplifier 50.

[0074] For example, the PHY controller 72 can control the tunable duty cycle generator 80 to generate a local oscillator signal LOP / LON with a first duty cycle ratio DCRA=1 as an overlapping local oscillator signal during a first time period, during which the transmitted RF signal RFSIG will exhibit a first set of one or more characteristics (e.g., optimizing the balance between linearity and efficiency when the RF signal RFSIG exhibits relatively low power and relatively high PAPR). The tunable duty cycle generator 80 can also be controlled to generate a local oscillator signal LOP / LON with a second duty cycle ratio DCRB=55 / 45 as a non-overlapping local oscillator signal during a second time period, during which the transmitted RF signal RFSIG will exhibit a second set of one or more characteristics (e.g., optimizing the balance between linearity and efficiency when the RF signal RFSIG exhibits relatively high power and / or relatively high PAPR). The tunable duty cycle generator 80 can be controlled to generate a local oscillator signal LOP / LON with a second duty cycle ratio DCRB=53 / 47 as a non-overlapping local oscillator signal during a third time period. During this third time period, the transmitted radio frequency signal RFSIG will exhibit a third set of one or more characteristics (e.g., optimizing the balance between linearity and efficiency when the radio frequency signal RFSIG exhibits a first intermediate power and / or a first intermediate PAPR). The tunable duty cycle generator 80 can also be controlled to generate a local oscillator signal LOP / LON with a third duty cycle ratio DCRB=52 / 48 as a non-overlapping local oscillator signal during a fourth time period. During this fourth time period, the transmitted radio frequency signal RFSIG will exhibit a fourth set of one or more characteristics (e.g., optimizing the balance between linearity and efficiency when the radio frequency signal RFSIG exhibits a second intermediate power and / or a second intermediate PAPR), etc. The duty cycle between the non-overlapping local oscillator signals LOP and LON can be any desired value (e.g., 51 / 49, 52 / 48, 53 / 47, 54 / 46, 55 / 45, 56 / 44, 57 / 43, 58 / 42, 59 / 41, 60 / 40, 61 / 39, etc.).

[0075] Figure 6 This is a circuit diagram of a tunable duty cycle generator 80, illustrating an example of how the tunable duty cycle generator 80 can generate local oscillator signals LOP and LON with a specific duty cycle ratio DCR set by the PHY controller 72 using the control signal CTRL. Figure 6As shown, the tunable duty cycle generator 80 may include a first group of M inverters 100 for generating a local oscillator signal LOP, and may include a second group of M inverters 114 for generating a local oscillator signal LON (e.g., the first and second groups of inverters may each be an M-bit binary-controlled tunable local oscillator signal generator). Figure 6 In the example, M=5 (for example, inverters 100-0, 100-1, 100-2, 100-3, and 100-4 together generate the local oscillator signal LOP, while inverters 114-0, 114-1, 114-2, 114-3, and 114-4 together generate the local oscillator signal LON). In general, M can be any desired integer.

[0076] Each inverter 100 and each inverter 114 may be a CMOS inverter. Each CMOS inverter may include a first PMOS transistor 102, a second PMOS transistor 106, a first NMOS transistor 108, and a second NMOS transistor 104, series coupled between power lines (rails) 112 and 110. Power line 112 carries the supply voltage VDD. Power line 110 carries a reference voltage VREF (e.g., ...). Figure 4 The reference voltage is 66). PMOS transistors 102 and 106 are sometimes referred to herein as p-type transistors. NMOS transistors 108 and 104 are sometimes referred to herein as n-type transistors. Transistors 106 and 108 are sometimes referred to as enable transistors, weighted transistors, or binary weighted transistors.

[0077] A first source-drain terminal (e.g., a source terminal) of transistor 102 may be coupled to power supply line 112. A second source-drain terminal (e.g., a drain terminal) of transistor 102 may be coupled to a first source-drain terminal (e.g., a source terminal) of transistor 106. A second source-drain terminal (e.g., a drain terminal) of transistor 106 may be coupled to a first source-drain terminal (e.g., a drain terminal) of transistor 108. A second source-drain terminal (e.g., a source terminal) of transistor 108 may be coupled to a first source-drain terminal (e.g., a drain terminal) of transistor 104. A second source-drain terminal (e.g., a source terminal) of transistor 104 may be coupled to power supply line 110. Each inverter 100 may have an output terminal (node) 111 coupled in parallel to signal line 60P. Each inverter 114 may have an output terminal (node) 111 coupled in parallel to signal line 60N. Each output terminal 111 may be coupled to the second source-drain terminal (e.g., drain terminal) of transistor 106 and may be coupled to the first source-drain terminal (e.g., drain terminal) of transistor 108 in its corresponding inverter 100 or 114.

[0078] The gate terminals of transistors 102 and 104 in each inverter 100 may receive a first oscillation signal OSCP (e.g., with duty cycle DCA). The gate terminals of transistors 102 and 104 in each inverter 104 may receive a second oscillation OSCN (e.g., with duty cycle DCA). The oscillation signals OSCP / OSCN may, for example, be co-formed. Figure 5 The differential signal pair of the OSC oscillation signal. Controlled by PHY controller 72 ( Figure 3 The control signal CTRL supplied to the tunable duty cycle generator 80 may include an M-bit enable signal EN, which is represented as a differential signal pair ENP / ENN (e.g., where the enable signal ENP is the inverted version of the enable signal ENP). The first bit ENP of the control signal CTRL <0> It can be supplied to the gate terminal of transistor 106 in inverter 100-0 and the gate terminal of transistor 108 in inverter 114-0. The first bit ENN of the control signal CTRL <0> It can be supplied to the gate terminal of transistor 108 in inverter 100-0 and the gate terminal of transistor 106 in inverter 114-0. The second bit ENP of the control signal CTRL <1> It can be supplied to the gate terminal of transistor 106 in inverter 100-1 and the gate terminal of transistor 108 in inverter 114-1. The second bit ENN of the control signal CTRL. <1> The gate terminals of transistor 108 in inverter 100-1 and transistor 106 in inverter 114-1 can be provided. Similarly, additional bits of the control signal CTRL can be provided to the gate terminals of transistors 106 and 108 in the other inverters 100 and 114 of the tunable duty cycle generator 80. In this way, each of the M bits of the control signal CTRL can be provided to transistors 106 and 108 in the corresponding inverters 100 and 114, which can form a binary-weighted CMOS inverter.

[0079] A control signal CTRL (e.g., enable signals ENP / ENN) controls inverter 100 to generate a local oscillator signal LOP based on an oscillation signal OSCP. The enable signal can be used as a binary weight that selectively enables and disables transistors 106 and 108 in different inverters 100 (e.g., according to corresponding bits of the M-bit control signal CTRL) to co-modulate the rising and falling edges of each pulse of the oscillation signal OSCP, thereby generating corresponding pulses of the local oscillator signal LOP with a first duty cycle DCP on signal line 60P (e.g., where the rising and falling edges of the local oscillator signal LOP represent rising and falling edges of the oscillation signal OSC that have been delayed by a specific amount). Simultaneously, the control circuit CTRL (e.g., enable signals ENP and ENN) controls inverter 114 to generate a local oscillator signal LON based on the oscillation signal OSCP. The enable signal can be used as a binary weight that selectively enables and disables transistors 106 and 108 in different inverters 114 (e.g., according to the corresponding bits of the M-bit control signal CTRL) to co-modulate the rising and falling edges of each pulse of the oscillator signal OSCN, thereby generating corresponding pulses of a local oscillator signal LON with a second duty cycle DCN at the output on signal line 60P. The duty cycles DCP and DCN can be selected to configure the local oscillator signals LOP / LON to collectively exhibit the desired duty cycle ratio DCR = DCP / DCN. When the local oscillator signal is output as an overlay local oscillator signal, the duty cycle ratio DCR is equal to one (e.g., ...). Figure 4 The duty cycle ratio (DCRA). When the local oscillator signal is output as a non-overlapping local oscillator signal, the duty cycle ratio (DCR) can be equal to a value other than one (e.g., Figure 5 Duty cycle ratio (DCRB).

[0080] The PHY controller 72 can use the control signal CTRL to change, tune, or adjust the binary weighting on the M inverters 100 and M inverters 114 in the tunable duty cycle generator 80 over time, thereby changing the duty cycle ratio DCR of the local oscillator signal LOP / LON in a way that produces an optimal balance of linearity and efficiency when driving the amplifier 50, depending on the characteristics of the RF signal RFSIG output by the amplifier (e.g., by fine-tuning the rise and fall delays of each oscillator signal to individually and precisely tune the local oscillator duty cycle for the PMOS and NMOS portions of the amplifier 50). For example, the PHY controller 72 can pre-adjust the tunable duty cycle generator 80 for each transmission cycle of the RF signal RFSIG (e.g., because the PHY controller 72 knows the characteristics of each data packet to be carried by the RF signal RFSIG, such as transmit power level, modulation type, frequency band, etc.). By increasing the bit depth (integer M) of the control signal CTRL and the number of inverters 100 and 114 in the tunable duty cycle generator 80, the PHY controller 72 can increase the accuracy / resolution of setting / adjusting the duty cycle ratio DCR (e.g., to finely balance the overall efficiency and linearity of amplifier 50 based on the signal power, bandwidth, and / or modulation scheme of the RF signal RFSIG). Duty cycle calibration can be performed if needed to suppress even-order harmonic emissions. The tunable duty cycle generator 80 can also be an auxiliary duty cycle calibration block to extend the calibration range if required.

[0081] Figure 7 This is a state diagram illustrating the exemplary operating mode 120 of amplifier 50 and tunable duty cycle generator 80. (Example...) Figure 7 As shown, amplifier 50 and tunable duty cycle generator 80 can operate in at least a first state (mode) 120A and a second state (mode) 120B. In state 120A (sometimes referred to herein as high-power mode 120A), tunable duty cycle generator 80 can generate a local oscillator signal LOP / LON as a non-overlapping local oscillator signal (e.g., having...). Figure 5 The duty cycle ratio (DCRB). For example, this allows amplifier 50 to send an RF signal RFSIG that delivers relatively low PAPR data at a relatively high output power level with sufficient efficiency (e.g., without excessive power consumption) and linearity.

[0082] In state 120B (sometimes referred to herein as low-power mode 120B), the tunable duty cycle generator 80 can generate a local oscillator signal LOP / LON as an overlapped local oscillator signal (e.g., having...). Figure 4The duty cycle ratio (DCRA) can be used. For example, this allows amplifier 50 to transmit an RF signal RFSIG that delivers relatively high PAPR data at a relatively low output power level with sufficient linearity and efficiency. This can be extended to any desired number of modes. The tunable duty cycle generator 80 can clock amplifier 50 in each mode using local oscillator signals LOP / LON with different corresponding duty cycle ratios (DCR) to optimize linearity and efficiency for any desired number of transmitted signals.

[0083] Figure 8 This is a flowchart illustrating an exemplary operation that can be performed by the transmitting circuit 58 to transmit the radio frequency signal RFSIG. At operation 122, the PHY controller 72 may identify one or more characteristics of the radio frequency signal RFSIG to be transmitted. This may include, for example, modulation scheme, frequency, bandwidth, transmit power level, type of data carried, and / or any other desired characteristics of the radio frequency signal RFSIG and / or the wireless data carried by the radio frequency signal RFSIG.

[0084] At operation 124, PHY controller 72 can use the control signal CTRL to configure inverters 100 and 114 in tunable duty cycle generator 80. Figure 6 The PHY controller 72 generates a local oscillator signal LOP / LON with a duty cycle ratio DCR selected based on the identified characteristics of the radio frequency signal RFSIG. The selected duty cycle ratio DCR can be a duty cycle ratio that optimizes the efficiency and linearity of amplifier 50 when transmitting the radio frequency signal with the identified characteristics. For example, in response to the PHY controller 72 detecting that the radio frequency signal RFSIG will be transmitted at a relatively low power level and / or with a relatively high PAPR, the PHY controller 72 can use the control signal CTRL to configure the tunable duty cycle generator 80 to generate a local oscillator signal LOP / LON as an overlapping local oscillator signal (e.g., having...). Figure 4 The duty cycle ratio (DCRA) is used to place amplifier 50 and tunable duty cycle generator 80 in a position that allows the amplifier to operate at a duty cycle ratio of 50, thus placing the ... to a position that allows the amplifier to operate at a duty cycle ratio of 50, thus placing the amplifier to a position that allows the amplifier to operate at a duty cycle ratio of 50, Figure 7 The high-power mode is 120A. On the other hand, in response to the PHY controller 72 detecting that the RF signal RFSIG will be transmitted at a relatively high power level and / or at a relatively low PAPR, the PHY controller 72 can use the control signal CTRL to configure the tunable duty cycle generator 80 to generate local oscillator signals LOP / LON as non-overlapping local oscillator signals (e.g., having...). Figure 5 The duty cycle ratio (DCRB) is used to place amplifier 50 and tunable duty cycle generator 80 in a position that allows the amplifier to operate at a duty cycle ratio of 50 to 60. Figure 7 The low-power mode 120B.

[0085] At operation 126, amplifier 50 can transmit an RF signal RFSIG with the identified characteristics based on a selected duty cycle ratio DCR using the supply voltage VDD (e.g., amplitude modulation carrying the RF signal) and the local oscillator signal LOP / LON (e.g., phase modulation carrying the RF signal). Given the identified characteristics, amplifier 50 can transmit the RF signal with a sufficiently high level of linearity and efficiency. When the characteristics of the RF signal RFSIG change, processing can loop back to operation 122 via path 128.

[0086] Figure 9 This is a graph of amplitude modulation to phase modulation (AMPM) distortion as a function of the power supply voltage VDD of amplifier 50. Curve 134 plots the distortion when a non-overlapping local oscillator signal LOP / LON is supplied to amplifier 50 while the power supply voltage VDD is relatively low (e.g., less than 100 kcal / kg). Figure 4 The AMPM distortion is shown at the threshold V1. Curve 132 plots the AMPM distortion when an overlapping local oscillator signal LOP / LON is supplied to amplifier 50 while the supply voltage VDD is at the same relatively low level. As shown in curves 130 and 132, when the supply voltage VDD is relatively low, clocking amplifier 50 using an overlapping local oscillator signal can be used to improve AMPM distortion (e.g., shifting AMPM distortion closer to zero, as indicated by arrow 134).

[0087] Figure 10 This is a graph illustrating how the dynamic duty cycle of amplifier 50 can improve the ACLR of amplifier 50. Curve 140 plots the ACLR when a non-overlapping local oscillator signal LOP / LON is supplied to amplifier 50 while the supply voltage VDD is relatively low (e.g., less than 100 kcal / kg). Figure 4 The output power level of the radio frequency signal RFSIG at a threshold V1 (as a function of frequency). As shown in curve 140, RFSIG can be transmitted within a corresponding frequency allocation 136 extending from frequency FA to frequency FB. Frequency allocation 136 may span one or more consecutive resource blocks, resource elements, sub-channels, and / or another set of spectrum / resources, and is sometimes referred to herein as frequency range 136 (e.g., a consecutive set of resource blocks / elements, frequency channels, some or all of a frequency / communication band, etc.). Frequency allocation 136 may be determined by communication scheduling of device 10 (e.g., as maintained by a wireless network), by one or more applications running on device 10, by one or more communication requests imposed on device 10, etc.

[0088] As shown by curve 140, the radio frequency signal RFSIG can exhibit a signal peak within frequency allocation 136. However, the low level of the supply voltage VDD places amplifier 50 in a non-linear region below the threshold V1. This causes the radio frequency signal RFSIG to exhibit a relatively high signal level at frequencies outside frequency allocation 136 (e.g., where the signal level gradually decreases with increasing offset from frequency allocation 136). This can cause amplifier 50 to exhibit a relatively high or excessively high ACLR. The signal level of the radio frequency signal RFSIG can, for example, approach or exceed a threshold or limit, such as transmit mask 142. Transmit mask 142 can represent an upper limit (e.g., imposed on device 10 by the manufacturer, regulatory agency or organization of device 10 or wireless circuit 24, a communication protocol or standard governing the transmission of transmit circuit 58, one or more applications running on device 10, etc.). Exceeding transmit mask 142 outside frequency allocation 136 can, for example, cause wireless circuit 24 to disable the transmit mask and / or may otherwise degrade the wireless performance of amplifiers, other circuitry in device 10, and / or external devices receiving radio frequency signals.

[0089] Curve 138 plots the output power level (as a function of frequency) of the RF signal RFSIG when an overlapping local oscillator signal LOP / LON is supplied to amplifier 50 while the supply voltage VDD is at the same relatively low level. As shown in curve 138, clocking amplifier 50 using the overlapping local oscillator signal LOP / LON can reduce the power level of the RF signal RFSIG outside of frequency allocation 136 (e.g., where the signal level drops rapidly with increasing offset from frequency allocation 136). This allows amplifier 50 to exhibit a relatively low ACLR. Figure 9 and Figure 10 The examples are illustrative rather than restrictive. In practice, curves 130, 132, 138, and 140 may have other shapes.

[0090] The above text combined Figures 1 to 10 The described methods and operations can be performed by components of device 10 using software, firmware, and / or hardware (e.g., dedicated circuitry or hardware). Software code for performing these operations may be stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) stored on one or more components of device 10 (e.g., ...). Figure 1The storage device circuitry 16 and / or wireless communication circuitry 24). This software code may sometimes be referred to as software, data, instructions, program instructions, or code. Non-transitory computer-readable storage media may include drives, non-volatile memory such as non-volatile random access memory (NVRAM), removable flash drives or other removable media, other types of random access memory, etc. The software stored on the non-transitory computer-readable storage medium may be processed by processing circuitry on one or more components of device 10 (e.g., processing circuitry in wireless communication circuitry 24, ...). Figure 1 The processing circuitry (e.g., 18) executes the operation. This processing circuitry may include a microprocessor, application processor, digital signal processor, central processing unit (CPU), application-specific integrated circuit (ASIC) with processing circuitry, or other processing circuitry.

[0091] As used herein, the term "concurrent" means at least partially overlapping in time. In other words, the first and second events are referred to herein as "concurrent" if at least some of the first events occur simultaneously with at least some of the second events (e.g., if at least some of the first events occur during, concurrently with, or when at least some of the second events occur). The first and second events can be concurrent if they are synchronized (e.g., if the entire duration of the first event overlaps with the entire duration of the second event in time), but they can also be concurrent if they are asynchronous (e.g., if the first event begins before or after the second event, ends before or after the second event, or does not partially overlap in time). As used herein, the term "at the time of" is synonymous with "concurrent".

[0092] As is widely recognized, the use of personally identifiable information should comply with privacy policies and measures that are generally accepted to meet or exceed industry or governmental requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly explained to users.

[0093] According to one embodiment, a wireless circuit includes: a tunable clock generator configured to generate a first local oscillator (LO) signal and a second LO signal, the tunable clock generator being configured to adjust a duty cycle ratio between the first LO signal and the second LO signal over time; and an amplifier configured to output a radio frequency (RF) signal, wherein the first LO signal and the second LO signal transmit phase modulation of the RF signal, and the amplifier includes: a first power input receiving a power supply voltage transmitting amplitude modulation of the RF signal; a second power input receiving a reference voltage; a p-type transistor coupled to the first power input and having a gate terminal configured to receive the first LO signal; and an n-type transistor coupled to the second power input and having a gate terminal configured to receive the second LO signal.

[0094] According to another embodiment, the tunable clock generator is optionally configured to set the duty cycle ratio between the first LO signal and the second LO signal based on the characteristics of the radio frequency signal.

[0095] According to another implementation, this characteristic may optionally include output power level, bandwidth, frequency, modulation scheme, or peak-to-average power ratio.

[0096] According to another embodiment, the wireless circuit optionally further includes a physical layer (PHY) controller configured to control the tunable clock generator to generate the first LO signal and the second LO signal having a first duty cycle ratio during a first time period, the characteristic having a first value during the first time period, and configured to control the tunable clock generator to generate the first LO signal and the second LO signal having a second duty cycle ratio different from the first duty cycle ratio during a second time period, the characteristic having a second value different from the first value during the second time period.

[0097] According to another implementation, the first duty cycle ratio is optionally equal to one and the second duty cycle ratio is not equal to one.

[0098] According to another embodiment, the feature optionally includes an output power level having a first value during the first time period and having a second value greater than the first value during the second time period.

[0099] According to another embodiment, the characteristic optionally includes a peak-to-average power ratio (PAPR), which has a first value during the first time period and a second value that is less than the first value during the second time period.

[0100] According to another embodiment, the amplifier optionally includes: a p-type common-source stage, the p-type common-source stage including the p-type transistor; and an n-type common-source stage, the n-type common-source stage including the n-type transistor.

[0101] According to another embodiment, the wireless circuit optionally further includes: a first signal line that couples the tunable clock generator to the gate terminal of the p-type transistor; and a second signal line that couples the tunable clock generator to the gate terminal of the n-type transistor, wherein the tunable clock generator is configured to generate the first LO signal and the second LO signal based on an oscillation signal and a binary enable signal.

[0102] According to another embodiment, the wireless circuit optionally further includes: a first clock driver disposed on the first signal line; a first capacitor disposed on the first signal line between the first clock driver and the gate terminal of the p-type transistor; a second clock driver disposed on the second signal line; and a second capacitor disposed on the first signal line between the first clock driver and the gate terminal of the n-type transistor.

[0103] According to another embodiment, the tunable clock generator optionally includes: a first set of complementary metal-oxide-semiconductor (CMOS) inverters having output terminals coupled in parallel to the first signal line; and a second set of CMOS inverters having output terminals coupled in parallel to the second signal line, wherein the binary enable signal is configured to control the first set of CMOS inverters to generate the first LO signal having a first duty cycle, the binary enable signal is configured to control the second set of CMOS inverters to generate the second LO signal having a second duty cycle, and the first duty cycle and the second duty cycle define the duty cycle ratio between the first LO signal and the second LO signal.

[0104] According to another embodiment, the CMOS inverter in the first set of CMOS inverters and the second set of CMOS inverters optionally includes: a first p-channel metal-oxide-semiconductor (PMOS) transistor having a source terminal coupled to a first power supply line and a gate terminal for receiving the oscillation signal; a second PMOS transistor having a source terminal coupled to the drain terminal of the first PMOS transistor; a first n-channel metal-oxide-semiconductor (NMOS) transistor having a drain terminal coupled to the drain terminal of the second PMOS transistor; and a second NMOS transistor having a drain terminal coupled to the source terminal of the first NMOS transistor, a source terminal coupled to a second power supply line, and a gate terminal for receiving the oscillation signal, wherein the gate terminals of the second PMOS transistor and the first NMOS transistor receive corresponding bits of the binary enable signal.

[0105] According to another embodiment, the binary enable signal optionally includes an M-bit binary enable signal, the first set of CMOS inverters includes a first set of M CMOS inverters, the second set of CMOS inverters includes a second set of M CMOS inverters, and each bit of the M-bit binary enable signal is provided to the gate terminal of the second PMOS transistor and the first NMOS transistor in different corresponding CMOS inverters of the first set, and is also provided to the gate terminal of the second PMOS transistor and the first NMOS transistor in different corresponding CMOS inverters of the second set.

[0106] According to another embodiment, the wireless circuit optionally further includes a physical layer (PHY) controller configured to provide the M-bit binary enable signal to the first set of CMOS inverters and the second set of CMOS inverters, wherein the M-bit binary enable signal controls the first set of CMOS inverters and the second set of CMOS inverters to output the first LO signal and the second LO signal having the duty cycle ratio by shifting the rising and falling edges of the oscillation signal.

[0107] According to one embodiment, a method of transmitting a radio frequency (RF) signal includes: supplying a power supply voltage to a power input terminal of an amplifier, wherein the power supply voltage carries amplitude modulation of the RF signal; supplying a first LO signal to a p-channel metal-oxide-semiconductor (PMOS) portion of the amplifier and a second LO signal to an n-channel metal-oxide-semiconductor (NMOS) portion of the amplifier using a local oscillator (LO) generator, wherein the first LO signal and the second LO signal carry phase modulation of the RF signal; and using one or more processors to control the LO generator to adjust the duty cycle ratio between the first LO signal and the second LO signal based on characteristics of the RF signal.

[0108] According to another implementation, this characteristic may optionally include output power level, bandwidth, frequency, modulation scheme, or peak-to-average power ratio.

[0109] According to another embodiment, controlling the LO generator to adjust the duty cycle ratio optionally includes: controlling the LO generator to generate the first LO signal and the second LO signal using a first duty cycle ratio during a first time period, the first duty cycle ratio being equal to one; and controlling the LO generator to generate the first LO signal and the second LO signal using a second duty cycle ratio different from the first duty cycle ratio during a second time period different from the first time period.

[0110] According to another embodiment, the method optionally further includes: generating the first LO signal using a first set of inverters in the LO generator based on an oscillation signal; and generating the second LO signal using a second set of inverters in the LO generator based on the oscillation signal, wherein controlling the LO generator to adjust the duty cycle ratio includes providing a binary enable signal to the binary weighted transistors in the first set of inverters and the second set of inverters, wherein the binary enable signal controls the first set of inverters to adjust the rising and falling edges of the first LO signal and the binary enable signal controls the second set of inverters to adjust the rising and falling edges of the second LO signal.

[0111] According to one embodiment, the wireless circuit includes: a polar coordinate amplifier configured to output a radio frequency (RF) signal; a clock circuit configured to supply a first local oscillator (LO) signal and a second LO signal to the polar coordinate amplifier, wherein the first LO signal and the second LO signal transmit phase modulation of the RF signal; and one or more processors configured to control the clock circuit to switch between supplying the first LO signal and the second LO signal as overlapping signals to the polar coordinate amplifier and supplying the first LO signal and the second LO signal as non-overlapping signals to the polar coordinate amplifier based on one or more characteristics of the RF signal.

[0112] According to another embodiment, the one or more processors are optionally further configured to: control the clock circuit to output the first LO signal and the second LO signal as the overlapping signal when the radio frequency signal has a first characteristic; control the clock circuit to output the first LO signal and the second LO signal with a first duty cycle ratio as the non-overlapping signal when the radio frequency signal has a second characteristic different from the first characteristic; and control the clock circuit to output the first LO signal and the second LO signal with a second duty cycle ratio different from the first duty cycle ratio as the non-overlapping signal when the radio frequency signal has a third characteristic different from the first characteristic and the second characteristic.

[0113] The foregoing is merely illustrative and various modifications can be made to the described implementation scheme. The foregoing implementation scheme can be implemented individually or in any combination.

Claims

1. A wireless circuit, the wireless circuit comprising: A tunable clock generator configured to generate a first local oscillator (LO) signal and a second LO signal, the tunable clock generator being configured to adjust the duty cycle ratio between the first LO signal and the second LO signal over time; and An amplifier configured to output a radio frequency (RF) signal, wherein a first LO signal and a second LO signal transmit phase modulation of the RF signal, and the amplifier includes... The first power input terminal receives the amplitude-modulated power supply voltage that transmits the radio frequency signal. The second power input terminal receives the reference voltage. A p-type transistor, the p-type transistor being coupled to the first power input terminal and having a gate terminal configured to receive the first LO signal, and An n-type transistor, the n-type transistor being coupled to the second power input and having a gate terminal configured to receive the second LO signal.

2. The wireless circuit of claim 1, wherein the tunable clock generator is configured to set the duty cycle ratio between the first LO signal and the second LO signal based on the characteristics of the radio frequency signal.

3. The wireless circuit according to claim 2, wherein the characteristics include output power level, bandwidth, frequency, modulation scheme or peak-to-average power ratio.

4. The wireless circuit according to claim 2, further comprising: A physical layer (PHY) controller is configured to control the tunable clock generator to generate a first LO signal and a second LO signal having a first duty cycle ratio during a first time period, the characteristic having a first value during the first time period, and is configured to control the tunable clock generator to generate the first LO signal and the second LO signal having a second duty cycle ratio different from the first duty cycle ratio during a second time period, the characteristic having a second value different from the first value during the second time period.

5. The wireless circuit of claim 4, wherein the first duty cycle ratio is equal to one and the second duty cycle ratio is not equal to one.

6. The wireless circuit of claim 5, wherein the characteristic includes an output power level having a first value during the first time period and a second value greater than the first value during the second time period.

7. The wireless circuit of claim 5, wherein the characteristic includes a peak-to-average power ratio (PAPR), the PAPR having a first value during the first time period and a second value less than the first value during the second time period.

8. The wireless circuit of claim 1, wherein the amplifier comprises: p-type common-source stage, wherein the p-type common-source stage includes the p-type transistor; as well as The n-type common-source stage includes the n-type transistor.

9. The wireless circuit according to claim 1, further comprising: A first signal line, the first signal line coupling the tunable clock generator to the gate terminal of the p-type transistor; as well as A second signal line couples the tunable clock generator to the gate terminal of the n-type transistor, wherein the tunable clock generator is configured to generate the first LO signal and the second LO signal based on an oscillation signal and a binary enable signal.

10. The wireless circuit according to claim 9, further comprising: A first clock driver is disposed on the first signal line; A first capacitor is disposed on the first signal line between the first clock driver and the gate terminal of the p-type transistor; A second clock driver is configured on the second signal line; as well as A second capacitor is disposed on the first signal line between the first clock driver and the gate terminal of the n-type transistor.

11. The wireless circuit of claim 9, wherein the tunable clock generator comprises: The first set of complementary metal-oxide-semiconductor (CMOS) inverters has an output terminal coupled in parallel to the first signal line; as well as A second set of CMOS inverters, the second set of CMOS inverters having output terminals coupled in parallel to the second signal line, wherein the binary enable signal is configured to control the first set of CMOS inverters to generate a first LO signal with a first duty cycle, the binary enable signal is configured to control the second set of CMOS inverters to generate a second LO signal with a second duty cycle, and the first duty cycle and the second duty cycle define the duty cycle ratio between the first LO signal and the second LO signal.

12. The wireless circuit of claim 11, wherein the CMOS inverter in the first group of CMOS inverters and the second group of CMOS inverters comprises: A first p-channel metal-oxide-semiconductor (PMOS) transistor, the first p-channel metal-oxide-semiconductor (PMOS) transistor having a source terminal coupled to a first power supply line and a gate terminal for receiving the oscillation signal; A second PMOS transistor having a source terminal coupled to the drain terminal of the first PMOS transistor; A first n-channel metal-oxide-semiconductor (NMOS) transistor, the first n-channel metal-oxide-semiconductor (NMOS) transistor having a drain terminal coupled to the drain terminal of the second PMOS transistor; as well as The second NMOS transistor has a drain terminal coupled to the source terminal of the first NMOS transistor, a source terminal coupled to a second power supply line, and a gate terminal for receiving the oscillation signal, wherein the gate terminals of the second PMOS transistor and the first NMOS transistor receive corresponding bits of the binary enable signal.

13. The wireless circuit of claim 12, wherein the binary enable signal comprises an M-bit binary enable signal, the first set of CMOS inverters comprises a first set of M CMOS inverters, the second set of CMOS inverters comprises a second set of M CMOS inverters, and each bit of the M-bit binary enable signal is provided to the gate terminals of the second PMOS transistor and the first NMOS transistor in different corresponding CMOS inverters of the first set, and is also provided to the gate terminals of the second PMOS transistor and the first NMOS transistor in different corresponding CMOS inverters of the second set.

14. The wireless circuit of claim 13, further comprising: A physical layer (PHY) controller is configured to provide the M-bit binary enable signal to the first set of CMOS inverters and the second set of CMOS inverters, wherein the M-bit binary enable signal controls the first set of CMOS inverters and the second set of CMOS inverters to output the first LO signal and the second LO signal having the duty cycle ratio by shifting the rising and falling edges of the oscillation signal.

15. A method for transmitting a radio frequency signal, the method comprising: A power supply voltage is supplied to the power input terminal of the amplifier, wherein the power supply voltage carries the amplitude modulation of the radio frequency signal; A first LO signal is supplied to the p-channel metal-oxide-semiconductor (PMOS) portion of the amplifier using a local oscillator (LO) generator, and a second LO signal is supplied to the n-channel metal-oxide-semiconductor (NMOS) portion of the amplifier, wherein the first LO signal and the second LO signal carry the phase modulation of the radio frequency signal; as well as One or more processors are used to control the LO generator to adjust the duty cycle ratio between the first LO signal and the second LO signal based on the characteristics of the radio frequency signal.

16. The method of claim 15, wherein the characteristics include output power level, bandwidth, frequency, modulation scheme, or peak-to-average power ratio.

17. The method of claim 15, wherein controlling the LO generator to adjust the duty cycle ratio comprises: The LO generator is controlled to generate the first LO signal and the second LO signal using a first duty cycle ratio during a first time period, the first duty cycle ratio being equal to one; as well as The LO generator is controlled to generate the first LO signal and the second LO signal using a second duty cycle ratio different from the first duty cycle ratio during a second time period different from the first time period.

18. The method according to claim 15, further comprising: The first LO signal is generated using the first set of inverters in the LO generator based on the oscillation signal; as well as The second LO signal is generated using a second set of inverters in the LO generator based on the oscillation signal, wherein controlling the LO generator to adjust the duty cycle ratio includes: A binary enable signal is provided to the binary weighted transistors in the first set of inverters and the second set of inverters, wherein the binary enable signal controls the first set of inverters to adjust the rising and falling edges of the first LO signal and the binary enable signal controls the second set of inverters to adjust the rising and falling edges of the second LO signal.

19. A wireless circuit, the wireless circuit comprising: A polar coordinate amplifier configured to output a radio frequency signal; A clock circuit configured to supply a first local oscillator (LO) signal and a second LO signal to the polar coordinate amplifier, wherein the first LO signal and the second LO signal transmit phase modulation of the radio frequency signal; as well as One or more processors are configured to control the clock circuit to switch between supplying the first LO signal and the second LO signal as overlapping signals to the polar coordinate amplifier and supplying the first LO signal and the second LO signal as non-overlapping signals to the polar coordinate amplifier based on one or more characteristics of the radio frequency signal.

20. The wireless circuit of claim 19, wherein the one or more processors are further configured to: The clock circuit is controlled to output the first LO signal and the second LO signal as the overlapping signal when the radio frequency signal has the first characteristic. The clock circuit is controlled to output the first LO signal and the second LO signal with a first duty cycle ratio as the non-overlapping signal when the radio frequency signal has a second characteristic different from the first characteristic; as well as The clock circuit is controlled to output the first LO signal and the second LO signal, which have a second duty cycle ratio different from the first duty cycle ratio, as the non-overlapping signal when the radio frequency signal has a third characteristic different from the first characteristic and the second characteristic.

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