A digital input monitoring circuit and method

Abstract

A digital input monitoring circuit and method include: an output terminal of a logic processing unit connected to the input terminal of an optocoupler isolation circuit; an input terminal of the logic processing unit connected to the input terminals of each digital input circuit; the logic processing unit outputs a control signal to the optocoupler isolation circuit and receives feedback signals from each digital input circuit; the feedback signals are compared and verified by the logic processing unit, and based on pulse width error and their presence or absence, it determines whether the digital input circuit or monitoring circuit is abnormal; both output terminals of the optocoupler isolation circuit are connected to each test branch; the output terminal of each test branch is connected to the pulse input terminal of a digital input circuit, and the test branch is used to generate test pulses; the digital input circuit is used to isolate the signals output by the test branches and external input signals, and output feedback signals. This invention reduces cost and circuit area, increases board functional density, and effectively ensures accurate and stable acquisition of digital input signals.

Description

Technical Field

[0001] This invention belongs to the technical field of industrial control, and more specifically, relates to a digital input monitoring circuit and method. Background Technology

[0002] Digital inputs have a wide range of applications in many fields such as industrial automation, energy and power, transportation, and smart buildings.

[0003] In the field of control and protection, the reliability requirements for digital inputs are high. For example, in power system relay protection, digital inputs are used for fault type identification and fault location. If monitoring fails and causes misjudgments or missed judgments, it will lead to malfunctions or failures of protection devices, resulting in power outages and other accidents. In industrial automated production lines, abnormal digital inputs can cause equipment malfunctions, threatening personnel safety and production continuity. Therefore, digital monitoring needs to have high accuracy, high stability, and strong anti-interference capabilities. It needs to accurately monitor digital input signals, promptly detect and handle abnormal situations, and avoid system failures caused by signal errors.

[0004] In power control and protection, digital inputs are often achieved through high input voltage and optocoupler isolation, combined with software filtering to ensure signal reception. However, optocouplers are susceptible to failure due to electrostatic damage, aging, and other factors. To improve input reliability, optocoupler feedback monitoring and redundant channel monitoring methods are typically employed.

[0005] Optocoupler feedback monitoring methods require an additional reverse isolation optocoupler for each digital input channel. Monitoring is typically triggered by the action of the digital input, making real-time detection impossible when there is no input. Furthermore, the additional optocouplers increase hardware costs and circuit complexity, and failures in the feedback optocouplers themselves can easily lead to false positives. While multi-channel redundancy can improve reliability, it requires significant hardware investment (doubling the number of components), and failures in redundant channels can still cause false positives and false negatives, failing to fundamentally meet high reliability requirements. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a digital input monitoring circuit and method.

[0007] The present invention adopts the following technical solution.

[0008] The first aspect of this invention provides a digital input monitoring circuit, comprising a logic processing unit, several digital input circuits, several test branches, an optocoupler isolation circuit, and an isolation power supply, specifically: The output of the logic processing unit is connected to the input of the optocoupler isolation circuit, and the input of the logic processing unit is connected to the output of each digital input circuit. The logic processing unit outputs control signals to the optocoupler isolation circuit and receives feedback signals from each digital input circuit. The two outputs of the optocoupler isolation circuit are connected to each test branch; the output of each test branch is connected to the pulse input of a digital input circuit. The test branch consists of a reverse-current protection diode D6, a ninth current-limiting resistor R9, a PMOS device Q1, a gate protection TVS diode D3, a sixth voltage divider resistor R6, and a tenth voltage divider resistor R10. The cathode of the reverse-current protection diode D6 serves as the output terminal of the test branch and is connected to the pulse input terminal of the corresponding digital input circuit. The anode of the reverse-current protection diode D6 is connected to the source of the PMOS device Q1 through the ninth current-limiting resistor R9. The drain of the PMOS device Q1 is connected to the output terminal of the isolation power supply, and the gate of the PMOS device Q1 is connected to the first output terminal of the optocoupler isolation circuit. The second output terminal of the optocoupler isolation circuit is grounded through the tenth voltage divider resistor R10. The sixth voltage divider resistor R6 and the gate protection TVS diode D3 are connected in parallel between the drain and the gate of the PMOS device Q1. The cathode of the gate protection TVS diode D3 is connected to the drain of the PMOS device Q1, and the anode of the gate protection TVS diode D3 is connected to the gate of the PMOS device Q1. The digital input circuit is used to isolate the signal output from the test branch and the external input signal, and output the feedback signal.

[0009] Preferably, if the voltage output by the isolation power supply exceeds the maximum allowable voltage of the PMOS device Q1 in the test branch, a voltage divider resistor is added to the corresponding test branch, and the added voltage divider resistor is connected between the gate of the PMOS device Q1 and GND.

[0010] Preferably, the digital input circuit consists of a reverse polarity protection diode D1, a second current-limiting resistor R2 and a third current-limiting resistor R3, a filter capacitor C1, a second protection diode D2, a fifth shunt resistor R5, a first isolation optocoupler U1, a pull-up resistor R1, and a level output terminal resistor R4. The external digital input terminal of the digital input circuit is connected to the anode of the reverse connection protection diode D1. The cathode of the reverse connection protection diode D1 is connected to the anode of the light-emitting diode of the first isolation optocoupler U1 through the second current-limiting resistor R2 and the third current-limiting resistor R3 in sequence. The cathode of the light-emitting diode of the first isolation optocoupler U1 is grounded. The filter capacitor C1, the second protection diode D2, and the fifth shunt resistor R5 are connected in parallel between the anode and cathode of the light-emitting diode of the first isolation optocoupler U1. The cathode of the second protection diode D2 is connected to the anode of the light-emitting diode of the first isolation optocoupler U1, and the anode of the second protection diode D2 is connected to the cathode of the light-emitting diode of the first isolation optocoupler U1. The collector of the output transistor of the first isolation optocoupler U1 is connected to one end of the pull-up resistor R1 and one end of the level output resistor R4; the other end of the pull-up resistor R1 is connected to the power supply voltage, and the other end of the level output resistor R4 serves as the output terminal of the digital input circuit; the emitter of the output transistor of the first isolation optocoupler U1 is grounded.

[0011] Preferably, the external digital input terminal of the digital input circuit receives external digital input from a device, wherein the external digital input is a DC voltage, and the DC voltage value is 24V, 110V or 220V. Compatibility of different voltage levels is achieved by adjusting the resistance values ​​of the second current-limiting resistor R2 and the third current-limiting resistor R3. The sum of the resistance values ​​of the second current-limiting resistor R2 and the third current-limiting resistor R3 is equal to the corresponding voltage level divided by the set current of the LED of the first isolation optocoupler.

[0012] Preferably, the optocoupler isolation circuit includes a seventh resistor R7, an eighth resistor R8, a fourth protection diode D4, and a second optocoupler U2; The input terminal of the optocoupler isolation circuit is connected to the cathode of the light-emitting diode of the second optocoupler U2 through the eighth resistor; the supply voltage is connected to the anode of the light-emitting diode of the second optocoupler U2; the seventh resistor R7 and the fourth protection diode D4 are connected in parallel between the anode and cathode of the light-emitting diode of the second optocoupler U2, wherein the cathode of the fourth protection diode D4 is connected to the anode of the light-emitting diode of the second optocoupler U2, and the anode of the fourth protection diode D4 is connected to the cathode of the light-emitting diode of the second optocoupler U2. The collector of the output transistor of the second optocoupler U2 is the first output terminal of the optocoupler isolation circuit, and the emitter of the output transistor of the second optocoupler U2 is the second output terminal of the optocoupler isolation circuit.

[0013] A second aspect of the present invention provides a method for monitoring digital inputs using the circuit described in the first aspect of the present invention, specifically as follows: When the logic processing unit determines that there is no external digital input and the preset detection period has been reached, the logic processing unit outputs a control signal, which is a narrow pulse Ts1 with a pulse width within the set width range. The narrow pulse Ts1 is converted into a reverse pulse Ts2 through an optocoupler isolation circuit. The reverse pulse Ts2 triggers each test branch, and the test branch injects a positive pulse with an amplitude of the isolation power supply voltage VDI and a pulse width of Ts2 into the digital input module. After isolating the positive pulse, the digital input circuit outputs a weak electrical signal as a feedback signal to the logic processing unit. The logic processing unit compares the width of the feedback signal pulse with the narrow pulse Ts1 to determine whether the digital input circuit and the digital input monitoring circuit are abnormal. When the logic processing unit detects a valid external digital input, it switches back to the external digital input response logic. The external digital input response logic means that the logic processing unit stops sending pulses and only receives external digital inputs.

[0014] Preferably, the pulse width of the narrow pulse Ts1 is greater than the minimum resolvable time of the digital input circuit, which is the hardware circuit filtering time plus the signal rise and fall times, and less than the minimum detection time of the digital input, which is the digital input software filtering time.

[0015] Preferably, the hardware circuit filtering time is the filtering time of the hardware circuit composed of the third current-limiting resistor R3 and the filter capacitor C1. The signal rise and fall time is the maximum rise and fall time of the signal when the logic processing unit sends the signal and when the optocoupler itself in the optocoupler isolation circuit transmits the signal. The digital input software filtering time is the minimum signal duration in the logic processing unit to determine whether there is a digital input. If the logic unit receives a digital input that is less than the minimum signal duration, it is considered to be external interference.

[0016] Preferably, during detection, parallel detection of multiple digital inputs is supported, and the logic processing unit sequentially selects the feedback signals transmitted by the digital input monitoring circuit through time-division multiplexing.

[0017] Preferably, the logic processing unit compares the width of the returned signal pulse with the narrow pulse Ts1 to determine whether the digital input circuit and the digital input monitoring circuit are abnormal, specifically: If the error between the returned pulse width and the narrow pulse Ts1 is within the set range, the digital input circuit is considered normal. If the error between the returned pulse width and the narrow pulse Ts1 output by some digital input circuits exceeds the set range, a lifespan alarm for the corresponding digital isolation input circuit is triggered. If the error between the returned pulse width and the narrow pulse Ts1 output by all digital input circuits exceeds the set range, the digital input monitoring circuit is considered abnormal. If no returned pulse signal is received from some digital input circuits, a fault alarm for the corresponding digital isolation input circuit is triggered. If no returned pulse signal is received from all digital input circuits, the digital input monitoring circuit is considered abnormal.

[0018] The beneficial effects of this invention are that, compared with the prior art, it achieves real-time, active, and accurate monitoring of digital input circuits through logic processing unit scheduling, active triggering of test branches, and the coordinated operation of optocoupler isolation circuits. This solves the problem of reliable digital quantity monitoring, significantly reduces the number of components used, lowers costs, reduces circuit area, and increases functional circuit density. The fifth shunt resistor R5 allows for fine-tuning of the input threshold voltage by setting the shunt value of the optocoupler input, thereby improving the anti-twisting performance of the input circuit. Attached Figure Description

[0019] Figure 1 Schematic diagram of digital input monitoring method; Figure 2 This is a schematic diagram of a digital input monitoring circuit. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this invention.

[0021] like Figure 2 As shown, Embodiment 1 of the present invention proposes a digital input monitoring circuit, including a logic processing unit, several digital input circuits, several test branches, an optocoupler isolation circuit, and an isolation power supply, specifically: The output of the logic processing unit is connected to the input of the optocoupler isolation circuit, and the input of the logic processing unit is connected to the output of each digital input circuit. The logic processing unit outputs control signals to the optocoupler isolation circuit and receives feedback signals from each digital input circuit. It should be noted that the logic processing unit is a programmable processor such as DSP / ARM / FPGA; The two outputs of the optocoupler isolation circuit are connected to each test branch; the output of each test branch is connected to the pulse input of a digital input circuit. The test branch consists of a reverse-current protection diode D6, a ninth current-limiting resistor R9, a PMOS device Q1, a gate protection TVS diode D3, a sixth voltage divider resistor R6, and a tenth voltage divider resistor R10. The cathode of the reverse-current protection diode D6 serves as the output terminal of the test branch and is connected to the pulse input terminal of the corresponding digital input circuit. The anode of the reverse-current protection diode D6 is connected to the source of the PMOS device Q1 through the ninth current-limiting resistor R9. The drain of the PMOS device Q1 is connected to the output terminal of the isolation power supply, and the gate of the PMOS device Q1 is connected to the first output terminal of the optocoupler isolation circuit. The second output terminal of the optocoupler isolation circuit is grounded through the tenth voltage divider resistor R10. The sixth voltage divider resistor R6 and the gate protection TVS diode D3 are connected in parallel between the drain and the gate of the PMOS device Q1. The cathode of the gate protection TVS diode D3 is connected to the drain of the PMOS device Q1, and the anode of the gate protection TVS diode D3 is connected to the gate of the PMOS device Q1. The digital input circuit is used to isolate the signal output from the test branch and the external input signal, and output the feedback signal.

[0022] It should be noted that, Figure 2 The test branch in is Figure 1 Test branch 1 in the circuit is provided for each digital input isolation circuit. The anti-reverse current diode D6 prevents voltage from flowing into the test branch when there is an input voltage to the external digital input DI1. The ninth current-limiting resistor R9, together with the third current-limiting resistor R3 in the digital input circuit described below, limits the current flowing through the first isolation optocoupler U1. When the primary diode of U2 is not lit, the gate of PMOS device Q1 is connected to the isolation power supply voltage VDI through the sixth voltage divider resistor R6, and PMOS device Q1 is cut off. When the LED of the optocoupler isolation circuit U2 is lit, the gate of PMOS device Q1 is grounded through R10, and PMOS device Q1 is turned on. At this time, the voltage at V1 is approximately equal to VDI × R3 / (R3 + R9) (ignoring the voltage drop across diode U1, D6, and Q1). This monitored input voltage causes the LED of PMOS device U1 to light up, and the output transistor is turned on. Gate protection TVS D3 is the gate protection TVS for PMOS device Q1, preventing damage to the gate of PMOS device Q1 due to overvoltage.

[0023] In this preferred embodiment, if the voltage output by the isolation power supply exceeds the maximum allowable voltage of the PMOS device Q1 in the test branch, a voltage divider resistor is added to the corresponding test branch, and the newly added voltage divider resistor is connected between the gate of the PMOS device Q1 and GND.

[0024] In this preferred embodiment, the digital input circuit consists of a reverse polarity protection diode D1, a second current-limiting resistor R2 and a third current-limiting resistor R3, a filter capacitor C1, a second protection diode D2, a fifth shunt resistor R5, a first isolation optocoupler U1, a pull-up resistor R1, and a level output terminal resistor R4. The external digital input terminal of the digital input circuit is connected to the anode of the reverse connection protection diode D1. The cathode of the reverse connection protection diode D1 is connected to the anode of the light-emitting diode of the first isolation optocoupler U1 through the second current-limiting resistor R2 and the third current-limiting resistor R3 in sequence. The cathode of the light-emitting diode of the first isolation optocoupler U1 is grounded. The filter capacitor C1, the second protection diode D2, and the fifth shunt resistor R5 are connected in parallel between the anode and cathode of the light-emitting diode of the first isolation optocoupler U1. The cathode of the second protection diode D2 is connected to the anode of the light-emitting diode of the first isolation optocoupler U1, and the anode of the second protection diode D2 is connected to the cathode of the light-emitting diode of the first isolation optocoupler U1. The collector of the output transistor of the first isolation optocoupler U1 is connected to one end of the pull-up resistor R1 and one end of the level output resistor R4; the other end of the pull-up resistor R1 is connected to the power supply voltage, and the other end of the level output resistor R4 serves as the output terminal of the digital input circuit; the emitter of the output transistor of the first isolation optocoupler U1 is grounded.

[0025] It should be noted that the filter capacitor C1, together with the second current-limiting resistor R2 and the third current-limiting resistor R3, performs input filtering, and the low-pass filter cutoff frequency is: 1 / (2π*(R2+R3)*C1); The second protection diode D2 protects the input of the first isolation optocoupler U1, preventing reverse overvoltage, etc. The fifth shunt resistor R5 can fine-tune the input threshold voltage by setting the shunt value of the optocoupler input. The digital input threshold voltage refers to V1 voltage that just turns on the light-emitting diode (primary LED) of the first isolation optocoupler U1. The primary-side conduction condition of the first isolation optocoupler is: V1 VD2 VLED = IF × R5, where VD2 is the regulated voltage of the second protection diode D2, VLED is the forward voltage drop of the LED of the first isolation optocoupler U1 (approximately 1.2V), and IF is the primary-side turn-on threshold current of the first isolation optocoupler. To increase the threshold voltage (i.e., to make it conduct only when V1 is higher), the voltage drop across R5 needs to be greater for the same IF. To lower the optocoupler input threshold voltage, increase R5; to increase the optocoupler input threshold voltage, decrease R5. Adjusting R5 can improve the anti-twist performance of the input circuit (a sufficiently high voltage or a sufficiently large current is required for R5 to conduct).

[0026] The first isolation optocoupler U1 provides isolation between external input digital signals and the weak electrical signals inside the control board. VCC_IO is the IO power supply voltage for the logic processing unit inside the board. When there is an external digital input, DIin1 is pulled to the DGND level; when there is no external digital input, DIin1 is pulled to the VCC_IO level by R1. Figure 2 The diagram only shows one digital input module circuit. The digital input monitoring method supports simultaneous detection of multiple digital inputs.

[0027] In this preferred embodiment, the external digital input terminal of the digital input circuit receives external digital input from a device. The external digital input is a DC voltage, and the DC voltage value is 24V, 110V, or 220V. Compatibility of different voltage levels is achieved by adjusting the resistance values ​​of the second current-limiting resistor R2 and the third current-limiting resistor R3. The sum of the resistance values ​​of the second current-limiting resistor R2 and the third current-limiting resistor R3 is equal to the corresponding voltage level divided by the set LED current of the first isolation optocoupler. The LED current of the first isolation optocoupler is typically 2~20mA.

[0028] In this preferred embodiment, the optocoupler isolation circuit includes a seventh resistor R7, an eighth resistor R8, a fourth protection diode D4, and a second optocoupler U2; The input terminal of the optocoupler isolation circuit is connected to the cathode of the light-emitting diode of the second optocoupler U2 through the eighth resistor; the supply voltage is connected to the anode of the light-emitting diode of the second optocoupler U2; the seventh resistor R7 and the fourth protection diode D4 are connected in parallel between the anode and cathode of the light-emitting diode of the second optocoupler U2, wherein the cathode of the fourth protection diode D4 is connected to the anode of the light-emitting diode of the second optocoupler U2, and the anode of the fourth protection diode D4 is connected to the cathode of the light-emitting diode of the second optocoupler U2. The collector of the output transistor of the second optocoupler U2 is the first output terminal of the optocoupler isolation circuit, and the emitter of the output transistor of the second optocoupler U2 is the second output terminal of the optocoupler isolation circuit.

[0029] It should be noted that in the fourth protection diode, D4 ​​serves as reverse overvoltage protection for the second optocoupler U2, the eighth resistor R8 is a current-limiting resistor, and the seventh resistor R7 is a shunt resistor, which can prevent the second optocoupler U2 from being mis-activated under interference. When the logic processing unit IO output TDI is high, the second optocoupler U2 does not emit light and is cut off; when the logic processing unit IO output TDI is low, the second optocoupler U2 emits light, and the output transistor of the second optocoupler U2 is turned on.

[0030] Embodiment 2 of the present invention proposes a digital input monitoring method using the circuit described in Embodiment 1 of the present invention, specifically as follows: Figure 1The schematic diagram shows the circuit implementation principle of the digital input monitoring method. The external inputs 1 to n in the block diagram are external digital inputs of the device. The input voltage is DC, usually 24VDC, 110VDC and 220VDC. When there is a digital input, the voltage is connected and converted into a high or low level of the input logic processing unit through the isolation of digital inputs 1 to n.

[0031] When the logic processing unit determines that there is no external digital input and the preset detection period has been reached, the logic processing unit outputs a control signal, which is a narrow pulse Ts1 with a pulse width within the set width range. The narrow pulse Ts1 is converted into a reverse pulse Ts2 (the pulse width of the reverse pulse Ts2 is approximately equal to that of the narrow pulse Ts1) through an optocoupler isolation circuit. The reverse pulse Ts2 triggers each test branch. Test branches 1 to n are powered by an isolated power supply with a voltage of VDI. After receiving the reverse pulse Ts2, they generate a positive pulse signal with an amplitude equal to VDI and a pulse width of Ts2, which is sent to digital inputs 1 to n respectively. After signal isolation, the weak signal is sent to the logic processing unit to complete one digital input monitoring test.

[0032] After isolating the positive pulse, the digital input circuit outputs a weak electrical signal as a feedback signal to the logic processing unit. The logic processing unit compares the width of the feedback signal pulse with the narrow pulse Ts1 to determine whether the digital input circuit and the digital input monitoring circuit are abnormal. When the logic processing unit detects a valid external digital input, it switches back to the external digital input response logic. The external digital input response logic means that the logic processing unit stops sending pulses and only receives external digital inputs.

[0033] In this preferred embodiment, the pulse width of the narrow pulse Ts1 is greater than the minimum resolvable time of the digital input circuit. The minimum resolvable time of the digital input circuit is the hardware circuit filtering time plus the signal rise and fall times, and is less than the minimum detection time of the digital input, which is the digital input software filtering time.

[0034] In this preferred embodiment, the hardware circuit filtering time is the filtering time of the hardware circuit composed of the third current-limiting resistor R3 and the filter capacitor C1. The signal rise and fall time is the maximum rise and fall time of the signal when the logic processing unit sends the signal and when the optocoupler itself in the optocoupler isolation circuit transmits the signal. The digital input software filtering time is the minimum signal duration in the logic processing unit to determine whether there is a digital input. If the logic unit receives a digital input that is less than the minimum signal duration, it considers it to be external interference rather than a digital input.

[0035] In this preferred embodiment, during detection, parallel detection of multiple digital inputs is supported, and the logic processing unit sequentially selects the feedback signals transmitted by the digital input monitoring circuit through time-division multiplexing.

[0036] In this preferred embodiment, the logic processing unit compares the width of the returned signal pulse with the narrow pulse Ts1 to determine whether the digital input circuit and the digital input monitoring circuit are abnormal. Specifically: If the error between the returned pulse width and the narrow pulse Ts1 is within the set range, the digital input circuit is considered normal. If the error between the returned pulse width and the narrow pulse Ts1 output by some digital input circuits exceeds the set range, a lifespan alarm for the corresponding digital isolation input circuit is triggered. If the error between the returned pulse width and the narrow pulse Ts1 output by all digital input circuits exceeds the set range, the digital input monitoring circuit is considered abnormal. If no returned pulse signal is received from some digital input circuits, a fault alarm for the corresponding digital isolation input circuit is triggered. If no returned pulse signal is received from all digital input circuits, the digital input monitoring circuit is considered abnormal.

[0037] Specifically, the set range is ±10% of the narrow pulse Ts1.

[0038] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0039] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0040] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0041] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A digital input monitoring circuit, comprising a logic processing unit, several digital input circuits, several test branches, an optocoupler isolation circuit, and an isolation power supply, characterized in that: The output of the logic processing unit is connected to the input of the optocoupler isolation circuit, and the input of the logic processing unit is connected to the output of each digital input circuit. The logic processing unit outputs control signals to the optocoupler isolation circuit and receives feedback signals from each digital input circuit. The two outputs of the optocoupler isolation circuit are connected to each test branch; the output of each test branch is connected to the pulse input of a digital input circuit. The test branch consists of a reverse-current protection diode D6, a ninth current-limiting resistor R9, a PMOS device Q1, a gate protection TVS diode D3, a sixth voltage divider resistor R6, and a tenth voltage divider resistor R10. The cathode of the reverse-current protection diode D6 serves as the output terminal of the test branch and is connected to the pulse input terminal of the corresponding digital input circuit. The anode of the reverse-current protection diode D6 is connected to the source of the PMOS device Q1 through the ninth current-limiting resistor R9. The drain of the PMOS device Q1 is connected to the output terminal of the isolation power supply, and the gate of the PMOS device Q1 is connected to the first output terminal of the optocoupler isolation circuit. The second output terminal of the optocoupler isolation circuit is grounded through the tenth voltage divider resistor R10. The sixth voltage divider resistor R6 and the gate protection TVS diode D3 are connected in parallel between the drain and the gate of the PMOS device Q1. The cathode of the gate protection TVS diode D3 is connected to the drain of the PMOS device Q1, and the anode of the gate protection TVS diode D3 is connected to the gate of the PMOS device Q1. The digital input circuit is used to isolate the signal output from the test branch and the external input signal, and output the feedback signal.

2. The digital input monitoring circuit according to claim 1, characterized in that: If the voltage output by the isolation power supply exceeds the maximum allowable voltage of the PMOS device Q1 in the test branch, a voltage divider resistor is added to the corresponding test branch. The new voltage divider resistor is connected between the gate of the PMOS device Q1 and GND.

3. The digital input monitoring circuit according to claim 1, characterized in that: The digital input circuit consists of a reverse polarity protection diode D1, a second current-limiting resistor R2 and a third current-limiting resistor R3, a filter capacitor C1, a second protection diode D2, a fifth shunt resistor R5, a first isolation optocoupler U1, a pull-up resistor R1, and a level output terminal resistor R4. The external digital input terminal of the digital input circuit is connected to the anode of the reverse connection protection diode D1. The cathode of the reverse connection protection diode D1 is connected to the anode of the light-emitting diode of the first isolation optocoupler U1 through the second current-limiting resistor R2 and the third current-limiting resistor R3 in sequence. The cathode of the light-emitting diode of the first isolation optocoupler U1 is grounded. The filter capacitor C1, the second protection diode D2, and the fifth shunt resistor R5 are connected in parallel between the anode and cathode of the light-emitting diode of the first isolation optocoupler U1. The cathode of the second protection diode D2 is connected to the anode of the light-emitting diode of the first isolation optocoupler U1, and the anode of the second protection diode D2 is connected to the cathode of the light-emitting diode of the first isolation optocoupler U1. The collector of the output transistor of the first isolation optocoupler U1 is connected to one end of the pull-up resistor R1 and one end of the level output resistor R4; the other end of the pull-up resistor R1 is connected to the power supply voltage, and the other end of the level output resistor R4 serves as the output terminal of the digital input circuit; the emitter of the output transistor of the first isolation optocoupler U1 is grounded.

4. The digital input monitoring circuit according to claim 3, characterized in that: The external digital input terminal of the digital input circuit receives external digital input from the device class. The external digital input from the device class is a DC voltage, and the voltage value of the DC voltage is 24V, 110V or 220V. Compatibility of different voltage levels can be achieved by adjusting the resistance values ​​of the second current limiting resistor R2 and the third current limiting resistor R3. The sum of the resistance values ​​of the second current limiting resistor R2 and the third current limiting resistor R3 is equal to the corresponding voltage level divided by the set current of the LED of the first isolation optocoupler.

5. The digital input monitoring circuit according to claim 1, characterized in that: The optocoupler isolation circuit includes a seventh resistor R7, an eighth resistor R8, a fourth protection diode D4, and a second optocoupler U2. The input terminal of the optocoupler isolation circuit is connected to the cathode of the light-emitting diode of the second optocoupler U2 through the eighth resistor; the supply voltage is connected to the anode of the light-emitting diode of the second optocoupler U2; the seventh resistor R7 and the fourth protection diode D4 are connected in parallel between the anode and cathode of the light-emitting diode of the second optocoupler U2, wherein the cathode of the fourth protection diode D4 is connected to the anode of the light-emitting diode of the second optocoupler U2, and the anode of the fourth protection diode D4 is connected to the cathode of the light-emitting diode of the second optocoupler U2. The collector of the output transistor of the second optocoupler U2 is the first output terminal of the optocoupler isolation circuit, and the emitter of the output transistor of the second optocoupler U2 is the second output terminal of the optocoupler isolation circuit.

6. A digital input monitoring method using the circuit described in any one of claims 3-5, characterized in that: When the logic processing unit determines that there is no external digital input and the preset detection period has been reached, the logic processing unit outputs a control signal, which is a narrow pulse Ts1 with a pulse width within the set width range. The narrow pulse Ts1 is converted into a reverse pulse Ts2 through an optocoupler isolation circuit. The reverse pulse Ts2 triggers each test branch, and the test branch injects a positive pulse with an amplitude of the isolation power supply voltage VDI and a pulse width of Ts2 into the digital input module. After isolating the positive pulse, the digital input circuit outputs a weak electrical signal as a feedback signal to the logic processing unit. The logic processing unit compares the width of the feedback signal pulse with the narrow pulse Ts1 to determine whether the digital input circuit and the digital input monitoring circuit are abnormal. When the logic processing unit detects a valid external digital input, it switches back to the external digital input response logic. The external digital input response logic means that the logic processing unit stops sending pulses and only receives external digital inputs.

7. The digital input monitoring method according to claim 6, characterized in that: The pulse width of the narrow pulse Ts1 is greater than the minimum resolvable time of the digital input circuit, which is the hardware circuit filtering time plus the signal rise and fall times, and less than the minimum detection time of the digital input, which is the digital input software filtering time.

8. The digital input monitoring method according to claim 7, characterized in that: The hardware circuit filtering time is the filtering time of the hardware circuit composed of the third current-limiting resistor R3 and the filter capacitor C1. The signal rise and fall time is the maximum rise and fall time of the signal when the logic processing unit sends the signal and when the optocoupler itself in the optocoupler isolation circuit transmits the signal. The digital input software filtering time is the minimum signal duration in the logic processing unit to determine whether there is a digital input. If the logic unit receives a digital input that is less than the minimum signal duration, it is considered to be external interference.

9. The digital input monitoring method according to claim 6, characterized in that: During testing, it supports parallel detection of multiple digital inputs. The logic processing unit sequentially selects the feedback signals transmitted by the digital input monitoring circuit through time-division multiplexing.

10. The digital input monitoring method according to claim 9, characterized in that: The logic processing unit compares the width of the returned signal pulse with the narrow pulse Ts1 to determine whether the digital input circuit and the digital input monitoring circuit are abnormal. Specifically: If the error between the feedback pulse width and the narrow pulse Ts1 is within the set range, the digital input circuit is determined to be normal; if the error between the feedback pulse width and the narrow pulse Ts1 output by some digital input circuits exceeds the set range, the corresponding digital isolation input circuit life alarm is triggered; if the error between the feedback pulse width and the narrow pulse Ts1 output by all digital input circuits exceeds the set range, the digital input monitoring circuit is determined to be abnormal. If no feedback pulse signal is received from the output of a certain digital input circuit, a fault alarm is triggered for the corresponding digital isolation input circuit. If no feedback pulse signals are received from all digital input circuits, the digital input monitoring circuit is deemed to be malfunctioning.

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