Aperiodic data frequency acquisition and lock detection circuit and method

Abstract

This invention discloses an aperiodic data frequency acquisition and lock detection circuit and method, comprising: a frequency detection circuit configured to use a single flip-flop to sample a voltage-controlled oscillator (VCO) clock signal via the rising edge of aperiodic data, generating a pulse signal related to the frequency difference, wherein the duty cycle of the pulse signal monotonically changes during frequency acquisition; a frequency scanning circuit connected to the frequency detection circuit, configured to generate an oscillation frequency control signal based on the pulse signal to control the oscillation frequency of the VCO in the clock data recovery circuit to increase or decrease; and a lock detection circuit connected to the frequency detection circuit, configured to perform lock detection based on the duty cycle change of the pulse signal, and output a lock indication signal when lock is determined. This invention can expand the frequency acquisition range, achieve higher reliability, and reduce power consumption and area.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and in particular to a non-periodic data frequency acquisition and locking detection circuit and method. Background Technology

[0002] Clock data recovery (CDR) circuits receive noisy and jittery non-periodic data and recover a periodic clock signal. The recovered clock signal simultaneously re-timing and sampling the input data to obtain data as clean as the recovered clock. To ensure optimal sampling, the recovered clock and input data have a certain phase relationship, typically with the clock edge aligned to the midpoint of the data bits. The process of achieving this optimal sampling phase relationship between the clock and data is called the locking process. Practical engineering applications often require CDR circuits to cover multiple operating rates and temperature variations. In such cases, CDR circuits need to utilize frequency detection (FD) circuits to enhance their frequency acquisition capability. Frequency detection and other auxiliary acquisition circuits complete the non-periodic data frequency acquisition to extend the operating rate range of the CDR circuit, while the lock-in detection (LD) circuit indicates the current state of the CDR circuit. Phase-locked loop (PLL) based CDR circuits are a common structure, and their basic block diagram is shown below. Figure 1 As shown, this structure typically includes an aperiodic data phase detector (PD), a loop filter (LF), a voltage-controlled oscillator (VCO), and aperiodic data frequency detection (FD) and lock-in detection (LD) circuits.

[0003] Unlike periodic clock frequency acquisition and lock-on detection in frequency synthesizers, aperiodic data frequency acquisition and lock-on detection requires processing aperiodic input data. Aperiodic data does not contain spectral lines representing data bit intervals and does not provide direct information for frequency detection.

[0004] The non-periodic data frequency detection circuit and latch detection are crucial to the latch range and latch time of the clock data recovery circuit. Improvements in design specifications such as operating speed, latch range, latch time, and integration density of the clock data recovery circuit also place new demands on the non-periodic data frequency detection circuit and latch detection circuit. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to address the shortcomings of the prior art by providing an aperiodic data frequency acquisition and lock detection circuit and method, which can extend the frequency acquisition range, improve reliability, and reduce power consumption and area.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A non-periodic data frequency acquisition and lock detection circuit, comprising: The frequency detection circuit is configured to use a single flip-flop to sample the voltage-controlled oscillator clock signal through the rising edge of non-periodic data, generate a pulse signal related to the frequency difference, and the duty cycle of the pulse signal changes monotonically during the frequency acquisition process.

[0007] The frequency scanning circuit, connected to the frequency detection circuit, is configured to generate an oscillation frequency control signal based on a pulse signal to control the oscillation frequency of the voltage-controlled oscillator in the clock data recovery circuit to increase or decrease.

[0008] A lock detection circuit, connected to the frequency detection circuit, is configured to perform lock detection based on the duty cycle change of the pulse signal, and output a lock indication signal when a lock is determined.

[0009] The frequency detection circuit is a first D flip-flop. Its data terminal is used to receive the clock signal from the voltage-controlled oscillator, its clock terminal is used to receive non-periodic data, its non-inverting output terminal outputs the first pulse signal, and its inverting output terminal outputs the second pulse signal.

[0010] The frequency scanning circuit includes an analog-to-digital converter configured to compare the oscillation frequency control signal with preset high and low thresholds and output quantization information.

[0011] The digital logic circuit, connected to the analog-to-digital converter, is configured to operate based on quantization information and the current lock indication signal. Generate frequency scanning direction control signal.

[0012] The charge / discharge scanning circuit, connected to the digital logic circuit, is configured to integrate according to the frequency scanning direction control signal. The capacitor is charged or discharged to generate a linearly increasing or decreasing oscillation frequency control signal.

[0013] The charge / discharge scanning circuit includes: The charging scanning branch, capable of charging the integrating capacitor, includes a first current source, a first switch, and a first [other component] connected in sequence. A current mirror; wherein the first switch is connected to the output terminal of the digital logic circuit, including a first transistor and a second transistor that are mirrored.

[0014] The discharge scanning branch can discharge the integrating capacitor and includes a second current source, a second switch, and a second current mirror; wherein the second switch is connected to the output terminal of the digital logic circuit and includes a mirrored third transistor and a fourth transistor.

[0015] The integrating capacitor has its lower plate grounded, and its upper plate is connected to the first current mirror, the second current mirror, and the frequency control terminal of the voltage-controlled oscillator, respectively.

[0016] The lock detection circuit includes: A programmable counter, whose clock terminal is used to receive the clock signal from the voltage-controlled oscillator, whose reset terminal is connected to the inverting output terminal of the frequency detection circuit, and whose counting capacity can be programmed.

[0017] The second D flip-flop has its clock terminal connected to the overflow signal output terminal of the programmable counter, its reset terminal connected to the inverted output terminal of the frequency detection circuit, and its output terminal providing the lockout indication signal.

[0018] A clock data recovery circuit includes a non-periodic data frequency capture and lock detection circuit.

[0019] A method for non-periodic data frequency acquisition and lock detection includes the following steps.

[0020] S1. Frequency detection: Using a single flip-flop, the voltage-controlled oscillator clock signal is sampled by the rising edge of non-periodic data to generate a pulse signal related to the frequency difference. The duty cycle of the pulse signal changes monotonically during the frequency acquisition process.

[0021] S2. Frequency Scan: Based on the pulse signal, an oscillation frequency control signal is generated to control the oscillation frequency of the voltage-controlled oscillator to increase or decrease, thereby achieving frequency scanning and capture of the entire oscillation frequency band.

[0022] S3. Lock detection: Lock detection is performed based on the duty cycle change of the pulse signal. When the pulse signal is continuously at a high level for a preset number of voltage-controlled oscillator clock cycles, the clock data recovery circuit is determined to be locked, and a lock indication signal is output.

[0023] In S1, a first D flip-flop is used. Its data terminal is input with a voltage-controlled oscillator clock signal, its clock terminal is input with non-periodic data, its non-inverting output terminal outputs a first pulse signal related to the frequency difference, and its inverting output terminal outputs a second pulse signal related to the frequency difference. The first pulse signal and the second pulse signal are complementary signals.

[0024] In S2, the frequency scan includes: S2-1. Compare the oscillation frequency control signal with preset high and low thresholds, and output quantization information; S2-2. Based on the quantization information and the current lock indication signal, generate a frequency scanning direction control signal; S2-3. According to the frequency scanning direction control signal, the integrating capacitor is alternately charged and discharged through the charging scanning circuit and the discharging scanning circuit to generate the oscillation frequency control signal that increases or decreases linearly.

[0025] In S3, lock detection includes: S3-1. A programmable counter is used to count the clock signal of the voltage-controlled oscillator. The counting capacity is adjustable and is used to set the locking detection window. S3-2. Reset the programmable counter and the second D flip-flop using the second pulse signal; S3-3. When the second pulse signal remains at a high level for a voltage-controlled oscillator clock cycle equal to the counter capacity, the programmable counter generates an overflow signal. S3-4. Use the overflow signal to trigger the second D flip-flop, causing it to output a lock indication signal.

[0026] S3-5, the lock indicator signal is used for resetting digital logic circuits.

[0027] The present invention has the following beneficial effects: 1. This invention is used in clock data recovery circuits. With the help of a single flip-flop frequency detection and frequency scanning circuit, it can capture the frequency of non-periodic data in the entire VCO oscillation frequency band without relying on the linearity of frequency detection, thus achieving a larger frequency capture range and greatly expanding the operating speed range of the CDR circuit.

[0028] 2. This invention utilizes the characteristic of a single flip-flop to detect changes in the duty cycle of the output pulse, simultaneously controlling frequency scanning and latch-up detection. Digital logic frequency detection and latch-up detection improve the reliability of the circuit under variations in process technology and temperature, while reducing chip layout area and chip power consumption.

[0029] 3. In this invention, the size of the lock detection window can be flexibly set by a programmable counter, which can be adjusted according to system requirements, effectively preventing false detection and missed detection, and improving the accuracy of lock detection. Attached Figure Description

[0030] Figure 1 This is a block diagram of a clock data recovery circuit based on a phase-locked loop.

[0031] Figure 2 This is a block diagram illustrating the principle of an aperiodic data frequency acquisition and lock detection circuit provided in an embodiment of the present invention.

[0032] Figure 3 This is a circuit diagram of the frequency scanning circuit in an embodiment of the present invention.

[0033] Figure 4 This is a circuit diagram of the analog-to-digital conversion circuit in an embodiment of the present invention.

[0034] Figure 5 This is a digital logic timing waveform diagram of a key node in an embodiment of the present invention. Detailed Implementation

[0035] The present invention will now be described in further detail with reference to the accompanying drawings and specific preferred embodiments.

[0036] In the description of this invention, it should be understood that the terms "left side," "right side," "upper part," "lower part," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. "First," "second," etc., do not indicate the importance of the components, and therefore should not be construed as a limitation of this invention. The specific dimensions used in this embodiment are only for illustrating the technical solution and do not limit the scope of protection of this invention.

[0037] like Figure 2 As shown, a non-periodic data frequency acquisition and lock detection method includes a frequency detection circuit, a frequency scanning circuit, and a lock detection circuit.

[0038] The frequency detection circuit described above is configured to utilize a single flip-flop, preferably a first D flip-flop. Its data terminal D is used to receive the voltage-controlled oscillator clock signal, its clock terminal CK is used to receive non-periodic data, its non-inverting output Q outputs the first pulse Q1, and its inverting output QB outputs... Figure 5 The second pulse signal Q1B in the signal is Q1, where Q1 and Q1B are complementary signals.

[0039] The frequency detection circuit samples the voltage-controlled oscillator clock signal through the rising edge of non-periodic data, generating pulse signals (Q1 and Q1B) related to the frequency difference, and the duty cycle of the pulse signals changes monotonically during the frequency acquisition process.

[0040] When the clock data recovery circuit is unlocked, the pulse frequencies of Q1 and Q1B are close to their frequency difference. During the clock data recovery circuit locking process, the duty cycle of Q1 gradually decreases, while the duty cycle of Q1B gradually increases. The output of D flip-flop 1 drives the frequency scanning circuit.

[0041] The aforementioned frequency scanning circuit includes a charge / discharge scanning circuit, an analog-to-digital conversion circuit, and a digital logic circuit; it can generate an oscillation frequency control signal based on a pulse signal to control the oscillation frequency of the voltage-controlled oscillator in the clock data recovery circuit to increase or decrease.

[0042] like Figure 4 As shown, the analog-to-digital converter circuit includes comparator 1 and comparator 2, which compare the oscillation frequency control signal with the set high threshold and low threshold respectively, and output two bits of quantization information MSB or LSB.

[0043] The aforementioned digital logic circuit has its input terminals connected to an analog-to-digital converter (ADC) circuit, enabling it to receive quantization information from the ADC circuit; The RST pin can receive the current lock indication signal; the output pin is connected to the charge / discharge scan circuit and outputs the frequency scan direction control signal.

[0044] like Figure 3 As shown, the above-mentioned charge-discharge scanning circuit includes a charging scanning branch, a discharging scanning branch, and an integrating capacitor.

[0045] The above-mentioned charging scanning branch can charge the integrating capacitor, including a first current source I1, a first switch and a first current mirror (also called current mirror 1) connected in sequence; wherein, the first switch is connected to the output terminal of the digital logic circuit, including a first transistor M1 and a second transistor M2 that are mirrored.

[0046] The above-mentioned discharge scanning branch can discharge the integrating capacitor, including a second current source I2, a second switch and a second current mirror (also called current mirror 2); wherein, the second switch is connected to the output terminal of the digital logic circuit and includes a third transistor M3 and a fourth transistor M4 that are mirrored.

[0047] The aforementioned integrating capacitor has its lower plate grounded, and its upper plate connected to the first current mirror, the second current mirror, and the frequency control terminal of the voltage-controlled oscillator, respectively.

[0048] The aforementioned charge / discharge scanning circuit charges or discharges the integrating capacitor according to the frequency scanning direction control signal, generating a linearly increasing or decreasing oscillation frequency control signal to control the increase or decrease of the voltage-controlled oscillator's oscillation frequency. The oscillation frequency control signal is quantized by an analog-to-digital converter circuit, and then the digital logic generates a frequency scanning control signal. The digital logic controls the frequency scanning direction based on the quantization information and the current lock indication signal, allowing the voltage-controlled oscillator frequency to scan back and forth across the entire oscillation frequency band, thus achieving frequency capture across the entire oscillation frequency band.

[0049] The aforementioned lock detection circuit includes a programmable counter and a second D flip-flop, which can perform lock detection based on the duty cycle change of the pulse signal and output a lock indication signal when a lock is determined.

[0050] The clock input CK of the aforementioned programmable counter is used to receive the clock signal from the voltage-controlled oscillator (VCO). Its reset input RSTB is connected to the inverting output Q of the frequency detection circuit and can receive the second pulse signal Q1B. The counting capacity of the programmable counter can be programmed, thereby setting the size of the locking detection window. The overflow signal output of the programmable counter can output... Figure 5 The counter overflow signal C is shown in the figure.

[0051] The second D flip-flop described above has its clock input CK connected to the overflow signal output of the programmable counter, and can be triggered by the rising edge of the counter overflow signal; its reset input RSTB is connected to the inverting output Q of the frequency detection circuit, and can receive the second pulse signal Q1B; its non-inverting output Q is connected to the reset input RST of the digital logic circuit, and can receive the second pulse signal Q1B by providing... Figure 5 The lock indicator signal Q2 is used to reset the digital logic circuit.

[0052] A clock data recovery circuit includes the aforementioned non-periodic data frequency capture and lock detection circuit.

[0053] A method for non-periodic data frequency acquisition and lock detection includes the following steps.

[0054] S1. Frequency detection: Using a single flip-flop, the voltage-controlled oscillator clock signal is sampled by the rising edge of non-periodic data to generate pulse signals (Q1 and Q1B) related to the frequency difference. The duty cycle of the pulse signal changes monotonically during the frequency acquisition process.

[0055] S2. Frequency Scan: Based on the pulse signal, an oscillation frequency control signal is generated to control the oscillation frequency of the voltage-controlled oscillator to increase or decrease, thereby achieving frequency scanning and capture of the entire oscillation frequency band.

[0056] The frequency scanning described above preferably includes the following steps.

[0057] S2-1. Compare the oscillation frequency control signal with preset high and low thresholds, and output quantization information.

[0058] S2-2. Based on the quantization information and the current lock indication signal, generate a frequency scanning direction control signal.

[0059] S2-3. According to the frequency scanning direction control signal, the charging scanning circuit and the discharging scanning circuit alternately scan the product... The capacitor is charged and discharged to generate the oscillation frequency control signal that increases or decreases linearly.

[0060] S3. Lock detection: Lock detection is performed based on the duty cycle change of the pulse signal. When the pulse signal is continuously at a high level for a preset number of voltage-controlled oscillator clock cycles, the clock data recovery circuit is determined to be locked, and a lock indication signal is output.

[0061] The above-mentioned process for identifying and locking down idols includes the following steps.

[0062] S3-1. A programmable counter is used to count the clock signal of the voltage-controlled oscillator. The counting capacity is adjustable and is used to set the lock detection window. The larger the window, the higher the tolerance for phase jitter, which can effectively prevent misjudgment caused by random jitter of the input data and improve the reliability of lock detection.

[0063] S3-2. The programmable counter and the second D flip-flop are reset using the second pulse signal.

[0064] S3-3. When the second pulse signal remains at a high level for a voltage-controlled oscillator clock cycle equal to the counter capacity, the programmable counter generates an overflow signal.

[0065] S3-4. Use the overflow signal to trigger the second D flip-flop, causing it to output a lock indication signal.

[0066] S3-5, the lock indicator signal is used for resetting digital logic circuits.

[0067] This invention combines Figure 5 The working principle of the digital logic timing waveform shown is explained below.

[0068] Unlocked State: When there is a frequency difference between the average frequency of the non-periodic data signal and the frequency of the VCO clock signal, Q1B will generate periodic low-level pulses. These low-level pulses continuously reset the programmable counter and the second D flip-flop. Therefore, the programmable counter is cleared before reaching the preset capacity, and no rising edge of the overflow signal C is generated. The output Q2 of the second D flip-flop remains low, indicating that the circuit is unlocked.

[0069] Locked State: When frequency acquisition is complete and the CDR circuit enters the locked state, Q1B will remain high for a voltage-controlled oscillator clock cycle equal to the counter's capacity. During this time, the programmable counter can count continuously until it overflows, generating a rising edge of the overflow signal C. This rising edge of the overflow signal C triggers the second D flip-flop, causing its output Q2 to flip high, indicating that the circuit is locked. In the locked state, Q1B remains high, the counter will periodically generate the overflow signal C, and Q2 will remain high.

[0070] Unlocked State: If the locked CDR circuit is unlocked for any reason, Q1B will generate a low-level pulse again. This low-level pulse will immediately reset the second D flip-flop, causing its output Q2 to flip low, thus indicating that the circuit has been unlocked. At this time, the programmable counter capacity adjusts the lockout determination window to prevent false judgments.

[0071] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.

Claims

1. A non-periodic data frequency acquisition and lock detection circuit, characterized in that: include: The frequency detection circuit is configured to use a single flip-flop to sample the voltage-controlled oscillator clock signal through the rising edge of non-periodic data, generate a pulse signal related to the frequency difference, and the duty cycle of the pulse signal changes monotonically during the frequency acquisition process. A frequency scanning circuit, connected to the frequency detection circuit, is configured to generate an oscillation frequency control signal based on a pulse signal to control the oscillation frequency of the voltage-controlled oscillator in the clock data recovery circuit to increase or decrease. A lock detection circuit, connected to the frequency detection circuit, is configured to perform lock detection based on the duty cycle change of the pulse signal, and output a lock indication signal when a lock is determined.

2. The non-periodic data frequency acquisition and lock detection circuit according to claim 1, characterized in that: The frequency detection circuit is a first D flip-flop. Its data terminal is used to receive the clock signal from the voltage-controlled oscillator, its clock terminal is used to receive non-periodic data, its non-inverting output terminal outputs the first pulse signal, and its inverting output terminal outputs the second pulse signal.

3. The non-periodic data frequency acquisition and lock detection circuit according to claim 1, characterized in that: The frequency scanning circuit includes: The analog-to-digital converter circuit is configured to compare the oscillation frequency control signal with preset high and low thresholds and output quantization information. The digital logic circuit, connected to the analog-to-digital converter circuit, is configured to generate a frequency scan direction control signal based on quantization information and the current lock indication signal; The charge / discharge scanning circuit, connected to the digital logic circuit, is configured to charge or discharge the integrating capacitor according to the frequency scanning direction control signal, so as to generate a linearly increasing or decreasing oscillation frequency control signal.

4. The non-periodic data frequency acquisition and locking detection method according to claim 3, characterized in that: The charge / discharge scanning circuit includes: The charging scanning branch can charge the integrating capacitor and includes a first current source, a first switch and a first current mirror connected in sequence; wherein, the first switch is connected to the output terminal of the digital logic circuit and includes a first transistor and a second transistor that are mirrored. The discharge scanning branch can discharge the integrating capacitor and includes a second current source, a second switch, and a second current mirror; wherein, the second switch is connected to the output terminal of the digital logic circuit and includes a mirrored third transistor and a fourth transistor; The integrating capacitor has its lower plate grounded, and its upper plate is connected to the first current mirror, the second current mirror, and the frequency control terminal of the voltage-controlled oscillator, respectively.

5. The non-periodic data frequency acquisition and lock detection circuit according to claim 1, characterized in that: The lock detection circuit includes: A programmable counter, whose clock terminal is used to receive the clock signal from the voltage-controlled oscillator, whose reset terminal is connected to the inverting output terminal of the frequency detection circuit, and whose counting capacity can be programmed. The second D flip-flop has its clock terminal connected to the overflow signal output terminal of the programmable counter, its reset terminal connected to the inverted output terminal of the frequency detection circuit, and its output terminal providing the lockout indication signal.

6. A clock data recovery circuit, characterized in that, Includes the non-periodic data frequency acquisition and lock detection circuit as described in any one of claims 1 to 5.

7. A method for non-periodic data frequency acquisition and locking detection, characterized in that: include: S1. Frequency detection: Using a single flip-flop, the voltage-controlled oscillator clock signal is sampled by the rising edge of non-periodic data to generate a pulse signal related to the frequency difference. The duty cycle of the pulse signal changes monotonically during the frequency acquisition process. S2. Frequency scanning: Based on the pulse signal, an oscillation frequency control signal is generated to control the oscillation frequency of the voltage-controlled oscillator to increase or decrease, thereby achieving frequency scanning and capture of the entire oscillation frequency band. S3. Lock detection: Lock detection is performed based on the duty cycle change of the pulse signal. When the pulse signal is continuously at a high level for a preset number of voltage-controlled oscillator clock cycles, the clock data recovery circuit is determined to be locked, and a lock indication signal is output.

8. The non-periodic data frequency acquisition and locking detection method according to claim 7, characterized in that: In S1, a first D flip-flop is used. Its data terminal is input with a voltage-controlled oscillator clock signal, its clock terminal is input with non-periodic data, its non-inverting output terminal outputs a first pulse signal related to the frequency difference, and its inverting output terminal outputs a second pulse signal related to the frequency difference. The first pulse signal and the second pulse signal are complementary signals.

9. The non-periodic data frequency acquisition and locking detection method according to claim 7, characterized in that: In S2, the frequency scan includes: S2-1. Compare the oscillation frequency control signal with preset high and low thresholds, and output quantization information; S2-2. Based on the quantization information and the current lock indication signal, generate a frequency scanning direction control signal; S2-3. According to the frequency scanning direction control signal, the integrating capacitor is alternately charged and discharged through the charging scanning circuit and the discharging scanning circuit to generate the oscillation frequency control signal that increases or decreases linearly.

10. The non-periodic data frequency acquisition and locking detection method according to claim 8, characterized in that: In S3, lock detection includes: S3-1. A programmable counter is used to count the clock signal of the voltage-controlled oscillator. The counting capacity is adjustable and is used to set the locking detection window. S3-2. Reset the programmable counter and the second D flip-flop using the second pulse signal; S3-3. When the second pulse signal remains at a high level for a voltage-controlled oscillator clock cycle equal to the counter capacity, the programmable counter generates an overflow signal. S3-4. Use the overflow signal to trigger the second D flip-flop, causing it to output a lock indication signal; S3-5, the lock indicator signal is used for resetting digital logic circuits.

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