Low phase noise phase locked loop

Abstract

An apparatus and method for generating a signal. A controlled oscillator generates an output signal having an output signal frequency based on a control input signal. A frequency divider generates a divided output at a frequency equal to the output signal frequency divided by a value. A detector and a filter generate a filtered phase error signal based on the phase difference between the divided output and a frequency reference signal. A variable LC time reference has a resonant frequency based on a low-pass filtered error signal, and generates a time reference signal with a determined time delay relative to the output signal when the output signal frequency is at the resonant frequency. A time error detector determines an error signal based on the time difference between the output signal and the time reference signal, wherein the control input signal is based on the filtered time error signal.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to AC signal generation, and more specifically, to AC signal generators with low phase noise. Background Technology

[0002] Many radio frequency (RF) systems incorporate signal generators that produce stable waveforms. These stable waveforms are used, for example, as frequency references, signals that can be processed for RF transmission, signals used for basic processing of received RF signals at the receiver, other uses, or combinations thereof. Many circuits can benefit from signal generators with low phase noise characteristics. Summary of the Invention

[0003] A signal generator includes a controlled oscillator circuit configured to generate an output signal having an output signal frequency based on a control input signal. The signal generator includes a frequency divider circuit configured to generate a divided output with a frequency equal to the output signal frequency divided by a value. The signal generator includes a phase frequency detector circuit configured to generate a phase error signal based on the phase difference between the divided output and a frequency reference signal. The signal generator includes a phase-locked loop (PLL) filter circuit configured to generate a low-pass filtered error signal at a frequency based on low-pass filtering of the phase error signal. The signal generator includes a tunable LC time reference circuit including an LC resonant circuit having a resonant frequency based on the low-pass filtered error signal. The tunable LC time reference circuit is configured to receive the output signal, generate a time reference signal, and introduce a determined time delay relative to the output signal when the output signal frequency is at the resonant frequency. The signal generator includes a time error detector circuit configured to determine a filtered time error signal indicating a time error between the output signal and the time reference signal. The control input signal is based on the filtered time error signal.

[0004] The signal generator may additionally include a phase-shift N-dividend circuit configured to receive the output signal and generate an in-phase feedback signal and a phase-shifted feedback signal. The in-phase feedback signal and the phase-shifted feedback signal may have frequencies equal to the output signal frequency divided by a value. The phase-shifted feedback signal may be offset by ninety degrees from the in-phase feedback signal. The time error detector circuit may include a current comparator circuit configured to receive the time reference signal and generate an adjusted time reference signal. The time error detector circuit may also include a time comparator circuit configured to determine a time error signal based on the time difference between the adjusted time reference signal and the phase-shifted feedback signal. A filtered time error signal is based on the time error signal.

[0005] A phase-shift N divider circuit can include a fractional N divider circuit. A phase-shift N divider circuit can also include an integer N divider circuit.

[0006] The signal generator may additionally include an N-division circuit configured to receive the output signal and generate a feedback signal. The feedback signal may have a frequency equal to the frequency of the output signal divided by a value. The time error detector circuit may include a voltage comparator circuit configured to receive the time reference signal and generate an adjusted time reference signal. The time error detector circuit may also include a time comparator circuit configured to determine a time error signal based on the time difference between the adjusted time reference signal and the feedback signal. A filtered time error signal is based on this time error signal.

[0007] The tunable LC time base circuit can induce a 90-degree phase shift between the output signal and the time base signal. The time error detector circuit may further include a time error capacitor configured to receive the time base signal and couple the tunable LC time base circuit to the current comparator circuit. The time error detector circuit may further include an inverter circuit configured to invert the feedback signal and provide the inverted feedback signal to the time comparator circuit.

[0008] A method for generating a signal includes: generating an output signal having an output signal frequency based on a control input signal; generating a frequency-divided output with a frequency equal to the output signal frequency divided by a value; generating a phase error signal based on a phase difference between the divided output and a frequency reference signal; low-pass filtering the phase error signal to generate a low-pass filtered error signal; generating a time reference signal based on the output signal, wherein the time reference signal is generated by a tunable LC time reference circuit having a resonant frequency based on the low-pass filtered error signal, and wherein the time reference signal has a defined time delay relative to the output signal when the output signal frequency is at the resonant frequency; and determining a filtered time error signal indicating a time error between the output signal and the time reference signal. The control input signal is based on the filtered time error signal.

[0009] The method may further include: generating an in-phase feedback signal and a phase-shifted feedback signal based on the output signal. The in-phase feedback signal and the phase-shifted feedback signal may have frequencies equal to the frequency of the output signal divided by a value. The phase-shifted feedback signal may be offset by ninety degrees from the in-phase feedback signal. The method may further include: generating an adjusted time reference signal based on the time reference signal. The method may further include: determining a time error signal based on the time difference between the adjusted time reference signal and the phase-shifted feedback signal. The filtered time error signal may be based on the time error signal.

[0010] Values ​​can include decimal values. Values ​​can also include integer values.

[0011] The method may further include: generating a feedback signal based on the output signal. The feedback signal may have a frequency equal to the frequency of the output signal divided by a value. The method may further include generating an adjusted time base signal based on the time base signal. The method may further include determining a time error signal based on the time difference between the adjusted time base signal and the feedback signal. The filtered time error signal may be based on the time error signal. Attached Figure Description

[0012] Embodiments of the present invention are shown by way of example and are not limited to the accompanying drawings, in which similar reference numerals indicate similar elements. The elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0013] Figure 1 A phase-locked loop (PLL) circuit with broadband feedback is shown according to an example.

[0014] Figure 2 An example of a tunable LC time reference circuit is shown, based on the example.

[0015] Figure 3 The first example PLL with broadband feedback is shown, based on the example example.

[0016] Figure 4 A second example PLL with broadband feedback is shown, based on the example.

[0017] Figure 5 The process for generating a signal is shown in the example. Detailed Implementation

[0018] The systems and methods described below provide phase-locked loop (PLL) oscillators with reduced phase noise characteristics. These systems and methods enable improved phase noise performance without incorporating costly process options or expensive discrete components. They reduce phase noise characteristics by incorporating a broadband feedback loop around the PLL oscillator, thereby reducing phase noise by including a time base circuit based on a series inductor-capacitor resonant circuit (LC resonant) within the broadband feedback loop. The LC resonant-based time base circuit has a variable resonant frequency, which is adjusted based on a phase or frequency error detected in the PLL circuit. The LC resonant-based time base circuit introduces a specific time delay. At the resonant frequency of the time base circuit, the output frequency of the PLL is controlled to maintain this specific time delay.

[0019] In the context of the present discussion, phase noise of a signal, such as a frequency reference signal, refers to the spectral components near the desired frequency of a particular signal. Those skilled in the art will readily understand phase noise and generally consider it an unwanted component of the signal. In some cases, the phase noise of the generated signal is influenced by and can be reduced by characteristics of a feedback circuit that controls the operation of one or more oscillators generating the particular signal.

[0020] Figure 1 A phase-locked loop (PLL) circuit 100 with wideband feedback is illustrated according to an example. The illustrated PLL circuit 100 with wideband feedback depicts a high-level block diagram of a PLL oscillator incorporating a wideband feedback loop 106 and components for improving its phase noise performance. The illustrated PLL circuit 100 with wideband feedback is an example of a signal generator. Various PLL architectures can be utilized in various embodiments of the PLL circuit 100 with wideband feedback. In various embodiments of the PLL circuit 100 with wideband feedback, designs incorporating techniques such as analog or digital circuitry, integer or fractional division of the feedback signal, and combinations thereof, can be incorporated.

[0021] A PLL circuit 100 with broadband feedback generates an output signal 104, the frequency of which is set by the configuration of the components shown for the PLL circuit 100 with broadband feedback. In the illustrated example, the frequency of the output signal 104 is determined by a reference frequency (F). ref The reference frequency signal 102 is controlled by a suitable reference familiar to those skilled in the art.

[0022] The PLL circuit 100 with broadband feedback includes a variable frequency oscillator circuit 110 that generates an output signal 104 at a frequency controlled by a frequency control input signal 138. The variable frequency oscillator circuit 110 is an example of a controlled oscillator circuit and is used to change the frequency of the output signal 104 based on the input received as the frequency control input signal 138. The process performed by the components of the PLL circuit 100 with broadband feedback to generate the frequency control input signal 138 is described in more detail below. In various examples, the variable frequency oscillator circuit 110 can be implemented as a voltage-controlled oscillator (VCO) based on a parallel LC resonant circuit, a voltage-controlled ring oscillator, a current-controlled ring oscillator, other designs, or combinations thereof.

[0023] The output signal 104 generated by the variable frequency oscillator circuit 110 of the PLL circuit 100 with broadband feedback is provided to two feedback loops. The output signal 104 is provided to the frequency divider circuit 112 and the tunable LC time base circuit 120. The operation of these two feedback loops is described below.

[0024] Frequency divider circuit 112 generates the divided output signal 108 by dividing the frequency of output signal 104 by a value used to generate the divided output signal 108. In the illustrated example, frequency divider circuit 112 is configured to divide the frequency of output signal 104 by a value to obtain the same frequency as the reference frequency signal 102, so as to allow comparison of the divided output signal 108 with the reference frequency signal 102, thereby appropriately controlling the frequency of output signal 104, as described below. In various examples, frequency divider circuit 112 is configured to divide the frequency of output signal 104 by a value that can include an integer value, a fractional value (in the case of a fractional-N frequency divider circuit, the fractional value can be a non-integer value less than or greater than one (1)), or any combination of these.

[0025] A reference frequency signal 102 and a divided output signal 108 are provided to a phase frequency detector circuit 114. The phase frequency detector circuit 114 generates an error signal 130 indicating the phase or frequency error between the reference frequency signal 102 and the divided output signal 108. In this example, the error signal 130 may have an amplitude, such as voltage, current, digital data, other indicators, or a combination thereof, to indicate the phase or frequency difference between the reference frequency signal 102 and the divided output signal 108.

[0026] Error signal 130 is filtered by phase-locked loop (PLL) filter circuit 116 to generate filtered error signal 132. Typically, PLL filter circuit 116 is a low-pass filter used to adjust the frequency-divided output signal 108 to generate filtered error signal 132 with time response characteristics suitable for appropriately controlling the frequency of output signal 104 according to various design criteria.

[0027] A tunable LC time reference circuit 120 is used to generate a time reference signal 134. The tunable LC time reference circuit 120 receives an output signal 104. The output signal 104 drives a series LC resonant circuit within the tunable LC time reference circuit 120 to generate the time reference signal 134. The operation of the tunable LC time reference circuit 120 delays the time reference signal 134 based on a combination of the frequency of the output signal 104 and the values ​​of the inductor and capacitor connected in series in the series LC resonant circuit. In this example, the values ​​of one or more components in the series LC resonant circuit within the tunable LC time reference circuit 120, and therefore the resonant frequency of the series LC resonant circuit, vary based on a low-pass filtered error signal 132. An example of the tunable LC time reference circuit 120 is described below. In the example, the series LC resonant circuit within the tunable LC time reference circuit 120 introduces a defined time delay at the resonant frequency of the series LC resonant circuit (in the example, the defined time delay is a 90-degree phase shift of the output signal 104), and introduces other phase shifts at frequencies different from the resonant frequency of the series LC resonant circuit.

[0028] Time reference signal 134 and output signal 104 are provided to time error detector circuit 122. Time error detector circuit 122 determines a time error signal 136 between time reference signal 134 and output signal 104. In this example, the time error signal is proportional to the phase difference between output signal 104 and time reference signal 134, which is offset by ninety degrees (90°). This operation minimizes the time error signal when the frequency of output signal 104 is equal to the resonant frequency of the series LC resonant circuit within the tunable LC time reference circuit 120, i.e., when the frequency shift introduced by the LC resonant circuit is ninety degrees (90°).

[0029] The time error signal 136 is filtered by the oscillator filter 124 to generate a frequency control input signal 138, which controls the frequency of the output signal 104 generated by the variable frequency oscillator circuit 110.

[0030] Figure 2 An example tunable LC time reference circuit 200 is shown according to an example. The example tunable LC time reference circuit 200 depicts an example circuit for implementing the aforementioned tunable LC time reference circuit 120. The example tunable LC time reference circuit 200 forms a series LC resonant circuit, which is driven by the aforementioned output signal 104 and generates a time reference signal 134 delayed based on the frequency of the output signal 104. In other examples, the LC resonant circuit is driven by a signal derived from the output signal 104, such as a signal whose frequency is equal to the frequency of the output signal 104 divided by a value that is constant in this example.

[0031] The illustrated example of a tunable LC time base circuit 200 includes an inductor 206 arranged in series as a circuit 208, a series resistor 204 representing the parasitic resistance of the inductor 206, and a variable capacitor 202. The series circuit 208 includes the inductor and capacitor connected in series. These components in the series circuit 208 are selected to have a desired resonant frequency corresponding to a desired frequency of the time base signal 134.

[0032] The series circuit 208 is driven by the inverting amplifier circuit 210. In the example shown, the inverting amplifier circuit 210 is a hard-limited amplifier that generates a square wave at its amplifier output 212. Typically, the configuration of the series circuit 208 and the inverting amplifier circuit 210 produces a substantially square-wave voltage (V) across the series circuit 208. IN V Furthermore, the operation of the series circuit 208 causes a sinusoidal current to flow through the series circuit 208, thus generating a sinusoidal voltage (V) across the capacitor 202. LC The voltage across capacitor 202 is the output of the tunable LC time reference circuit 200 and is generated as the time reference signal 134. In other examples, the LC resonant circuit is driven by a signal derived from the output signal 104, such as a signal whose frequency is equal to the frequency of the output signal 104 divided by a value that can be constant. Clearly, the frequency of the output signal 104 or other signal driving the LC resonant circuit is the basis for the frequency of the time reference signal 134.

[0033] The illustrated example of a tunable LC time reference circuit 200 includes a variable capacitor 202 with a capacitance value controlled by the aforementioned filtered error signal 132. In this example, the variable capacitor can be a variable reactor, referred to as a varactor diode, with a capacitance value based on the voltage across its terminals. In this example, the circuit system (not shown) generates a voltage across the variable capacitor 202 proportional to the filtered error signal 132. The filtered error signal 132 controls the value of the variable capacitor 202, thereby changing the frequency of the time reference signal 134. Therefore, the filtered error signal 132 is a fundamental part of the frequency of the time reference signal 134.

[0034] The example tunable LC time reference circuit 200 shown uses a series arrangement of inductive (L) components such as inductor 206 and capacitive (C) components such as variable capacitor 202 to form a series LC resonant circuit. It has been found that combining this tunable LC time reference circuit using a series LC connection with the aforementioned PLL 100 with broadband feedback improves phase noise performance compared to a tunable LC time reference circuit 120 using inductive and capacitive components connected in parallel.

[0035] Figure 3A first example PLL 300 with broadband feedback is shown according to an example. The first example PLL 300 with broadband feedback illustrates an example of a circuit for implementing a version of the PLL circuit 100 with broadband feedback described above. The first example PLL 300 with broadband feedback includes a first example broadband feedback loop 306 with a first example time error detector circuit 308.

[0036] The first example PLL 300 with broadband feedback includes the aforementioned elements of the first example PLL circuit 100 with broadband feedback. Specifically, the elements including the aforementioned variable frequency oscillator circuit 110, frequency divider circuit 112, phase frequency detector circuit 114, and PLL filter circuit 116 operate as described above and generate their respective signals as described above. The first example PLL 300 with broadband feedback includes a first example broadband feedback loop 306, as an example of an embodiment of the aforementioned broadband feedback loop 106, which has a first example time error detector circuit 308. The elements and operation of the first example broadband feedback loop 306 are described below. As described below, the first example broadband feedback loop 306 includes components for supporting the operation of the first example time error detector circuit 308.

[0037] The first example broadband feedback loop 306 includes an N-division-by-N (÷ N) circuit 310 that receives the output signal 104 and is used to divide the frequency of the output signal 104 by the number "N". In this example, the frequency of the output signal 104 is divided by the N-division circuit 310 so that the elements of the first example broadband feedback loop 306 (e.g., the tunable LC time reference circuit 120) can be designed to operate and thus optimized for frequencies different from the frequency of the output signal 104. In various examples, N can be an integer or a decimal number to be divided by the frequency of the output signal 104. The N-division circuit 310 generates a feedback signal 330 consisting of a signal whose frequency is equal to the frequency of the output signal 104 divided by "N".

[0038] The feedback signal 330 is amplified by the feedback amplifier circuit 312 to adjust the feedback signal 330 and generate a first amplified feedback signal 332 as the input to the tunable LC time base circuit 120. An example of the tunable LC time base circuit 120 has been described above with respect to the example tunable LC time base circuit 200.

[0039] A tunable LC time reference circuit 120 generates a first time reference signal 334. The tunable LC time reference circuit 120 introduces a time delay between the first amplified feedback signal 332 and the first time reference signal 334, the time delay being based on the frequency of the amplified feedback signal related to the resonant frequency of the LC resonant circuit within the tunable LC time reference circuit 120. In the illustrated example, the tunable LC time reference circuit 120 generates the first time reference signal 334, which has a 90-degree (90°) phase shift from its input (i.e., the first amplified feedback signal 332) when the frequency of the first amplified feedback signal 332 is at the resonant frequency of the LC resonant circuit.

[0040] A first time reference signal 334 is provided to a voltage comparator circuit 320, which in some examples generates a square wave first time reference signal 336 at the frequency of the first time reference signal 334. The square wave first time reference signal 336 is an example of an adjusted time reference signal and is amplified by a time reference amplifier circuit 324 to generate an amplified time reference signal 342. In this specification, a square wave refers to any signal in which a transition across a value (e.g., zero) is used to convey information, and in some examples, such a square wave signal can have a slew rate within a specified minimum slew rate value, a maximum slew rate value, or both minimum and maximum slew rate values. In this example, the time reference amplifier circuit 324 is a hard-limited amplifier that generates a two-level signal. The amplified time reference signal 342 is provided to the first input of the time comparator circuit 326.

[0041] The feedback signal 330 is returned to the reference feedback signal 330, which is amplified by the second feedback signal amplifier circuit 322 to generate a second amplified feedback signal 340. In this example, the second feedback signal amplifier circuit 322 is a hard-limited amplifier that generates a two-level signal. The second amplified feedback signal 340 is provided as a second input to the time comparator circuit 326.

[0042] Time comparator circuit 326 compares two inputs, namely, the amplified time reference signal 342 and the second amplified feedback signal 340, to generate a time error signal 136. The time comparison performed by time comparator circuit 326 is equivalent to phase difference detection for a given signal frequency (e.g., the frequencies of the second amplified feedback signal 340 and the amplified time reference signal 342). Time error signal 136 indicates the time difference between the second amplified feedback signal 340 and the amplified time reference signal 342 introduced by the tunable LC time reference circuit 120. In this example, time comparator circuit 326 produces an output proportional to the phase difference between one of its inputs and the other input shifted by ninety degrees (90°). In this example, both the amplified time reference signal 342 and the second amplified feedback signal 340 are square wave signals, and time comparator circuit 326 is implemented as a mixer. In other examples, time comparator circuit 326 can be an exclusive-OR gate, other forms of analog multipliers, other circuits, or combinations thereof. The time error signal 136 is provided to the oscillator filter 124 to control the frequency of the variable frequency oscillator circuit 110, as described above with respect to the PLL circuit 100 with broadband feedback.

[0043] Figure 4 A second example PLL 400 with broadband feedback is shown according to the example. The second example PLL 400 with broadband feedback illustrates an example of a circuit for implementing a version of the PLL circuit 100 with broadband feedback described above. The second example PLL 400 with broadband feedback includes a second example broadband feedback loop 406 with a second example time error detector circuit 408.

[0044] The second example PLL 400 with broadband feedback includes the aforementioned elements of the first example PLL circuit 100 with broadband feedback. Specifically, the elements including the aforementioned variable frequency oscillator circuit 110, frequency divider circuit 112, phase frequency detector circuit 114, and PLL filter circuit 116 operate as described above and generate their respective signals as described above. The second example PLL 400 with broadband feedback includes a second example broadband feedback loop 406, which is an example of an embodiment of the aforementioned broadband feedback loop 106, and has a second example time error detector circuit 408. The elements of the second example broadband feedback loop 406 and its operation are described below. As described below, the second example broadband feedback loop 406 includes components for supporting the operation of the second example time error detector circuit 408.

[0045] The second example wideband feedback loop 406 includes a phase-shifted N-dividend (÷ N) circuit 410 that receives the output signal 104 and is used to divide the frequency of the output signal 104 by the number "N". In this example, the frequency of the output signal 104 is divided by the phase-shifted N-dividend circuit 410 so that the elements of the second example wideband feedback loop 406 (e.g., the tunable LC time reference circuit 120) can be designed to operate for and thus optimized for frequencies different from the frequency of the output signal 104. In various examples, N can be an integer or a fractional number to be divided by the frequency of the output signal 104. When N is not an integer, the phase-shifted N-dividend circuit 410 dividing the frequency of the output signal 104 by this fractional number (i.e., a non-integer) is referred to as a fractional N-dividend circuit. The phase-shifted N-dividend circuit 410 generates an in-phase feedback signal 430 and a phase-shifted feedback signal 432 consisting of a signal whose frequency is equal to the frequency of the output signal 104 divided by "N". The phase-shifted feedback signal 432 is a copy of the in-phase feedback signal 430, but shifted by ninety degrees (90°). This ninety-degree (90°) phase shift is introduced to match the ninety-degree (90°) phase shift added by the time error capacitor 414.

[0046] The in-phase feedback signal 430 is amplified by the in-phase amplifier 412 to adjust the in-phase feedback signal 430 into an amplified in-phase feedback signal 431, which is used as the input to the tunable LC time base circuit 120. An example of the tunable LC time base circuit 120 has been described above with respect to the example tunable LC time base circuit 200.

[0047] A tunable LC time reference circuit 120 generates a second time reference signal 434. The tunable LC time reference circuit 120 introduces a time delay between the amplified in-phase feedback signal 431 and the second time reference signal 434, the time delay being based on the frequency of the amplified in-phase feedback signal 431, which is related to the resonant frequency of the LC resonant circuit within the tunable LC time reference circuit 120. In the illustrated example, the tunable LC time reference circuit 120 generates the second time reference signal 434, which has a 90-degree (90°) phase shift from its input (i.e., the amplified in-phase feedback signal 431) when the frequency of the amplified in-phase feedback signal 431 is at the resonant frequency of the LC resonant circuit.

[0048] A second time reference signal 434 is provided to a time error capacitor 414 connected in series with the current comparator circuit 420. In addition to the 90-degree phase shift introduced by the tunable LC time reference circuit 120, the time error capacitor 414 and the current comparator circuit 420 introduce another 90-degree phase shift, generating a buffered second time reference signal 436 at a frequency offset by 180 degrees from the amplified in-phase feedback signal 431. In some examples, the current comparator circuit 420 generates a square wave as the buffered second time reference signal 436.

[0049] The buffered second time reference signal 436 is amplified by the time reference amplifier circuit 424 to generate the amplified time reference signal 442. In this example, the time reference amplifier circuit 424 is a hard-limited amplifier that generates a two-level signal. The amplified time reference signal 442 is provided to the first input of the time comparator circuit 426.

[0050] Returning to the phase-shifted feedback signal 432, this signal is amplified by the inverting feedback signal amplifier circuit 422 to generate the inverted feedback signal 440. In this example, the inverting feedback signal amplifier circuit 422 is an example of an inverter circuit used as a hard-limiting amplifier to generate the inverted feedback signal 440, which is therefore a two-level signal offset by 180 degrees from the in-phase feedback signal 430. This 180-degree phase shift matches the phase shift of the amplified time reference signal 442 relative to the in-phase feedback signal 430. The inverted feedback signal 440 is provided as a second input to the time comparator circuit 426.

[0051] Time comparator circuit 426 compares two inputs, namely, the amplified time reference signal 442 and the inverted feedback signal 440, to generate a time error signal 136. The time comparison performed by time comparator circuit 426 is equivalent to phase difference detection for a given signal frequency (e.g., the frequencies of the inverted feedback signal 440 and the amplified time reference signal 442). Time error signal 136 indicates the time difference between the inverted feedback signal 440 and the amplified time reference signal 442, partially introduced by tunable LC time reference circuit 120. In this example, both the amplified time reference signal 442 and the inverted feedback signal 440 are square wave signals, and time comparator circuit 426 is implemented as a mixer. In other examples, time comparator circuit 426 can be an exclusive-OR gate, other forms of analog multipliers, other circuitry, or combinations thereof. The time error signal 136 is provided to the oscillator filter 124 to control the frequency of the variable frequency oscillator circuit 110, as described above with respect to the PLL circuit 100 with broadband feedback.

[0052] The first example PLL 300 with broadband feedback and the second example PLL 400 with broadband feedback described above are two (2) variations of the PLL circuit 100 with broadband feedback. Other variations of the PLL circuit 100 with broadband feedback described above can be implemented based on variations of the first example PLL 300 with broadband feedback and the second example PLL 400 with broadband feedback. For example, alternative designs can combine the time comparator circuit 326 or the time comparator circuit 426 and the oscillator filter 124 into a single circuit structure. In some examples, the tunable LC time reference circuit 120, the first example broadband feedback loop 306, the second example broadband feedback loop 406, or combinations thereof can be implemented as a differential structure or a single-ended circuit structure. In various examples, the oscillator filter 124 can be implemented by any suitable structure, such as active or passive circuitry, proportional control operation, integral control operation, or any combination thereof.

[0053] Figure 5 The process 500 for generating a signal is illustrated according to an example. As described above, the process 500 for generating a signal is performed by any one of a PLL circuit 100 with wideband feedback, a first example PLL 300 with wideband feedback, or a second example PLL 400 with wideband feedback.

[0054] The process 500 for generating the signal generates an output signal at 502 with an output signal frequency based on the control input signal. In this example, the output signal is generated by the aforementioned variable frequency oscillator circuit 110.

[0055] At 504, the generated frequency is equal to the output signal frequency divided by a value representing the divided output. In this example, the divided output is generated by the frequency divider circuit 112 described above. In some examples, the value of dividing the output signal frequency by this value can be a constant.

[0056] At position 506, a phase error signal is generated based on the phase difference between the divided output and the frequency reference signal. In this example, the phase error signal is generated by the phase frequency detector circuit 114 described above.

[0057] At position 508, the phase error signal is low-pass filtered. In this example, the low-pass filtering of the phase error signal is performed by the aforementioned PLL filter circuit 116.

[0058] At position 510, a time base signal is generated based on a tunable LC time base circuit controlled by a low-pass filtered error signal. The frequency of the time base signal is controlled by the low-pass filtered error signal, and the tunable LC time base circuit receives the output signal.

[0059] At point 512, a filtered time error signal indicating the time difference between the output signal and the time reference signal is determined. The control input signal discussed above regarding the generation of the output signal with an output signal frequency based on the control input signal at point 502 is based on this filtered time error signal. Then, the process for generating the signal at point 500 ends.

[0060] In this example, signal generator 100 includes a controlled oscillator circuit 110 configured to generate an output signal 104 having a frequency based on an output signal frequency of a control input signal 138. The signal generator also includes a frequency divider circuit 112 configured to generate a divided output 108 with a frequency equal to the output signal frequency divided by a value. The signal generator further includes a phase frequency detector circuit 114 configured to generate a phase error signal 130 based on the phase difference between the divided output and a frequency reference signal 102. The signal generator also has a phase-locked loop (PLL) filter circuit 116 configured to generate a low-pass filtered error signal 132 at a frequency based on a low-pass filter applied to the phase error signal. The signal generator has a tunable LC time reference circuit 120 including an LC resonant circuit 208 having a resonant frequency based on the low-pass filtered error signal. This tunable LC time reference circuit is configured to receive the output signal, generate a time reference signal 134, and introduce a determined time delay relative to the output signal when the output signal frequency is at the resonant frequency. The signal generator also includes a time error detector circuit 122, which is configured to determine a filtered time error signal 136 indicating the time error between the output signal and the time reference signal, wherein the control input signal is based on the filtered time error signal 138.

[0061] In another example, the signal generation method 500 includes generating 502 an output signal 104 having a frequency based on the output signal frequency of the control input signal 138, generating 504 a divided output 108 with a frequency equal to the output signal frequency divided by a value, generating 506 a phase error signal 130 based on the phase difference between the divided output and the frequency reference signal 102, and low-pass filtering 508 on the phase error signal to generate a filtered error signal 132. The method further includes generating 510 a time reference signal 134 based on the output signal, wherein the time reference signal is generated by a tunable LC time reference circuit 208 having a resonant frequency based on the low-pass filtered error signal, and wherein the time reference signal has a defined time delay relative to the output signal when the output signal frequency is at the resonant frequency. The method further includes determining 512 a filtered time error signal 138 indicating the time error between the output signal and the time reference signal, wherein the control input signal is based on the filtered time error signal.

[0062] As used herein, the term "coupling" is defined as "connection" and covers the coupling of devices that can be physically, electrically, or communicatively connected, but said coupling may not necessarily be direct or mechanical. The term "configured to" describes hardware, software, or a combination of hardware and software that is suitable for, set up, arranged, constructed, constituted, designed, or has any combination of these characteristics to perform a given function. The term "suitable for" describes hardware, software, or a combination of hardware and software that is capable of, able to adapt to, perform, or appropriate for performing a given function.

[0063] As used herein, the terms “a (a)” or “an (an)” are defined as one or more. Furthermore, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed as implying that any particular claim containing such an element is limited to embodiments of the invention containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a (a)” or “an (an)”. The same applies to the use of definite articles. Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate temporal or other priorities of such elements. As used herein, the term “coupled” is not intended to be limited to direct or mechanical coupling, and one or more additional elements may be inserted between the two coupled elements.

[0064] As those skilled in the art will understand, aspects of this disclosure may be embodied as systems, methods, or computer program products. Therefore, aspects of this disclosure may be in the form of entirely hardware embodiments, entirely software embodiments (including firmware, resident software, microcode, etc.), or embodiments combining software and hardware aspects (which may generally be referred to herein in their entirety as "circuit" or "system").

[0065] One or more embodiments of the present invention may be a system, method, and / or computer program product. A computer program product may include one or more computer-readable storage media having computer-readable program instructions thereon to cause a processor to perform aspects of embodiments of the present invention.

[0066] In one embodiment, a computer program product includes a non-transitory storage medium that is readable by processing circuitry and stores instructions executable by the processing circuitry to perform a method. The computer-readable storage medium can be a tangible means capable of holding and storing instructions for use by an instruction execution device. The computer-readable storage medium can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed as a transient signal, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0067] Computer-readable program instructions used to perform the operations of embodiments of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages. Programming languages ​​include object-oriented programming languages ​​such as Smalltalk and C++, as well as traditional procedural programming languages ​​such as the "C" programming language or similar languages. The computer-readable program instructions may be executed entirely or partially on a user's computer, or entirely or partially on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including local area networks (LANs), wide area networks (WANs), and ultra-wideband (UWB) networks, or may be connected to an external computer (e.g., via the Internet). In some embodiments, an electronic circuit system including, for example, a programmable logic circuit system, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions by personalizing the electronic circuit system using state information from the computer-readable program instructions, in order to perform aspects of embodiments of the present invention.

[0068] Aspects of one or more embodiments of the present invention have been described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. Each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, may be implemented by computer-readable program instructions.

[0069] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer, create components for implementing the functions / actions specified in the boxes of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that directs a computer to function in a particular manner, such that the computer-readable storage medium storing the instructions includes an article of writing comprising instructions for implementing aspects of the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0070] The description of this disclosure has been presented for purposes of illustration and description, but it is not intended to be exhaustive or limited to embodiments of the invention in the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments of the invention. One or more embodiments were chosen and described to explain the principles of the subject matter of the invention and its practical application, and to enable those skilled in the art to understand the subject matter of the invention in combination with various modifications suitable for the particular purpose contemplated.

[0071] Although specific embodiments of the invention have been disclosed, those skilled in the art will understand that changes can be made to the specific embodiments without departing from the spirit and scope of the invention. Therefore, the scope of the invention is not limited to the specific embodiments described, and the appended claims are intended to cover any and all such applications, modifications, and embodiments within the scope of the invention.

Claims

1. A signal generator, characterized in that, include: A controlled oscillator circuit, configured to generate an output signal having an output signal frequency based on a control input signal; A frequency divider circuit is configured to produce a frequency-divided output equal to the frequency of the output signal divided by a value. A phase frequency detector circuit is configured to generate a phase error signal based on the phase difference between the divided output and the frequency reference signal; A phase-locked loop (PLL) filter circuit is configured to generate a low-pass filtered error signal at a frequency based on a low-pass filtered phase error signal. A tunable LC time reference circuit includes an LC resonant circuit having a resonant frequency based on the low-pass filtered error signal, the tunable LC time reference circuit being configured to receive the output signal, generate a time reference signal, and introduce a determined time delay relative to the output signal when the frequency of the output signal is at the resonant frequency. as well as A time error detector circuit is configured to determine a filtered time error signal indicating the time error between the output signal and the time reference signal. The control input signal is based on a filtered time error signal.

2. The signal generator according to claim 1, characterized in that, In addition, including: A phase-shifted N-dividend circuit is configured to receive the output signal and generate both an in-phase feedback signal and a phase-shifted feedback signal. The in-phase feedback signal and the phase-shifted feedback signal have frequencies equal to the output signal frequency divided by a value, and The phase-shifted feedback signal is offset by ninety degrees from the in-phase feedback signal. The time error detector circuit includes: A current comparator circuit is configured to receive the time base signal and generate an adjusted time base signal; as well as A time comparator circuit is configured to determine a time error signal based on the time difference between the adjusted time reference signal and the phase-shifted feedback signal, wherein the filtered time error signal is based on the time error signal.

3. The signal generator according to claim 2, characterized in that, The phase-shift N-dividend circuit includes a fractional N-dividend circuit.

4. The signal generator according to claim 2, characterized in that, The phase-shift N-dividend circuit includes an integer N-dividend circuit.

5. The signal generator according to claim 1, characterized in that, In addition, including: An N-division circuit is configured to receive the output signal and generate a feedback signal, wherein the feedback signal has a frequency equal to the frequency of the output signal divided by a value, and The time error detector circuit includes: A voltage comparator circuit is configured to receive the time reference signal and generate an adjusted time reference signal; as well as A time comparator circuit is configured to determine a time error signal based on the time difference between the adjusted time reference signal and the feedback signal, wherein the filtered time error signal is based on the time error signal.

6. The signal generator according to claim 5, characterized in that, The tunable LC time reference circuit causes a 90-degree phase shift between the output signal and the time reference signal, and The time error detector circuit further includes: A time error capacitor, configured to receive the time reference signal and couple the tunable LC time reference circuit to a current comparator circuit; and An inverter circuit is configured to invert the feedback signal and provide the inverted feedback signal to the time comparator circuit.

7. A method for generating a signal, characterized in that, include: Generate an output signal with an output signal frequency based on the control input signal; The frequency of the output signal is equal to the frequency of the output signal divided by a value, resulting in a frequency-divided output. A phase error signal is generated based on the phase difference between the frequency-divided output and the frequency reference signal; The phase error signal is low-pass filtered to generate a low-pass filtered error signal; A time reference signal is generated based on the output signal, wherein the time reference signal is generated by a tunable LC time reference circuit having a resonant frequency based on the low-pass filtered error signal, and wherein the time reference signal has a defined time delay relative to the output signal when the output signal frequency is at the resonant frequency; and Determine a filtered time error signal that indicates the time error between the output signal and the time reference signal. The control input signal is based on a filtered time error signal.

8. The method according to claim 7, characterized in that, In addition, including: Based on the output signal, an in-phase feedback signal and a phase-shifted feedback signal are generated. The in-phase feedback signal and the phase-shifted feedback signal have frequencies equal to the output signal frequency divided by a value, and The phase-shifted feedback signal is offset by ninety degrees from the in-phase feedback signal; An adjusted time base signal is generated based on the aforementioned time base signal; as well as A time error signal is determined based on the time difference between the adjusted time reference signal and the phase-shifted feedback signal, wherein the filtered time error signal is based on the time error signal.

9. The method according to claim 8, characterized in that, The values ​​include decimals.

10. The method according to claim 7, characterized in that, In addition, including: A feedback signal is generated based on the output signal, wherein the feedback signal has a frequency equal to the frequency of the output signal divided by a value, and An adjusted time base signal is generated based on the aforementioned time base signal; as well as A time error signal is determined based on the time difference between the adjusted time reference signal and the feedback signal, wherein the filtered time error signal is based on the time error signal.

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