Single-channel analog-to-digital converter calibration system based on memory-aware grey-box neural networks

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to a single-channel analog-to-digital converter calibration system based on a memory-aware gray-box neural network. The calibration system adopts a double-layer dynamic gray-box neural network architecture, which comprises: an input layer, which is used for receiving digital output codes of an analog-to-digital converter and performing bit weight-related scaling processing; a recursive storage layer, which is used for storing output information of the analog-to-digital converter at a previous moment; a hidden processing module, which adopts a rectified linear unit as an activation function to perform nonlinear transformation on the input information; and an output layer module, which adopts a multipath data selector to replace a multiplier to generate a calibrated digital output signal. The application can realize efficient collaborative compensation of nonlinear characteristics and memory effects of the analog-to-digital converter, and significantly reduce the calculation complexity and power consumption of the calibration circuit. While ensuring calibration accuracy, the application has the characteristics of fast convergence speed and low hardware overhead.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a single-channel analog-to-digital converter calibration system based on a memory-aware gray-box neural network. Background Technology

[0002] With the development of mixed-signal circuits, the performance of analog-to-digital converters (ADCs) has been significantly improved. However, in practical applications, their non-ideal effects still significantly affect system performance and reliability. For example, due to manufacturing limitations and mismatches in circuit design, ADCs often suffer from gain errors, bias errors, and nonlinear distortion. These errors not only reduce conversion accuracy but can also lead to high-frequency signal distortion, thus affecting the effectiveness of the entire system. Therefore, to achieve such high-performance designs in advanced technologies, digital calibration techniques are used to overcome various technical defects, such as mismatch, nonlinearity, and parasitic effects. For example, instead of increasing the power of the margin amplifier to improve its linearity, a better solution might be to save amplifier power and correct it through digital calibration. As technology scales up, digital processing often becomes more efficient, while improvements in analog performance are limited. By accurately detecting and compensating for ADC errors, calibration techniques can effectively improve ADC performance and extend the boundaries of its application scenarios. The significance of calibration lies not only in overcoming limitations in hardware design but also in providing an important guarantee for the realization of high-speed, high-precision signal processing.

[0003] Current mainstream research on digital calibration still focuses on model-based calibration strategies. For example, adding digital logic after the analog-to-digital converter (ADC) output enables the chip to successfully compensate for errors caused by capacitor mismatch, comparator offset, charge injection, finite operational amplifier gain, and capacitor nonlinearity. Since this calibration is performed only in the digital domain, the ADC no longer requires additional clock cycles and analog circuitry for calibration assistance. However, with increasing performance, technological advancements, and circuit complexity, the types and complexity of calibrations are also increasing. Existing calibration compensation methods largely rely on modeled error models and numerical optimization algorithms. When the modeling is inadequate or unpredictable distortions occur, calibration may experience convergence difficulties or false convergence. Furthermore, in the calibration of high-precision ADCs, existing polynomial-based error compensation formulas suffer from poor fitting and incomplete calibration when multiple distortions are mixed.

[0004] In recent years, with the revolutionary success of artificial intelligence, especially deep learning technology, in fields such as image and speech recognition, its powerful nonlinear mapping and feature extraction capabilities have attracted great attention from researchers in the field of analog-to-digital converter (ADC) calibration. Preliminary studies show that even relatively shallow neural networks can potentially outperform complex traditional linear calibrators in terms of calibration effectiveness. However, current research in this area is still in its early exploratory stages and has significant shortcomings: most neural network circuits cannot calibrate the dynamic errors in high-speed ADCs and cannot simultaneously achieve both high calibration performance and low hardware cost. This invention employs a two-layer dynamic gray-box neural network architecture. The input layer introduces a bit-weighted scaling mechanism and adds a recursive layer to store temporal dynamic information, achieving efficient synergistic compensation for the nonlinear characteristics and memory effects of the ADC. The output layer uses a multiplexer instead of a traditional multiplier. This allows the calibration scheme to maintain calibration accuracy while also featuring fast convergence speed and low hardware overhead. Summary of the Invention

[0005] The purpose of this invention is to propose an analog-to-digital converter (ADC) calibration system based on a memory-aware gray-box neural network, in order to solve the problem that traditional ADC calibration techniques are unable to effectively compensate for dynamic memory effects and nonlinear errors.

[0006] The single-channel analog-to-digital converter calibration system based on a memory-aware gray-box neural network provided by this invention includes:

[0007] The input layer module is used to receive the digital output code from the analog-to-digital converter and perform bit-weight-related scaling processing.

[0008] The recursive storage layer module is used to store the analog-to-digital converter output information from the previous moment.

[0009] The hidden processing module uses rectified linear units as activation functions to perform nonlinear transformations on the input information;

[0010] The output layer module uses a multiplexer instead of a multiplier to generate a calibrated digital output signal.

[0011] Furthermore:

[0012] The input layer module includes a bit-weight scaling operator. This scaling operator assigns scaling coefficients based on the bit weights of the analog-to-digital converter (ADC) output code, satisfying the relationship: the weight of the i-th input neuron in the input layer is equal to 2 raised to the power of (iN), where N is the total number of bits. This design fully utilizes the inherent characteristics of the ADC's binary output, directly embedding bit-weight information into the neural network input layer, avoiding additional weight training overhead.

[0013] The recursive storage module is configured to store all historical codewords and input neuron values, and weights the historical information using a configurable scaling factor. Traditional feedforward neural networks can only process the current input and cannot compensate for dynamic memory effects introduced by charge residue, finite setup time, etc. This invention introduces historical information through a recursive storage module, which can adaptively compensate for nonlinear errors and historical correlation interference introduced by the dynamic memory effects of analog-to-digital converters (such as charge residue, finite setup time), significantly improving the calibration effect.

[0014] The hidden processing module uses a rectified linear unit (CLU) as the activation function to perform a nonlinear transformation on the input information. Its operation is as follows: for an input value greater than zero, the output is unchanged; for an input value less than or equal to zero, the output is zero, thus achieving efficient nonlinear mapping. Compared to traditional Sigmoid or Tanh functions, the CLU has the advantages of simple computation and unsaturated gradients, making it more suitable for hardware implementation.

[0015] The weights of the output layer module are binary weights, with values ​​of only +1 or -1. The multiplexer selects the corresponding hidden layer output for accumulation based on the weight value. Specifically, when the sign is positive (+1), the corresponding hidden layer output value is passed directly; when the sign is negative (-1), a built-in inversion path is selected to invert the corresponding value before passing it. All results passing through the selector are then sent to the adder for accumulation, thus efficiently completing the multiplication and accumulation calculation of the output layer. This innovative design completely avoids the use of multipliers in traditional neural networks, significantly reducing hardware complexity and power consumption, while the binary weights also simplify the parameter update process.

[0016] Based on the above calibration system, the present invention also provides a single-channel analog-to-digital converter calibration method, the specific steps of which are as follows:

[0017] Step 1: Receive the current digital code output by the analog-to-digital converter;

[0018] Step 2: Perform bit weight scaling on the current digital code. Specifically, scale the input according to the weight of each bit: For each bit of the N-bit original binary code (usually in two's complement or offset binary form) output by the analog-to-digital converter, scale it according to its physical bit weight in the analog-to-digital converter (the highest bit corresponds to a weight of 2). N-1 The lowest bit corresponds to a weight of 2. 0 ), through scaling factor 2 i-N (where i is the bit index, from 1 to N, i=1 represents the most significant bit, and i=N represents the least significant bit) Perform a linear transformation to convert the discrete logic value (0 or 1) of each bit into a real value distributed in the interval [-1, 1].

[0019] Step 3: Read the digital code information of the previous moment stored in the recursive storage module, and weight the historical information through a configurable scaling factor to compensate for the dynamic memory effect;

[0020] Step 4: Input the processed current code and historical code into the hidden processing module, and perform nonlinear mapping through the rectified linear unit to extract high-order nonlinear features;

[0021] Step 5: Use a multiplexer to perform weighted selection on the hidden layer output, and select the original value or the inverted value according to the sign of the binarized weights for accumulation to generate the calibration result;

[0022] Step Six: Update the neural network parameters based on the calibration error to complete adaptive calibration. Specifically, after each calibration output, the calibration result generated by the neural network is compared with the currently desired ideal target signal, and the difference between the two is calculated, i.e., the calibration error. Subsequently, this error is propagated layer by layer to each neuron in the network through the backpropagation algorithm, and the contribution of each weight and bias parameter in the output layer, hidden layer, and recursive storage layer to the total error is calculated. Based on this, the gradient descent optimization method is used to update the parameters of each layer according to the set learning rate: parameters with positive contributions are appropriately decreased, and parameters with negative contributions are appropriately increased, so that the calibration output of the network gradually approaches the ideal target signal, thereby completing adaptive calibration.

[0023] Optionally, the calibration method supports a feedforward calibration mode, where the target signal is obtained through a sine curve fitting method. Specifically, during the training phase, a pure sine signal is input to the analog-to-digital converter, and the output code is fitted with a sine curve, with the fitted value used as the ideal target signal.

[0024] The parameter update described in step six uses the gradient descent algorithm, which calculates the mean square error between the calibration output and the target signal, and then backpropagates to update the weights and bias parameters.

[0025] The beneficial effects of this invention are as follows:

[0026] Memory perception capability: By introducing historical information through a recursive storage module, it can effectively compensate for the dynamic memory effect of the analog-to-digital converter, such as nonlinear errors introduced by charge residue and finite settling time, which is something that traditional static calibration methods cannot achieve.

[0027] Gray-box neural network architecture: Integrating prior knowledge of the bit weights of the analog-to-digital converter into the input layer design not only preserves the adaptive ability of the neural network, but also reduces the number of parameters that need to be trained, thus accelerating the convergence speed.

[0028] Multiplier-free design: The output layer uses binarized weights and multiplexers to replace traditional multipliers, which greatly reduces hardware resource consumption and power consumption while maintaining computational accuracy. It is particularly suitable for resource-constrained on-chip integration scenarios.

[0029] Adaptive calibration capability: By updating network parameters in real time through the gradient descent algorithm, it can track characteristic drift caused by factors such as temperature, voltage, and aging, and achieve long-term stable high-performance conversion.

[0030] Low hardware complexity: The rectifier linear unit activation function and recursive storage module have simple structures, are easy to implement with digital logic, have small overall circuit area and low power consumption, and are suitable for integration into analog-to-digital converter chips.

[0031] In summary, this invention proposes an analog-to-digital converter calibration scheme that integrates memory perception mechanism, gray-box prior knowledge, and hardware-friendly computation, achieving a good balance between compensation accuracy, adaptability, and hardware efficiency, and has significant engineering application value. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the memory-sensing gray box neural network structure of the present invention.

[0033] Figure 2 This is a schematic diagram of the hardware structure of a single neuron in a neural network.

[0034] Figure 3 This is a schematic diagram of the overall calibration architecture.

[0035] Figure 4 This is a schematic diagram illustrating the application of a calibration scheme to a split pipeline analog-to-digital converter. Detailed Implementation

[0036] The single-channel analog-to-digital converter calibration system based on a memory-aware gray-box neural network, as designed in this invention, will be further described below with reference to the accompanying drawings.

[0037] The overall structure of the single-channel analog-to-digital converter calibration system based on memory-aware gray-box neural network of the present invention is as follows: Figure 1 As shown, it comprises four core modules: an input layer module, a recursive storage module, a hidden processing module, and an output layer module. The input layer module is used to receive the digital code X output by the analog-to-digital converter. i And according to the weight W of each one i The system performs a scaling factor of S; a recursive storage module is used to save the output information of the analog-to-digital converter from the previous time step; the hidden processing module uses a rectified linear unit as the activation function f. act The input information undergoes a nonlinear transformation; the output layer module employs a multiplexer W. selInstead of a traditional multiplier, a calibrated digital output signal Y is generated. The recursive storage module is configured to store the output codewords of the analog-to-digital converter from the previous moment and weights this historical information using a configurable scaling factor. In high-speed analog-to-digital converters, dynamic error is a significant issue, potentially caused by factors such as capacitor dielectric relaxation, incomplete amplifier reset, and residual charge. These dynamic errors are correlated with historical input codewords and can be described by a weighted sum of historical codewords. The recursive storage module Z of this invention... -1 By storing historical information and assigning adjustable weights to it, the nonlinear errors and historical correlation interference introduced by the dynamic memory effect of the analog-to-digital converter can be adaptively compensated. Considering that the dynamic error accounts for a small proportion of the overall signal and is related to the code weight, the recursive storage module also adopts a bit-weight scaling mechanism to process historical codewords.

[0038] Figure 2 This demonstrates the hardware implementation structure of a single neuron in a neural network. Input weight W i First, the input code X is processed by a multiplexer, then a scaling operation of S times related to the bit weight is performed by a shift register. Finally, it passes through an accumulator and an activation function f. act After processing, a bias b is added, and the final output is determined by the multiplexer with respect to the output weight W. o The selection process is performed using only adders, multiplexers, and shift operations, completely avoiding the use of multipliers, thus significantly reducing hardware overhead and power consumption.

[0039] The input layer module includes a bit-weight scaling operator, which assigns different scaling factors based on the weight of each bit in the analog-to-digital converter (ADC) output code. For an N-bit ADC, the highest bit has the largest weight, and the lowest bit has the smallest weight. The scaling factor for the i-th neuron in the input layer is set to 2 to the power of (iN). This design is based on a deep understanding of the characteristics of ADCs: higher-order bits typically correspond to larger capacitances, resulting in more significant capacitance mismatches and a greater contribution to parasitic capacitance and memory effects. By introducing this bit-weight scaling mechanism, the neural network can more accurately approximate the error distribution characteristics of actual ADCs, thereby reducing network complexity while accelerating training convergence. The hidden processing module uses rectified linear units (RCUs) as the activation function. Its working mechanism is very simple and intuitive: for input values, if they are greater than zero, the output remains unchanged; if they are less than or equal to zero, the output is zero. Compared to traditional sigmoid or tanh functions, this activation function has advantages such as computational simplicity and gradient non-saturation, making it very suitable for hardware implementation and providing nonlinear fitting capabilities while maintaining low resource consumption. The output layer module employs an innovative binary weight design, where all weights take only two values: positive or negative. Based on the sign of the weight, a multiplexer selects the corresponding hidden layer output for accumulation: when the weight is positive, the corresponding hidden layer output value passes directly; when the weight is negative, the corresponding value is inverted via a built-in inversion path before passing. All results processed by the selector are then sent to an adder for accumulation, thus efficiently completing the multiplication and accumulation calculation of the output layer. This design completely eliminates the multipliers heavily used in traditional neural networks, achieving the same functionality solely through multiplexers and adders, significantly reducing hardware complexity and power consumption. Combined with a bit-weight scaling operator and binary output weights, the entire network can achieve efficient analog-to-digital converter calibration at extremely low hardware costs.

[0040] Figure 3 The overall front-end calibration architecture is demonstrated, and its operation is as follows: The analog input signal Vin first enters the analog-to-digital converter (ADC) to be calibrated, and after conversion, it generates the raw digital code X. This digital code is simultaneously sent to two processing paths: one is an ideal weighted combiner (IWC), which performs preliminary weighted combining processing on the raw code and outputs the weighted value Y. IWC The other approach is a memory-aware gray-box neural network, which uses its input layer, recursive storage layer, and hidden layers to perform non-linear calibration on the digital code, outputting a neural network correction value Y. NN Due to the inherent latency in neural network processing, a delay module is needed for time alignment. Then, the weighted processed value and the neural network correction value are added together to obtain the final calibrated output. Simultaneously, the sine-fit module receives the digital code output from the analog-to-digital converter and generates the ideal target signal Y by fitting a sine curve to a large number of sampling points. TargetUltimately, the difference between the calibration output and the target signal is used to train a memory-aware gray-box neural network. The network parameters are continuously updated using a gradient descent algorithm, gradually bringing the neural network output closer to the ideal value, thus achieving non-linear calibration of the analog-to-digital converter. Throughout the process, the neural network can directly correct the output of the analog-to-digital converter in real time after calibration.

[0041] Figure 4 This paper demonstrates the calibration verification of the present invention in a split pipelined successive approximation analog-to-digital converter (ADC). The ADC is split into two identical channels, each equipped with a neural network containing forward propagation and training modules. Due to the small dynamic error of this type of ADC, the recursive storage layer is omitted in this application. To ensure that the two split channels do not produce nonlinearities in the same way, a dither signal is injected in the analog domain. The neural network receives the output codeword D of the channel. A and D B As input, its output O A 2 and O B 2 This is superimposed onto an ideal weighted combiner to compensate for nonlinearity. The jitter subtraction module in the digital domain is responsible for removing injected jitter, generating the final channel output O. A and O B The difference Δ between the two channel outputs A and Δ B It is used to train neural networks in the background without interrupting the normal operation of the analog-to-digital converter during the entire training process.

[0042] While the contents and advantages of the present invention have been disclosed in detail above, it must be noted that the scope of the present invention is not limited to the specific embodiments such as the methods and steps described in the specification. Without departing from the spirit and scope of the present invention, any person skilled in the art can make many variations and modifications based on the contents disclosed in the present invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A calibration system for an analog-to-digital converter based on a memory-aware gray-box neural network, characterized in that, include: The input layer module is used to receive the digital output code from the analog-to-digital converter and perform bit-weight-related scaling processing. The recursive storage layer module is used to store the analog-to-digital converter output information from the previous moment. The hidden processing module uses rectified linear units as activation functions to perform nonlinear transformations on the input information; The output layer module uses a multiplexer instead of a multiplier to generate a calibrated digital output signal.

2. The analog-to-digital converter calibration circuit according to claim 1, characterized in that, The input layer module includes a bit-weight scaling operator. The scaling operator assigns scaling coefficients according to the bit weights of the analog-to-digital converter output code, satisfying the following relationship: the weight of the i-th input neuron in the input layer is equal to 2 to the power of (i - N), where N is the total number of bits.

3. The analog-to-digital converter calibration system according to claim 1, characterized in that, The recursive storage module is configured to store all historical codewords and input neuron values, and to weight the historical information using a configurable scaling factor, thereby adaptively compensating for nonlinear errors and historical correlation interference introduced by the dynamic memory effect of the analog-to-digital converter.

4. The analog-to-digital converter calibration system according to claim 1, characterized in that, The hidden processing module uses a rectified linear unit as the activation function to perform nonlinear transformation on the input information. Its working principle is: for the input value, if it is greater than zero, it outputs the original value; if it is less than or equal to zero, it outputs zero, thereby achieving nonlinear mapping.

5. The analog-to-digital converter calibration system according to claim 1, characterized in that, The weights of the output layer module are binary weights, with values ​​of only +1 or -1; the multi-channel data selector selects the corresponding hidden layer outputs for accumulation based on the weight values; When the sign is positive (+1), the corresponding hidden layer output value is selected and passed directly; when the sign is negative (-1), a built-in inversion path is selected to invert the corresponding value and pass it; all results passing through the selector are then sent to the adder for accumulation, thereby efficiently completing the multiplication and accumulation calculation of the output layer.

6. A calibration method for an analog-to-digital converter based on the calibration circuit according to any one of claims 1-5, characterized in that, The specific steps are as follows: Step 1: Receive the current digital code output by the analog-to-digital converter; Step 2: Perform bit-weight scaling on the current digital code. Specifically, scale the input according to the weight of each bit: For each bit of the N-bit original binary code output by the analog-to-digital converter, scale it using a scaling factor of 2 based on its physical bit weight in the converter. i-N A linear transformation is performed to convert each discrete logic value (0 or 1) into a real value distributed in the interval [-1, 1]; wherein, the physical bit weights, with the highest bit corresponding to a weight of 2. N-1 The lowest bit corresponds to a weight of 2. 0 The scaling factor 2 i-N , where i is the bit index, from 1 to N, i=1 represents the most significant bit, and i=N represents the least significant bit; Step 2: Perform bit weight scaling on the current digital code. Scale the input according to the weight 2^(iN) of each bit to convert the binary code into a numerical representation suitable for neural network processing. Step 3: Read the digital code information of the previous moment stored in the recursive storage module, and weight the historical information through a configurable scaling factor to compensate for the dynamic memory effect; Step 4: Input the processed current code and historical code into the hidden processing module, and perform nonlinear mapping through the rectified linear unit to extract high-order nonlinear features; Step 5: Use a multiplexer to perform weighted selection on the hidden layer output, and select the original value or the inverted value according to the sign of the binarized weights for accumulation to generate the calibration result; Step Six: After each calibration output, compare the calibration result generated by the neural network with the currently desired ideal target signal and calculate the difference between them, i.e., the calibration error. Then, propagate this error layer by layer to each neuron in the network through the backpropagation algorithm, and calculate the contribution of each weight and bias parameter in the output layer, hidden layer, and recursive storage layer to the total error. Based on this, the gradient descent optimization method is used to update the parameters of each layer according to the set learning rate: parameters with positive contributions are appropriately decreased, and parameters with negative contributions are appropriately increased, so that the calibration output of the network gradually approaches the ideal target signal, completing the adaptive calibration.

7. The calibration method according to claim 6, characterized in that, It supports a feedforward calibration mode, in which the target signal is obtained through a sine fitting method; specifically, during the training phase, a pure sine signal is input to the analog-to-digital converter, and the output code is fitted with a sine curve, with the fitted value used as the ideal target signal.

8. The calibration method according to claim 7, characterized in that, The parameter update described in step six uses the gradient descent algorithm, which calculates the mean square error between the calibration output and the target signal, and then backpropagates to update the weights and bias parameters.

Images