Address allocation method of distributed system, distributed system, device and medium

Abstract

The application discloses a kind of address allocation method of distributed system, distributed system, equipment and medium, it is related to distributed system technical field.Distributed system's main control device enters the addressing state by controlling the first slave control device, and sends first address allocation command to bus, to make the first slave control device update the address of itself in the addressing state in response to first address allocation command;Based on bus, the addressing control command is sent to the n-1th slave control device, to make the n-1th slave control device control the nth slave control device enters the addressing state, and sends the n address allocation command to bus, to make the nth slave control device update the address of itself in the addressing state in response to the n address allocation command;2≤n≤N, N≥2.The application realizes the automatic allocation of address to each slave control device, relative to traditional manual address allocation method, without human participation, not prone to human error, and improve address allocation efficiency.

Description

Technical Field

[0001] This application relates to the field of distributed system technology, and in particular to an address allocation method, distributed system, device and medium for a distributed system. Background Technology

[0002] Current energy storage systems generally adopt a distributed communication architecture, which can effectively achieve hierarchical management at the module and system levels. An energy storage system mainly consists of a master control device and multiple slave control devices, enabling the master control device to monitor the system's operating status in real time based on feedback information.

[0003] To enable communication between the master control device and multiple slave control devices, the master control device needs to assign addresses to each slave control device. The traditional address assignment method is to manually assign addresses to each slave control device through software configuration. The problems are that it requires a lot of manual intervention, the address assignment efficiency is low, and it is prone to human error. Summary of the Invention

[0004] This application provides a method for address allocation in a distributed system, a distributed system, a device, and a medium to solve the problems of traditional manual address allocation methods, which involve a lot of human intervention, are prone to human error, and have low address allocation efficiency.

[0005] In a first aspect, embodiments of this application provide an address allocation method for a distributed system, the method being executed by a master control device of the distributed system; wherein the distributed system includes a master control device and N slave control devices, N≥2; the master control device and the N slave control devices are connected in series, and the master control device and the N slave control devices are connected via a bus communication connection; the method includes:

[0006] The first slave device is controlled to enter the addressing state and a first address allocation command is sent to the bus so that the first slave device updates its own address in response to the first address allocation command in the addressing state.

[0007] Based on the bus, an addressing control command is sent to the (n-1)th slave device, so that the (n-1)th slave device controls the nth slave device to enter the addressing state, and an nth address allocation command is sent to the bus, so that the nth slave device responds to the nth address allocation command in the addressing state to update its own address; 2≤n≤N;

[0008] Wherein, the first address allocation command includes the address allocated by the master control device to the first slave control device, and the nth address allocation command includes the address allocated by the master control device to the nth slave control device.

[0009] In another aspect, embodiments of this application provide an address allocation method for a distributed system, wherein the method is executed by the nth slave device of the distributed system, where 2≤n≤N; wherein the distributed system includes a master device and N slave devices, where N≥2; the master device and the N slave devices are connected in series, and the master device and the N slave devices are connected via bus communication.

[0010] The method includes:

[0011] The device controls itself to enter the addressing state based on the addressing enable signal output by the (n-1)th slave device;

[0012] The master device receives an address allocation command sent to the bus and updates its own address in response to the address allocation command in the addressing state; the address allocation command includes the address allocated by the master device to the nth slave device.

[0013] Thirdly, embodiments of this application provide a distributed system comprising: a master control device and N slave control devices; N≥2; the master control device and the N slave control devices are connected in series, and the master control device and the N slave control devices are connected via a bus communication connection;

[0014] The master control device is used to control the first slave control device to enter the addressing state and send a first address allocation command to the bus, so that the first slave control device updates its own address in response to the first address allocation command in the addressing state;

[0015] The master control device is used to send an addressing control command to the (n-1)th slave control device via the bus, so that the (n-1)th slave control device controls the nth slave control device to enter the addressing state, and sends an nth address allocation command to the bus, so that the nth slave control device responds to the nth address allocation command in the addressing state to update its own address;

[0016] Wherein, the first address allocation command includes the address allocated by the master control device to the first slave control device, and the nth address allocation command includes the address allocated by the master control device to the nth slave control device; 2≤n≤N.

[0017] Fourthly, embodiments of this application provide an electronic device, the electronic device comprising:

[0018] At least one processor; and

[0019] A memory communicatively connected to the at least one processor; wherein,

[0020] The memory stores a computer program that is executed by the at least one processor, which causes the at least one processor to perform the address allocation method of the distributed system according to any embodiment of this application.

[0021] Fifthly, embodiments of this application provide a computer-readable storage medium storing computer instructions that, when executed by a processor, implement the address allocation method of the distributed system described in any embodiment of this application.

[0022] The technical solution of this application embodiment is applied to a distributed system, which includes a master control device and N slave control devices, where N≥2; the master control device and the N slave control devices are connected in series, and the master control device and the N slave control devices are connected via a bus for communication. The master control device of the distributed system controls the first slave control device to enter an addressing state and sends a first address allocation command to the bus, so that the first slave control device updates its own address in response to the first address allocation command in the addressing state; based on the bus, it sends an addressing control command to the (n-1)th slave control device, so that the (n-1)th slave control device controls the nth slave control device to enter an addressing state and sends an nth address allocation command to the bus, so that the nth slave control device updates its own address in response to the nth address allocation command in the addressing state; wherein, the first address allocation command includes the address assigned by the master control device to the first slave control device, and the nth address allocation command includes the address assigned by the master control device to the nth slave control device; 2≤n≤N. By sequentially controlling the serially connected slave devices to update their own addresses based on the address allocation commands transmitted via the bus in the addressing state, the automatic address allocation of each slave device is achieved. Compared with the traditional manual address allocation method, it does not require manual intervention, is less prone to human error, and improves the address allocation efficiency.

[0023] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A flowchart illustrating an address allocation method for a distributed system provided in Embodiment 1 of this application;

[0026] Figure 2 A flowchart illustrating an address allocation method for a distributed system provided in Embodiment 2 of this application;

[0027] Figure 3 This is a schematic diagram of the structure of a distributed system provided in Embodiment 3 of this application;

[0028] Figure 4 This is a schematic diagram of another distributed system provided in Embodiment 3 of this application;

[0029] Figure 5 This is a schematic diagram of another distributed system provided in Embodiment 3 of this application;

[0030] Figure 6 A circuit diagram of a master control addressing enable module or a slave control addressing enable unit provided in Embodiment 3 of this application;

[0031] Figure 7 This is a circuit diagram of a slave control addressing input unit provided in Embodiment 3 of this application;

[0032] Figure 8 This is a schematic diagram of another distributed system provided in Embodiment 3 of this application;

[0033] Figure 9 A schematic diagram of the structure of an electronic device for implementing the address allocation method of the distributed system in the embodiments of this application. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0035] It should be noted that the terms "first," "second," "n-1," "n," and "n+1," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0036] In this embodiment of the application, the distributed system includes a master control device and N slave control devices, where N≥2; the master control device and the N slave control devices are connected in series, and the master control device and the N slave control devices are connected via bus communication.

[0037] In a distributed system, the master control device can be understood as the device responsible for coordinating and managing the core nodes or services of the entire system; the slave control devices can be understood as devices that perform specific tasks and are managed and coordinated by the master control device. In address allocation within a distributed system, the master control device is responsible for managing and allocating addresses to the slave control devices, which then accept control and configure their addresses.

[0038] In this embodiment, the distributed system includes a master control device and at least two slave control devices. The master control device and the N slave control devices are connected via bus communication; and the master control device and the N slave control devices are connected in series. The bus communication connection methods between the master control device and each slave control device include, but are not limited to, Controller Area Network (CAN) connection, Ethernet connection, and RS485 connection.

[0039] Example 1

[0040] Figure 1 This is a flowchart of an address allocation method for a distributed system provided in Embodiment 1 of this application. This embodiment is applicable to situations where a master control device allocates addresses to slave control devices in a distributed system. This method can be executed by the master control device of the distributed system.

[0041] like Figure 1 As shown, the method includes:

[0042] S110. Control the first slave device to enter the addressing state and send a first address allocation command to the bus so that the first slave device responds to the first address allocation command in the addressing state and updates its own address; the first address allocation command includes the address allocated by the master device to the first slave device.

[0043] In this context, the first slave device can be considered as a slave device directly connected in series with the master device. The first address allocation command can be understood as a command used to assign an address to the first slave device. The first address allocation command includes at least the address assigned by the master device to the first slave device. Addressing status can be understood as the state in which the device updates its own address. An address can be understood as a unique identifier for communication between the slave device and other devices.

[0044] Specifically, before the first slave device is assigned an address, the master device cannot control the slave devices via the bus. The master device needs to output a signal to the first slave device in series to control it into addressing mode. After the first slave device enters addressing mode, the master device sends a first address allocation command to the bus. This command includes at least the address assigned to the first slave device by the master device. Since all slave devices are connected to the master device via the bus, each slave device will receive the first address allocation command from the master device. However, only the first slave device is in addressing mode at this time. Therefore, only the first slave device can update its own address based on the address in the received first address allocation command, thus enabling the master device to update the address of the first slave device. Understandably, after updating its own address, the first slave device exits addressing mode.

[0045] For example, the way the master control device controls the first slave control device to enter the addressing state may include: the master control device outputs a first addressing enable signal to the first slave control device. The first addressing enable signal can be understood as an enable signal used to control the first slave control device to enter the addressing state, so that the first slave control device can control itself to enter the addressing state based on the input first addressing enable signal.

[0046] S120. Based on the bus, send an addressing control command to the (n-1)th slave device, so that the (n-1)th slave device controls the nth slave device to enter the addressing state, and send an nth address allocation command to the bus, so that the nth slave device responds to the nth address allocation command in the addressing state and updates its own address; where 2≤n≤N; the nth address allocation command includes the address allocated by the master device to the nth slave device.

[0047] The addressing control command can be understood as the command that controls the slave device to enter the addressing state. The nth address allocation command can be understood as the command used to allocate an address to the nth slave device, where 2 ≤ n ≤ N. The nth address allocation command includes at least the address allocated by the master device to the nth slave device.

[0048] Specifically, after the master device completes address allocation for the (n-1)th slave device, it sends an addressing control command to the (n-1)th slave device via the bus based on the slave device's address. This causes the (n-1)th slave device to output a signal to the nth slave device in series, controlling the nth slave device to enter the addressing state. After the nth slave device enters the addressing state, it sends an nth address allocation command to the bus. The nth address allocation command includes at least the address assigned by the master device to the first slave device.

[0049] Since all slave devices are connected to the master device via a bus, each slave device receives the nth address allocation command from the master device. However, only the nth slave device is in addressing mode at this time. Therefore, only the nth slave device can update its own address based on the address in the received nth address allocation command, thus enabling the master device to update the address of the nth slave device. It is understandable that after updating its own address, the nth slave device exits the addressing mode.

[0050] For example, the master control device can control the nth slave device to enter the addressing state through the (n-1)th slave device in a manner that includes: the master control device sending an addressing control command to the (n-1)th slave device via a bus. The (n-1)th slave device responds to the addressing control command and outputs an nth addressing enable signal to the nth slave device. The nth addressing enable signal can be understood as an enable signal used to control the nth slave device to enter the addressing state, thereby enabling the nth slave device to control itself to enter the addressing state based on the input nth addressing enable signal.

[0051] The technical solution of this application embodiment is applied to a distributed system, which includes a master control device and N slave control devices, where N≥2; the master control device and the N slave control devices are connected in series, and the master control device and the N slave control devices are connected via a bus for communication. The master control device of the distributed system controls the first slave control device to enter an addressing state and sends a first address allocation command to the bus, so that the first slave control device updates its own address in response to the first address allocation command in the addressing state; it then sends an addressing control command to the (n-1)th slave control device via the bus, so that the (n-1)th slave control device controls the nth slave control device to enter an addressing state and sends an nth address allocation command to the bus, so that the nth slave control device updates its own address in response to the nth address allocation command in the addressing state; wherein, the first address allocation command includes the address assigned by the master control device to the first slave control device, and the nth address allocation command includes the address assigned by the master control device to the nth slave control device; 2≤n≤N. By sequentially controlling the serially connected slave devices to update their own addresses based on the address allocation commands transmitted via the bus in the addressing state, the automatic address allocation of each slave device is achieved. Compared with the traditional manual address allocation method, it does not require manual intervention, is less prone to human error, and improves the address allocation efficiency.

[0052] As an optional embodiment of this application, S110, controlling the first slave device to enter the addressing state and sending a first address allocation command to the bus, includes:

[0053] S111. Output a first addressing enable signal to the first slave device. The first addressing enable signal is used to control the first slave device to enter the addressing state and to make the first slave device send the first addressing state information to the bus.

[0054] The first addressing status information can be understood as information used to indicate the addressing status of the first slave device. The addressing status can include addressing enabled or addressing disabled.

[0055] Specifically, the master control device outputs a first addressing enable signal to the first slave control device in series, so that the first slave control device controls itself to enter the addressing state according to the input first addressing enable signal, and after entering the addressing state, sends the first addressing state information to the master control device based on the bus, which is used to feedback to the master control device that the first slave control device has entered the addressing state.

[0056] S112. After obtaining the first addressing status information, send a first address allocation command to the bus.

[0057] Specifically, the master device monitors the bus in real time. After obtaining the first addressing status information from the bus, it sends a first address allocation command containing the address to be allocated to the first slave device to the bus.

[0058] In an optional embodiment, after outputting the first addressing enable signal to the first slave device, if the first addressing status information is not obtained, the address allocation state is exited.

[0059] Specifically, if the master control device does not receive the first addressing status information from the first slave control device within a preset time after outputting the first addressing enable signal to the first slave control device, it assumes that the first slave control device does not exist and cannot allocate an address to the first slave control device, and then exits the address allocation state.

[0060] In this embodiment, the master control device controls the first slave control device to enter the addressing state by outputting the first addressing enable signal, and sends the first address allocation command to the first slave control device that has entered the addressing state based on the bus, thereby realizing automatic address allocation for the first slave control device.

[0061] As an optional embodiment of this application, S120, the step of sending an addressing control command to the (n-1)th slave device based on the bus, so that the (n-1)th slave device controls the nth slave device to enter the addressing state; and sending an nth address allocation command to the bus, so that the nth slave device updates its own address in response to the nth address allocation command in the addressing state, includes:

[0062] S121. Based on the bus, send an addressing control command to the (n-1)th slave device. The addressing control command includes at least the address of the (n-1)th slave device and is used to control the (n-1)th slave device to output an nth addressing enable signal to the nth slave device. The nth addressing enable signal is used to control the nth slave device to enter the addressing state and send the nth addressing state information to the bus.

[0063] The nth addressing status information can be understood as information representing the addressing status of the nth slave device. The addressing control command can be understood as a command that instructs the (n-1)th slave device to enter the addressing state. The addressing control command sent to the (n-1)th slave device includes at least the address of the (n-1)th slave device, which, from the master device's perspective, can be considered the address previously assigned to the slave device.

[0064] Specifically, the master device sends an addressing control command to the bus. This addressing control command contains the address of the (n-1)th slave device, causing the (n-1)th slave device to respond to the addressing control command and output the nth addressing enable signal to the nth slave device in series. This enables the nth slave device to control itself to enter the addressing state based on the input nth addressing enable signal. After entering the addressing state, the nth addressing status information is sent to the master device via the bus to provide feedback to the master device that the nth slave device has entered the addressing state.

[0065] S122. When the nth addressing status information is obtained, an nth address allocation command is sent to the bus.

[0066] Specifically, the master device monitors the bus in real time. After obtaining the nth addressing status information from the bus, it sends an nth address allocation command to the bus, which contains the address to be allocated to the nth slave device.

[0067] It should be noted that after receiving the addressing status information (first addressing status information or nth addressing status information) from the slave devices, the master device does not need to determine which slave device has entered the addressing state, nor does it need to know which slave device should be assigned an address. It only needs to generate an address allocation command (first address allocation command or nth address allocation command) based on the address to be allocated and send it to the bus. Since each slave device receives the address allocation command, but only the slave device that has entered the addressing state will respond to the address allocation command and perform addressing, the orderly addressing of each slave device can be guaranteed.

[0068] In an optional embodiment, after sending the addressing control command to the Nth slave device based on the bus, the method further includes: S123, if the Nth addressing status information is not obtained, then exit address allocation.

[0069] Specifically, after sending the addressing control command to the Nth slave device via the bus, if the Nth addressing status information is not obtained, the master device assumes that there are no slave devices connected in series after the Nth slave device, and has completed the address allocation for all slave devices connected to the distributed system, and then exits the address allocation process.

[0070] In this embodiment, the master control device sends an addressing control command to the (n-1)th slave control device, causing the (n-1)th slave control device to output the nth addressing enable signal to control the nth slave control device to enter the addressing state. Furthermore, the master control device sends the nth address allocation command to the nth slave control device that has entered the addressing state via the bus, enabling the master control device to directly control the addressing of each slave control device and improving address allocation efficiency.

[0071] As an optional embodiment of this application, before controlling the first slave device to enter the addressing state, the method further includes:

[0072] A1. Obtain the address of each slave device based on the bus.

[0073] In this distributed system, slave devices use default initial addresses, such as 0000, before being assigned addresses. The slave devices' addresses are only updated after the master device assigns an address.

[0074] For example, the way to obtain the address of each slave device based on the bus can be to send an address request command to the bus so that the slave device connected to the distributed system returns the address to the bus; or the slave device connected to the distributed system sends the address to the bus so that the master device listens to the bus to obtain the address of the slave device.

[0075] In an optional embodiment, obtaining the address of each of the slave devices based on the bus includes: after the distributed system is powered on, sending an address request command to the bus so that the slave devices connected to the distributed system return an address to the bus.

[0076] The address request command can be understood as a command used to request the address of the slave device.

[0077] Specifically, during the initialization process after the distributed system is powered on, an address request command is sent to the bus so that the slave devices connected to the distributed system can return the current address to the bus.

[0078] In another alternative embodiment, obtaining the address of each slave device based on the bus includes: after adding or replacing the slave device, receiving the address sent by the slave device of the distributed system to the bus.

[0079] Specifically, if a new slave device is added or an existing slave device is replaced in a distributed system, the slave device can actively send its address to the bus so that the master device can receive the current address of the new or replaced slave device based on the bus.

[0080] A2. Determine whether the address of each slave device is in the device address table.

[0081] The device address table can be understood as the storage address table that the master device assigns to each slave device.

[0082] Specifically, the master device compares the addresses received from each slave device with the addresses stored in the device address table to determine if the master device is in the device address table. If the slave device's address is not in the device address table, it means that the slave device is waiting for address allocation; if the slave device's address is not in the device address table, it means that the slave device has already been allocated an address.

[0083] A3. If the address of at least one slave device is not in the device address table, then address allocation is initiated.

[0084] Specifically, if at least one slave device's address is not in the device address table among the received slave device addresses, it means that at least one slave device is waiting for address allocation. At this time, the master device starts address allocation and allocates addresses to all slave devices in sequence.

[0085] A4. If all the addresses are in the device address table and at least two addresses are duplicated, then address allocation is initiated.

[0086] Specifically, if the addresses of all the slave devices received are in the device address table, then it is determined whether the addresses of each slave device are duplicated, that is, the number of each address received; if there are at least two duplicate addresses, that is, if the number of addresses is greater than 1, it means that there are at least two slave devices that are the same, which does not meet the uniqueness of the address, and address allocation needs to be started, and the addresses of all slave devices are reassigned in turn.

[0087] It is understood that if all the addresses are in the device address table and there are no duplicate addresses, it means that each slave device has been assigned a unique address and there is no need to start address allocation.

[0088] It should be noted that there are two possible scenarios for slave devices connected after the distributed system is powered on: one is adding new slave devices after power-on, i.e., connecting a new slave device in series with the last slave device; the other is replacing one of the slave devices with a new one after power-on. In both scenarios, if the new slave device's communication address is the initial address, address allocation can be initiated to reassign addresses to all slave devices connected to the distributed system. If the new slave device's communication address has already been assigned and does not conflict with the addresses of other slave devices connected to the distributed system, address allocation does not need to be initiated. If it conflicts with the addresses of other slave devices connected to the distributed system, address allocation can also be initiated to reassign addresses to all slave devices connected to the distributed system.

[0089] This embodiment determines whether to enable address allocation by judging whether the address of each slave device is in the device address table. During the initialization process of the distributed system power-on and when a new slave device is connected after the distributed system is powered on, the slave devices connected to the distributed system can be allocated addresses in an orderly manner.

[0090] As an optional embodiment of this application, before controlling the nth slave device to enter the addressing state through the (n-1)th slave device, the method further includes:

[0091] In response to the address update information fed back to the bus by the (n-1)th slave device after updating its own address, the allocated address is marked in the device address table.

[0092] The address update information is used to indicate the information of the slave device completing the addressing process, and the address update information includes at least the updated address of the slave device.

[0093] Specifically, after the (n-1)th slave device, in addressing mode, responds to the (n-1)th address allocation command sent by the master device to the bus and updates its own address, it sends address update information back to the bus. The master device listens to the bus to obtain the address update information from the (n-1)th slave device, marks the allocated address in the device address table according to the address update information, and updates the device address table. Then, it begins address allocation for the next slave device.

[0094] In this embodiment, the device address table is updated by the address update information fed back by the (n-1)th slave device, so that the device address table is synchronized with the allocated address of the slave device.

[0095] Example 2

[0096] Figure 2 This is a flowchart of an address allocation method for a distributed system provided in Embodiment 2 of this application. This embodiment is applicable to the situation where slave devices in a distributed system are addressed according to the address allocated by the master device. This method can be executed by the nth slave device in the distributed system, where 2≤n≤N.

[0097] like Figure 2 As shown, the method includes:

[0098] S210. Control itself to enter the addressing state according to the addressing enable signal output by the (n-1)th slave device.

[0099] The addressing enable signal can be understood as an enable signal used to control the slave device to enter the addressing state.

[0100] Specifically, when the nth slave device receives the addressing enable signal output by the (n-1)th slave device, it controls itself to enter the addressing state according to the addressing enable signal.

[0101] S220: Receives the address allocation command sent by the master device to the bus, and updates its own address in response to the address allocation command in the addressing state; the address allocation command includes the address assigned by the master device to the nth slave device.

[0102] Specifically, when the nth slave device receives an address allocation command on the bus, if the nth slave device is in the addressing state, it responds to the address allocation command and updates its own address according to the address allocated to the nth slave device by the master device in the address allocation command.

[0103] The technical solution of this invention involves the nth (2≤n≤N) slave device controlling itself to enter an addressing state based on the addressing enable signal output by the (n-1)th slave device; receiving an address allocation command sent by the master device via the bus, and updating its own address in response to the address allocation command in the addressing state; the address allocation command includes the address assigned by the master device to the nth slave device. Each slave device is in an addressing state under the control of the master device, and updates its own address based on the address in the address allocation command transmitted via the bus, thus achieving automatic address allocation by the master device to each slave device. Compared to the traditional manual address allocation method, this eliminates the need for manual intervention, reduces the likelihood of human error, and improves address allocation efficiency.

[0104] As an optional embodiment of this application, after controlling itself to enter the addressing state according to the received addressing enable signal, and before receiving the address allocation command sent by the master control device to the bus, the method further includes:

[0105] Send addressing status information to the bus; the addressing status information is used to report to the master device that the nth slave device has entered the addressing state.

[0106] Specifically, after the nth slave device enters the addressing state, it sends addressing status information to the bus to report to the master device that the nth slave device has entered the addressing state. After the master device listens to the bus and obtains the addressing status information, it executes the next operation and assigns an address to the nth slave device.

[0107] In this embodiment, after the nth slave device enters the addressing state, it sends the addressing status information to the bus, which can promptly inform the master device of the addressing status of the slave device, so that the master device can allocate an address to the nth slave device.

[0108] As an optional embodiment of this application, after updating its own address in response to the address allocation command in the addressing state, the method further includes:

[0109] S230. Return address update information to the bus so that the master control device updates the device address table based on the address update information.

[0110] Specifically, after updating its own address, the nth slave device returns address update information to the bus, allowing the master device to listen to the bus and receive the address update information from the nth slave device. Based on the address update information, the master device marks the allocated address in the device address table and updates the device address table. Then, it begins to allocate addresses for the next slave device.

[0111] In this embodiment, the (n-1)th slave device feeds back address update information to the master device, so that the master device updates the device address table according to the address update information, and synchronizes the device address table with the allocated address of the slave device.

[0112] As an optional embodiment of this application, after updating its own address in response to the address allocation command in the addressing state, the method further includes:

[0113] In response to the addressing control command sent by the master control device based on the bus, the master control device outputs the (n+1)th addressing enable signal to the (n+1)th slave control device to control the (n+1)th slave control device to enter the addressing state; the addressing control command includes at least the address of the nth slave control device.

[0114] Specifically, for the nth slave device, after updating its own address, if it receives an addressing control command from the master device on the bus, it recognizes the addressing control command. If the addressing control command includes its own address, it responds to the addressing control command and outputs the (n+1)th addressing enable signal to the (n+1)th slave device to control the (n+1)th slave device to enter the addressing state. If the addressing control command does not include its own address, it does not respond to the addressing control command.

[0115] In this embodiment, the slave device not only controls itself to enter the addressing state, but also controls the next slave device to enter the addressing state, thereby ensuring the orderly addressing of each slave device.

[0116] Example 3

[0117] Figure 3 This is a schematic diagram of the structure of a distributed system provided in Embodiment 3 of this application. Figure 3 As shown, the distributed system includes: a master control device 31 and N slave control devices 32; N≥2; the master control device 31 and the N slave control devices 32 are connected in series, and the master control device 31 and the N slave control devices 32 are connected by bus communication.

[0118] Among them, the master control device 31 is used to control the first slave control device 32 to enter the addressing state and send a first address allocation command to the bus so that the first slave control device 32 responds to the first address allocation command in the addressing state and updates its own address;

[0119] The master control device 310 is used to send an addressing control command to the (n-1)th slave control device 32 via the bus, so that the (n-1)th slave control device controls the nth slave control device 32 to enter the addressing state, and sends an nth address allocation command to the bus, so that the nth slave control device 32 responds to the nth address allocation command in the addressing state to update its own address;

[0120] The first address allocation command includes the address allocated by the master device 31 to the first slave device 32, and the nth address allocation command includes the address allocated by the master device 31 to the nth slave device 32; 2≤n≤N.

[0121] As an optional embodiment of this application, Figure 4 This is a schematic diagram of another distributed system provided in Embodiment 3 of this application. Figure 4 As shown, the master control device 31 includes: a master control module 311, a master control communication module 312 and a master control addressing enable module 313 controlled by the master control module 311; each slave control device 32 includes: a slave control module 321, a slave control communication module 322 and a slave control addressing module 323 controlled by the slave control module 321;

[0122] The master control communication module 312 of the master control device 31 and the slave control communication modules 322 of the N slave control devices 32 are connected based on the bus;

[0123] The slave addressing module 323 of the first slave device 32 is connected to the master addressing enable module 313 of the master device 31; the master addressing enable module 313 is used to control the slave addressing module 323 of the first slave device 32 to enter the addressing state;

[0124] The slave addressing module 323 of the nth slave device 32 is connected to the slave addressing module 323 of the (n-1)th slave device 32. The slave addressing module 323 of the (n-1)th slave device 32 is used to control itself and the slave addressing module 323 of the nth slave device 32 to enter the addressing state.

[0125] Specifically, the master control communication module and the slave control communication module are used to transmit address information issued by the master control device and addressing feedback information fed back by the slave control device via a bus. The addressing feedback information may include addressing status information and address update information.

[0126] The master control communication module and the slave control communication module can be star-connected communication circuits such as CAN communication circuits, Ethernet communication circuits, and RS485 communication circuits. This application embodiment does not impose restrictions on the communication circuits of the master control communication module and the slave control communication module. The master control module 311 and the slave control module 321 can be chips including, but not limited to, DSP, ARM, FPGA, CPLD, etc.

[0127] The function of the master control addressing enable module is to control the first slave device to enter the addressing state. The function of the slave control addressing module of the (n-1)th slave device is to control the slave control addressing module of the nth slave device to enter the addressing state.

[0128] As an optional embodiment of this application, Figure 5 This is a schematic diagram of another distributed system provided in Embodiment 3 of this application. Figure 5 As shown, the slave addressing module 323 of the nth slave device includes: a slave addressing input unit 3231 and a slave addressing enable unit 3232;

[0129] If 2≤n≤N-1, the slave addressing input unit 3231 of the nth slave device 32 is connected to the slave addressing enable unit 3232 of the (n-1)th slave device, and the slave addressing enable unit 3232 of the nth slave device 32 is connected to the slave addressing input unit 3231 of the (n+1)th slave device 32; wherein, the slave addressing input unit 3231 of the nth slave device 32 is used to receive the nth addressing enable signal sent by the (n-1)th slave addressing enable unit 3232, and control the nth slave device to enter the addressing state; the slave addressing enable unit 3232 of the nth slave device 32 is used to output the (n+1)th addressing enable signal to the slave addressing input unit 3231 of the (n+1)th slave device 32, and control the (n+1)th slave device 32 to enter the addressing state.

[0130] Specifically, the function of the slave addressing input unit 3231 of the nth slave device 32 is to receive the addressing enable signal sent by the previous device and control itself to enter the addressing state; the function of the slave addressing enable unit 3232 of the nth slave device 32 is to send the addressing enable signal to the next device and control the next device to enter the addressing state.

[0131] For example, the master addressing enable module or the slave addressing enable unit can be a circuit composed of one or more digital-to-analog converters, relays, transistors, MOSFETs, optocouplers, thyristors, etc. The slave addressing input unit can be a circuit composed of one or more analog-to-digital converters, transistors, MOSFETs, optocouplers, RC networks, etc. This application does not impose limitations on the circuitry of the slave addressing enable unit and the slave addressing input unit.

[0132] In an optional embodiment, the master control addressing enable module includes: a first switching transistor; the gate of the first switching transistor is connected to the master control module for receiving a first control signal from the master control module, and the drain and source of the first switching transistor are connected to the slave control addressing input unit of the slave control module of the first slave control device for outputting a first addressing enable signal;

[0133] The slave addressing enable unit of the nth slave device includes: a second switch transistor; the gate of the second switch transistor is connected to the slave module of the nth slave device for receiving the nth control signal from the slave module; the drain and source of the second switch transistor are connected to the slave addressing input unit of the (n+1)th slave module for outputting the (n+1)th addressing enable signal. For example, Figure 6 This is a circuit diagram of a master control addressing enable module or slave control addressing enable unit based on a MOS transistor, provided in Embodiment 3 of this application.

[0134] In another alternative embodiment, the slave addressing input unit of the nth slave device includes: an optocoupler;

[0135] The input terminal of the optocoupler is connected to the slave addressing enable unit of the (n-1)th slave device, and is used to receive the nth addressing enable signal output by the slave addressing enable unit; the output terminal of the optocoupler is connected to the slave module of the nth slave device, and is used to output the nth addressing enable signal to the slave module. For example, Figure 7 This is a circuit diagram of a slave addressing input unit based on a MOS transistor, provided in Embodiment 3 of this application.

[0136] As an optional embodiment of this application, Figure 8 This is a schematic diagram of another distributed system provided in Embodiment 3 of this application. Figure 8 As shown, the main control device 31 also includes a main control isolation module 314, which is connected to the main control module 311, the main control communication module 312 and the main control addressing enable module 313 respectively.

[0137] The slave control device 32 further includes a slave control isolation module 324, which is connected to the slave control module 321, the slave control communication module 322 and the slave control addressing module 323 respectively; the slave control addressing module 323 includes a slave control addressing input unit 3231 and a slave control addressing enable unit 3232.

[0138] Specifically, the master control isolation module and the slave control isolation module serve to isolate signals to meet system safety requirements. These modules can be circuits composed of devices such as digital isolation chips, optocouplers, and signal transformers. This application does not impose any limitations on this aspect.

[0139] The distributed system provided in this application can execute the address allocation method of the distributed system provided in any embodiment of this application, and has the corresponding functional modules and beneficial effects of the execution method.

[0140] Example 4

[0141] Figure 9 A schematic diagram of an electronic device 10, which can be used to implement embodiments of this application, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein.

[0142] like Figure 9 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer programs stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 may also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via the bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0143] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0144] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as address allocation methods for distributed systems.

[0145] In some embodiments, the address allocation method for the distributed system may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the address allocation method for the distributed system described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the address allocation method for the distributed system by any other suitable means (e.g., by means of firmware).

[0146] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0147] In some embodiments, the address allocation method of the distributed system can be implemented as a computer program, which is implicitly included in a computer program product. When executed by a processor, the computer program implements the address allocation method of the distributed system of this application. The computer program product can be understood as a software product that primarily implements its solution through a computer program. The computer program used to implement the method of this application can be written in any combination of one or more programming languages. These computer programs can be provided to the processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program can be executed entirely on the machine, partially on the machine, or as a standalone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0148] In the context of this application, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0149] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0150] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0151] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0152] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0153] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for address allocation in a distributed system, characterized in that, The method is executed by the master control device of the distributed system; wherein, the distributed system includes a master control device and N slave control devices, N≥2; the master control device and the N slave control devices are connected in series, and the master control device and the N slave control devices are connected via a bus communication connection; the method includes: The first slave device is controlled to enter the addressing state and a first address allocation command is sent to the bus so that the first slave device updates its own address in response to the first address allocation command in the addressing state. Based on the bus, an addressing control command is sent to the (n-1)th slave device, so that the (n-1)th slave device controls the nth slave device to enter the addressing state; and an nth address allocation command is sent to the bus, so that the nth slave device updates its own address in response to the nth address allocation command in the addressing state; 2≤n≤N; Wherein, the first address allocation command includes the address allocated by the master control device to the first slave control device, and the nth address allocation command includes the address allocated by the master control device to the nth slave control device.

2. The method according to claim 1, characterized in that, The process of controlling the first slave device to enter the addressing state and sending a first address allocation command to the bus includes: A first addressing enable signal is output to the first slave device. The first addressing enable signal is used to control the first slave device to enter the addressing state and to enable the first slave device to send the first addressing state information to the bus. After obtaining the first addressing status information, a first address allocation command is sent to the bus.

3. The method according to claim 1, characterized in that, The step of sending an addressing control command to the (n-1)th slave device based on the bus, so that the (n-1)th slave device controls the nth slave device to enter the addressing state; and sending an nth address allocation command to the bus, so that the nth slave device updates its own address in response to the nth address allocation command in the addressing state, includes: Based on the bus, an addressing control command is sent to the (n-1)th slave device. The addressing control command includes at least the address of the (n-1)th slave device and is used to control the (n-1)th slave device to output an nth addressing enable signal to the nth slave device. The nth addressing enable signal is used to control the nth slave device to enter the addressing state and send the nth addressing state information to the bus. When the nth addressing status information is obtained, the nth address allocation command is sent to the bus so that the nth slave device responds to the nth address allocation command in the addressing status and updates its own address.

4. The method according to any one of claims 1-3, characterized in that, Before controlling the first slave device to enter the addressing state, the following steps are also included: The addresses of each slave device are obtained based on the bus; Determine whether the address of each slave device is in the device address table; If the address of at least one slave device is not in the device address table, then address allocation is initiated; If all the addresses are in the device address table and at least two addresses are duplicated, then address allocation is initiated.

5. The method according to claim 4, characterized in that, The step of obtaining the address of each slave device based on the bus includes: After the distributed system is powered on, it sends an address request command to the bus so that the slave devices connected to the distributed system return an address to the bus.

6. The method according to claim 4, characterized in that, The step of obtaining the address of each slave device based on the bus includes: After adding or replacing the slave device, the system receives the address sent from the slave device of the distributed system to the bus.

7. The method according to claim 4, characterized in that, Before controlling the nth slave device to enter the addressing state via the (n-1)th slave device, the process also includes: In response to the address update information fed back to the bus by the (n-1)th slave device after updating its own address, the allocated address is marked in the device address table.

8. An address allocation method for a distributed system, characterized in that, The method is executed by the nth slave device of the distributed system, where 2 ≤ n ≤ N; wherein the distributed system includes a master device and N slave devices, where N ≥ 2; the master device and the N slave devices are connected in series, and the master device and the N slave devices are connected via bus communication. The method includes: The device controls itself to enter the addressing state based on the addressing enable signal output by the (n-1)th slave device; The master device receives an address allocation command sent to the bus and updates its own address in response to the address allocation command in the addressing state; the address allocation command includes the address allocated by the master device to the nth slave device.

9. The method according to claim 8, characterized in that, After controlling itself to enter the addressing state according to the received addressing enable signal, and before receiving the address allocation command sent by the master control device to the bus, the process also includes: Send addressing status information to the bus; the addressing status information is used to report to the master device that the nth slave device has entered the addressing state.

10. The method according to claim 8 or 9, characterized in that, After updating its own address in response to the address allocation command in the addressing state, the system further includes: The address update information is returned to the bus so that the master device updates the device address table based on the address update information.

11. The method according to claim 8 or 9, characterized in that, After updating its own address in response to the address allocation command in the addressing state, the system further includes: In response to the addressing control command sent by the master control device based on the bus, the master control device outputs the (n+1)th addressing enable signal to the (n+1)th slave control device to control the (n+1)th slave control device to enter the addressing state; the addressing control command includes at least the address of the nth slave control device.

12. A distributed system, characterized in that, The distributed system includes: a master control device and N slave control devices; N≥2; the master control device and the N slave control devices are connected in series, and the master control device and the N slave control devices are connected via bus communication. The master control device is used to control the first slave control device to enter the addressing state and send a first address allocation command to the bus, so that the first slave control device updates its own address in response to the first address allocation command in the addressing state; The master control device is used to send an addressing control command to the (n-1)th slave control device via the bus, so that the (n-1)th slave control device controls the nth slave control device to enter the addressing state, and sends an nth address allocation command to the bus, so that the nth slave control device responds to the nth address allocation command in the addressing state to update its own address; Wherein, the first address allocation command includes the address allocated by the master control device to the first slave control device, and the nth address allocation command includes the address allocated by the master control device to the nth slave control device; 2≤n≤N.

13. The distributed system according to claim 12, characterized in that, The master control device includes: a master control module, a master control communication module and a master control addressing enable module controlled by the master control module; each slave control device includes: a slave control module and a slave control communication module and a slave control addressing module controlled by the slave control module; The master control communication module of the master control device and the slave control communication modules of the N slave control devices are connected based on the bus. The slave addressing module of the first slave device is connected to the master addressing enable module of the master device; the master addressing enable module is used to control the slave addressing module of the first slave device to enter the addressing state; The slave addressing module of the nth slave device is connected to the slave addressing module of the (n-1)th slave device; the slave addressing module of the (n-1)th slave device is used to control itself and the slave addressing module of the nth slave device to enter the addressing state.

14. The distributed system according to claim 13, characterized in that, The slave addressing module of the nth slave device includes: a slave addressing input unit and a slave addressing enable unit; The slave addressing input unit of the nth slave device is connected to the slave addressing enable unit of the (n-1)th slave device, and the slave addressing enable unit of the nth slave device is connected to the slave addressing input unit of the (n+1)th slave device; wherein, the slave addressing input unit of the nth slave device is used to receive the nth addressing enable signal sent by the (n-1)th slave addressing enable unit, and control the nth slave device to enter the addressing state; the slave addressing enable unit of the nth slave device is used to output the (n+1)th addressing enable signal to the slave addressing input unit of the (n+1)th slave device, and control the (n+1)th slave device to enter the addressing state.

15. The distributed system according to claim 14, characterized in that, The master control addressing enable module includes: a first switching transistor; the gate of the first switching transistor is connected to the master control module for receiving a first control signal from the master control module, and the drain and source of the first switching transistor are connected to the slave control addressing input unit of the slave control module of the first slave control device for outputting a first addressing enable signal; The slave addressing enable unit of the nth slave device includes: a second switch transistor; the gate of the second switch transistor is connected to the slave module of the nth slave device for receiving the nth control signal of the slave module; the drain and source of the second switch transistor are connected to the slave addressing input unit of the (n+1)th slave module for outputting the (n+1)th addressing enable signal.

16. The distributed system according to claim 14 or 15, characterized in that, The slave addressing input unit of the nth slave device includes: an optocoupler; The input terminal of the optocoupler is connected to the slave addressing enable unit of the (n-1)th slave device, and is used to receive the nth addressing enable signal output by the slave addressing enable unit; the output terminal of the optocoupler is connected to the slave module of the nth slave device, and is used to output the nth addressing enable signal to the slave module.

17. The distributed system according to claim 13, characterized in that, The main control device also includes a main control isolation module, which is connected to the main control module, the main control communication module and the main control addressing enable module respectively; The slave control device further includes a slave control isolation module, which is connected to the slave control module, the slave control communication module, and the slave control addressing module, respectively.

18. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that is executed by the at least one processor to cause the at least one processor to perform the address allocation method of the distributed system according to any one of claims 1-11.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that are used to cause a processor to execute the address allocation method of the distributed system according to any one of claims 1-11.

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