Semiconductor device

Abstract

A semiconductor device according to an example embodiment of the present disclosure can include a lower channel pattern extending in a vertical direction, a lower gate electrode overlapping the lower channel pattern in a first horizontal direction, an upper channel pattern overlapping the lower channel pattern in the vertical direction, an upper gate electrode overlapping the upper channel pattern in the first horizontal direction, and a charge storage region extending in the vertical direction and contacting the upper channel pattern. The lower channel pattern can include a first source / drain region, a second source / drain region spaced apart from the first source / drain region in the vertical direction, and a channel region between the first source / drain region and the second source / drain region, and at least a portion of the charge storage region can overlap the lower channel pattern in a second horizontal direction intersecting the first horizontal direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] With the increasing demand for high performance, high speed, and / or multifunctionality in semiconductor devices, the integration density of semiconductor devices has increased. In response to the trend of high integration in semiconductor devices, it is necessary to manufacture semiconductor devices with fine patterns, which require patterns with fine widths or fine spacing. Summary of the Invention

[0003] One aspect of this disclosure is to provide a semiconductor device including bit lines shared by adjacent memory cells.

[0004] A semiconductor device according to an example embodiment may include: a lower channel pattern extending in a vertical direction; a lower gate electrode overlapping the lower channel pattern in a first horizontal direction; an upper channel pattern overlapping the lower channel pattern in the vertical direction; an upper gate electrode overlapping the upper channel pattern in the first horizontal direction; and a charge storage region extending in the vertical direction and contacting the upper channel pattern. The lower channel pattern may include a first source / drain region, a second source / drain region spaced apart from the first source / drain region in the vertical direction, and a channel region located between the first source / drain region and the second source / drain region, and at least a portion of the charge storage region may overlap the lower channel pattern in a second horizontal direction intersecting the first horizontal direction.

[0005] A semiconductor device according to an example embodiment may include: a lower channel pattern extending in a vertical direction and spaced apart from each other in a first horizontal direction; a lower gate electrode adjacent to the lower channel pattern in a second horizontal direction intersecting the first horizontal direction and extending in the first horizontal direction; an upper channel pattern overlapping the lower channel pattern in the vertical direction; an upper gate electrode adjacent to the upper channel pattern in the second horizontal direction and extending in the first horizontal direction; and a charge storage region extending in the vertical direction and contacting a lower surface of the upper channel pattern. The lower portion of the charge storage region is alternately disposed with the lower channel pattern in the first horizontal direction.

[0006] A semiconductor device according to an example embodiment may include: a lower channel pattern extending in a vertical direction; a conductive structure contacting a lower surface of the lower channel pattern; a lower gate electrode overlapping the lower channel pattern in a first horizontal direction; an upper channel pattern overlapping the lower channel pattern in the vertical direction; a bit line structure located between the lower channel pattern and the upper channel pattern; an upper gate electrode overlapping the upper channel pattern in the first horizontal direction; a charge storage region extending in the vertical direction and contacting the upper channel pattern; a dielectric pattern located between a lower portion of the charge storage region and the lower channel pattern; and a spacer structure located between a upper portion of the charge storage region and the bit line structure. At least a portion of the charge storage region overlaps the lower channel pattern in a second horizontal direction intersecting the first horizontal direction.

[0007] According to an example embodiment of the technical concept of this disclosure, the lower channel pattern and the lower gate electrode overlap with the upper channel pattern and the upper gate electrode in the vertical direction, respectively, and the charge storage region overlaps with the lower channel pattern in the horizontal direction, thereby reducing the size of the semiconductor device.

[0008] The advantages and effects of this disclosure are not limited to the foregoing, and can be more readily understood in the process of describing specific exemplary embodiments of this disclosure. Attached Figure Description

[0009] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a conceptual circuit diagram of a memory cell of a semiconductor device according to an example embodiment; Figure 2 This is a schematic perspective view of a semiconductor device according to an example embodiment; Figure 3 This is a top view of a semiconductor device according to an example embodiment; Figure 4 It is along Figure 3 The diagram shows vertical cross-sectional views of the semiconductor device taken from lines I-I' and II-II'. Figure 5 It is along Figure 3 The diagram shows a vertical cross-section of the semiconductor device taken along line III-III'. Figure 6A , Figure 6B and Figure 6C yes Figure 4 A partially enlarged view of the semiconductor device shown; Figure 7 , Figure 8 and Figure 9 This is a vertical cross-sectional view of a semiconductor device according to an example embodiment; Figure 10A , Figure 10B , Figure 10C , Figure 10D and Figure 10E This is a vertical cross-sectional view of a semiconductor device according to an example embodiment; Figure 11 and Figure 12 This is a vertical cross-sectional view of a semiconductor device according to an example embodiment; Figure 13 This is a top view of a semiconductor device according to an example embodiment; Figure 14 It is along Figure 13 The diagram shows vertical cross-sectional views of the semiconductor device taken from lines IV-IV' and V-V'. Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 22C , Figure 23A , Figure 23B , Figure 23C , Figure 24A , Figure 24B , Figure 24C , Figure 25A , Figure 25B , Figure 26A , Figure 26B , Figure 27A , Figure 27B , Figure 28A , Figure 28B , Figure 29A and Figure 29B These are top views and vertical cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of this disclosure, arranged in process sequence. Detailed Implementation

[0010] In the following description, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0011] Figure 1 This is a conceptual circuit diagram of a memory cell of a semiconductor device according to an example embodiment. Figure 2This is a schematic perspective view of a semiconductor device according to an example embodiment.

[0012] refer to Figure 1 and Figure 2 The memory cell MC can be connected to the bit line BL and the word lines WWL and RWL. Each memory cell MC may include a write transistor WTr, a read transistor RTr, and a memory node SN. Each of the write transistor WTr and the read transistor RTr may include a channel WCh and a channel RCh. The memory node SN can be used as the gate (e.g., a floating gate) of the read transistor RTr and can be electrically connected to the write transistor WTr. For example, the memory node SN can be electrically connected to the channel WCh of the write transistor WTr.

[0013] Each memory cell (MC) can be selected by bit lines (BL) and word lines (WWL and RWL). Each memory cell (MC) can operate as a DRAM memory cell in which write operations and read operations are performed, and may not include capacitors. For example, each memory cell (MC) can store information in memory node (SN) instead of in capacitors, and may be referred to as a 2T memory cell.

[0014] The write transistor WTr can store charge in the memory node SN. The threshold voltage of the read transistor RTr, which acts as the gate of the memory node SN, changes depending on the amount of charge stored in the memory node SN. Depending on the threshold voltage of the read transistor RTr, the information stored in the memory cell can be read as either "0" or "1".

[0015] One end of the channel WCh of the write transistor WTr can be connected to the bit line BL, and the other end can be connected to the memory node SN. The gate of the write transistor WTr can be electrically connected to the write word line WWL extending in the Y direction. The write gate dielectric layer WGD can be disposed between the channel WCh of the write transistor WTr and the write word line WWL.

[0016] The channel RCh of the read transistor RTr can overlap with the channel WCh of the write transistor WTr in the vertical direction (Z direction). For example, the channel RCh of the read transistor RTr can be located below the channel WCh of the write transistor WTr. One end of the channel RCh of the read transistor RTr can be connected to the bit line BL, and the other end can be grounded. The gate of the read transistor RTr can be electrically connected to the read word line RWL extending in the Y direction. The memory node SN and the read word line RWL can be used for the turn-on / turn-off operation of the read transistor RTr. The read gate dielectric layer RGD can be disposed between the channel RCh of the read transistor RTr and the read word line RWL.

[0017] Bit line BL can be electrically connected to the memory cell MC. For example, bit line BL can extend in the X direction between the channel WCh of the write transistor WTr and the channel RCh of the read transistor RTr, and can be electrically connected to channels WCh and RCh. Figure 1 In this embodiment, the write word line WWL and the read word line RWL are shown as separate interconnects, but this disclosure is not limited thereto. In an example embodiment, the write word line WWL may be electrically connected to the read word line RWL and may be used as a single interconnect.

[0018] According to an example embodiment of this disclosure, because the write word line WWL and the read word line RWL are configured to overlap in the vertical direction, the area of ​​the semiconductor device can be reduced and the integration density of the memory cell MC can be increased compared to the case where the write word line WWL and the read word line RWL are configured to be on the same plane. Furthermore, because the write word line WWL and the read word line RWL, which are spaced apart from each other in the vertical direction, can operate independently, the electrical characteristics of the write transistor WTr and the read transistor RTr can be improved.

[0019] Figure 3 This is a top view of a semiconductor device according to an example embodiment. Figure 4 It is along Figure 3 The diagram shows vertical cross-sectional views of lines I-I' and II-II' of the semiconductor device. Figure 5 It is along Figure 3 The diagram shows a vertical cross-sectional view of the semiconductor device along line III-III'. Figures 6A to 6C yes Figure 4 An enlarged view of a portion of the semiconductor device shown.

[0020] refer to Figures 3 to 6C The semiconductor device 100 according to an example embodiment of the present disclosure may include a lower channel pattern 12, a dielectric pattern 16, a lower gate dielectric layer 30, a lower gate electrode 32, a bit line structure 40, an upper gate dielectric layer 60, an upper gate electrode 62, a charge storage region 66, an upper channel pattern 72, and a conductive structure 80.

[0021] refer to Figure 1 and Figure 2 The described write transistor WTr may include an upper channel pattern 72. The upper channel pattern 72 may correspond to... Figure 2 The upper gate electrode 62 may correspond to the write word line WWL. The upper gate dielectric layer 60 may correspond to the write gate dielectric layer WGD. The portion of the upper gate electrode 62 that overlaps with the upper channel pattern 72 in the X direction may be used as the gate of the write transistor WTr. The portion of the upper gate dielectric layer 60 between the upper channel pattern 72 and the upper gate electrode 62 may be included in the write transistor WTr.

[0022] refer to Figure 1 and Figure 2 The described read transistor RTR may include a lower channel pattern 12. The lower channel pattern 12 may correspond to... Figure 2 The channel RCh is defined, and the lower gate electrode 32 may correspond to the read word line RWL. The lower gate dielectric layer 30 may correspond to the read gate dielectric layer RGD. The charge storage region 66 may be electrically connected to the upper channel pattern 72 and may include a reference. Figure 1 and Figure 2 The described storage node SN. The charge storage region 66 can also be used as the gate of the read transistor RTR. The portion of the dielectric pattern 16 between the lower channel pattern 12 and the charge storage region 66 can be included in the read transistor RTR.

[0023] Bit line structure 40 can be electrically connected to lower channel pattern 12 and upper channel pattern 72. Bit line structure 40 may include a reference. Figure 1 and Figure 2 The bit line BL is described.

[0024] The lower channel pattern 12, dielectric pattern 16, lower gate dielectric layer 30, lower gate electrode 32, upper gate dielectric layer 60, upper gate electrode 62, charge storage region 66, and upper channel pattern 72 may be included in the memory cell MC. The memory cell MC may have the same characteristics as the reference. Figure 1 and Figure 2 The described storage unit MC has the same or similar structure.

[0025] The lower channel pattern 12 may extend in the vertical direction and may be spaced apart from each other in the X and Y directions. The lower channel pattern 12 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium.

[0026] According to an example embodiment, the lower channel pattern 12 may include at least one of a polycrystalline semiconductor material, an oxide semiconductor material such as indium gallium zinc oxide (IGZO), or a two-dimensional material such as MoS2. In an example embodiment, the lower channel pattern 12 may include an oxide semiconductor material.

[0027] In an example embodiment, the lower channel pattern 12 may include a single-crystal semiconductor material such as single-crystal silicon, and as... Figure 6BAs shown, the lower channel pattern 12 may include a first source / drain region 12a, a second source / drain region 12b, and a channel region 12c. The first source / drain region 12a may contact the bit line structure 40, and the second source / drain region 12b may contact the conductive structure 80. The channel region 12c may be disposed between the first source / drain region 12a and the second source / drain region 12b. The first source / drain region 12a and the second source / drain region 12b are shown not to horizontally overlap with the lower gate electrode 32, but this disclosure is not limited thereto. In an example embodiment, at least a portion of the first source / drain region 12a or the second source / drain region 12b may horizontally overlap with the lower gate electrode 32.

[0028] The first source / drain region 12a and the second source / drain region 12b may include impurities. In an example embodiment, when the read transistor RTr is an NMOS transistor, the first source / drain region 12a and the second source / drain region 12b may include N-type impurities, such as P or As. In an example embodiment, when the read transistor RTr is a PMOS transistor, the first source / drain region 12a and the second source / drain region 12b may include P-type impurities, such as B or Al.

[0029] The semiconductor device 100 may further include a lower insulating pattern 22. The lower insulating pattern 22 may be disposed adjacent to a lower channel pattern 12. For example, two lower channel patterns 12 may be disposed between two lower insulating patterns 22 adjacent to each other in the X direction. The lower channel pattern 12 may contact two side surfaces of each lower insulating pattern 22, and the lower insulating pattern 22 may electrically insulate the lower channel patterns 12 from each other. The lower insulating pattern 22 may extend in a vertical direction, and for example, the upper and lower surfaces of the lower insulating pattern 22 may be coplanar with the upper and lower surfaces of the lower channel pattern 12, respectively. The lower insulating patterns 22 may extend in the Y direction and may be spaced apart from each other in the X direction.

[0030] The lower insulating pattern 22 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, low-k dielectric, or combinations thereof. For example, the lower insulating pattern 22 may include silicon oxide.

[0031] The lower gate electrode 32 can extend in the Y direction and can be spaced apart from each other in the X direction. The lower gate electrode 32 can be disposed adjacent to the lower channel pattern 12. For example, the lower gate electrode 32 can overlap with a portion of the lower channel pattern 12 in the X direction. Two lower gate electrodes 32 can be disposed between two lower insulating patterns 22 that are adjacent to each other in the X direction. The length of the lower gate electrode 32 in the vertical direction can be less than the length of the lower channel pattern 12 in the vertical direction. For example, the lower surface of the lower gate electrode 32 can be disposed at a height higher than the lower surface of the lower channel pattern 12, and the upper surface of the lower gate electrode 32 can be disposed at a height lower than the upper surface of the lower channel pattern 12.

[0032] The lower gate electrode 32 may comprise doped polycrystalline silicon, metal, conductive metal nitride, metal-semiconductor compound, metal compound, conductive metal oxide, graphene, carbon nanotube, or a combination thereof. For example, at least one lower gate electrode 32 may be made of doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or IrO. x RuO x It is formed from graphene, carbon nanotubes, or combinations thereof.

[0033] A lower gate dielectric layer 30 may be disposed between the lower channel pattern 12 and the lower gate electrode 32. For example, the lower gate dielectric layer 30 may contact the side surface of the lower channel pattern 12 facing the adjacent lower gate electrode 32, and may also contact the side surface of the lower gate electrode 32 facing the adjacent lower channel pattern 12. The lower gate dielectric layer 30 may extend in the vertical direction, and for example, the upper and lower surfaces of the lower gate dielectric layer 30 may be coplanar with the upper and lower surfaces of the lower channel pattern 12, respectively. The lower gate dielectric layers 30 may extend in the Y direction and may be spaced apart from each other in the X direction.

[0034] Each lower gate dielectric layer 30 may comprise at least one of silicon oxide or a high-k dielectric. For example, the high-k dielectric may be formed of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or combinations thereof, but this disclosure is not limited thereto. Each lower gate dielectric layer 30 may be formed of a single layer or multiple layers of the above materials.

[0035] The semiconductor device 100 may further include a lower cover layer 34. The lower cover layer 34 may cover lower gate electrodes 32 that are adjacent to each other in the X direction. For example, the lower cover layer 34 may cover the side surface, lower surface, and upper surface of the lower gate electrodes 32, and may electrically insulate the lower gate electrodes 32 from each other. The lower cover layer 34 may also be in contact with the lower gate dielectric layer 30.

[0036] The lower capping layer 34 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-k dielectric, or a combination thereof. For example, the lower capping layer 34 may include silicon oxide. Each lower capping layer 34 is shown as a single layer, but this disclosure is not limited thereto. In example embodiments, each lower capping layer 34 may be formed of multiple layers.

[0037] Bit line structures 40 can be disposed on the lower channel pattern 12 and can be electrically connected to the lower channel pattern 12. Bit line structures 40 can extend in the X direction and can be spaced apart from each other in the Y direction. The lower surface of the bit line structures 40 can contact the lower channel pattern 12, the lower insulating pattern 22, the lower gate dielectric layer 30, and the lower capping layer 34.

[0038] Bit line structure 40 may include conductive materials, such as doped single-crystal silicon, doped polycrystalline silicon, metals, conductive metal nitrides, metal-semiconductor compounds, conductive metal oxides, conductive graphene, carbon nanotubes, or combinations thereof. In an example embodiment, bit line structure 40 may include a first conductive pattern 40a, a second conductive pattern 40b, and a third conductive pattern 40c stacked sequentially. For example, the first conductive pattern 40a may include doped polycrystalline silicon, the second conductive pattern 40b may include a silicide material, and the third conductive pattern 40c may include a metal. The first conductive pattern 40a may contact the first source / drain region 12a of the lower channel pattern 12. However, according to the example embodiment, the number of layers and material type of bit line structure 40 may vary.

[0039] Charge storage regions 66 can be disposed between the lower channel patterns 12 and between the bit line structures 40. For example, in a top view, charge storage regions 66 can be spaced apart from the lower channel patterns 12 in the Y direction and can be alternately disposed in the Y direction. Charge storage regions 66 can extend in the vertical direction and can be spaced apart from each other in the X and Y directions. The lower surface of charge storage regions 66 can be disposed at a height higher than the lower surface of the lower channel patterns 12, and the upper surface of charge storage regions 66 can be disposed at a height higher than the upper surface of the bit line structures 40.

[0040] The portion of the charge storage region 66 that is lower than the lower surface of the bit line structure 40 can be referred to as the lower portion 67, and the portion of the charge storage region 66 that is higher than the lower surface of the bit line structure 40 can be referred to as the upper portion 68. The lower portion 67 can be disposed between the lower channel patterns 12, and the upper portion 68 can be disposed between the bit line structures 40. In an example embodiment, the horizontal width of the lower portion 67 can be different from the horizontal width of the upper portion 68. For example, as... Figure 6A As shown, the horizontal width of the lower part 67 can be greater than the horizontal width of the upper part 68.

[0041] The charge storage region 66 may include a conductive material, such as doped single-crystal silicon, doped polycrystalline silicon, a metal, a conductive metal nitride, a metal-semiconductor compound, a conductive metal oxide, conductive graphene, carbon nanotubes, or combinations thereof. In an example embodiment, the charge storage region 66 may include an oxide semiconductor, such as IGZO.

[0042] The semiconductor device 100 may further include a spacer structure 44 and a lower insulating layer 69. The spacer structure 44 may cover the side surface of the bit line structure 40 and may be disposed between the upper portion 68 of the charge storage region 66 and the bit line structure 40. The spacer structure 44 may further extend above the upper surface of the bit line structure 40 and the upper surface of the charge storage region 66. For example, the upper end of the spacer structure 44 may be disposed at a height higher than the upper surface of the bit line structure 40 and the upper surface of the charge storage region 66.

[0043] In an example embodiment, each spacer structure 44 may include a first spacer 45 that contacts the bit line structure 40 and a second spacer 46 that covers the side surface of the first spacer 45 and contacts the upper portion 68 of the charge storage region 66. The spacer structures 44 may cover the side surfaces of the bit line structures 40 to prevent or reduce oxidation of the bit line structures 40 during the manufacturing process. The spacer structures 44 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, low-k dielectric, or combinations thereof. For example, the first spacer 45 may include silicon nitride, and the second spacer 46 may include silicon oxide.

[0044] A lower insulating layer 69 may be disposed below the charge storage region 66. For example, the lower insulating layer 69 may contact the lower surface of the lower portion 67 of the charge storage region 66. The lower insulating layer 69 can spatially and electrically isolate the charge storage region 66 from the conductive structure 80. The lower insulating layer 69 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, low-k dielectric, or combinations thereof. For example, the lower insulating layer 69 may include silicon oxide.

[0045] A dielectric pattern 16 may be disposed between the lower channel pattern 12 and the charge storage region 66. For example, the dielectric pattern 16 may contact the side surface of the lower channel pattern 12 perpendicular to the Y direction, and may contact the lower portion 67 and the lower insulating layer 69 of the charge storage region 66. The upper surface of the dielectric pattern 16 may be coplanar with the upper surface of the lower channel pattern 12, and may contact the spacer structure 44. The lower surface of the dielectric pattern 16 may contact the conductive structure 80.

[0046] Each dielectric pattern 16 may include at least one of silicon oxide or a high-k dielectric. Each dielectric pattern 16 may be formed as a single layer or multiple layers.

[0047] The semiconductor device 100 may further include an upper conductive layer 70 disposed on the bit line structure 40. The upper conductive layer 70 may contact the upper surface of the bit line structure 40 and may contact the side surface of the spacer structure 44. The upper conductive layer 70 may be alternately disposed with the upper portion 68 of the charge storage region 66 in the Y direction. At least a portion of the upper conductive layer 70 may overlap with the lower channel pattern 12 in the vertical direction, and the upper conductive layers 70 may be spaced apart from each other in the X and Y directions.

[0048] The upper conductive layer 70 can electrically connect the bit line structure 40 to the upper channel pattern 72. In an exemplary embodiment, the upper surface of the upper conductive layer 70 may be disposed at the same height as the upper surface of the upper portion 68 of the charge storage region 66, but this disclosure is not limited thereto. In an exemplary embodiment, the upper conductive layer 70 may be formed simultaneously with the charge storage region 66 and may comprise the same material as the charge storage region 66.

[0049] The semiconductor device 100 may further include an insulating structure 74. The insulating structure 74 may be disposed between the upper channel patterns 72. For example, the insulating structure 74 may extend from the upper surface of the upper channel pattern 72 in a vertical direction and may contact the spacer structure 44. The insulating structures 74 may be spaced apart from each other in the Y direction and may be alternately disposed with the upper channel patterns 72 in the Y direction. The insulating structure 74 may spatially and electrically isolate the upper channel patterns 72 from each other. The insulating structure 74 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, low-k dielectric, or combinations thereof. For example, the insulating structure 74 may include silicon oxide.

[0050] The upper channel pattern 72 can contact and be electrically connected to the charge storage region 66. The upper channel pattern 72 can also contact the upper conductive layer 70 and be electrically connected to the bit line structure 40. For example... Figure 6CAs shown, each upper channel pattern 72 may include an upper portion 72a, a first lower portion 72b, and a second lower portion 72c. The upper portion 72a may be disposed at a height higher than the lower surface of the insulating structure 74, and the first lower portion 72b and the second lower portion 72c may be disposed at a height lower than the lower surface of the insulating structure 74. The upper portion 72a may be disposed on the first lower portion 72b and the second lower portion 72c, and may be disposed between the insulating structures 74.

[0051] The first lower portion 72b may overlap with the charge storage region 66 in the vertical direction and may contact the upper portion 68 of the charge storage region 66. The second lower portion 72c may overlap with the lower channel pattern 12 in the vertical direction and may contact the upper conductive layer 70. The first lower portion 72b may be spaced apart from the second lower portion 72c in the Y direction, and the spacer structure 44 is located between the first lower portion 72b and the second lower portion 72c. The upper portion 72a, the first lower portion 72b, and the second lower portion 72c may be integrally formed.

[0052] The upper channel pattern 72 may include a material different from the lower channel pattern 12. For example, the upper channel pattern 72 may include an oxide semiconductor material. The oxide semiconductor material may be indium gallium zinc oxide (IGZO). However, the example embodiment is not limited to this. For example, the oxide semiconductor material may include indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAGO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), ZnO, indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), indium zinc oxide (InZnO), oxygen At least one of indium gallium zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), or indium gallium silicon oxide (InGaSiO).

[0053] Two-dimensional materials may include at least one of a transition metal dichalcogenide material layer (TMD material layer), a black phosphorus material layer, or a hexagonal boron nitride material layer (hBN material layer) that may have semiconductor properties. For example, two-dimensional materials may include at least one of BiOSe, CrI, WSe2, MoS2, TaS, WS, SnSe, ReS, β-SnTe, MnO, AsS, P (black), InSe, h-BN, GaSe, GaN, SrTiO, MXene, or Janus 2D materials that can form two-dimensional materials.

[0054] The semiconductor device 100 may further include an upper insulating pattern 52. The upper insulating pattern 52 may be disposed adjacent to an upper channel pattern 72. For example, two upper channel patterns 72 may be disposed between two upper insulating patterns 52 adjacent to each other in the X direction. The upper channel pattern 72 and the upper conductive layer 70 may contact two side surfaces of each upper insulating pattern 52. The upper insulating pattern 52 may extend in a vertical direction. For example, the upper surface of the upper insulating pattern 52 may be coplanar with the upper surface of the upper channel pattern 72, and the lower surface of the upper insulating pattern 52 may be coplanar with the lower surface of the upper conductive layer 70. The upper insulating patterns 52 may extend in the Y direction and be spaced apart from each other in the X direction.

[0055] The upper insulating pattern 52 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, low-k dielectric, or combinations thereof. For example, the upper insulating pattern 52 may include silicon oxide.

[0056] The upper gate electrodes 62 may extend in the Y direction and be spaced apart from each other in the X direction. The upper gate electrodes 62 may be disposed adjacent to the upper channel pattern 72. For example, the upper gate electrodes 62 may overlap with a portion of the upper channel pattern 72 in the X direction. Two upper gate electrodes 62 may be disposed between two upper insulating patterns 52 adjacent to each other in the X direction. The lower and upper surfaces of the upper gate electrodes 62 may be disposed at heights lower than the lower and upper surfaces of the upper channel pattern 72, respectively. In an example embodiment, the upper gate electrodes 62 may overlap with the upper portion 68 of the charge storage region 66 in the X direction.

[0057] The upper gate electrode 62 may comprise doped polycrystalline silicon, a metal, a conductive metal nitride, a metal-semiconductor compound, a metal compound, a conductive metal oxide, graphene, carbon nanotubes, or combinations thereof. For example, at least one upper gate electrode 62 may be made of doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or IrO. x RuO xIt is formed from graphene, carbon nanotubes, or combinations thereof.

[0058] An upper gate dielectric layer 60 may be disposed between the upper channel pattern 72 and the upper gate electrode 62. For example, in a cross-sectional view, the upper gate dielectric layer 60 may have a U-shape and may contact the side and lower surfaces of the adjacent upper gate electrode 62. The upper gate dielectric layer 60 may also contact the bit line structure 40, the upper conductive layer 70, and the upper channel pattern 72. The upper gate dielectric layers 60 extend in the Y direction and may be spaced apart from each other in the X direction.

[0059] Each upper gate dielectric layer 60 may comprise at least one of silicon oxide or a high-k dielectric. For example, the high-k dielectric may be formed of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or combinations thereof, but this disclosure is not limited thereto. Each upper gate dielectric layer 60 may be formed of a single layer or multiple layers of the above materials.

[0060] The semiconductor device 100 may further include an upper capping layer 64. The upper capping layer 64 may cover upper gate electrodes 62 that are adjacent to each other in the X direction. For example, the upper capping layer 64 may cover the side surfaces and the top surfaces of the upper gate electrodes 62, and may electrically insulate the upper gate electrodes 62 from each other. The upper capping layer 64 may also be in contact with the upper gate dielectric layer 60.

[0061] The upper capping layer 64 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-k dielectric, or a combination thereof. For example, the upper capping layer 64 may include silicon oxide. Each upper capping layer 64 may be formed of a single layer or multiple layers.

[0062] Semiconductor device 100 may also include an upper sacrificial pattern 48. For example... Figure 3 and Figure 5 As shown, the upper sacrificial pattern 48 may overlap perpendicularly with the lower gate electrode 32 and the upper gate electrode 62, and may be disposed between the bit line structures 40. The upper sacrificial pattern 48 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, low-k dielectric, or combinations thereof. For example, the upper sacrificial pattern 48 may include silicon nitride.

[0063] The conductive structure 80 may be disposed below the lower channel pattern 12. For example, the conductive structure 80 may be in contact with the lower channel pattern 12, the dielectric pattern 16, the lower insulating pattern 22, the lower gate dielectric layer 30, the lower capping layer 34, and the lower insulating layer 69. The conductive structure 80 may be grounded. In an example embodiment, the conductive structure 80 may include a first conductive layer 80a in contact with the lower channel pattern 12 and a second conductive layer 80b located below the first conductive layer 80a.

[0064] The conductive structure 80 may include a conductive material and may include, for example, doped single-crystal silicon, doped polycrystalline silicon, a metal, a conductive metal nitride, a metal-semiconductor compound, a conductive metal oxide, conductive graphene, carbon nanotubes, or combinations thereof. For example, the first conductive layer 80a may include a silicide material, and the second conductive layer 80b may include a metal. However, according to the example embodiment, the number of layers and the material type of the bit line structure 40 may vary. In the example embodiment, the first conductive layer 80a may further include a conductive layer that contacts the lower channel pattern 12 and includes doped polycrystalline silicon.

[0065] According to an exemplary embodiment of this disclosure, the lower channel pattern 12 and the lower gate electrode 32 may overlap with the upper channel pattern 72 and the upper gate electrode 62 in the vertical direction, respectively. Therefore, compared to the case where the lower channel pattern 12 and the lower gate electrode 32 are disposed at the same height as the upper channel pattern 72 and the upper gate electrode 62, the horizontal dimension (area in top view) of the semiconductor device 100 can be reduced. Furthermore, since the charge storage region 66 is disposed at the same height as the lower channel pattern 12, the horizontal dimension (area in top view) of the semiconductor device 100 can be further reduced. Because the lower gate electrode 32 is spaced apart from the upper gate electrode 62 in the vertical direction, the lower gate electrode 32 and the upper gate electrode 62 can be controlled independently. Therefore, the electrical characteristics of the read transistor RTr and the write transistor WTr can be improved.

[0066] Figures 7 to 9 This is a vertical cross-sectional view of a semiconductor device according to an example embodiment.

[0067] refer to Figure 7 The semiconductor device 100a may include charge storage regions 66 disposed between the lower channel patterns 12 and the bit line structures 40. In an example embodiment, the horizontal width of the lower portion 67 of the charge storage region 66 may be the same as the horizontal width of the upper portion 68 of the charge storage region 66.

[0068] refer to Figure 8 The semiconductor device 100b may include charge storage regions 66 disposed between the lower channel patterns 12 and the bit line structures 40. In an example embodiment, the horizontal width of the lower portion 67 of the charge storage region 66 may differ from the horizontal width of the upper portion 68. For example, the horizontal width of the lower portion 67 of the charge storage region 66 may be smaller than the horizontal width of the upper portion 68. The upper surface of the dielectric pattern 16 may contact the lower surface of the upper portion 68 of the charge storage region 66.

[0069] refer to Figure 9The semiconductor device 100c may include charge storage regions 66 disposed between the lower channel patterns 12 and between the bit line structures 40. In an example embodiment, the first conductive pattern 40a of the bit line structures 40 may be omitted. For example, each bit line structure 40 may include a second conductive pattern 40b and a third conductive pattern 40c. The second conductive pattern 40b may contact the first source / drain region 12a of the lower channel pattern 12.

[0070] Figures 10A to 10E This is a vertical cross-sectional view of a semiconductor device according to an example embodiment.

[0071] Figures 10A to 10E Each of the semiconductor devices 100d, 100e, 100f, 100g, and 100h may include a channel pattern CH, a gate electrode WL, a gate dielectric layer GD, and a capping layer CL. In an example embodiment, the channel pattern CH, gate electrode WL, gate dielectric layer GD, and capping layer CL may correspond to a lower channel pattern 12, a lower gate electrode 32, a lower gate dielectric layer 30, and a lower capping layer 34, respectively. In an example embodiment, the channel pattern CH, gate electrode WL, gate dielectric layer GD, and capping layer CL may correspond to an upper channel pattern 72, an upper gate electrode 62, an upper gate dielectric layer 60, and an upper capping layer 64, respectively. Figures 10A to 10D Semiconductor devices 100d, 100e, 100f, and 100g illustrate example embodiments in which the vertical length of the gate electrode WL varies according to the horizontal distance from the side surface of the channel pattern CH.

[0072] refer to Figure 10A In an example embodiment, the surface S of the gate electrode WL of the semiconductor device 100d may be concave. In an example embodiment, the gate electrode WL may correspond to the lower gate electrode 32, and the surface S may correspond to at least one of the lower surface or the upper surface of the lower gate electrode 32. For example, at least one of the lower surface or the upper surface of the lower gate electrode 32 may be concave. In an example embodiment, the gate electrode WL may correspond to the upper gate electrode 62, and the surface S may correspond to the upper surface of the upper gate electrode 62. For example, the upper surface of the upper gate electrode 62 may be concave.

[0073] refer to Figure 10B In an example embodiment, the surface S of the gate electrode WL of the semiconductor device 100e may be convex. In an example embodiment, the gate electrode WL may correspond to the lower gate electrode 32, and the surface S may correspond to at least one of the lower surface or the upper surface of the lower gate electrode 32. For example, at least one of the lower surface or the upper surface of the lower gate electrode 32 may be convex. In an example embodiment, the gate electrode WL may correspond to the upper gate electrode 62, and the surface S may correspond to the upper surface of the upper gate electrode 62. For example, the upper surface of the upper gate electrode 62 may be convex.

[0074] refer to Figure 10C In an example embodiment, the surface S of the gate electrode WL of the semiconductor device 100f may be inclined relative to the lower surface of the channel pattern CH. In an example embodiment, the gate electrode WL may correspond to the lower gate electrode 32, and the surface S may correspond to at least one of the lower or upper surfaces of the lower gate electrode 32. For example, at least one of the lower or upper surfaces of the lower gate electrode 32 may be inclined, and the vertical length of the lower gate electrode 32 may increase as the lower gate electrode 32 approaches the lower channel pattern 12. In an example embodiment, the gate electrode WL may correspond to the upper gate electrode 62, and the surface S may correspond to the upper surface of the upper gate electrode 62. For example, the upper surface of the upper gate electrode 62 may be inclined, and the vertical length of the upper gate electrode 62 may increase as the upper gate electrode 62 approaches the upper channel pattern 72.

[0075] refer to Figure 10D In an example embodiment, the surface S of the gate electrode WL of the semiconductor device 100g may be rounded. In an example embodiment, the gate electrode WL may correspond to the lower gate electrode 32, and the surface S may correspond to at least one of the lower or upper surfaces of the lower gate electrode 32. For example, at least one of the lower or upper surfaces of the lower gate electrode 32 may be rounded, and the vertical length of the lower gate electrode 32 may increase as it approaches the lower channel pattern 12. In an example embodiment, the gate electrode WL may correspond to the upper gate electrode 62, and the surface S may correspond to the upper surface of the upper gate electrode 62. For example, the upper surface of the upper gate electrode 62 may be rounded, and the vertical length of the upper gate electrode 62 may increase as it approaches the upper channel pattern 72.

[0076] refer to Figure 10E The semiconductor device 100h may further include a conductive layer L located on the surface S of the gate electrode WL. The conductive layer L can be used to control the threshold voltage of the write transistor WTr or the read transistor RTr. For example, the conductive layer L may include a material different from the gate electrode WL, and may include a material having a work function different from that of the gate electrode WL. In an example embodiment, the conductive layer L may include at least one of a metal, a metal nitride, or polysilicon. For example, the conductive layer L may include at least one of Ti, Ta, W, TiN, TaN, WN, or polysilicon. The conductive layer L may also include a work function adjustment element, and the work function adjustment element may include at least one of La, Sr, Sb, Y, Al, Ta, Hf, Ir, Zr, or Mg.

[0077] Figure 11 and Figure 12 This is a vertical cross-sectional view of a semiconductor device according to an example embodiment.

[0078] refer to Figure 11 The charge storage region 66, the upper conductive layer 70, and the upper channel pattern 72 of the semiconductor device 100i may comprise the same material and may be integrally formed. The boundaries between the charge storage region 66 and the upper channel pattern 72, as well as the boundaries between the upper conductive layer 70 and the upper channel pattern 72, will not be observable. For example, the charge storage region 66, the upper conductive layer 70, and the upper channel pattern 72 may comprise an oxide semiconductor material, such as IGZO.

[0079] refer to Figure 12 Each dielectric pattern 16 of the semiconductor device 100j may include a first dielectric pattern 16a and a second dielectric pattern 16b. The first dielectric pattern 16a and the second dielectric pattern 16b may be spaced apart from each other in the Y direction, and a lower channel pattern 12 is located between the first dielectric pattern 16a and the second dielectric pattern 16b. For example, each lower channel pattern 12 may include a first side surface perpendicular to the Y direction and a second side surface opposite to the first side surface. The first dielectric pattern 16a may be in contact with the first side surface, and the second dielectric pattern 16b may be in contact with the second side surface.

[0080] In an example embodiment, the horizontal width of the first dielectric pattern 16a in the Y direction may be greater than the horizontal width of the second dielectric pattern 16b in the Y direction. For example, for each lower channel pattern 12, the distance between the lower channel pattern 12 and two adjacent charge storage regions 66 may be different. For each lower channel pattern 12, the distance between the charge storage region 66 in contact with the first dielectric pattern 16a and the lower channel pattern 12 may be greater than the distance between the charge storage region 66 in contact with the second dielectric pattern 16b and the lower channel pattern 12.

[0081] Figure 13 This is a top view of a semiconductor device according to an example embodiment. Figure 14 It is along Figure 13 The diagram shows a vertical cross-sectional view of the semiconductor device taken from lines IV-IV' and V-V'.

[0082] refer to Figure 13 and Figure 14The semiconductor device 100k may include a dielectric pattern 16k, a lower gate dielectric layer 30k, a lower gate electrode 32k, a first lower cover layer 34k, and a second lower cover layer 36k. In an example embodiment, the lower insulating pattern 22 of the semiconductor device 100 may be omitted, and the lower gate electrode 32k may be alternately disposed with the lower channel pattern 12 in the X direction. The lower gate dielectric layer 30k may contact the side surface of each lower channel pattern 12 and the side surface of each lower gate electrode 32k. The first lower cover layer 34k may be disposed on the lower gate electrode 32k, and the second lower cover layer 36k may be disposed below the lower gate electrode 32k. The dielectric pattern 16k may cover the side surface of the lower channel pattern 12 and may be disposed between the lower channel pattern 12 and the charge storage region 66.

[0083] Semiconductor device 100k may include an upper gate dielectric layer 60k, an upper gate electrode 62k, and an upper capping layer 64k. In an example embodiment, the upper insulating pattern 52 of semiconductor device 100 may be omitted, and the upper gate electrode 62k may be alternately disposed with the upper channel pattern 72 in the X direction. The upper gate dielectric layer 60k may cover the lower surface and side surface of each upper gate electrode 62k. The upper capping layer 64k may cover the upper surface of the upper gate electrode 62k.

[0084] Figures 15A to 29B These are top views and vertical cross-sectional views illustrating a method for manufacturing a semiconductor device according to an example embodiment, arranged in process sequence. Specifically, Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A and Figure 28A Is with Figure 3 The corresponding top view. Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B , Figure 27A , Figure 28B and Figure 29A Is with Figure 4 The corresponding vertical cross-sectional view. Figure 22C , Figure 23C, Figure 24C and Figure 29B Is with Figure 5 The corresponding vertical cross-sectional view.

[0085] refer to Figure 15A and Figure 15B A mask layer 14 can be formed on substrates 8 and 10. Substrates 8 and 10 may include an insulating layer 8 and a semiconductor pattern 10 located on the insulating layer 8. In an example embodiment, substrates 8 and 10 may be SOI substrates, and a semiconductor material layer may be further disposed below the insulating layer 8. In an example embodiment, the substrate may be a bulk silicon substrate, and the insulating layer 8 may be omitted.

[0086] The semiconductor pattern 10 can be formed by patterning a semiconductor material layer located on the insulating layer 8. For example, a mask layer 14 can be formed on the semiconductor material layer, and the semiconductor pattern 10 can be formed by an anisotropic etching process using the mask layer 14 as an etching mask. The mask layer 14 can cover the upper surface of the semiconductor pattern 10. The semiconductor pattern 10 can extend in the X direction and can be spaced apart from each other in the Y direction. The semiconductor pattern 10 can include semiconductor materials, such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors.

[0087] refer to Figure 16A and Figure 16B A dielectric material layer 16p and a lower sacrificial pattern 18 can be formed. The dielectric material layer 16p can conformally cover the insulating layer 8 and the semiconductor pattern 10. For example, the dielectric material layer 16p can cover the upper surface of the insulating layer 8 and the side and upper surfaces of the semiconductor pattern 10. The lower sacrificial pattern 18 can be formed on the dielectric material layer 16p and can fill the spaces between the semiconductor patterns 10. The lower sacrificial pattern 18 can form a sacrificial material layer on the dielectric material layer 16p and can be formed by removing the upper part of the sacrificial material layer via a planarization process to expose the dielectric material layer 16p. The lower sacrificial patterns 18 can extend in the X direction and can be spaced apart from each other in the Y direction.

[0088] The dielectric material layer 16p may include a dielectric material, and may include, for example, silicon oxide, but this disclosure is not limited thereto. The lower sacrificial pattern 18 may include a material that has etch selectivity relative to the dielectric material layer 16p. For example, the lower sacrificial pattern 18 may include silicon nitride.

[0089] refer to Figure 17A and Figure 17BA sacrificial layer 20 and a lower insulating pattern 22 can be formed. The sacrificial layer 20 can cover the dielectric material layer 16p and the lower sacrificial pattern 18. The lower insulating pattern 22 can be formed by etching the semiconductor pattern 10, mask layer 14, dielectric material layer 16p, lower sacrificial pattern 18 and sacrificial layer 20 in an anisotropic etching process and then filling the etched portions with an insulating material. The lower insulating pattern 22 can protrude upward from the upper surface of the semiconductor pattern 10, and the lower surface of the lower insulating pattern 22 can contact the insulating layer 8. The lower insulating patterns 22 can extend in the Y direction and can be spaced apart from each other in the X direction.

[0090] The lower insulating pattern 22 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, low-k dielectric, or combinations thereof. For example, the lower insulating pattern 22 may include silicon oxide. The sacrificial layer 20 may include a material that has etch selectivity relative to the lower insulating pattern 22. For example, the sacrificial layer 20 may include silicon nitride.

[0091] refer to Figure 18A and Figure 18B The sacrificial layer 20 can be removed, and a first material layer 24 and a second material layer 26 can be formed. Because the sacrificial layer 20 has etch selectivity relative to the lower insulating pattern 22, it can be selectively removed. After removing the sacrificial layer 20, the first material layer 24 can be formed to conformally cover the dielectric material layer 16p and the lower insulating pattern 22. The second material layer 26 can be formed on the first material layer 24 and can be disposed between the lower insulating patterns 22. For example, the second material layer 26 can be arranged alternately with the lower insulating pattern 22 in the X direction. The second material layers 26 can extend in the Y direction and can be spaced apart from each other in the X direction. A portion of the first material layer 24 can be exposed and not covered by the second material layer 26.

[0092] The first material layer 24 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low-k dielectric, or a combination thereof. For example, the first material layer 24 may include silicon oxide. The second material layer 26 may include a material that has etch selectivity relative to the first material layer 24. For example, the second material layer 26 may include polysilicon.

[0093] refer to Figure 19A and Figure 19BThe portion of the first material layer 24 not covered by the second material layer 26 and the upper portion of the lower insulating pattern 22 can be removed, and a mask pattern 28 can be formed. For example, the first material layer 24 and the lower insulating pattern 22 can be selectively etched by a wet etching process. After the mask pattern 28 is formed between the second material layers 26, the second material layers 26 can be removed. The remaining first material layer 24 can be completely removed, but this disclosure is not limited thereto. According to an example embodiment, the first material layer 24 can be retained to cover the upper surface of the dielectric material layer 16p. The mask patterns 28 can extend in the Y direction and can be spaced apart from each other in the X direction. At least a portion of the mask patterns 28 can overlap with the lower insulating pattern 22 in the vertical direction, and the horizontal width of the mask pattern 28 in the X direction can be greater than the horizontal width of the lower insulating pattern 22 in the X direction.

[0094] refer to Figure 20A and Figure 20B The semiconductor pattern 10 can be etched using an anisotropic etching process that uses mask pattern 28 as an etching mask to form the lower channel pattern 12. The lower channel pattern 12 can extend in the vertical direction and can be spaced apart from each other in the X and Y directions. The lower channel pattern 12 can be disposed on two side surfaces of the lower insulating pattern 22.

[0095] After forming the lower channel pattern 12, a dielectric material layer 30p, a gate material layer 32p, and an insulating material layer 34p can be formed. The dielectric material layer 30p can be formed to cover the insulating layer 8 and the lower channel pattern 12. In a cross-sectional view, the dielectric material layer 30p can have a U-shape and can extend in the Y direction. The gate material layer 32p can be formed by forming a conductive material layer on the dielectric material layer 30p and then etching the conductive material layer back. The gate material layers 32p can extend in the Y direction and can be spaced apart from each other in the X direction. The gate material layers 32p can be disposed between the lower channel patterns 12. For example, two gate material layers 32p can be disposed between two lower channel patterns 12 that are adjacent to each other in the X direction. The insulating material layer 34p can be formed on the gate material layer 32p. The insulating material layer 34p can cover the upper surface and side surface of the gate material layer 32p. After the insulating material layer 34p is formed, a planarization process can be performed to expose the upper surface of the lower insulating pattern 22 and the upper surface of the lower channel pattern 12.

[0096] refer to Figure 21A and Figure 21B The bit line structure 40 and the cover layer 42 can be formed. A conductive material layer and an insulating material layer can be formed to cover the lower channel pattern 12 and the lower sacrificial pattern 18, and the bit line structure 40 and the cover layer 42 can be formed by patterning the conductive material layer and the insulating material layer.

[0097] Bit line structures 40 can be disposed on the lower channel pattern 12, and can extend in the X direction and be spaced apart from each other in the Y direction. Bit line structures 40 can contact and be electrically connected to the lower channel pattern 12. Cover layers 42 can be disposed on the bit line structures 40, and can extend in the X direction and be spaced apart from each other in the Y direction. Lower sacrificial pattern 18 can be exposed and not covered by bit line structures 40.

[0098] Bit line structure 40 may include a first conductive pattern 40a, a second conductive pattern 40b, and a third conductive pattern 40c stacked sequentially. The first conductive pattern 40a may include a semiconductor material such as polysilicon and may be a layer doped with impurities. The second conductive pattern 40b may include a silicide material, and the third conductive pattern 40c may include a metallic material. The capping layer 42 may include silicon nitride.

[0099] In the example embodiment, an annealing process may be performed after the conductive material layer is formed to cover the lower channel pattern 12 and the lower sacrificial pattern 18, and before the bit line structure 40 is formed. Through the annealing process, impurities included in the first conductive pattern 40a can diffuse into the lower channel pattern 12, and a first source / drain region 12a can be formed (see [link to example]). Figure 6B According to an example embodiment, the first source / drain region 12a can be formed by implanting impurities into the lower channel pattern 12 via an ion implantation process. In this case, the first conductive pattern 40a can be omitted, and the upper surface of the lower channel pattern 12 can contact the second conductive pattern 40b.

[0100] refer to Figures 22A to 22C A spacer structure 44, an upper sacrificial pattern 48, a first upper sacrificial layer 50, and a second upper sacrificial layer 51 can be formed. The spacer structure 44 can cover the side surfaces of the bit line structure 40 and the cover layer 42, and can extend in the X direction. The upper sacrificial pattern 48 can be formed on the upper surface of the lower sacrificial pattern 18 and the side surface of the spacer structure 44, and can extend in the X direction. After forming the upper sacrificial pattern 48, a planarization process can be performed so that the upper surface of the upper sacrificial pattern 48 is coplanar with the upper surface of the cover layer 42.

[0101] The spacer structure 44 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, low-k dielectric, or combinations thereof, and may be formed of multiple layers. For example, as Figure 6A As shown, because the spacer structure 44 includes a first spacer 45 containing silicon nitride, the metal material of the bit line structure 40 can be prevented from being oxidized in subsequent processes.

[0102] A first upper sacrificial layer 50 and a second upper sacrificial layer 51 may be sequentially stacked on the capping layer 42 and the upper sacrificial pattern 48. The first upper sacrificial layer 50 may include a material having etch selectivity relative to the spacer structure 44 and the second upper sacrificial layer 51, and may include, for example, polysilicon. The second upper sacrificial layer 51 may include silicon nitride.

[0103] refer to Figures 23A to 23C An upper insulating pattern 52 and a mask pattern 54 can be formed. After anisotropically etching the cover layer 42, the first upper sacrificial layer 50, and the second upper sacrificial layer 51, the etched portions can be filled with an insulating material layer. After forming the insulating material layer, the second upper sacrificial layer 51 can be removed, exposing the side surfaces of the insulating material layer. An insulating spacer layer can be formed on the side surfaces of the insulating material layer, thereby forming the upper insulating pattern 52 and the mask pattern 54.

[0104] The portion of the insulating material layer disposed below the upper surface of the first upper sacrificial layer 50 may be referred to as the upper insulating pattern 52. The portion of the insulating material layer disposed above the upper surface of the first upper sacrificial layer 50 and the insulating spacer layer may be referred to as the mask pattern 54. The upper insulating pattern 52 and the mask pattern 54 may be integrally formed and may include silicon oxide.

[0105] The upper insulating pattern 52 and the mask pattern 54 may extend in the Y direction and may be spaced apart from each other in the X direction. At least a portion of the upper insulating pattern 52 may overlap with the lower insulating pattern 22 in the vertical direction. The horizontal width of the mask pattern 54 in the X direction may be greater than the horizontal width of the upper insulating pattern 52 in the X direction.

[0106] refer to Figures 24A to 24C The capping layer 42 and the first upper sacrificial layer 50 can be etched using an anisotropic etching process that uses mask pattern 54 as an etching mask. The etched capping layer 42 and the first upper sacrificial layer 50 can then be disposed on the two side surfaces of the upper insulating pattern 52.

[0107] An upper gate dielectric layer 60, an upper gate electrode 62, and an upper capping layer 64 can be formed. The upper gate dielectric layer 60 can be formed to cover the bit line structure 40, the capping layer 42, and the first upper sacrificial layer 50. In a cross-sectional view, the upper gate dielectric layer 60 can be U-shaped and can extend in the Y direction. The upper gate electrode 62 can be formed by forming a conductive material layer on the upper gate dielectric layer 60 and then etching back the conductive material layer. The upper gate electrodes 62 can extend in the Y direction and can be spaced apart from each other in the X direction. The upper gate electrodes 62 can be disposed between upper insulating patterns 52. For example, two upper gate electrodes 62 can be disposed between two upper insulating patterns 52 adjacent to each other in the X direction. The upper capping layer 64 can be formed on the upper gate electrode 62. The upper capping layer 64 can cover the upper surface and side surface of the upper gate electrode 62. After forming the upper capping layer 64, a planarization process can be performed to expose the upper surface of the upper insulating pattern 52.

[0108] refer to Figure 25A and Figure 25B The lower sacrificial pattern 18, upper sacrificial pattern 48, capping layer 42, and first upper sacrificial layer 50 can be selectively removed, and a first opening OP1 and a second opening OP2 can be formed. For example, the space where the lower sacrificial pattern 18 and upper sacrificial pattern 48 have been removed can be referred to as the first opening OP1. The first opening OP1 can expose the dielectric material layer 16p and the spacer structure 44. The space where the capping layer 42 and first upper sacrificial layer 50 have been removed can be referred to as the second opening OP2. The second opening OP2 can expose the bit line structure 40, the upper insulating pattern 52, and the upper gate dielectric layer 60. In a top view, the first opening OP1 and the second opening OP2 can be formed on two side surfaces of the upper insulating pattern 52, and can be formed alternately in the Y direction.

[0109] refer to Figure 26A and Figure 26B A charge storage region 66 and an upper conductive layer 70 can be formed. After forming a conductive material layer to fill the first opening OP1 and the second opening OP2 and cover the spacer structure 44, the conductive material layer can be etched back to expose at least a portion of the spacer structure 44, thus forming the charge storage region 66 and the upper conductive layer 70. The portion of the conductive material layer formed within the first opening OP1 can be referred to as the charge storage region 66. The lower portion 67 of the charge storage region 66 can cover the dielectric material layer 16p, and the upper portion 68 of the charge storage region 66 can cover the side surface of the spacer structure 44. The upper surface of the upper portion 68 of the charge storage region 66 can be positioned at a height lower than the upper end of the spacer structure 44. The lower portion 67 of the charge storage region 66 can be alternately arranged with the lower channel pattern 12 in the Y direction.

[0110] The portion of the conductive material layer formed within the second opening OP2 can be referred to as the upper conductive layer 70. The upper conductive layer 70 can cover the upper surface of the bit line structure 40 and the side surface of the spacer structure 44. The upper surface of the upper conductive layer 70 can be positioned at a lower height than the upper portion of the spacer structure 44. In an example embodiment, the upper surface of the upper conductive layer 70 can be positioned at the same height as the upper surface of the upper portion 68 of the charge storage region 66, but this disclosure is not limited thereto. The charge storage region 66 and the upper conductive layer 70 may not completely fill the first opening OP1 and the second opening OP2. In a top view, the charge storage region 66 and the upper conductive layer 70 can be positioned on both sides of the upper insulating pattern 52 and can be arranged alternately in the Y direction.

[0111] The charge storage region 66 and the upper conductive layer 70 may include a conductive material. In an example embodiment, the charge storage region 66 and the upper conductive layer 70 may include a metallic material, but this disclosure is not limited thereto. In an example embodiment, the charge storage region 66 and the upper conductive layer 70 may include an oxide semiconductor material, such as IGZO.

[0112] refer to Figure 27A and Figure 27B A channel material layer 72p can be formed. The channel material layer 72p can fill the first opening OP1 and the second opening OP2, and can contact the upper surface of the charge storage region 66 and the upper surface of the upper conductive layer 70. After forming the channel material layer 72p, a planarization process can be performed to expose the upper insulating pattern 52 and the upper capping layer 64. The channel material layer 72p can include an oxide semiconductor material, such as IGZO.

[0113] refer to Figure 28A and Figure 28B The channel material layer 72p can be patterned to form an upper channel pattern 72, and an insulating structure 74 can be formed between the upper channel patterns 72. The insulating structures 74 can extend in the X direction and can be spaced apart from each other in the Y direction. The insulating structures 74 can spatially and electrically isolate the upper channel patterns 72. The insulating structures 74 can extend from the upper surface of the upper channel patterns 72 in the vertical direction and can contact the upper surface of the spacer structure 44. The insulating structure 74 can include, for example, silicon oxide.

[0114] The upper channel patterns 72 can be spaced apart from each other in the X and Y directions. Each upper channel pattern 72 can be in contact with the upper surface of a charge storage region 66 and the upper surface of an upper conductive layer 70.

[0115] refer to Figure 29A and Figure 29B It can be flipped Figure 28A and Figure 28BThe resulting structure can be obtained by removing the insulating layer 8 to expose the dielectric material layer 30p. A portion of the dielectric material layer 30p can be removed to expose the gate material layer 32p. The gate material layer 32p can be etched back to form the lower gate electrode 32. The lower portion 67 of the charge storage region 66 can also be partially etched by the back etching process. The lower portion 67 of the charge storage region 66 can be etched simultaneously with the gate material layer 32p, or it can be etched by a process separate from the back etching process of the gate material layer 32p.

[0116] An insulating material layer can be formed to cover the lower gate electrode 32 and the lower portion 67 of the charge storage region 66. The insulating material layer can be integrally formed with an insulating material layer 34p covering the side surface of the gate material layer 32p to form a lower capping layer 34. Although the lower capping layer 34 is... Figure 29A The lower cover layer 34 is shown as being formed of a single layer, but this disclosure is not limited thereto. According to an example embodiment, the lower cover layer 34 may be formed of multiple layers. The insulating material layer covering the lower portion 67 of the charge storage region 66 may be referred to as the lower insulating layer 69.

[0117] Refer again Figures 3 to 6C A conductive structure 80 can be formed to manufacture a semiconductor device 100. The conductive structure 80 can contact and be electrically connected to the lower channel pattern 12. The conductive structure 80 may include a first conductive layer 80a in contact with the lower channel pattern 12 and a second conductive layer 80b located below the first conductive layer 80a.

[0118] In the example embodiment, prior to forming the conductive structure 80, impurities can be implanted into the lower channel pattern 12 via an ion implantation process to form the second source / drain region 12b (see [link]). Figure 6B In an example embodiment, a polysilicon layer including impurities may be further disposed between the lower channel pattern 12 and the first conductive layer 80a. The impurities included in the polysilicon layer may be diffused into the interior of the lower channel pattern 12 by an annealing process to form a second source / drain region 12b.

[0119] This disclosure is not limited to the above embodiments and drawings, but is defined by the appended claims. Therefore, those skilled in the art can make various substitutions, modifications, changes, and combinations to the exemplary embodiments without departing from the scope of this disclosure as defined by the appended claims, and such substitutions, modifications, or changes should be interpreted as being included within the scope of this disclosure.

Claims

1. A semiconductor device, the semiconductor device comprising: Lower channel pattern, the lower channel pattern extending in the vertical direction; A lower gate electrode, wherein the lower gate electrode overlaps with the lower channel pattern in a first horizontal direction; An upper groove pattern, wherein the upper groove pattern overlaps with the lower groove pattern in the vertical direction; An upper gate electrode, wherein the upper gate electrode overlaps with the upper channel pattern in the first horizontal direction; as well as A charge storage region that extends in the vertical direction and contacts the upper channel pattern. The lower channel pattern includes a first source / drain region, a second source / drain region spaced apart from the first source / drain region in the vertical direction, and a channel region located between the first source / drain region and the second source / drain region. At least a portion of the charge storage region overlaps with the lower channel pattern in a second horizontal direction intersecting the first horizontal direction.

2. The semiconductor device according to claim 1, wherein, The lower part of the charge storage region is adjacent to the side surface of the lower channel pattern, and The upper part of the charge storage region is in contact with the upper channel pattern.

3. The semiconductor device according to claim 2, wherein, The horizontal width of the lower part of the charge storage region is different from the horizontal width of the upper part of the charge storage region.

4. The semiconductor device according to claim 2, wherein, The upper portion of the charge storage region overlaps with the upper gate electrode in the first horizontal direction.

5. The semiconductor device according to claim 1, further comprising: The bitline structure is located between the lower channel pattern and the upper channel pattern. The bit line structure is in contact with the upper surface of the lower channel pattern.

6. The semiconductor device according to claim 5, further comprising: An upper conductive layer is provided, which is in contact with the upper surface of the bit line structure and the lower surface of the upper channel pattern. The upper surface of the upper conductive layer is positioned at the same height as the upper surface of the charge storage region.

7. The semiconductor device according to claim 5, further comprising: A spacer structure that covers the side surface of the bit line structure and is disposed between the charge storage region and the bit line structure. The upper end of the spacer structure is positioned at a height higher than the upper surface of the bit line structure.

8. The semiconductor device according to claim 7, wherein, The upper channel pattern includes a first lower portion that contacts the charge storage region and a second lower portion that overlaps with the bit line structure in the vertical direction. The first lower portion and the second lower portion are spaced apart, and the spacer structure is located between the first lower portion and the second lower portion.

9. The semiconductor device according to claim 1, wherein, The lower channel pattern comprises a material different from the upper channel pattern.

10. The semiconductor device according to claim 1, wherein, The charge storage region comprises a material different from the upper channel pattern.

11. The semiconductor device according to claim 1, wherein, The vertical length of the lower gate electrode varies depending on the distance from the side surface of the lower channel pattern.

12. The semiconductor device according to claim 1, further comprising: A conductive layer is disposed on at least one of the lower surface or the upper surface of the lower gate electrode, and comprises a material different from that of the lower gate electrode.

13. The semiconductor device according to claim 11, wherein, The charge storage region comprises the same material as the upper channel pattern and is integrally formed with the upper channel pattern.

14. A semiconductor device, the semiconductor device comprising: Lower channel patterns, which extend in a vertical direction and are spaced apart from each other in a first horizontal direction; The lower gate electrode is adjacent to the lower channel pattern in a second horizontal direction intersecting the first horizontal direction and extends in the first horizontal direction; An upper groove pattern, wherein the upper groove pattern overlaps with the lower groove pattern in the vertical direction; An upper gate electrode, which is adjacent to the upper channel pattern in the second horizontal direction and extends in the first horizontal direction; as well as A charge storage region that extends in the vertical direction and contacts the lower surface of the upper channel pattern. The lower part of the charge storage region is alternately arranged with the lower channel pattern in the first horizontal direction.

15. The semiconductor device of claim 14, further comprising: A bitline structure extending in the second horizontal direction between the lower groove pattern and the upper groove pattern. The bit line structure is in contact with the upper surface of the lower channel pattern.

16. The semiconductor device according to claim 15, wherein, The upper part of the charge storage region is alternately disposed with the bit line structure in the first horizontal direction.

17. The semiconductor device of claim 15, further comprising: An upper conductive layer is alternately disposed along the upper part of the charge storage region in the first horizontal direction. The upper conductive layer is in contact with the upper surface of the bit line structure and the lower surface of the upper channel pattern.

18. The semiconductor device of claim 14, further comprising: A dielectric pattern located between the lower channel pattern and the charge storage region.

19. The semiconductor device according to claim 14, wherein, The charge storage region includes a first charge storage region and a second charge storage region that are adjacent to each other in the first horizontal direction, and The lower channel pattern located between the first charge storage region and the second charge storage region is configured to be closer to the first charge storage region than to the second charge storage region.

20. A semiconductor device, the semiconductor device comprising: Lower channel pattern, the lower channel pattern extending in the vertical direction; A conductive structure that is in contact with the lower surface of the lower channel pattern; A lower gate electrode, wherein the lower gate electrode overlaps with the lower channel pattern in a first horizontal direction; An upper groove pattern, wherein the upper groove pattern overlaps with the lower groove pattern in the vertical direction; Bit line structure, the bit line structure being located between the lower groove pattern and the upper groove pattern; An upper gate electrode, wherein the upper gate electrode overlaps with the upper channel pattern in the first horizontal direction; A charge storage region that extends in the vertical direction and contacts the upper channel pattern; A dielectric pattern, wherein the dielectric pattern is located between the lower part of the charge storage region and the lower channel pattern; as well as A spacer structure is provided, located above the charge storage region and between the bit line structure. Wherein, at least a portion of the charge storage region overlaps with the lower channel pattern in a second horizontal direction intersecting the first horizontal direction.

Images