A dual transistor memory and its production method and control method
By using an array-arranged dual-crystal memory cell structure and control method, the problems of large space occupation and low device density of dual-transistor memory are solved, achieving the effects of reduced chip area, reduced cost and reduced power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Filing Date
- 2026-04-07
- Publication Date
- 2026-07-10
AI Technical Summary
Existing dual-transistor memories occupy a large space, have low device density, and high production costs.
The dual-crystal memory cell structure is arranged in an array. The write transistor and read transistor are composed of two metal layer patterns and two active layer patterns. The drain of the write transistor serves as the top gate of the read transistor. Combined with the design of vertical bit lines and control lines, the coverage area of the metal layer patterns and parasitic capacitance are reduced.
It significantly reduces chip area, increases device density, lowers production costs and power consumption, simplifies wiring design, and improves product yield and data security.
Smart Images
Figure CN122373341A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of transistor technology, and in particular to a dual-transistor memory and its manufacturing and control methods. Background Technology
[0002] Dual-transistor indium gallium zinc oxide (IGZO) DRAM is a recognized promising technology. Utilizing the extremely low off-state current of indium gallium zinc and other oxide thin-film transistors, a very small amount of charge can be held for a sufficiently long time. Therefore, a separate capacitor is unnecessary; the parasitic capacitance of the read transistor is used to store the charge, achieving a hold time far exceeding that of silicon-based transistors. By connecting the drain of the write transistor to the gate of the read transistor, the write voltage can control the on-state current of the read transistor, thus enabling lossless reading.
[0003] However, the existing planar 2T0C memory cells still occupy a large area, and compared with other existing technical solutions, such as silicon-based DRAM 6F2, the density is still too low and the production cost is high.
[0004] Therefore, how to further reduce the space footprint of dual-transistor memories, increase device density, and reduce production costs is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0005] The purpose of this invention is to provide a dual-transistor memory and its manufacturing and control methods to solve the problems of large space occupation and low device density in existing dual-transistor memories.
[0006] To solve the above-mentioned technical problems, the present invention provides a dual-transistor memory, including dual-crystal memory cells arranged in an array;
[0007] The dual-crystal memory cell includes, from bottom to top, a first metal layer pattern, a first active layer pattern, a second active layer pattern, and a second metal layer pattern;
[0008] The second metal layer pattern and the second active layer pattern together form a write transistor;
[0009] The second active layer pattern, the first metal layer pattern, and the first active layer pattern together constitute a read transistor; wherein, the first metal layer pattern is the bottom gate of the read transistor, and the drain region of the write transistor in the second active layer pattern is the top gate of the read transistor.
[0010] Optionally, in the dual-transistor memory, the dual-transistor memory cell includes a vertical bit line, a write control line, and a read control line;
[0011] The vertical bit line extends in the thickness direction of the dual-crystal memory cell;
[0012] The write control line is a second metal layer pattern extending in the extension direction of the dual-crystal memory cell;
[0013] The read control line is a first metal layer pattern extending in the extension direction of the dual-crystal memory cell.
[0014] Optionally, in the dual-transistor memory, a single dual-transistor memory cell includes only one read-write multiplexed bit line.
[0015] Optionally, in the dual-transistor memory, both the first metal layer pattern and the second metal layer pattern extend along a first direction.
[0016] Optionally, in the dual-transistor memory, the first active layer pattern and the second metal layer pattern extend along a first direction;
[0017] The second active layer pattern extends along the second direction;
[0018] The first metal layer pattern includes a strip-shaped body extending along the second direction, and a branch protrusion connected to the strip-shaped body and extending along the first direction;
[0019] The first direction is perpendicular to the second direction.
[0020] A method for manufacturing a dual-transistor memory, the method being used to manufacture any of the dual-transistor memories described above, comprising:
[0021] A patterned metal layer is prepared to obtain the first metal layer pattern;
[0022] The first active layer pattern is formed on the surface of the first metal layer;
[0023] A second active layer pattern is disposed on the surface of the first active layer pattern, and the second active layer pattern, the first metal layer pattern, and the first active layer pattern constitute a readout transistor;
[0024] The second metal layer pattern is disposed on the surface of the second active layer pattern, and the second metal layer pattern and the second active layer pattern constitute a write transistor.
[0025] Optionally, in the method for manufacturing the dual-transistor memory, the first metal layer pattern includes a strip-shaped main body and branch protrusions;
[0026] Accordingly, the fabrication of the patterned metal layer to obtain the first metal layer pattern includes:
[0027] The strip-shaped main body and the branch protrusions are obtained through two metal patterning settings.
[0028] Optionally, in the method for manufacturing the dual-transistor memory, the strip-shaped main body and the branch protrusion are obtained through two metal patterning steps, including:
[0029] The strip-shaped main body is obtained through the first metal patterning;
[0030] The branch protrusions are obtained by a second metal patterning process on the strip-shaped body.
[0031] Optionally, in the method for manufacturing the dual-transistor memory, the second active layer pattern is a strip pattern that continuously extends through multiple dual-transistor memory cells in the extension direction;
[0032] Accordingly, the second metal layer pattern is formed on the surface of the second active layer pattern, including:
[0033] The second metal layer pattern and the third metal layer pattern are disposed on the surface of the second active layer pattern; the third metal layer pattern spans the second active layer pattern and forms an isolation transistor that is always in the off state in the adjacent dual-crystal memory cell.
[0034] A control method for a dual-transistor memory, the control method for the dual-transistor memory being used to control any of the above-described dual-transistor memories, comprising:
[0035] Turn off the odd-numbered read control line and read the data in the dual-crystal memory cell between two adjacent read control lines;
[0036] Turn off the even-numbered read control line and read the data in the dual-crystal memory cell between two adjacent read control lines.
[0037] The dual-transistor memory provided by this invention includes an array of dual-transistor memory cells. Each dual-transistor memory cell, from bottom to top, includes a first metal layer pattern, a first active layer pattern, a second active layer pattern, and a second metal layer pattern. The second metal layer pattern and the second active layer pattern form a write transistor. The second active layer pattern, the first metal layer pattern, and the second active layer pattern form a read transistor. The first metal layer pattern serves as the bottom gate of the read transistor, and the drain region of the write transistor in the second active layer pattern serves as the top gate of the read transistor. This invention uses two metal layer patterns and two active layer patterns to form the write transistor and the read transistor, and directly uses the drain of the write transistor as the top gate of the read transistor, thereby significantly reducing the space occupied by the two-transistor structure and effectively improving the device density of the dual-transistor memory compared to other related technologies. This invention also provides a method for manufacturing and controlling a dual-transistor memory with the above-mentioned beneficial effects. Attached Figure Description
[0038] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0039] Figure 1 A cross-sectional structural schematic diagram of a specific embodiment of the dual-transistor memory provided by the present invention;
[0040] Figure 2 A cross-sectional structural diagram of another specific embodiment of the dual-transistor memory provided by the present invention;
[0041] Figure 3 A partial structural schematic diagram of a specific embodiment of the dual-transistor memory provided by the present invention;
[0042] Figure 4 A flowchart illustrating a specific embodiment of the manufacturing method for a dual-transistor memory provided by the present invention;
[0043] Figure 5 A partial structural schematic diagram of another specific embodiment of the dual-transistor memory provided by the present invention;
[0044] Figure 6 A cross-sectional structural schematic diagram of another specific embodiment of the dual-transistor memory provided by the present invention;
[0045] Figure 7A partial structural schematic diagram of another specific embodiment of the dual-transistor memory provided by the present invention;
[0046] Figure 8 This is a flowchart illustrating a specific embodiment of the control method for a dual-transistor memory provided by the present invention.
[0047] Figure label:
[0048] M1 - First metal layer pattern; M2 - Second metal layer pattern; A1 - First active layer pattern; A2 - Second active layer pattern; M1-1 - Strip-shaped main body; M1-2 - Branch protrusion; M3 - Third metal layer pattern. Detailed Implementation
[0049] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0050] The core of this invention is to provide a dual-transistor memory, the structural schematic diagram of one specific embodiment of which is shown below. Figures 1 to 3 As shown, this is referred to as Specific Implementation Method 1, which includes dual-crystal memory cells arranged in an array.
[0051] The dual-crystal memory cell includes, from bottom to top, a first metal layer pattern M1, a first active layer pattern A1, a second active layer pattern A2, and a second metal layer pattern M2;
[0052] The second metal layer pattern M2 and the second active layer pattern A2 together form a write transistor;
[0053] The second active layer pattern A2, the first metal layer pattern M1, and the first active layer pattern A1 constitute a read transistor; wherein, the first metal layer pattern M1 is the bottom gate of the read transistor, and the drain region of the write transistor in the second active layer pattern A2 is the top gate of the read transistor.
[0054] By setting the drain region of the write transistor in the second active layer pattern A2 as the top gate of the read transistor, the present invention achieves compatibility with low-resistance metal materials (such as copper) for signal transmission, greatly improving the versatility of the present invention.
[0055] In one specific implementation, the dual-transistor memory cell includes a vertical bit line, a write control line, and a read control line;
[0056] The vertical bit line extends in the thickness direction of the dual-crystal memory cell;
[0057] The write control line is a second metal layer pattern M2 extending in the extension direction of the dual-crystal memory cell;
[0058] The read control line is a first metal layer pattern M1 extending in the extension direction of the dual crystal memory cell.
[0059] You can refer to this. Figure 3 In this specific embodiment, the specific functions of the first metal layer pattern M1 and the second metal layer pattern M2 are clarified, and the bit line is further specified to be a bit line perpendicular to the memory cell array. This is equivalent to limiting that in the dual transistor memory, each layer of the memory cell array has only two metal lines in its plane: the write control line and the read control line. This greatly reduces the coverage area of the metal layer pattern in the plane, which in turn significantly reduces the parasitic capacitance in the plane, thereby reducing the power consumption and shortening the latency of the memory.
[0060] Furthermore, each of the dual-transistor memory cells includes only one read-write multiplexed bit line.
[0061] In this specific embodiment, only one bit line is used to read and write the memory cell, which directly halves the number of bit lines, making the wiring more compact and significantly reducing the chip area. At the same time, it can further reduce circuit complexity and parasitic capacitance and parasitic resistance.
[0062] Furthermore, both the first metal layer pattern M1 and the second metal layer pattern M2 extend along the first direction.
[0063] That is, the first metal layer pattern M1 and the second metal layer pattern M2 are arranged in parallel. The parallel arrangement of the two metal layer patterns can not only reduce the design and processing difficulty of the metal patterns on the chip and reduce the possibility of short circuits in the metal layer patterns, but also further reduce the overlapping area of the metal layer patterns, further reduce parasitic capacitance, and reduce memory power consumption and latency.
[0064] In another specific implementation, the first active layer pattern A1 and the second metal layer pattern M2 extend along a first direction;
[0065] The second active layer pattern A2 extends along the second direction;
[0066] The first metal layer pattern M1 includes a strip-shaped body M1-1 extending along the second direction, and a branch protrusion M1-2 connected to the strip-shaped body M1-1 and extending along the first direction.
[0067] The first direction is perpendicular to the second direction.
[0068] You can continue to refer to this. Figure 3 In this specific embodiment, the extension direction and structure of the first active layer pattern A1, the second metal layer pattern M2, the second active layer pattern A2 and the first metal layer pattern M1 are defined. With the first direction and the second direction as reference benchmarks, the chip structure design is facilitated, the design cost is reduced and the yield of the finished product is improved.
[0069] Please refer to all factors. Figure 1 , Figure 2 and Figure 3 ,like Figure 3 As shown, Figure 3 This is a schematic diagram of a planar structure of a specific embodiment of the dual-transistor memory. The diagram shows four transistors forming two 2TOC cells, with an area of 4F*4F=16F. 2 (a single transistor in) Figure 3 (Extended by a dashed box), therefore the area of each storage unit is 8F. 2 It is much smaller than the transistor area occupied by existing related technologies. Furthermore, Figure 3 A cross-sectional diagram at position A-A' is shown below. Figure 1 As shown, the second metal layer pattern M2 and the second active layer pattern A2 form a write transistor, where the drain is represented by Drain, the source by Source, and the gate by Channel. When a high level is applied to the second metal layer pattern M2, the write transistor turns on, writing the signal from the vertical bit line (Via) into the drain. The drain region of the second active layer pattern A2, together with the first active layer pattern A1 and the first metal layer pattern M1, forms a small capacitor to store charge. Then, a low level is applied to the second metal layer pattern, storing the charge in the drain region of the second active layer pattern A2, completing the data writing process. Figure 2 As shown Figure 3 The cross-sectional diagram at position B-B' shows that the second active layer pattern A2, the first active layer pattern A1, and the first metal layer pattern M1 form a top-bottom dual-gate transistor as the read transistor. The drain region of the second active layer pattern A2 is the corresponding top gate, and the first metal layer pattern M1 is the corresponding bottom gate. When writing data, the first metal layer pattern M1 remains at a low level, and the read transistor is off, keeping the two bit lines independent. When reading data, the first metal layer pattern M1 rises to a high level, and the read transistor is on. However, the read current is still related to the voltage of the top gate (i.e., the drain region of the second active layer pattern A2). The higher the voltage, the larger the current. Therefore, the level of data stored in the drain region of the second active layer pattern A2 can be deduced from the read current.
[0070] The dual-transistor memory provided by this invention includes an array of dual-transistor memory cells. Each dual-transistor memory cell, from bottom to top, includes a first metal layer pattern M1, a first active layer pattern A1, a second active layer pattern A2, and a second metal layer pattern M2. The second metal layer pattern M2 and the second active layer pattern A2 form a write transistor. The second active layer pattern A2, the first metal layer pattern M1, and the first active layer pattern A1 form a read transistor. The first metal layer pattern M1 serves as the bottom gate of the read transistor, and the drain region of the write transistor in the second active layer pattern A2 serves as the top gate of the read transistor. This invention uses two metal layer patterns and two active layer patterns to form both a write transistor and a read transistor, and directly uses the drain of the write transistor as the top gate of the read transistor, thereby significantly reducing the space occupied by the two-transistor structure and effectively improving the device density of the dual-transistor memory compared to other related technologies.
[0071] The present invention also provides a method for manufacturing a dual-transistor memory, the flowchart of one specific embodiment of which is shown below. Figure 4 As shown, referred to as Specific Embodiment Two, the method for producing the dual-transistor memory is used to produce any of the dual-transistor memories described above, comprising:
[0072] S101: Prepare a patterned metal layer to obtain the first metal layer pattern M1.
[0073] S102: The first active layer pattern A1 is formed on the surface of the first metal layer.
[0074] S103: A second active layer pattern A2 is disposed on the surface of the first active layer pattern A1, and the second active layer pattern A2, the first metal layer pattern M1 and the first active layer pattern A1 constitute a readout transistor.
[0075] S104: The second metal layer pattern M2 is disposed on the surface of the second active layer pattern A2, and the second metal layer pattern M2 and the second active layer pattern A2 form a write transistor.
[0076] In a preferred embodiment, the first metal layer pattern M1 includes a strip-shaped main body M1-1 and branch protrusions M1-2;
[0077] Accordingly, the fabrication of the patterned metal layer to obtain the first metal layer pattern M1 includes:
[0078] The strip-shaped main body M1-1 and the branch protrusion M1-2 are obtained through two metal patterning settings.
[0079] In this specific embodiment, the first metal layer pattern M1 is not a straight strip-shaped metal structure, but a strip-shaped structure with many "serrations" (i.e., the branch protrusions M1-2). If a complex-shaped first metal layer pattern M1 is obtained through a single etching process, the manufacturing process becomes significantly more difficult. In this preferred embodiment, the first metal layer pattern M1 is divided into two parts and patterned separately: one part is a strip-shaped structure without serrations, and the other part is a short dot-shaped structure. These two parts are directly overlapped to obtain the first metal layer pattern M1. The strip-shaped main body M1-1 can be made of a low-resistance metal, and its thickness can be maximized to reduce resistance. The branch protrusions M1-2 have no resistance requirements and can be made of other metal materials, while their thickness can be minimized. (See reference...) Figure 5 , Figure 5 In order to be in Figure 3 Based on this, a structural diagram showing the result after disassembling the first metal layer pattern M1 is provided. Figure 6 for Figure 5 The corresponding cross-sectional view.
[0080] Furthermore, the strip-shaped main body M1-1 and the branch protrusion M1-2 are obtained through two metal patterning settings, including:
[0081] A1: The strip-shaped main body M1-1 is obtained through the first metal patterning.
[0082] A2: The branch protrusion M1-2 is obtained by a second metal patterning on the strip-shaped main body M1-1.
[0083] In this preferred embodiment, the strip-shaped main body M1-1 is first set, and then the branch protrusion M1-2 is set on the strip-shaped main body M1-1. This simplifies the process and further improves the yield of finished products, while reducing the defective rate of subsequent wafers.
[0084] As another specific implementation, the second active layer pattern A2 is a strip pattern that continuously extends through multiple dual-crystal memory cells in the extending direction;
[0085] Accordingly, the second metal layer pattern M2 is formed on the surface of the second active layer pattern A2, including:
[0086] The second metal layer pattern M2 and the third metal layer pattern M3 are disposed on the surface of the second active layer pattern A2; the third metal layer pattern M3 spans across the second active layer pattern A2 and forms an isolation transistor that is always in the off state in the adjacent dual-crystal memory cell.
[0087] You can refer to this. Figure 7 ,contrast Figure 5 , Figure 7 The second active layer pattern A2 is a continuous strip pattern, which greatly simplifies the process of setting the second active layer pattern A2 and improves the yield. In this specific embodiment, the third metal layer pattern M3 is further added. The third metal layer pattern M3 can be set in the same layer as the second metal layer pattern M2. Furthermore, the second metal layer pattern M2 and the third metal layer pattern M3 are the same layer metal layer patterns obtained by the same patterning step.
[0088] The third metal layer pattern M3 is continuously subjected to a low level so as to form an isolation transistor with the second active layer pattern A2 that is always in the off state, ensuring that the signals between different memory cells do not interfere with each other. While reducing the complexity of the pattern design, the isolation of adjacent dual-crystal memory cells is achieved.
[0089] The present invention provides a method for manufacturing a dual-transistor memory, used to produce any of the aforementioned dual-transistor memories. The method involves fabricating a patterned metal layer to obtain a first metal layer pattern M1; depositing a first active layer pattern A1 on the surface of the first metal layer; depositing a second active layer pattern A2 on the surface of the first active layer pattern A1; the second active layer pattern A2, the first metal layer pattern M1, and the first active layer pattern A1 together form a read transistor; and depositing a second metal layer pattern M2 on the surface of the second active layer pattern A2; the second metal layer pattern M2 and the second active layer pattern A2 together form a write transistor. In this invention, two metal layer patterns and two active layer patterns are used to form a write transistor and a read transistor, and the drain of the write transistor is directly used as the top gate of the read transistor, thereby significantly reducing the space occupied by the two-transistor structure and effectively improving the device density of the dual-transistor memory compared to other related technologies.
[0090] The present invention also provides a control method for a dual-transistor memory, the flowchart of one specific embodiment of which is shown below. Figure 8 As shown, the control method for the dual-transistor memory is used to control any of the dual-transistor memories described above, including:
[0091] S201: Turn off the odd-numbered read control line and read the data in the dual-crystal memory cell between two adjacent read control lines.
[0092] S202: Turn off the even-numbered read control line and read the data in the dual-crystal memory cell between two adjacent read control lines.
[0093] It is important to emphasize that when all read control lines are open, the entire column of bit lines will be short-circuited. Therefore, during reading, half of the read control lines must be closed (close every other read control line) to ensure that the bit lines do not interfere with each other, and the other half of the stored data must be read. Then, the first half of the read control lines is opened, the other half is closed, and the remaining half of the stored data is read. That is, in step S201, data is read from the dual-crystal memory cell corresponding to the even-numbered read control line, and in step S202, data is read from the dual-crystal memory cell corresponding to the odd-numbered read control line, thereby improving data security and reducing the possibility of data misreading.
[0094] The present invention provides a control method for a dual-transistor memory, which is used to control any of the aforementioned dual-transistor memories. By turning off the odd-numbered read control lines, data is read from the dual-transistor memory cells between two adjacent read control lines; conversely, by turning off the even-numbered read control lines, data is read from the dual-transistor memory cells between two adjacent read control lines. In this invention, a write transistor and a read transistor are formed using two metal layer patterns and two active layer patterns, and the drain of the write transistor is directly used as the top gate of the read transistor, thereby significantly reducing the space occupied by the two-transistor structure and effectively improving the device density of the dual-transistor memory compared to other related technologies.
[0095] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0096] It should be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0097] The foregoing has provided a detailed description of the dual-transistor memory and its manufacturing and control methods provided by this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.
Claims
1. A dual-transistor memory, characterized in that, Includes dual-crystal memory cells arranged in an array; The dual-crystal memory cell includes, from bottom to top, a first metal layer pattern, a first active layer pattern, a second active layer pattern, and a second metal layer pattern; The second metal layer pattern and the second active layer pattern together form a write transistor; The second active layer pattern, the first metal layer pattern, and the first active layer pattern together constitute a read transistor; wherein, the first metal layer pattern is the bottom gate of the read transistor, and the drain region of the write transistor in the second active layer pattern is the top gate of the read transistor.
2. The dual-transistor memory as described in claim 1, characterized in that, The dual-transistor memory cell includes a vertical bit line, a write control line, and a read control line; The vertical bit line extends in the thickness direction of the dual-crystal memory cell; The write control line is a second metal layer pattern extending in the extension direction of the dual-crystal memory cell; The read control line is a first metal layer pattern extending in the extension direction of the dual-crystal memory cell.
3. The dual-transistor memory as described in claim 2, characterized in that, Each of the dual-transistor memory cells includes only one read-write multiplexed bit line.
4. The dual-transistor memory as described in claim 2, characterized in that, Both the first metal layer pattern and the second metal layer pattern extend along the first direction.
5. The dual-transistor memory as described in claim 2, characterized in that, The first active layer pattern and the second metal layer pattern extend along a first direction; The second active layer pattern extends along the second direction; The first metal layer pattern includes a strip-shaped body extending along the second direction, and a branch protrusion connected to the strip-shaped body and extending along the first direction; The first direction is perpendicular to the second direction.
6. A method for manufacturing a dual-transistor memory, characterized in that, The method for producing the dual-transistor memory is used to produce the dual-transistor memory as described in any one of claims 1 to 5, comprising: A patterned metal layer is prepared to obtain the first metal layer pattern; The first active layer pattern is formed on the surface of the first metal layer; A second active layer pattern is disposed on the surface of the first active layer pattern, and the second active layer pattern, the first metal layer pattern, and the first active layer pattern constitute a readout transistor; The second metal layer pattern is disposed on the surface of the second active layer pattern, and the second metal layer pattern and the second active layer pattern constitute a write transistor.
7. The method for manufacturing a dual-transistor memory as described in claim 6, characterized in that, The first metal layer pattern includes a strip-shaped main body and branch protrusions; Accordingly, the fabrication of the patterned metal layer to obtain the first metal layer pattern includes: The strip-shaped main body and the branch protrusions are obtained through two metal patterning settings.
8. The method for manufacturing a dual-transistor memory as described in claim 7, characterized in that, The strip-shaped main body and the branch protrusions are obtained through two metal patterning steps, including: The strip-shaped main body is obtained through the first metal patterning; The branch protrusions are obtained by a second metal patterning process on the strip-shaped body.
9. The method for manufacturing a dual-transistor memory as described in claim 6, characterized in that, The second active layer pattern is a strip pattern that continuously extends through multiple dual-crystal memory cells in the extending direction; Accordingly, the second metal layer pattern is formed on the surface of the second active layer pattern, including: The second metal layer pattern and the third metal layer pattern are formed on the surface of the second active layer pattern; The third metal layer pattern spans the second active layer pattern and forms an isolation transistor that is always in the off state in the adjacent dual-crystal memory cell.
10. A control method for a dual-transistor memory, characterized in that, The control method for the dual-transistor memory is used to control the dual-transistor memory as described in any one of claims 2 to 5, comprising: Turn off the odd-numbered read control line and read the data in the dual-crystal memory cell between two adjacent read control lines; Turn off the even-numbered read control line and read the data in the dual-crystal memory cell between two adjacent read control lines.