Memory device and operating method thereof, memory system

Abstract

This disclosure provides a memory device and its operation method, as well as a memory system. The memory device includes: a memory cell array including a plurality of memory cells; word lines coupled to the memory cell array; and peripheral circuitry coupled to the memory cell array and the word lines, configured to: apply a programming voltage to selected word lines coupled to a plurality of selected memory cells during a programming time period; apply a first voltage to multiple bit lines coupled to the plurality of selected memory cells during a first time period, wherein the plurality of selected memory cells are not programmed; and reduce the bit lines from the first voltage to a second voltage during a second time period after the first time period, wherein at least some of the selected memory cells are programmed; wherein the first time periods correspond to different bit lines coupled to the plurality of selected memory cells.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, including but not limited to a memory device and its operating method, and a memory system. Background Technology

[0002] In three-dimensional NAND flash memory devices, memory cells can be programmed using charge trapping technology to store data. The amount of data stored in a memory cell depends on the amount of charge trapped in the memory layer. However, miniaturization of three-dimensional NAND flash memory devices becomes increasingly difficult as the number of stacked layers increases.

[0003] Based on industry research, incorporating ferroelectric materials into 3D NAND flash memory devices can improve their reliability and enable further miniaturization. The ferroelectric layer can be positioned between the gate electrode layer and the channel layer to form ferroelectric transistors, thus creating a ferroelectric memory device (FeNAND). The application of ferroelectric memory devices can reduce operating voltage, increase storage density, and significantly reduce manufacturing costs. Currently, there is an urgent need to improve the operating methods of ferroelectric memory devices. Summary of the Invention

[0004] In view of the above, embodiments of the present disclosure provide a memory device and a method for operating the same, as well as a memory system.

[0005] In a first aspect, embodiments of this disclosure provide a memory device, the memory device comprising: a memory cell array including a plurality of memory cells; word lines coupled to the memory cell array; and peripheral circuitry coupled to the memory cell array and the word lines, configured to: apply a programming voltage to selected word lines coupled to a plurality of selected memory cells during a programming time period; apply a first voltage to a plurality of bit lines coupled to the plurality of selected memory cells during a first time period within the programming time period, wherein the plurality of selected memory cells are not programmed; and reduce the bit lines from the first voltage to a second voltage during a second time period within the programming time period and after the first time period, wherein at least some of the selected memory cells are programmed; wherein the first time periods corresponding to the plurality of bit lines coupled to the plurality of selected memory cells are different.

[0006] In some embodiments, the peripheral circuitry further includes: a word line driving circuit coupled to a coupling node of the word line, configured to provide the programming voltage to the selected word line through a selected coupling node of the selected word line; wherein, among the plurality of selected memory cells, the smaller the distance between the selected memory cell and the selected coupling node, the later the selected memory cell is programmed during the application of the programming voltage.

[0007] In some embodiments, among the multiple bit lines coupled to the plurality of selected memory cells, the bit line coupled to the selected memory cell with a smaller distance from the selected coupling node has a larger first time period corresponding to the bit line during the application of the programming voltage.

[0008] In some embodiments, the multiple bit lines coupled to the plurality of selected memory cells include: a first bit line group and a second bit line group, wherein the distance between the selected memory cell coupled to the first bit line group and the selected coupling node is a first distance, and the distance between the selected memory cell coupled to the second bit line group and the selected coupling node is a second distance; wherein the first distance is less than the second distance, and the first time period corresponding to the bit line in the first bit line group is greater than the first time period corresponding to the bit line in the second bit line group.

[0009] In some embodiments, the multiple bit lines coupled to the plurality of selected memory cells further include: a third bit line group disposed between the first bit line group and the second bit line group, wherein the first time period corresponding to the bit line in the first bit line group is greater than the first time period corresponding to the bit line in the third bit line group, and the first time period corresponding to the bit line in the third bit line group is greater than the first time period corresponding to the bit line in the second bit line group.

[0010] In some embodiments, the difference between the first time period corresponding to the bit line in the first bit line group and the first time period corresponding to the bit line in the second bit line group is 1 microsecond to 20 microseconds.

[0011] In some embodiments, among the multiple bit lines coupled to the plurality of selected memory cells, the sum of the first time period and the second time period corresponding to each bit line is the same.

[0012] In some embodiments, the first voltage includes a programmable disable voltage, and the second voltage includes a ground voltage.

[0013] In some embodiments, the memory device further includes a selection transistor disposed between the bit line and the plurality of memory cells; the peripheral circuitry is further configured to apply a pass voltage to the gate of the selected selection transistor during the application of the programming voltage.

[0014] In some embodiments, the memory device includes a ferroelectric memory device, wherein the memory cell includes a channel layer, a gate electrode layer, and a ferroelectric layer disposed between the channel layer and the gate electrode layer.

[0015] Secondly, embodiments of this disclosure provide an operation method for a memory device, the memory device comprising: a memory cell array including a plurality of memory cells; word lines coupled to the memory cell array; and peripheral circuitry coupled to the memory cell array and the word lines; the operation method comprising: during a programming time period, applying a programming voltage to selected word lines coupled to a plurality of selected memory cells; during a first time period within the programming time period, applying a first voltage to a plurality of bit lines coupled to the plurality of selected memory cells, wherein the plurality of selected memory cells are not programmed; during the programming time period and during a second time period after the first time period, reducing the bit lines from the first voltage to a second voltage, wherein at least some of the selected memory cells are programmed; wherein the first time periods corresponding to the plurality of bit lines coupled to the plurality of selected memory cells are different.

[0016] In some embodiments, the peripheral circuitry further includes: a word line driving circuit coupled to a coupling node of the word line, configured to provide the programming voltage to the selected word line through a selected coupling node of the selected word line; wherein, among the plurality of selected memory cells, the smaller the distance between the selected memory cell and the selected coupling node, the later the selected memory cell is programmed during the application of the programming voltage.

[0017] In some embodiments, among the multiple bit lines coupled to the plurality of selected memory cells, the bit line coupled to the selected memory cell with a smaller distance from the selected coupling node has a larger first time period corresponding to the bit line during the application of the programming voltage.

[0018] In some embodiments, the multiple bit lines coupled to the plurality of selected memory cells include: a first bit line group and a second bit line group, wherein the distance between the selected memory cell coupled to the first bit line group and the selected coupling node is a first distance, and the distance between the selected memory cell coupled to the second bit line group and the selected coupling node is a second distance; wherein the first distance is less than the second distance, and the first time period corresponding to the bit line in the first bit line group is greater than the first time period corresponding to the bit line in the second bit line group.

[0019] In some embodiments, the multiple bit lines coupled to the plurality of selected memory cells further include: a third bit line group disposed between the first bit line group and the second bit line group, wherein the first time period corresponding to the bit line in the first bit line group is greater than the first time period corresponding to the bit line in the third bit line group, and the first time period corresponding to the bit line in the third bit line group is greater than the first time period corresponding to the bit line in the second bit line group.

[0020] In some embodiments, the difference between the first time period corresponding to the bit line in the first bit line group and the first time period corresponding to the bit line in the second bit line group is 1 microsecond to 20 microseconds.

[0021] In some embodiments, among the multiple bit lines coupled to the plurality of selected memory cells, the sum of the first time period and the second time period corresponding to each bit line is the same.

[0022] In some embodiments, the first voltage includes a programmable disable voltage, and the second voltage includes a ground voltage.

[0023] In some embodiments, the memory device further includes a selection transistor disposed between the bit line and the plurality of memory cells; the operation method further includes applying a pass voltage to the gate of the selected selection transistor during the application of the programming voltage.

[0024] In some embodiments, the memory device includes a ferroelectric memory device, wherein the memory cell includes a channel layer, a gate electrode layer, and a ferroelectric layer disposed between the channel layer and the gate electrode layer.

[0025] Thirdly, embodiments of this disclosure provide a memory system, the memory system comprising: a memory device as described in the above technical solutions; and a controller coupled to the memory device and configured to control the memory device.

[0026] This disclosure provides a memory device and its operation method, as well as a memory system. The memory device includes: a memory cell array including a plurality of memory cells; word lines coupled to the memory cell array; and peripheral circuitry coupled to the memory cell array and the word lines, configured to: apply a programming voltage to selected word lines coupled to a plurality of selected memory cells during a programming time period; apply a first voltage to multiple bit lines coupled to the plurality of selected memory cells during a first time period, wherein the plurality of selected memory cells are not programmed; and reduce the bit lines from the first voltage to a second voltage during a second time period after the first time period, wherein at least some of the selected memory cells are programmed; wherein the first time periods corresponding to the multiple bit lines coupled to the plurality of selected memory cells are different. In this embodiment of the present disclosure, during a first time period in the programming time period, a first voltage is applied to the bit line, at which time the selected memory cell is not programmed; during a second time period in the programming time period, the bit line is reduced from the first voltage to the second voltage, at which time at least some of the selected memory cells are programmed; the first time periods corresponding to the multiple bit lines coupled to the multiple selected memory cells are different, that is, the actual programming duration of the multiple selected memory cells coupled to the selected word lines is different, thereby achieving compensation for word line delay, and further achieving a narrower threshold voltage distribution width and an increased read window. Attached Figure Description

[0027] Figure 1 Figure (a) is a schematic diagram of a ferroelectric transistor during an erase operation; Figure 1 Figure (b) shows the relationship between drain current and gate voltage during the erase operation; Figure 1 Figure (c) is a schematic diagram of a ferroelectric transistor during programming operations; Figure 1 Figure (d) shows the relationship between drain current and gate voltage during programming operations;

[0028] Figure 2 Figure (a) shows the voltage at the near end and far end of the word line as a function of time. Figure 2 Figure (b) shows a schematic diagram of the proximal and distal ends of the character line; Figure 2 Figure (c) shows the relationship between threshold voltage and word line variation;

[0029] Figure 3 A schematic diagram of a memory device including a memory cell array provided for embodiments of this disclosure;

[0030] Figure 4 A cross-sectional schematic diagram of a storage cell array provided in an embodiment of this disclosure;

[0031] Figure 5 Voltage timing diagrams provided for embodiments of this disclosure;

[0032] Figure 6 A graph showing the relationship between the threshold voltage of a memory device and the word line, provided in an embodiment of this disclosure;

[0033] Figure 7 A block diagram of a memory device including peripheral circuitry provided for embodiments of this disclosure;

[0034] Figure 8 A block diagram of an electronic device provided in an embodiment of this disclosure;

[0035] Figure 9 This is a flowchart illustrating the operation method of a memory device provided in an embodiment of this disclosure. Detailed Implementation

[0036] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0037] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0038] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0039] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0040] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0042] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0043] The following is a brief explanation of the changes in the ferroelectric layer during the application and removal of an external electric field. When an external electric field is applied to the ferroelectric layer, the polarization P follows a hysteresis loop as the applied external electric field strength E changes. More specifically, when a positive external electric field is applied to the ferroelectric layer and the external electric field strength E is gradually increased, the polarization P of the ferroelectric layer also gradually increases until it reaches a saturation state Ps. Afterward, if the external electric field strength E is decreased, when the external electric field strength E is 0, the ferroelectric layer still has remanent polarization Pr. In other words, after removing the positive external electric field, the polarization in the ferroelectric layer does not disappear; the ferroelectric layer still has remanent polarization Pr. If it is necessary to completely depolarize the ferroelectric layer, a negative external electric field needs to be applied until the external electric field strength E reaches the negative coercivity field -Ec. Continuing to increase the external electric field strength E, the polarization P of the ferroelectric layer also gradually increases until it reaches a saturation state -Ps. Subsequently, if the external electric field strength E is reduced, the ferroelectric layer still exhibits negative remanent polarization -Pr when the external electric field strength E is 0. In other words, removing the negative external electric field does not eliminate the polarization in the ferroelectric layer; the ferroelectric layer still possesses remanent polarization -Pr. If it is necessary to completely depolarize the ferroelectric layer, a positive external electric field must be applied until the external electric field strength E reaches the coercive field Ec. In this way, the hysteresis loop can be repeated multiple times to change the polarization direction in the ferroelectric layer. Depending on the direction of spontaneous polarization in the ferroelectric layer, either "0" or "1" can be stored.

[0044] refer to Figure 1 Figures (a) and (b) Figure 1 Figure (a) shows a schematic diagram of a ferroelectric transistor during an erase operation. Figure 1 Figure (b) shows the relationship between drain current (Idrain) and gate voltage (Vgate) during the erase operation. Figure 1As shown in Figure (a), the ferroelectric transistor includes: a source and a drain disposed in a semiconductor layer; a ferroelectric layer disposed above the semiconductor layer, between the source and the drain; and a gate electrode layer disposed above the ferroelectric layer. The semiconductor layer may include a p-type substrate, and the semiconductor layer is doped to form the source and drain, which may be n-type doped regions. The gate electrode layer may include, for example, a metal gate electrode layer. During an erase operation, a positive voltage is applied to the channel of the ferroelectric transistor. When the polarization is upward, the ferroelectric layer induces a positive charge in the channel, resulting in a higher threshold voltage. Figure 1 As shown in Figure (b), the threshold voltage of the ferroelectric transistor increases after the erase operation is performed.

[0045] refer to Figure 1 Figures (c) and (d) Figure 1 Figure (c) is a schematic diagram of a ferroelectric transistor during programming operations. Figure 1 Figure (d) shows the relationship between drain current (Idrain) and gate voltage (Vgate) during programming operations. Figure 1 As shown in Figure (c), the structure of a ferroelectric transistor can be referenced. Figure 1 The relevant descriptions in Figure (a) will not be repeated here. During programming, a positive voltage is applied to the gate electrode layer of the ferroelectric transistor. When the polarization is downward, the ferroelectric layer induces negative charges in the channel, resulting in a lower threshold voltage. For example... Figure 1 As shown in Figure (d), the threshold voltage of the ferroelectric transistor decreases after the programming operation is performed.

[0046] The following explanation, in conjunction with the accompanying diagrams, clarifies the meanings of "voltage settling time," "near end of word line," "far end of word line," and "word line delay" in this document. Voltage settling time refers to the duration between the moment the target voltage is applied to the word line and the moment the word line reaches the target voltage. For example, applying a programming voltage Vpgm to a selected word line at a certain moment does not mean that the voltage of the selected word line will reach the programming voltage Vpgm at that moment. In other words, applying a programming voltage Vpgm to a selected word line at a certain moment indicates that, starting from that moment, the voltage of the selected word line begins to rise in a ramp-up manner, and after the voltage settling time, the voltage of the selected word line reaches the programming voltage Vpgm. The voltage settling time may be the same or different for different word lines.

[0047] The distance between the near end of a word line and the location where the word line receives the target voltage is less than the distance between the far end of the word line and the location where the word line receives the target voltage. For example, at a certain moment, when a programming voltage Vpgm is applied to the selected word line, due to the presence of word line resistance, the near end of the selected word line responds to the target voltage faster than the far end of the selected word line. That is, the time required for the near end of the selected word line to boost to the programming voltage Vpgm from that moment is less than the time required for the far end of the selected word line to boost to the programming voltage Vpgm from that moment.

[0048] refer to Figure 2 Figure (a) Figure 2 Figure (a) shows the voltage change over time at the near and far ends of the word line. Figure 2 As shown in Figure (a), the solid line illustrates the voltage change over time at the near end of the word line, while the dashed line illustrates the voltage change over time at the far end. When a target voltage is applied to the word line, the time it takes for the near end to reach the target voltage is shorter than the time it takes for the far end to reach the target voltage. Thus, during the process of the word line boosting to reach the target voltage, the voltage difference (Sel WL near far gap) between the near and far ends of the word line can be measured at the same time. This voltage difference between the near and far ends of the word line is the word line delay.

[0049] refer to Figure 2 Figures (b) and (c) Figure 2 Figure (b) shows a schematic diagram of the near end and far end of the character line. Figure 2 Figure (c) shows the relationship between the threshold voltage and the word line. For example... Figure 2 As shown in Figure (b), the distance between the word line driver circuit and the memory cell coupled to the near end of the word line is smaller than the distance between the word line driver circuit and the memory cell coupled to the far end of the word line. Figure 2 As shown in Figure (c), the horizontal axis represents the word line and the vertical axis represents the threshold voltage. Due to the influence of word line delay, the threshold voltage difference between the memory cells coupled to the near and far ends of the word line is large, resulting in a wide threshold voltage distribution.

[0050] Ferroelectric memory devices based on ferroelectric transistors achieve programming and erasing operations by controlling the flipping of ferroelectric domains. The flipping speed of ferroelectric domains is very fast, typically around 1 microsecond or less. However, word line delay is usually between 1 and 10 microseconds, significantly longer than the time required for ferroelectric domain flipping. During programming, due to word line delay, the gate voltage of the memory cell coupled to the near end of the word line reaches the target voltage more quickly, resulting in a large number of ferroelectric domain flips. Conversely, the gate voltage of the memory cell coupled to the far end of the word line reaches the target voltage more slowly, with relatively fewer ferroelectric domain flips. This results in a larger threshold voltage difference between the near and far ends of the word line, leading to a wider threshold voltage distribution. Therefore, compared to NAND flash memory devices, word line delay has a greater impact on ferroelectric memory devices; in other words, ferroelectric memory devices are more sensitive to word line delay.

[0051] In view of the above, embodiments of this disclosure provide a memory device and its operation method, as well as a memory system. (See references) Figure 3 , Figure 3 This is a schematic diagram of a memory device including a memory cell array, provided for embodiments of this disclosure. Figure 3 As shown, this disclosure provides a memory device 100, comprising: a memory cell array 102 including a plurality of memory cells 104; a word line 106 (WL) coupled to the memory cell array 102, the word line 106 being selectable which row is affected by read and program operations; a bit line 108 (BL) coupled to the memory cell array 102; and peripheral circuitry 110 coupled to the memory cell array 102, the word line 106, and the bit line 108, configured to: apply a programming voltage Vpgm to selected word lines coupled to a plurality of selected memory cells during a programming time period; apply a first voltage V1 to a plurality of bit lines 108 coupled to a plurality of selected memory cells during a first time period, the plurality of selected memory cells not being programmed; and reduce the bit lines 108 from the first voltage V1 to a second voltage V2 during a second time period after the first time period, at least some of the selected memory cells being programmed; wherein the first time periods corresponding to the plurality of bit lines 108 coupled to a plurality of selected memory cells are different.

[0052] Here, applying a programming voltage Vpgm to the selected word line can perform programming operations on at least a portion of the memory cells coupled to the selected word line. These memory cells that need to be programmed are the selected memory cells.

[0053] Here, the multiple bit lines 108 coupled to multiple selected memory cells may include multiple bit line groups, each bit line group including at least one bit line. The first time period corresponding to the bit lines in each bit line group is the same, and the first time period corresponding to the bit lines in different bit line groups is different.

[0054] like Figure 3 As shown, the peripheral circuit 110 may further include a word line drive circuit 112 coupled to a coupling node 114 of the word line 106, configured to provide a programming voltage Vpgm to the selected word line through the selected coupling node of the selected word line. Here, the coupling node 114 refers to the location where the word line 106 receives the target voltage; that is, when the target voltage is applied to the word line 106, the transmission of the electrical signal will sequentially pass through the coupling node, the near end of the word line, and the far end of the word line. The coupling node 114 is located between the word line 106 and the word line drive circuit 112. The coupling node 114 may refer to a portion of the word line 106, or it may refer to a portion of the lead-out structure of the word line 106.

[0055] In some embodiments, the memory cell array 102 and peripheral circuitry 110 can be fabricated on the same wafer, with the peripheral circuitry 100 located next to the memory cell array 102 (Peripheral Near Core, PNC). In other embodiments, the memory cell array 102 and peripheral circuitry 110 can be fabricated on different wafers, and the two wafers are bonded together to form the memory device 100, with the memory cell array 102 and peripheral circuitry 110 stacked. For example, the peripheral circuitry 100 can be located above the memory cell array 102 (Peripheral Above Core, PAC) or below the memory cell array 102 (Peripheral Under Core, PUC). Regardless of the relative positions of the memory cell array 102 and peripheral circuitry 110, the distance between the selected memory cell and the selected coupling node refers to the distance of electrical signal transmission. A programming voltage Vpgm is applied to the selected word line through the word line driving circuit 112, and the electrical signal transmission sequentially passes through the selected coupling node, the near end of the selected word line, and the far end of the selected word line.

[0056] In some embodiments, storage unit 104 stores string 118 (e.g. Figure 3 The array (shown in the dashed box) is provided, with each memory string 118 extending vertically above the substrate. That is, one memory string 118 corresponds to one channel structure, which will be discussed later in conjunction with... Figure 4A detailed description is provided. Each memory string 118 includes a plurality of memory cells 104 that are series-coupled and vertically stacked. Each memory string 118 may include a source-selective transistor 120 (SST), also referred to as a bottom-selective gate (BSG), at its source end, and a drain-selective transistor 124 (DST), also referred to as a top-selective gate (TSG), at its drain end. The source-selective transistor 120 and the drain-selective transistor 124 may be configured to activate a selected memory string 118 (column of the array) during read and program operations. In other embodiments, multiple channel structures coupled to the same drain-selective gate line collectively form a single memory string.

[0057] In some embodiments, the memory device 100 may further include: a source selective gate line 122 (SSL) coupled to a source selective transistor 120; a drain selective gate line 126 (DSL) coupled to a drain selective transistor 124; and the drain of the drain selective transistor 124 of each memory string 118 coupled to a corresponding bit line 108. Each memory string 118 is configured to be selected or deselected by applying a selection voltage (e.g., higher than a threshold voltage of the drain selective transistor 124) or a deselection voltage (e.g., 0V) to the corresponding drain selective transistor 124 via one or more drain selective gate lines 126; and / or by applying a selection voltage (e.g., higher than a threshold voltage of the source selective transistor 120) or a deselection voltage (e.g., 0V) to the corresponding source selective transistor 120 via one or more source selective gate lines 122.

[0058] In some embodiments, the storage strings 118 may be organized into multiple storage blocks 116, each of which may have a source line 128 (SL) (e.g., a common SL). The sources of the storage strings 118 in the same storage block 116 are coupled through the same source line 128. In other words, in some embodiments, all storage strings 118 in the same storage block 116 have an array common source (ACS).

[0059] refer to Figure 4 , Figure 4 This is a cross-sectional schematic diagram of a storage cell array provided in an embodiment of this disclosure. Figure 4As shown, the memory string 118 can extend vertically through the memory stack layer 204 above the substrate 202. The substrate 202 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0060] Here, the memory stack layer 204 may include alternating gate electrode layers 208 and gate dielectric layers 206. The number of pairs of gate electrode layers 208 and gate dielectric layers 206 in the memory stack layer 204 determines the number of memory cells 104 in the memory cell array 102. The gate electrode layer 208 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate electrode layer 208 includes a metal layer, such as a tungsten layer. In some embodiments, each gate electrode layer 208 includes a doped polysilicon layer. Each gate electrode layer 208 may include a control gate surrounding the memory cell 104 and may extend laterally at the top of the memory stack layer 204 as a drain select gate line 126, at the bottom of the memory stack layer 204 as a source select gate line 122, or between the drain select gate line 126 and the source select gate line 122 as a word line 106.

[0061] like Figure 4 As shown, the memory string 118 includes a channel structure 210 extending vertically through the memory stack layer 204. In some embodiments, the channel structure 210 may have a cylindrical shape (e.g., a pillar shape), and the channel structure 210 includes a ferroelectric layer 212, a channel layer 214, and a fill layer 216 in a radially inward direction. Here, the ferroelectric layer 212 may include a ferroelectric material, such as a transition metal oxide of hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (Ta2O5), tungsten oxide (WO3), molybdenum oxide (MO3), vanadium oxide (V2O3), lanthanum oxide (La2O3), and / or any combination thereof; the channel layer 214 may include a semiconductor material, such as polycrystalline silicon; and the fill layer 216 may include a dielectric material, such as silicon oxide.

[0062] In some embodiments, the memory device 100 includes a ferroelectric memory device, and the memory cell 104 includes a channel layer 214, a gate electrode layer 208, and a ferroelectric layer 212 disposed between the channel layer 214 and the gate electrode layer 208. Here, the memory cell 104 includes a ferroelectric transistor, and the ferroelectric layer 212 can serve as a storage layer, utilizing the polarization state of the ferroelectric layer 212 to store data.

[0063] In some embodiments, the memory cell 104 may further include an interface layer disposed between the ferroelectric layer 212 and the channel layer 214. The interface layer may be used to reduce the possibility of material mixing between the ferroelectric layer 212 and the channel layer 214. The material of the interface layer may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials.

[0064] In some embodiments, the memory cell 104 may further include a barrier layer disposed between the ferroelectric layer 212 and the gate electrode layer 208, the barrier layer being used to reduce the interaction between the ferroelectric layer 212 and the gate electrode layer 208. The material of the barrier layer may be, for example, silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials.

[0065] In some embodiments, wells (e.g., P-wells and / or N-wells) may be formed in substrate 202, and the source end of memory string 118 contacts the well. In some embodiments, memory string 118 further includes a channel plug at the drain end of memory string 118. It should be understood that, although in Figure 4 Additional components, not shown in the diagram, can form the memory cell array 102. These additional components include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0066] Return to reference Figure 3 The peripheral circuitry 110 can be coupled to the memory cell array 102 via bit line 108, word line 106, source line 128, source-select-gate line 122, and drain-select-gate line 126. The peripheral circuitry 110 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 102 by applying voltage and / or current signals to each target memory cell 104 and sensing voltage and / or current signals from each target memory cell 104 via bit line 108, word line 106, source line 128, source-select-gate line 122, and drain-select-gate line 126. The peripheral circuitry 110 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0067] It should be noted that, in this article, "programming time period" refers to the process of performing programming operations on the selected word line, including applying a programming voltage Vpgm to the selected word line, the voltage ramping up to the programming voltage Vpgm, and maintaining the voltage of the selected word line at the programming voltage Vpgm. The programming time period includes a first time period and a second time period, with the first time period preceding the second time period.

[0068] In this embodiment, during a first time period, a programming voltage Vpgm is applied to the selected word lines coupled to multiple selected memory cells, and a first voltage V1 is applied to multiple bit lines coupled to the multiple selected memory cells. At this time, the difference between the programming voltage Vpgm and the first voltage V1 is insufficient to program the selected memory cells; therefore, the multiple selected memory cells are not programmed. During a second time period, the programming voltage Vpgm is applied to the selected word lines coupled to the multiple selected memory cells, and the bit line 108 is reduced from the first voltage V1 to the second voltage V2. At this time, the difference between the programming voltage Vpgm and the second voltage V2 is sufficient to program the selected memory cells; therefore, at least some of the selected memory cells are programmed. In other words, the second time period corresponds to the actual programming duration of the selected memory cells. The actual programming durations of the multiple selected memory cells coupled to the selected word lines are different, thereby achieving compensation for word line delay, and further achieving a narrower threshold voltage distribution width and an increased read window.

[0069] In some embodiments, the first voltage V1 includes the programmable inhibit voltage Vinhibit, and the second voltage V2 includes the ground voltage VSS.

[0070] Here, the difference between the programming voltage Vpgm and the inhibit programming voltage Vinhibit is insufficient to program the selected memory cell; therefore, the selected memory cell, where both the selected word line and bit line are coupled, will not be programmed. The difference between the programming voltage Vpgm and the ground voltage VSS is sufficient to program the selected memory cell; in this case, the selected memory cell, where both the selected word line and bit line are coupled, will be programmed. This disclosure does not impose any specific limitations on the specific values ​​of the first voltage V1 and the second voltage V2; they are merely illustrative examples illustrating that the difference between the programming voltage Vpgm and the inhibit programming voltage Vinhibit can achieve the effect of inhibiting programming of the selected memory cell, and that the difference between the programming voltage Vpgm and the ground voltage VSS can achieve the effect of programming the selected memory cell.

[0071] In some embodiments, among the multiple selected memory cells coupled to the selected word line, the smaller the distance between the selected memory cell and the selected coupling node, that is, the closer the selected memory cell is to the near end of the selected word line, the faster the selected memory cell coupled to the near end of the selected word line responds to the programming voltage; and the later the selected memory cell is programmed during the application of the programming voltage, that is, the shorter the actual programming time of the selected memory cell coupled to the near end of the selected word line. Here, the distance between the selected memory cell and the selected coupling node refers to the distance of electrical signal transmission, that is, the distance the electrical signal travels through the selected coupling node and the selected memory cell.

[0072] Here, the greater the distance between the selected memory cell and the selected coupling node, that is, the more the selected memory cell is coupled to the far end of the selected word line, the slower the selected memory cell coupled to the far end of the selected word line responds to the programming voltage; the earlier the selected memory cell is programmed during the application of the programming voltage, that is, the longer the actual programming time of the selected memory cell coupled to the far end of the selected word line.

[0073] In some embodiments, among the multiple bit lines coupled to multiple selected memory cells, the bit lines coupled to selected memory cells with smaller distances to selected coupling nodes, for example, the selected memory cells coupled to the near-end bit lines have smaller distances to the selected coupling nodes. These selected memory cells are coupled to the near end of the selected word line and respond to programming voltage faster. During the application of programming voltage, the first time period corresponding to the near-end bit lines is larger (or the second time period corresponding to the near-end bit lines is smaller), that is, the actual programming time of the selected memory cells coupled to the near-end bit lines is smaller.

[0074] Here, the bit line coupled to the selected memory cell with a larger distance from the selected coupling node, for example, the selected memory cell coupled to the selected coupling node with a far-end bit line has a larger distance from the selected coupling node. This part of the selected memory cell is coupled to the far end of the selected word line and responds to the programming voltage more slowly. During the application of the programming voltage, the smaller the first time period corresponding to the far-end bit line (or the larger the second time period corresponding to the far-end bit line), that is, the longer the actual programming time of the selected memory cell coupled to the far-end bit line.

[0075] Return to reference Figure 3 This document explains the meanings of "near-end bit line" and "far-end bit line" in this article. The distance between the memory cell coupled to a near-end bit line and the coupled node is less than the distance between the memory cell coupled to a far-end bit line and the coupled node. The memory cell coupled to a near-end bit line is coupled to the near end of the word line, and the memory cell coupled to a far-end bit line is coupled to the far end of the word line.

[0076] In this embodiment, the near end of the selected word line responds to the programming voltage Vpgm faster than the far end of the selected word line. The actual programming time of the selected memory cell coupled to the near-end bit line is less than that of the selected memory cell coupled to the far-end bit line, thereby compensating for word line delay, and consequently achieving a narrower threshold voltage distribution width and an increased read window.

[0077] In some embodiments, the multiple bit lines coupled to multiple selected memory cells include at least two bit line groups, each bit line group including at least one bit line. The multiple bit lines coupled to multiple selected memory cells include: a first bit line group and a second bit line group. The distance between the selected memory cell coupled to the first bit line group and the selected coupled node is a first distance, and the distance between the selected memory cell coupled to the second bit line group and the selected coupled node is a second distance; wherein the first distance is less than the second distance. That is, the bit lines included in the first bit line group are near-end bit lines, and the bit lines included in the second bit line group are far-end bit lines. The first time period corresponding to the bit lines in the first bit line group is greater than the first time period corresponding to the bit lines in the second bit line group, and the second time period (i.e., actual programming time) of the selected memory cell coupled to the bit lines in the first bit line group is less than the second time period (i.e., actual programming time) of the selected memory cell coupled to the bit lines in the second bit line group.

[0078] refer to Figure 5 , Figure 5 A voltage timing diagram provided for embodiments of this disclosure. For example... Figure 5 As shown, at the first time T1, an initial programming voltage Vpgm0 is applied to the selected word line, a first voltage V1 is applied to both the near-end bit line (i.e., BL_near-end) and the far-end bit line (i.e., BL_far-end), and a pass voltage Vpass is applied to the drain-select gate line.

[0079] Taking the selected word line as an example, an initial programming voltage Vpgm0 is applied to the selected word line. After a voltage build-up period, the voltage ramp of the selected word line rises to the initial programming voltage Vpgm0. Similarly, the near-end and far-end bit lines also need to undergo a voltage build-up period, and their voltage ramps rise to the first voltage V1; the drain-select-gate line also needs to undergo a voltage build-up period, and its voltage ramp rises to the pass voltage Vpass. The voltage build-up periods experienced during the voltage ramp rise of the selected word line, the near-end bit line, the far-end bit line, and the drain-select-gate line can be the same or different.

[0080] At the second time T2, the programming voltage Vpgm is applied to the selected word line. Figure 5The solid line illustrates the voltage change over time at the near end of the word line, while the dashed line illustrates the voltage change over time at the far end of the word line. Here, considering the relatively large programming voltage Vpgm, the selected word line can be boosted twice to reach the programming voltage Vpgm. At the first time T1, the selected word line is boosted to the initial programming voltage Vpgm0, and at the second time T2, it is boosted again to a programming voltage Vpgm greater than the initial programming voltage Vpgm0.

[0081] At the third moment T3, the voltage at the far end of BL is reduced from the first voltage V1 to the second voltage V2.

[0082] At the fourth time T4, the voltage near the BL_proximal end is reduced from the first voltage V1 to the second voltage V2.

[0083] At time T5, the word line and drain select gate line begin to discharge.

[0084] In some embodiments, the peripheral circuit 110 is further configured to apply a pass voltage Vpass to the gate of the selected selection transistor during the application of the programming voltage Vpgm. Here, the process of applying the programming voltage Vpgm to the selected word line is from a first time point T1 to a fifth time point T5, i.e., the programming time period is from the first time point T1 to the fifth time point T5. The process of applying the pass voltage Vpass to the drain-select gate line (i.e., the gate of the selected selection transistor) is also from the first time point T1 to the fifth time point T5.

[0085] In summary, for the BL_ near end, the first time period is from time 1 to time 4, during which the memory cells coupled to the BL_ near end are not programmed; the second time period is from time 4 to time 5, during which the memory cells coupled to the BL_ near end are programmed. In other words, the actual programming time for the memory cells coupled to the BL_ near end is the second time period, specifically from time 4 to time 5.

[0086] For the BL_remote end, the first time period is from time T1 to time T3, during which the memory cells coupled to the BL_remote end are not programmed; the second time period is from time T3 to time T5, during which the memory cells coupled to the BL_remote end are programmed. In other words, the actual programming time for the memory cells coupled to the BL_remote end is the second time period, specifically from time T3 to time T5.

[0087] In this embodiment, during a first time period, a first voltage V1 (e.g., a programming disable voltage Vinhibit) is applied to all bit lines. During this time, all selected memory cells coupled to the selected word line will not be programmed. During a second time period, the voltage of the bit line corresponding to the selected memory cell coupled to the far end of the word line (i.e., BL_far end) is first reduced, at which point the selected memory cell coupled to BL_far end begins to be programmed first. Then, the voltage of the bit line corresponding to the selected memory cell coupled to the near end of the word line (i.e., BL_near end) is reduced, at which point the selected memory cell coupled to BL_near end begins to be programmed later. The word line delay is compensated for by the difference in the effective programming pulse width (i.e., the actual programming duration) of the selected memory cells coupled to BL_near end and BL_far end, thereby achieving a narrower threshold voltage distribution width. In other words, in this embodiment of the disclosure, the timing of the BL_near end and BL_far end during the programming operation is controlled by the page buffer circuit, thereby controlling the channel potential in the channel structure where the near end of the word line is located, and controlling the channel potential in the channel structure where the far end of the word line is located.

[0088] refer to Figure 6 , Figure 6 A graph showing the relationship between the threshold voltage of a memory device and the word line, provided for embodiments of this disclosure. Figure 6 As shown, the solid line illustrates the voltage change of the word line over time without word line delay compensation, while the dashed line illustrates the voltage change of the word line over time with word line delay compensation. With word line delay compensation, the threshold voltage distribution of the word line is narrower, or the threshold voltage distribution of the word line is more convergent.

[0089] In some embodiments, among the multiple bit lines coupled to multiple selected memory cells, the sum of the first time period and the second time period corresponding to each bit line is the same; that is, the sum of the first time period and the second time period corresponding to each bit line is the programming time period. For example, Figure 5 The programming time period is illustrated by the sum of the first time period (i.e., from time T1 to time T4) and the second time period (i.e., from time T4 to time T5) corresponding to the near end of BL_. Alternatively, the programming time period is the sum of the first time period (i.e., from time T1 to time T3) and the second time period (i.e., from time T3 to time T5) corresponding to the far end of BL_.

[0090] In some embodiments, the multiple bit lines coupled to multiple selected memory cells may further include: a third bit line group located between the first bit line group and the second bit line group, wherein the first time period corresponding to the bit line in the first bit line group is greater than the first time period corresponding to the bit line in the third bit line group, and the first time period corresponding to the bit line in the third bit line group is greater than the first time period corresponding to the bit line in the second bit line group. Here, the distance between the third bit line group and the selected coupled node is the third distance, and the first distance < the third distance < the second distance. The first time period corresponding to the bit line in the first bit line group > the first time period corresponding to the bit line in the third bit line group > the first time period corresponding to the bit line in the second bit line group, that is, the actual programming time of the selected memory cell coupled to the bit line in the first bit line group < the actual programming time of the selected memory cell coupled to the bit line in the third bit line group < the actual programming time of the selected memory cell coupled to the bit line in the second bit line group.

[0091] It should be noted that in this embodiment, the description uses multiple bit lines including a first bit line group, a second bit line group, and a third bit line group as an example. In practice, the multiple bit lines can be grouped into more groups, so that the control process of applying the first voltage V1 and the second voltage V2 to the bit lines can be more precise. It is even possible to treat each bit line as a separate group (i.e., each bit line group includes 1 bit line), and control the timing of each bit line decreasing from the first voltage V1 to the second voltage V2, so as to more accurately compensate for word line delay.

[0092] In some embodiments, the difference between the first time period corresponding to the bit line in the first bit line group and the first time period corresponding to the bit line in the second bit line group (e.g.) Figure 5 The ΔT shown in the diagram is 1 microsecond to 20 microseconds; or, the difference between the actual programming time of the selected memory cell coupled to the bit line in the first bit line group and the actual programming time of the selected memory cell coupled to the bit line in the second bit line group is 1 microsecond to 20 microseconds. Here, taking multiple bit lines coupled to multiple selected memory cells, including two bit line groups, as an example, the difference between the first time period corresponding to the bit line in the first bit line group and the first time period corresponding to the bit line in the second bit line group is 1 microsecond to 20 microseconds. Multiple bit lines coupled to multiple selected memory cells include multiple bit line groups, multiple bit line groups correspond to multiple first time periods, and the difference between the maximum and minimum values ​​in the multiple first time periods is 1 microsecond to 20 microseconds.

[0093] refer to Figure 7 , Figure 7 This is a block diagram illustrating a memory device including peripheral circuitry, as shown in an embodiment of this disclosure. Figure 7As shown, the peripheral circuitry 110 includes a page buffer / sensor amplifier 302, a column driver / bit line driver circuit 304, a row driver / word line driver circuit 306, a voltage generator 308, a control logic unit 310, a register 312, an interface 314 (I / F), and a data bus 316. It should be understood that in some embodiments, it may also include... Figure 7 Additional peripheral circuits not shown in the diagram.

[0094] Page buffer / sensor amplifier 302 can be configured to read data from memory cell array 102 and program (also known as write) data to memory cell array 102 according to control signals from control logic unit 310. In other embodiments, page buffer / sensor amplifier 302 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 104 coupled to selected word line 106. In still other embodiments, page buffer / sensor amplifier 302 can also sense a low-power signal from bit line 108 representing a data bit stored in memory cell 104 and amplify a small voltage swing to a recognizable logic level during read operations. Column driver / bit line driver circuit 304 can be configured to be controlled by control logic unit 310 and select one or more memory strings 118 by applying a bit line voltage generated from voltage generator 308.

[0095] The row driver / word line driver circuit 306 can be configured to be controlled by the control logic unit 310 and to select / deselect memory blocks 116 of the memory cell array 102 and to select / deselect word lines 106 of the memory blocks 116. The row driver / word line driver circuit 306 can also be configured to drive word lines 106 using word line voltages generated from the voltage generator 308. In some embodiments, the row driver / word line driver circuit 306 can also select / deselect and drive source select gate line 122 and drain select gate line 126. As described in detail below, the row driver / word line driver circuit 306 is configured to perform an erase operation on memory cells 104 coupled to (one or more) the selected word lines 106. The voltage generator 308 can be configured to be controlled by the control logic unit 310 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 102.

[0096] Control logic unit 310 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 312 can be coupled to control logic unit 310 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 314 can be coupled to control logic unit 310 and acts as a control buffer to buffer slave devices (…). Figure 7 (Not shown in the diagram) It receives control commands and relays them to control logic unit 310, and buffers status information received from control logic unit 310 and relays it to the host. Interface 314 can also be coupled to column driver / bit line driver circuit 304 via data bus 316, and acts as a data input / output (I / O) interface and data buffer to buffer data and relay it to or from memory cell array 102.

[0097] refer to Figure 8 , Figure 8 A block diagram of an electronic device provided in an embodiment of this disclosure. (As shown) Figure 8 As shown, this disclosure provides a memory system 404 (as shown in the figure). Figure 8 (shown in the dashed box) includes: a memory device 100 as described in the above technical solution; and a controller 406 coupled to the memory device 100 and configured to control the memory device 100.

[0098] In some embodiments, the controller 406 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0099] In some embodiments, the controller 406 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multi-media card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0100] Controller 406 can be configured to control the operation of memory device 100, such as read, erase, and program operations. Controller 406 can also be configured to manage various functions relating to data stored or to be stored in memory device 100, including but not limited to bad block management, garbage collection, logical address to physical address translation, wear leveling, etc. In some embodiments, controller 406 is also configured to process error correcting codes (ECCs) relating to data read from or written to memory device 100.

[0101] Controller 406 may also perform any other suitable function, such as formatting memory device 100. Controller 406 may communicate with external devices (e.g., host 402) according to a specific communication protocol. For example, controller 406 may communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Drive Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0102] The controller 406 and one or more memory devices 100 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 404 can be implemented and packaged into different types of end electronic products.

[0103] This disclosure also provides an electronic device 400, which may include a host 402 and a memory system 404.

[0104] In some embodiments, controller 406 is coupled to memory device 100 and host 402 and is configured to control memory device 100. Controller 406 can manage data stored in memory device 100 and communicate with host 402.

[0105] Here, electronic device 400 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory device therein.

[0106] Here, host 402 can be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). Host 402 can be configured to send data to memory device 100 or receive data from memory device 100.

[0107] refer to Figure 9 , Figure 9 This is a flowchart illustrating the operation method of a memory device provided in an embodiment of this disclosure. Figure 9 As shown, this disclosure provides an operation method for a memory device, the memory device including: a memory cell array including a plurality of memory cells; word lines coupled to the memory cell array; and peripheral circuitry coupled to the memory cell array and the word lines; the operation method includes:

[0108] Step S510: During the programming period, a programming voltage is applied to the selected word line coupled to the multiple selected memory cells;

[0109] Step S520: During the first time period of the programming time period, a first voltage is applied to multiple bit lines coupled to multiple selected memory cells, and the multiple selected memory cells are not programmed;

[0110] Step S530: During the programming time period and in the second time period after the first time period, the bit line is reduced from the first voltage to the second voltage, and at least some of the selected memory cells are programmed; wherein the first time periods correspond to the multiple bit lines coupled to the multiple selected memory cells are different.

[0111] In some embodiments, the peripheral circuitry further includes: a word line driving circuit coupled to a coupling node of the word line, configured to provide a programming voltage to the selected word line through a selected coupling node of the selected word line; wherein, among a plurality of selected memory cells, the smaller the distance between the selected memory cell and the selected coupling node, the later the selected memory cell is programmed during the application of the programming voltage.

[0112] In some embodiments, among the multiple bit lines coupled to multiple selected memory cells, the bit line coupled to the selected memory cell with a smaller distance from the selected coupling node has a larger first time period during the period when the programming voltage is applied.

[0113] In some embodiments, the multiple bit lines coupled to multiple selected memory cells include: a first bit line group and a second bit line group, wherein the distance between the selected memory cell coupled to the first bit line group and the selected coupled node is a first distance, and the distance between the selected memory cell coupled to the second bit line group and the selected coupled node is a second distance; wherein the first distance is less than the second distance, and the first time period corresponding to the bit line in the first bit line group is greater than the first time period corresponding to the bit line in the second bit line group.

[0114] In some embodiments, the multiple bit lines coupled to multiple selected memory cells further include: a third bit line group disposed between the first bit line group and the second bit line group, wherein the first time period corresponding to the bit line in the first bit line group is greater than the first time period corresponding to the bit line in the third bit line group, and the first time period corresponding to the bit line in the third bit line group is greater than the first time period corresponding to the bit line in the second bit line group.

[0115] In some embodiments, the difference between the first time period corresponding to the bit line in the first bit line group and the first time period corresponding to the bit line in the second bit line group is 1 microsecond to 20 microseconds.

[0116] In some embodiments, among the multiple bit lines coupled to multiple selected memory cells, the sum of the first time period and the second time period corresponding to each bit line is the same.

[0117] In some embodiments, the first voltage includes a programmable disable voltage, and the second voltage includes a ground voltage.

[0118] In some embodiments, the memory device further includes a selection transistor disposed between a bit line and a plurality of memory cells; the operation method further includes applying a pass voltage to the gate of the selected selection transistor during the application of a programming voltage.

[0119] In some embodiments, the memory device includes a ferroelectric memory device, wherein the memory cell includes a channel layer, a gate electrode layer, and a ferroelectric layer disposed between the channel layer and the gate electrode layer.

[0120] This disclosure provides a memory device and its operation method, as well as a memory system. The memory device includes: a memory cell array including a plurality of memory cells; word lines coupled to the memory cell array; and peripheral circuitry coupled to the memory cell array and the word lines, configured to: apply a programming voltage to selected word lines coupled to a plurality of selected memory cells during a programming time period; apply a first voltage to multiple bit lines coupled to the plurality of selected memory cells during a first time period, wherein the plurality of selected memory cells are not programmed; and reduce the bit lines from the first voltage to a second voltage during a second time period after the first time period, wherein at least some of the selected memory cells are programmed; wherein the first time periods corresponding to the multiple bit lines coupled to the plurality of selected memory cells are different. In this embodiment of the present disclosure, during the first time period of the programming time period, a first voltage is applied to the bit line, at which time the selected memory cell is not programmed; during the second time period of the programming time period, the bit line is reduced from the first voltage to the second voltage, at which time at least some of the selected memory cells are programmed; the first time periods corresponding to the multiple bit lines coupled to the multiple selected memory cells are different, that is, the actual programming time of the multiple selected memory cells coupled to the selected word lines is different, thereby achieving compensation for word line delay, and further achieving a narrower threshold voltage distribution width and an increased read window.

[0121] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0122] The above description is only a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. All equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A memory device, characterized in that, The memory device includes: A storage cell array, comprising multiple storage cells; Word lines coupled to the memory cell array; The peripheral circuitry coupled to the memory cell array and the word lines is configured as follows: During the programming period, a programming voltage is applied to the selected word line coupled to multiple selected memory cells; During a first time period of the programming time period, a first voltage is applied to multiple bit lines coupled to the plurality of selected memory cells, and the plurality of selected memory cells are not programmed. During the programming time period and in a second time period following the first time period, the bit line is reduced from the first voltage to the second voltage, and at least a portion of the selected memory cells are programmed; wherein the first time periods correspond to different bit lines coupled to the plurality of selected memory cells.

2. The memory device according to claim 1, characterized in that, The peripheral circuit also includes: A word line drive circuit coupled to a coupling node of the word line is configured to provide the programming voltage to the selected word line through a selected coupling node of the selected word line; wherein, among the plurality of selected memory cells, the smaller the distance between the selected memory cell and the selected coupling node, the later the selected memory cell is programmed during the application of the programming voltage.

3. The memory device according to claim 2, characterized in that, Among the multiple bit lines coupled to the plurality of selected memory cells, the bit line coupled to the selected memory cell with a smaller distance from the selected coupling node has a larger first time period corresponding to the bit line during the application of the programming voltage.

4. The memory device according to claim 2, characterized in that, The multiple bit lines coupled to the plurality of selected memory cells include: a first bit line group and a second bit line group. The distance between the selected memory cell coupled to the first bit line group and the selected coupling node is a first distance, and the distance between the selected memory cell coupled to the second bit line group and the selected coupling node is a second distance. The first distance is less than the second distance, and the first time period corresponding to the bit line in the first bit line group is greater than the first time period corresponding to the bit line in the second bit line group.

5. The memory device according to claim 4, characterized in that, The multiple bit lines coupled to the plurality of selected memory cells further include: a third bit line group disposed between the first bit line group and the second bit line group, wherein the first time period corresponding to the bit line in the first bit line group is greater than the first time period corresponding to the bit line in the third bit line group, and the first time period corresponding to the bit line in the third bit line group is greater than the first time period corresponding to the bit line in the second bit line group.

6. The memory device according to claim 4 or 5, characterized in that, The difference between the first time period corresponding to the bit line in the first bit line group and the first time period corresponding to the bit line in the second bit line group is 1 microsecond to 20 microseconds.

7. The memory device according to claim 1, characterized in that, In the multiple bit lines coupled to the plurality of selected memory cells, the sum of the first time period and the second time period corresponding to each bit line is the same.

8. The memory device according to claim 1, characterized in that, The first voltage includes a programmable disable voltage, and the second voltage includes a ground voltage.

9. The memory device according to claim 1, characterized in that, The memory device further includes: a selection transistor disposed between the bit line and the plurality of memory cells; The peripheral circuitry is also configured to apply a pass voltage to the gate of the selected transistor during the application of the programming voltage.

10. The memory device according to claim 1, characterized in that, The memory device includes a ferroelectric memory device, and the memory cell includes a channel layer, a gate electrode layer, and a ferroelectric layer disposed between the channel layer and the gate electrode layer.

11. A method of operating a memory device, characterized in that, The memory device includes: a memory cell array including a plurality of memory cells; word lines coupled to the memory cell array; and peripheral circuitry coupled to the memory cell array and the word lines; the operation method includes: During the programming period, a programming voltage is applied to the selected word line coupled to multiple selected memory cells; During a first time period of the programming time period, a first voltage is applied to multiple bit lines coupled to the plurality of selected memory cells, and the plurality of selected memory cells are not programmed. During the programming time period and in a second time period following the first time period, the bit line is reduced from the first voltage to the second voltage, and at least a portion of the selected memory cells are programmed; wherein the first time periods correspond to different bit lines coupled to the plurality of selected memory cells.

12. The operating method according to claim 11, characterized in that, The peripheral circuitry further includes: a word line driving circuit coupled to a coupling node of the word line, configured to provide the programming voltage to the selected word line through a selected coupling node of the selected word line; wherein, among the plurality of selected memory cells, the smaller the distance between the selected memory cell and the selected coupling node, the later the selected memory cell is programmed during the application of the programming voltage.

13. The operating method according to claim 12, characterized in that, Among the multiple bit lines coupled to the plurality of selected memory cells, the bit line coupled to the selected memory cell with a smaller distance from the selected coupling node has a larger first time period corresponding to the bit line during the application of the programming voltage.

14. The operating method according to claim 12, characterized in that, The multiple bit lines coupled to the plurality of selected memory cells include: a first bit line group and a second bit line group. The distance between the selected memory cell coupled to the first bit line group and the selected coupling node is a first distance, and the distance between the selected memory cell coupled to the second bit line group and the selected coupling node is a second distance. The first distance is less than the second distance, and the first time period corresponding to the bit line in the first bit line group is greater than the first time period corresponding to the bit line in the second bit line group.

15. The operating method according to claim 14, characterized in that, The multiple bit lines coupled to the plurality of selected memory cells further include: a third bit line group disposed between the first bit line group and the second bit line group, wherein the first time period corresponding to the bit line in the first bit line group is greater than the first time period corresponding to the bit line in the third bit line group, and the first time period corresponding to the bit line in the third bit line group is greater than the first time period corresponding to the bit line in the second bit line group.

16. The operating method according to claim 14 or 15, characterized in that, The difference between the first time period corresponding to the bit line in the first bit line group and the first time period corresponding to the bit line in the second bit line group is 1 microsecond to 20 microseconds.

17. The operating method according to claim 11, characterized in that, In the multiple bit lines coupled to the plurality of selected memory cells, the sum of the first time period and the second time period corresponding to each bit line is the same.

18. The operating method according to claim 11, characterized in that, The first voltage includes a programmable disable voltage, and the second voltage includes a ground voltage.

19. The operating method according to claim 11, characterized in that, The memory device further includes: a selection transistor disposed between the bit line and the plurality of memory cells; the operation method further includes: During the application of the programming voltage, a pass voltage is applied to the gate of the selected transistor.

20. The operating method according to claim 11, characterized in that, The memory device includes a ferroelectric memory device, and the memory cell includes a channel layer, a gate electrode layer, and a ferroelectric layer disposed between the channel layer and the gate electrode layer.

21. A memory system, characterized in that, The memory system includes: The memory device as claimed in any one of claims 1 to 10; and A controller coupled to the memory device and configured to control the memory device.

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