Structure with emitter contact wider than emitter terminal and related methods

Abstract

This disclosure provides a structure and related method for having an emitter contact that is wider than the emitter terminal. The structure of this disclosure includes an emitter contact located within an interlayer dielectric (ILD) layer and on the emitter terminal of a bipolar transistor, wherein the horizontal width of the emitter contact is greater than the horizontal width of the emitter terminal located below it.

Description

Technical Field

[0001] This disclosure relates to bipolar transistor structures and methods for forming such structures. Background Technology

[0002] Internet of Things (IoT) devices, wearables, smartphone processors, automotive electronics, and radio frequency integrated circuits (RFICs), including millimeter-wave (mmWave) ICs, can benefit from the inclusion of bipolar junction transistors (BJTs) because BJTs tend to have greater drive power and are generally considered better suited for analog functions than field-effect transistors (FETs). BJTs are typically formed as vertical devices (e.g., having an in-substrate collector, a base including an inner base region aligned above the collector region and an outer base region aligned on the opposite side of the inner base region, and an emitter aligned above the inner base region). In such vertical BJT structures, device size scaling (specifically, emitter region size scaling) is limited by the allowable limits of emitter contact coverage. Summary of the Invention

[0003] The illustrative aspects of this disclosure are designed to address the problems described herein and / or other problems not discussed herein.

[0004] Embodiments of this disclosure provide a structure including: an emitter contact located within an interlayer dielectric (ILD) layer and on the emitter terminal of a bipolar transistor, wherein the horizontal width of the emitter contact is greater than the horizontal width of the emitter terminal located below it.

[0005] Other embodiments of this disclosure provide a structure including: a collector terminal including an epitaxial semiconductor material on a sub-collector; an isolation layer on the sub-collector and adjacent to the collector terminal; a base terminal including: an inner base on the collector terminal, wherein a semiconductor film is located on the inner base; and an outer base adjacent to the semiconductor film and located on the upper surface of the isolation layer and in contact with the inner base; an emitter terminal on the semiconductor film; and an emitter contact located within an interlayer dielectric (ILD) layer and on the emitter terminal, wherein the horizontal width of the emitter contact is greater than the horizontal width of the emitter terminal located below it.

[0006] Additional embodiments of this disclosure provide a method comprising: forming an emitter contact within an interlayer dielectric (ILD) layer and on an emitter terminal of a bipolar transistor, wherein the horizontal width of the emitter contact is greater than the horizontal width of the emitter terminal located below it. Attached Figure Description

[0007] These and other features of the present disclosure will be more readily understood from the following detailed description of various aspects of the present disclosure, taken in conjunction with the accompanying drawings illustrating various embodiments thereof, wherein:

[0008] Figure 1 A cross-sectional view of a structure according to an embodiment of the present disclosure is shown.

[0009] Figure 2 An expanded cross-sectional view of a structure according to an embodiment of the present disclosure is shown.

[0010] Figure 3 A cross-sectional view of a structure according to another embodiment of the present disclosure is shown.

[0011] Figure 4 A cross-sectional view of a structure according to an additional embodiment of the present disclosure is shown.

[0012] Figure 5 An expanded cross-sectional view of a structure according to another embodiment of the present disclosure is shown.

[0013] Figure 6-10 A cross-sectional view of the process in a method of forming a structure according to an embodiment of the present disclosure is shown.

[0014] Figure 11 A cross-sectional view of a process in a method of forming a structure according to other embodiments of the present disclosure is shown.

[0015] Figure 12 A cross-sectional view of the process in a method of forming a structure according to an additional embodiment of the present disclosure is shown.

[0016] Note that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of this disclosure and should not be considered as limiting the scope of this disclosure. In the drawings, the same numbers denote the same elements between the figures. Detailed Implementation

[0017] In the following description, reference is made to the accompanying drawings, which form a part thereof, and specific exemplary embodiments in which the present teachings may be practiced are illustrated by way of illustration. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and modifications may be made without departing from the scope of the present teachings. Therefore, the following description is merely illustrative.

[0018] It will be understood that when an element, such as a layer, region, or substrate, is described as being "on" or "above" another element, it can be directly on the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly on" or "directly above" another element, there are no intermediate elements. It should also be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0019] References to "one embodiment" or "an embodiment" and other variations thereof in the specification mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment of the present disclosure. Therefore, the phrase "in one embodiment" or "in one embodiment," and any other variations appearing throughout the specification, do not necessarily refer to the same embodiment. It should be understood that the use of " / ", "and / or", and "at least one" in cases such as "A / B", "A and / or B", and "at least one of A and B" is intended to include selecting only the first listed option (A), or only the second listed option (B), or both options (A and B). As other examples, in the cases of “A, B, and / or C” and “at least one of A, B, and C”, these phrases are intended to encompass selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). As will be apparent to those skilled in the art, this can be extended to many of the listed items.

[0020] This disclosure provides structures and related methods for having emitter contacts that are wider than the emitter terminals. The structures of this disclosure include emitter contacts located within an interlayer dielectric (ILD) layer and on the emitter terminals of a bipolar transistor, wherein the horizontal width of the emitter contact is greater than the horizontal width of the emitter terminal located below it.

[0021] Bipolar junction transistor (BJT) structures (such as the BJT structures in the embodiments of this disclosure) operate using multiple “PN junctions.” The term “PN” refers to two adjacent materials with different types of conductivity (i.e., P-type and N-type), which can be induced by dopants within the adjacent materials. When formed in a device, a PN junction can function as a diode. A diode is a two-terminal device that behaves differently from the conductive or insulating materials between two electrical contacts. Specifically, a diode provides high conductivity from one contact to the other in one voltage bias direction (i.e., the “forward” direction), but provides little or no conductivity in the opposite direction (i.e., the “reverse” direction). In the case of a PN junction, the orientation of the diode in the forward and reverse directions can depend on the type and magnitude of the bias applied to the material composition of one or both terminals, which affects the size of the barrier. In the case of a junction between two semiconductor materials, the barrier will form along the interface between the two semiconductor materials. Typically, a BJT structure includes a base region located vertically or horizontally between the emitter material and the collector material. A BJT can be a PNP type BJT or an NPN type BJT. In a PNP type BJT, the emitter and collector regions are P-type conductive, and at least a portion of the base region is N-type conductive. In an NPN type BJT, the emitter and collector regions are N-type conductive, and at least a portion of the base is P-type conductive. It should also be noted that in conventional BJTs, the same semiconductor material (e.g., silicon) can be used for the base, collector, and emitter. Alternatively, a BJT can be a heterojunction bipolar transistor (HBT). In an HBT, the collector and emitter are at least partially made of one semiconductor material (e.g., silicon), and the base is at least partially made of a different semiconductor material (e.g., silicon-germanium). The use of different semiconductor materials at the emitter-base junction and the base-collector junction creates a heterojunction suitable for handling higher frequencies.

[0022] refer to Figure 1The structure 100 according to this disclosure may include a bipolar transistor (also simply referred to as a "BJT" to indicate a "bipolar junction transistor") 110. The bipolar transistor 110 may optionally be a heterojunction bipolar transistor (HBT). In any case, the BJT may be, for example, a vertically oriented bipolar transistor as discussed herein, wherein the emitter contact 146 has a horizontal width larger than the emitter terminal 114 of the bipolar transistor 110. In various embodiments, the emitter contact 146 may be at least partially located on a dielectric material (e.g., spacer 120 and / or interlayer dielectric (ILD) layer 140) and may vertically cover the outer base 116 and / or the silicide layer 148 on the outer base 116. The structure 100 may be formed on a sub-collector electrode 102 (i.e., a doped portion of a semiconductor substrate) comprising, for example, one or more single-crystal semiconductor materials. The sub-collector electrode 102 may include, but is not limited to, silicon, germanium, silicon-germanium (SiGe), silicon carbide, or any other common IC semiconductor substrate. In the case of SiGe, the germanium concentration in the sub-collector 102 can differ from other SiGe-based structures described herein. A portion or all of the sub-collector 102 may be strained. The sub-collector 102 can be doped (i.e., it can define a "doped well"), for example, to achieve coupling with a lower-active semiconductor material of the vertical bipolar transistor. The sub-collector 102 can have any conceivable doping type and / or doping composition suitable for use within and / or coupled to the collector terminals of the bipolar transistor. For example, the sub-collector 102 can have the same dopant type as the collector 106 formed thereon, for example, P-type doping in the case of a PNP type BJT, or N-type doping in the case of an NPN type BJT, and / or the sub-collector 102 can have a higher or lower dopant concentration therein.

[0023] Collector 106 may be located on sub-collector 102, for example, as a single layer or similarly doped but different layers formed on sub-collector 102 by epitaxial deposition of silicon, SiGe, and / or other semiconductor materials, and collector 106 may have a predetermined doping type, for example, by in-situ doping or by doping the semiconductor material of sub-collector 102 and / or during the formation of sub-collector 102. Collector 106 is structurally single-crystal. Collector 106 may define the active semiconductor material of a vertical bipolar transistor and thus may be vertically located below the other terminals of bipolar transistor 110 (i.e., the base (including the outer base region and the inner base region) and the emitter terminal discussed herein). Collector 106 is shown having a vertical sidewall located above sub-collector 102. However, collector 106 may have other shapes resulting from different manufacturing techniques (e.g., sloping sidewalls, curved sidewalls, etc.).

[0024] Structure 100 includes a set of isolation layers 108 located on 102 for providing additional electrical and physical separation of the bipolar transistor 110 from other components. Each isolation layer 108 may be horizontally adjacent to a corresponding side of the collector 106. The isolation layer 108 may extend above the sub-collector 102 to approximately the same height as the collector 106 and optionally lie across a portion of the inner base 112 on the collector 106. The isolation layer 108 thus allows for the simultaneous formation of an outer base 116 on portions of the isolation layer 108 and adjacent materials (e.g., the inner base 112 and its semiconductor film 118), as discussed elsewhere herein. The isolation layer 108 may include, for example, an oxide-based insulator (e.g., silicon dioxide (SiO2)), or other materials with similar properties. The isolation layer 108 may have the same composition as the insulator 109 discussed herein, but this is not required; therefore, where applicable, the isolation layer 108 is shown with a different cross-shading than the insulator 109. The isolation layer 108 can be formed, for example, by depositing the desired material on the sub-collector electrode 102, insulator 109, etc. In other examples, the isolation layer 108 may comprise multiple layers of different materials, and specifically may comprise an oxide-nitride-oxide (ONO) structure above the sub-collector electrode 102.

[0025] Insulator 109 may also be located on sub-collector 102 to horizontally separate various active semiconductor materials on substrate 104. Insulator 109 may optionally be subdivided into multiple layers and / or materials of varying widths and / or depths. As shown, some insulators 109 may extend vertically into substrate 104, while others may be located on sub-collector 102 to prevent electrical shorting between sub-collector 102 and the overlying region of bipolar transistor 110. As discussed elsewhere herein, insulator 109 may initially extend as a single layer over substrate 104. Some portions of insulator 109 may be removed to form trenches that may undercut certain remaining portions of insulator 109 near sub-collector 102. The undercut portions of insulator 109 may form generally triangular divots, recesses, etc., where collector 106 material can be grown. Therefore, collector 106 may be formed with a tapered or angled shape, as shown. When the collector 106 has tapered sidewalls, various materials on the collector 106 (e.g., the inner base 112 discussed herein) may also have tapered sidewall profiles, for example by selectively epitaxially growing additional materials on the collector 106.

[0026] Bipolar transistor 110 may include a base terminal, which collectively includes an inner base 112 located on collector 106 and an outer base 116 coupled to the inner base 112. The inner base 112 and outer base 116 may have different characteristics but serve as a single terminal in bipolar transistor 110. As shown, the inner base 112 may have inwardly tapered sidewalls such that the top surface of the inner base 112 is narrower in width than the top surface of collector 106. The inner base 112 may include, for example, single-crystal SiGe or any other single-crystal semiconductor material doped with a predetermined polarity. The inner base 112 may include a semiconductor material different from that of collector 106 and the emitter 114 above it (e.g., silicon germanium as opposed to silicon). The use of different semiconductor materials at the emitter-base junction and the base-collector junction creates heterojunctions, which are suitable for handling higher frequencies, for example. In this case, the BJT is referred to in the art as an HBT, as described herein. When the bipolar transistor is an NPN transistor and the sub-collector 102, collector 106, and emitter 114 are doped to n-type, the inner base 112 can be doped to p-type to form a PN junction, thereby forming a base-collector interface. It should also be understood that when the bipolar transistor is a PNP transistor, the inner base 112 can be doped to n-type. Regardless of the implementation, the inner base 12 can extend to a predetermined height above the collector 106. The inner base 112 is shown as having vertically extending sidewalls; however, the inner base 112 can have sidewalls with similar or different profiles than the collector 106 below it.

[0027] The inner base 112 may differ structurally and in composition from other portions of the base terminal of the bipolar transistor 110. Specifically, the inner base 112 may be lightly doped or may be undoped, while the outer base 116 elsewhere in the bipolar transistor 110 may be more heavily doped than the inner base 112. The inner base 112 may be formed, for example, by forming a layer of semiconductor material on the collector 106, which may be single-crystal silicon or SiGe as discussed herein. Additional semiconductor material may be formed to produce the inner base 112 by selective epitaxial growth and / or similar processes used to form additional semiconductor material, while maintaining the crystal orientation and / or composition of the underlying material. The selective epitaxial growth of the inner base 112 may specifically maintain the shape and orientation of the sidewalls of the collector 106.

[0028] The inner base 112 may also include a semiconductor film 118 on its upper surface to allow for the deposition and growth of other semiconductor materials with different conductivity types elsewhere during the formation of structure 100. The semiconductor film 118 may, for example, comprise undoped silicon (Si) in various crystalline forms, such as single-crystal oriented Si, polycrystalline Si, etc. As discussed herein, the semiconductor film 118 can be considered part of the inner base 112 and can be formed by forming the inner base 112 material to a desired height before forming the semiconductor film 118 on the inner base 112 and / or by removing a portion of the inner base 112 material to replace it with the semiconductor film 118. The semiconductor film 118 can also be formed by any other now-known or hereafter developed techniques for forming transition semiconductor materials suitable for subsequently forming materials with different conductivity types and / or dopant concentrations of the outer base 116 and / or emitter 114 thereon. The semiconductor film 118 may be electrically used as part of the inner base 112 but may have different compositions to control the position and size of the emitter 114 as an etch stop layer. Therefore, the individual references to the inner base 112 in this article can collectively refer to both the inner base 112 and the semiconductor film 118.

[0029] The base terminal of the bipolar transistor 110 may also include an outer base 116 located outside the inner base 112. The outer base 116 may comprise a polycrystalline semiconductor (e.g., polycrystalline SiGe) with the same doping type as the inner base 112, but with a relatively higher doping level (e.g., higher p-type doping than the inner base 112). For example, the outer base 116 may be formed by depositing an initial (seed) layer of single-crystal and / or other semiconductor material on the inner base 112. The outer base 116 to the desired height may be formed from the initial layer by selective epitaxial growth, deposition, and / or other processes. The outer base 116 formed by selective epitaxial growth may have sidewalls with shapes similar to and / or substantially aligned with the sidewalls of the inner base 112 (and possibly the collector 106) below it.

[0030] Emitter 114 may be located at the center of inner base 112. In one example, emitter 114 may be horizontally located between portions of outer base 116 extending vertically above semiconductor film 118. A set of spacers 120 positioned adjacent to emitter 114 may electrically isolate emitter 114 from outer base 116. Emitter 114 may be formed on and above inner base 112, for example, by forming a material stack including portions of outer base 116, removing a portion of the material stack, and forming emitter 114 and / or other components within and / or replacing the removed outer base 116 material. Emitter 114 may have the same doping type as sub-collector 102 and collector 106, and therefore have a doping type opposite to that of outer base 116 (and inner base 112, if doped). When the bipolar transistor 110 is an NPN device, the collector 106 and emitter 114 can be doped to n-type to provide two n-type active semiconductor materials, and the inner base 112 can be doped to p-type. The emitter 114 may comprise polycrystalline silicon and / or other single-crystal semiconductor materials, including one or more materials used elsewhere in structure 100 to form the sub-collector 102, collector 106, outer base 116 (with different doping), etc.

[0031] One or more spacers 120 may be adjacent to the emitter 114 and located above a proximal portion of the outer base 116. Although a spacer 120 is shown as adjacent to each sidewall of the emitter 114, such a spacer 120 may comprise multilayer materials of various arrangements. Other compositions and / or arrangements of spacers 120, now known or developed hereafter, may also be used. Thus, spacers 120 may comprise oxide materials, nitride materials, and / or any other insulating materials discussed herein, such as compositions similar to insulator 109 or other insulating structures. Spacers 120 may be formed, for example, by depositing multilayer spacer material as part of a stack, removing a portion of the stack where the emitter 114 is required, and optionally forming additional portions of spacer 120 material to cover any exposed surfaces and inner sidewalls of the outer base 116 before other materials (e.g., emitter 114) are formed adjacent to the desired portion of the spacer 120 on the semiconductor film 118. In some embodiments, spacers 120 may comprise a single layer or more than two layers. The spacers 120 may also extend vertically across the emitter 114, such that they are horizontally positioned between the emitter 114 and the outer base 116. The spacers 120 may have different compositions to control (e.g., increase) the electrical insulation between the emitter 114 and the outer base 116.

[0032] Structure 100 may include an interlayer dielectric (ILD) layer 140 located above insulator 109, outer base 116, emitter 114, spacer 120, etc. ILD layer 140 may include the same insulating material as insulator 109, or may include a different electrically insulating material to vertically separate the active material from the overlying material (e.g., various horizontally extending lines or vias). However, ILD layer 140 and insulator 109 constitute distinct components, for example, because insulator 109 is vertically located between sub-collector 102 and the various active components of structure 100. ILD layer 140 may be formed by deposition and / or other techniques for providing electrically insulating material, and may then be planarized (e.g., using CMP) such that its upper surface remains above any active components formed on sub-collector 102. One or more barrier layers 141, including, for example, nitride-based dielectric materials (e.g., silicon nitride (SiN)), can vertically separate different ILD layers 140, and as discussed elsewhere herein, can enable certain portions of the structure to be formed and treated differently from each other to affect the shape of the conductive contacts of the bipolar transistor 110.

[0033] A set of base contacts 142 passing through the ILD layer 140 can provide vertical electrical coupling between the outer base 116 and the overlying metal wiring and / or vias. It is noteworthy that the base contacts 142 do not extend to the inner base 112. Therefore, the inner base 112 is coupled to the base contacts 142 only through the outer base 116. For example, by providing a conductive metal such as cobalt (Co), titanium (Ti), nickel (Ni), platinum (Pt), or similar material on the upper surface of the target material, some portions of the outer base 116 can be transformed into a silicide layer 148 to improve conductivity between each base contact 142 and any portion of the outer base 116 beneath it. The conductive material can be annealed simultaneously with the underlying semiconductor contact to create the silicide layer 148, thereby electrically coupling the semiconductor material to any contact formed thereon. Excess conductive material can then be removed using any solution now known or developed later, such as etching.

[0034] Structure 100 also includes an emitter contact 146 to the emitter 114 and a collector contact 144 through the sub-collector 102 to the collector 106. (The remaining text appears to be a fragment and requires further context for accurate translation.) Figure 2In more detail, emitter contact 146 may be significantly larger than (e.g., wider in the horizontal direction than) emitter 114, and may also be wider than other contacts 142, 144 of structure 100. Each contact 146, 144 may also be coupled to emitter 114 or subset electrode 102, respectively, via a silicide layer 148 formed therein. Each contact 142, 144, 146 may also extend through ILD layer 140, thereby electrically connecting the active semiconductor material within subset electrode 102 or emitter 114 to overlying metal wiring, vias, etc., above structure 100. Contacts 142, 144, 146 may optionally be formed as part of a single operation, for example, by removing a portion of ILD layer 140 to form an opening, forming a silicide layer 148 on the semiconductor material exposed within the opening, and filling the opening with metal to define each contact 142, 144, 146. Contacts 142, 144, and 146 may include a refractory metal liner (not shown separately) on their sidewalls to impede or prevent electromigration degradation, shorting to other components, etc.

[0035] For example, by providing a conductive metal such as cobalt (Co), titanium (Ti), nickel (Ni), platinum (Pt), or similar material on the upper surface of the target material, portions of the subset electrode 102, emitter 114, and outer base 116 can be transformed into a silicide layer 148 to improve conductivity between each contact 142, 144, 146 and any active material beneath it. The conductive material can be annealed simultaneously with the underlying semiconductor contact to produce the silicide layer 148, thereby electrically coupling the semiconductor material to any contact formed thereon. Excess conductive material can then be removed using any solution now known or developed later, such as etching.

[0036] Now for reference Figure 2 It provides developed cross-sectional views of the base contact 142, emitter contact 146, and corresponding portions of the bipolar transistor 110, and discusses additional features of the structure 100. The emitter contact 146 may typically have a first width W1 within the ILD layer 140 and / or, where applicable, within the barrier film 141. The first horizontal width W1 may optionally be non-uniform. For example, the dimension of the first horizontal width W1 may be position-dependent if the emitter 146 includes tapered sidewalls or otherwise includes non-linear sidewalls. Figure 2In the example, emitter contact 146 is widest at its uppermost vertical position away from emitter 114 and narrowest at its lowermost vertical position near emitter 114. In this case, the first horizontal width W1 can be at a specific location, or it can be derived from different widths at various locations (e.g., it can be an average horizontal width, a maximum horizontal width, or a minimum horizontal width). Regardless of the calculation, the first horizontal width W1 is greater than the second horizontal width W2 of the emitter 114 located below it between spacers 120. In the example configuration, the minimum value of the horizontal width W1 in emitter contact 146 can still be greater than any value of the second horizontal width W2 along the vertical span of emitter 114. In some implementations, the difference between the first horizontal width W1 and the second horizontal width W2 can be large enough that the first horizontal width W1 is at least twice the size of the second horizontal width W2 (e.g., it can be three times larger or even more).

[0037] The difference in the horizontal widths W1 and W2 of the emitter contact 146 and the emitter 114 can produce specific structural characteristics. For example, the emitter contact 146 can be subdivided into a first portion 146a and a second portion 146b due to its horizontal width W1. The first portion 146a may include any or all of the portion of the emitter contact 146 directly above the emitter 114 (regardless of whether a silicide layer 148 is present therein). The second portion 146b of the emitter contact 146 may include any or all of the portion located vertically above components other than the emitter 114 and on the opposite side of the emitter 114 (e.g., dielectric material such as spacer 120, ILD layer 140, etc.). Figure 2 For example, the second portion 146b of the emitter contact 146 is physically connected to a plurality of dielectric materials by being located on the spacer 120 and on adjacent portions of the ILD 140. Thus, the first portion 146a may have a lower surface defining a conductive interface within the bipolar transistor 110, while the second portion 146b may have a lower surface defining a metal-dielectric material interface within the structure 100. Furthermore, at least a portion of the second portion 146b of the emitter contact 146 may be vertically above the silicide layer 148 located on the outer base 116. Therefore, in contrast to conventional bipolar transistor structures, portions of the emitter contact 146 vertically cover the active material included within the outer base 116. These and other physical characteristics discussed herein thus cause contacts 142, 146 to be closer to each other in the horizontal direction than the corresponding terminals 116, 114 of the bipolar transistor 110 below them.

[0038] Figure 3Another embodiment of structure 100 is shown, in which the emitter contact 146 is processed separately from the base contact 142 and the collector contact 144. In this case, instead of forming a barrier film 141 to define the lower extent of the emitter contact 146, embodiments of this disclosure may include forming an ILD layer 140, forming openings in the ILD layer 140 to form the base contact 142 and the collector contact 144, and then performing non-selective vertical etching (e.g., reactive ion etching (RIE)) separately over the contacts 142, 144 and non-targeted areas of the ILD 140 using a mask (not shown) to define the width of the final emitter contact 146. This etching can be controlled such that it terminates before removing a significant portion of the emitter 114, the spacer 120, and / or the silicide layer 148. Emitter contact 146 can then be formed by depositing conductive metal in the removed area. Thus, similar to other embodiments, emitter contact 146 can be located above emitter 114 and above adjacent portions of spacer 120 and ILD layer 140.

[0039] refer to Figure 4 Another embodiment of structure 100 may include an emitter contact 146 located in the underlying portion of the metal wiring layer 150, rather than the ILD layer 140. In some embodiments, a barrier film 141 may define a lower boundary of the metal wiring layer 150 to provide vertical and horizontal coupling with other device components. The metal wiring layer 150 may include another ILD layer 140 located therein. The metal wiring layer 150 may also include a base conductor 152 to a base contact 142 and a collector conductor 154 to a collector contact 144. Conductors 152, 154 may have the same or similar composition as the contacts 142, 144 below them, and may therefore include conductive metals (copper, aluminum, etc.). The difference between conductors 152, 154 and contacts 142, 144 may be that they are located within the metal wiring layer 150 rather than within the ILD layer 140 below the metal wiring layer 150 and the barrier film 141. The metal wiring layer 150 may also include an emitter contact 146 located therein. In this case, the emitter contact 146 can be formed together within the conductors 152 and 154 instead of being formed together with the other contacts 142 and 144. Therefore, the emitter contact 146 can be at least partially located above the contacts 142 and 144, but still exhibit a larger horizontal width than the emitter 114. Figure 4 In the example, and in any other embodiment of structure 100 discussed herein, the emitter contact 146 may optionally have a horizontal width greater than the combined horizontal width of the base contact 142 and collector contact 144 to the bipolar transistor 110. In this case, the emitter contact 146 may also have a horizontal width greater than the combined horizontal width of the base conductor 152 and collector conductor 154 to the bipolar transistor 110.

[0040] Turn to the diagram showing the unfolded portion of structure 100. Figure 5 Alternatively, a configuration can be used to form the base contact 144 and the emitter contact 146 within an ILD layer 140, while maintaining a larger horizontal width for the emitter contact 146. In this case, after forming the outer base 116, emitter 114, and spacer 120, a barrier film 141 can be conformally formed on these components. The portion of the barrier film 141 above the emitter 114 can be removed by vertical etching, and a silicide layer 148 can be formed on the emitter 114 in its place. The ILD layer 140 can then be formed on the silicide layer and the barrier film 141. Here, the base contact 144 can be formed by non-selective directional etching of the ILD layer 140 and the barrier film 141, and by forming a conductive material within the etched portion. However, the emitter contact 146 can be formed by selectively etching a wider area of ​​the ILD layer 140 above the silicide layer 148 and using the barrier film 141 and the silicide layer 148 as an "etch stop layer" to prevent the underlying portion of the emitter 114 from being removed. The emitter contact 146 can then be formed by replacing the removed material, such that the emitter contact 146 has a larger horizontal width than the emitter 114 below it.

[0041] Go to Figure 6 It provides a structure 100 for forming any configuration as discussed herein. Figure 1-5 The method involves forming a sub-collector electrode 102 on a substrate 104 (e.g., by targeted doping of a semiconductor material to a desired concentration), forming an insulator 109 and / or other isolation material adjacent to the sub-collector electrode 102 and the substrate 104, etc. Further processing may include forming an isolation layer 108 on the sub-collector electrode 102 and the insulator 109 adjacent to it, for example, by forming an insulating material layer on the substrate 104 and the sub-collector electrode 102 using deposition or other techniques now known or developed later to provide an insulating material. To form a collector electrode 106, an opening (not shown) may be formed within the deposited isolation layer 108, and the substrate 104 may be formed within the opening, for example, by epitaxial growth and doping of a semiconductor material on the sub-collector electrode 102 within the opening. In the case of formation by epitaxial growth, the collector electrode 106 may have a sidewall shape depending on the shape of the isolation layer 108, the manner of growth achieved, and / or the crystal orientation of the sub-collector electrode 102 beneath it. For example, by controlling the deposition time and back etch of the collector 106 material during formation, the collector 106 can not completely horizontally fill the opening in the isolation layer 108 during formation.

[0042] Further processing may include, for example, forming an inner base 112 on the collector 106 as a single-crystal semiconductor material. The inner base 112 may be undoped or have a doping type opposite to that of the collector 106; furthermore, the inner base 112 may have a lower concentration of dopant therein. The collector 106 and / or the inner base 112 may be doped by implantation and / or other doping techniques now known or developed later. The formation of the inner base 112 may begin only after the collector 106 is at or near the height of the isolation layer 132 above the sub-collector 102. A semiconductor film 118 may then be produced by non-selectively forming, for example, a layer of semiconductor material with different composition and / or crystal orientation on the inner base 112, said semiconductor material being doped during or after growth to have the same conductivity as the inner base 112. The semiconductor film 118 may be formed such that its upper surface is substantially coplanar with the adjacent upper surface of the isolation layer 108, or optionally located above the adjacent upper surface of the isolation layer 108. The semiconductor film 118 can be doped using any conceivable process, such as by thermal annealing after the semiconductor film 118 has been formed. In subsequent processing, the semiconductor film 118 can be used as part of the inner base 112, but can also provide an etch stop layer to control the emitter 114. Figure 1-5 The position and dimensions of the ) are as described in the various embodiments herein.

[0043] Emitter layer 160 (e.g., doped polycrystalline silicon (“polysilicon”)) may be located on isolation layer 108 and semiconductor film 118, for example by non-selectively depositing and doping a semiconductor material thereon. In subsequent processing discussed herein, emitter layer 160 may be recessed and / or partially removed to enable the formation of outer base 116 ( Figure 1-5 ) and adjacent spacers 120 to hold bipolar transistor 110 ( Figure 1-5 The final electrical and structural separation between the emitter and base terminals.

[0044] Figure 7 The bipolar transistor 110 is shown, for example, formed in the following manner ( Figure 1-5 The remaining active terminals of the emitter layer 160: make the emitter layer 160 ( Figure 6The inner base 112 is recessed to the desired height, and a mask (not shown) is formed on the emitter layer 160 above the inner base 112. The portion of the emitter layer 160 located below the mask is removed, and the remaining polysilicon material is doped to define an emitter 114 with the desired size and doping concentration. The emitter 114 can be doped to have the same doping type as the sub-collector 102 and collector 106, for example, P-type or N-type doping based on whether the final bipolar transistor 110 will have a PNP or NPN configuration. The spacer 120 can then be formed, for example, by depositing an insulating material layer to the desired thickness and then vertically etching the insulating material such that the vertical etching does not remove any portion of the dielectric material covering the sidewalls of the emitter 114. Similarly, the outer base 116 can be formed by forming a mask on the emitter 114 and / or the spacer 120, depositing, etching back, and / or doping a semiconductor material (e.g., silicon germanium (SiGe) or similar material) to have the desired configuration. Once formed, the outer base 116 may have an upper surface that is above the semiconductor film 118 but below the height of the spacer 120. The spacer 120 thus horizontally separates the outer base 116 from the emitter 114.

[0045] Turning Figure 8 The horizontal exterior of the isolation layer 108 and the outer base 116 is then removed by targeted etching. A silicide layer 148 can then be formed (optionally formed simultaneously) within the exposed upper surfaces of the subset electrode 102, emitter 114, and / or outer base 116 by depositing metal thereon, annealing the metal to diffuse metal ions into the underlying semiconductor material, and removing excess metal. Alternatively, a set of barrier films 141 can be formed by deposition on the exposed upper surfaces of the material (e.g., on any silicide layer 148, on insulator 109 and spacer 120, etc.) to protect the underlying material from further processing. An ILD layer 140 can then be formed over the partially formed structure via deposition and / or planarization.

[0046] Figure 9 and Figure 10 The structure 100 is shown in some embodiments. Figure 1-5 The remaining processes. For example, Figure 9 The diagram shows the ILD layer 140 partially recessed to approximately the height of the emitter 114, and then another barrier layer 141 formed thereon. The barrier layer 141 can be used as an etch stop layer to independently process different contacts, or it can simply be used to vertically separate the previously formed active material from the overlying metal wiring layer. Figure 10This illustrates forming another ILD layer 140 on the barrier layer 141, using the barrier layer 141 as an etch stop material to remove a target portion of the ILD layer 140 to a depth up to the emitter 114, and replacing the removed ILD layer 140 material with an emitter contact 146 of a predetermined desired horizontal width. Therefore, as... Figure 10 As shown, emitter contact 146 is formed without any other contacts (e.g., base contact 142 and collector contact 144, discussed herein) also formed in the corresponding locations. By first forming emitter contact 146, emitter contact 146 can have a larger horizontal width than the emitter 114 below it. Subsequent processing may then include, for example, covering emitter contact 146 and other portions of ILD layer 140 with a mask, and forming contacts 142, 144 by removing target areas of ILD layer 140 and barrier layer 141 and forming conductive material in the empty spaces to provide contacts 142, 144 where needed. Figure 1-5 ).

[0047] Let's refer to it together now. Figure 8 and 11 Alternative processing may include partially recessing the ILD layer 140 and removing any blocking layer 141 on the emitter 114, thereby exposing the silicide layer 148 for the emitter 114. A conductive layer 170 (e.g., copper, aluminum, or other conductors discussed herein) can then be formed by depositing such a material over the emitter 114 and the remaining area of ​​the ILD layer 140. Then, a final emitter contact 146 is formed. Figure 1-5 A temporary mask of the required width is used to cover the portion of conductive layer 170 above emitter 114. The portion of conductive layer 170 not covered by the mask can then be removed and replaced again by the material of ILD layer 140 through deposition of insulating material in its place. The resulting emitter contact 146 can thus be positioned substantially with a horizontal width larger than emitter 114, such as, for example... Figure 3 As shown. Then, base contact 142 and collector contact 144 can be formed, as per [reference to...]. Figure 10 As discussed elsewhere in this article.

[0048] refer to Figure 9 and Figure 12 Another implementation may include forming the base contact 142 and the collector contact 144 before the emitter contact 146. Here, after forming the barrier layer 141, further processing may include forming openings in the ILD layer 140 and the barrier layer 141, filling the openings with a conductive material to form contacts 142 and 144, and then forming the barrier layer 141 again on top of the contacts 142 and 144 to allow other materials to be formed thereon. Figure 4As shown in the example, subsequent processing may include forming a wiring layer 150 and, in addition to forming an emitter contact 146, forming conductors 152, 154 within the wiring layer 150.

[0049] The embodiments of this disclosure provide various technical and commercial advantages, examples of which are discussed herein. The embodiments of this disclosure aid in manufacturing tooling and facilitate the vertical placement of the emitter contact 146 on the emitter 114, which has a variable shape and reduced dimensions. Furthermore, the structures and methods discussed herein reduce base-to-emitter resistance and base-to-emitter capacitance by preventing spatial overlap between the semiconductor material (specifically, polysilicon) of the emitter 114 and the outer base 116. Additionally, the wider dimensions of the emitter contact 146 also improve thermal management by reducing the internal resistance along the path between the emitter 114 and the metal wiring layer above it.

[0050] The methods and structures described above are used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” indicates that an event or condition subsequently described may or may not occur, and the description includes cases where the event occurs and cases where the event does not occur.

[0052] The approximate language used throughout the specification and claims can be used to modify any quantitative expression that allows for variation without causing a change in its associated essential function. Therefore, values ​​modified by one or more terms such as “about,” “approximate,” and “substantially” are not limited to the specified exact values. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. In this document and throughout the specification and claims, range limitations can be combined and / or interchanged, such ranges being identified and including all subranges contained therein, unless the context or language indicates otherwise. The term “approximate” applied to a specific value within a range applies to both values ​​and, unless otherwise dependent on the precision of the instrument used to measure the value, may indicate + / - 10% of said value.

[0053] All the means or steps plus functional elements in the following claims are intended to include any structure, material, action, and equivalent that performs the function in combination with other claimed elements of the specific claim. The present disclosure has been described for purposes of illustration and description, but such description is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular intended use.

Claims

1. A structure comprising: An emitter contact is located within the interlayer dielectric (ILD) layer and on the emitter terminal of the bipolar transistor, wherein the horizontal width of the emitter contact is greater than the horizontal width of the emitter terminal located below it.

2. The structure according to claim 1, wherein, The emitter contact includes a first portion located on the emitter terminal and a second portion located on a dielectric layer adjacent to the emitter terminal and adjacent to the first portion.

3. The structure according to claim 2, wherein, The second portion is located above the outer base of the bipolar transistor, and wherein the outer base is horizontally away from the emitter terminal.

4. The structure according to claim 3, wherein, The second portion is located vertically above the silicide layer on the outer base.

5. The structure according to claim 2, wherein, The second portion of the emitter contact includes a lower surface that is in contact with the upper surface of a plurality of dielectric materials.

6. The structure according to claim 1, wherein, The horizontal width of the emitter contact is at least approximately twice the horizontal width of the emitter tip.

7. The structure according to claim 1, further comprising: The collector contact within the ILD layer is horizontally located away from the emitter contact; as well as The base contact within the ILD layer is horizontally located between the emitter contact and the collector contact, wherein the horizontal width of the emitter contact is greater than the combined horizontal width of the collector contact and the base contact.

8. A structure comprising: Collector terminal, comprising epitaxial semiconductor material located on a sub-collector; An isolation layer is located on the sub-collector and adjacent to the collector terminal; The base extremes include: An inner base electrode, located on the collector terminal, wherein a semiconductor film is located on the inner base electrode; and An outer base electrode, which is adjacent to the semiconductor film and located on the upper surface of the isolation layer and in contact with the inner base electrode; A firing tip, located on the semiconductor film; and An emitter contact is located within the interlayer dielectric (ILD) layer and on the emitter terminal, wherein the horizontal width of the emitter contact is greater than the horizontal width of the emitter terminal located below it.

9. The structure according to claim 8, wherein, The emitter contact includes a first portion located on the emitter terminal and a second portion located on a dielectric layer adjacent to the emitter terminal and adjacent to the first portion.

10. The structure according to claim 9, wherein, The second portion is located above the outer base, and wherein the outer base is horizontally away from the emitter terminal.

11. The structure according to claim 10, further comprising a silicide layer located on the outer base, wherein, The second portion is located vertically on the silicide layer.

12. The structure according to claim 8, wherein, The horizontal width of the emitter contact is at least about twice the horizontal width of the emitter tip.

13. The structure according to claim 8, further comprising: The collector contact, located on the sub-collector electrode and within the ILD layer, is horizontally away from the emitter contact; as well as A base contact located on the outer base and within the ILD layer is horizontally positioned between the emitter contact and the collector contact, wherein the horizontal width of the emitter contact is greater than the combined horizontal width of the collector contact and the base contact.

14. A method comprising: An emitter contact is formed within the interlayer dielectric (ILD) layer and on the emitter terminal of the bipolar transistor, wherein the horizontal width of the emitter contact is greater than the horizontal width of the emitter terminal located below it.

15. The method of claim 14, further comprising forming a first portion of the emitter contact on the emitter terminal, and forming a second portion on a dielectric layer adjacent to the emitter terminal and adjacent to the first portion.

16. The method of claim 15, further comprising forming the second portion above the outer base of the bipolar transistor, wherein, The outer base is horizontally away from the emitter end.

17. The method according to claim 16, wherein, The second portion is located vertically above the silicide layer on the outer base.

18. The method according to claim 15, wherein, The second portion of the emitter contact includes a lower surface that is in contact with the upper surface of a plurality of dielectric materials.

19. The method of claim 14, wherein, The horizontal width of the emitter contact is at least about twice the horizontal width of the emitter tip.

20. The method of claim 14, further comprising: A collector contact is formed horizontally and away from the emitter contact within the ILD layer; as well as A base contact is formed horizontally within the ILD layer between the emitter contact and the collector contact, wherein the horizontal width of the emitter contact is greater than the combined horizontal width of the collector contact and the base contact.

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