Method for improving gate-source-drain current

Abstract

This invention provides a method for improving gate-source leakage current. The method includes: providing a base structure comprising a trench, a first dielectric layer, and a first conductive material, wherein the top surface of the first conductive material is lower than the trench opening; thermally oxidizing the base structure; growing a second dielectric layer on the exposed surface of the first conductive material; wet etching the first dielectric layer, wherein the second dielectric layer protects the first dielectric layer on the side of the first conductive material from excessive lateral etching by utilizing the rate difference between the second and first dielectric layers in the etching solution; and depositing a third dielectric layer to fill the trench after wet etching. This invention improves the morphology of the field oxide layer after etching back through the protective effect of the thermal oxide layer, eliminates the potential for voids during subsequent dielectric filling, prevents leakage failure due to thin insulation, and significantly improves the consistency of the gate-source leakage current and its yield performance.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a method for improving gate-source leakage current, specifically applicable to the manufacturing process of Power-UDSGT platform products. Background Technology

[0002] In the fabrication of power semiconductor devices, especially split gate trench (SGT) devices, complex thin-film deposition and etching processes are required inside the trench to form the split gate structure. The morphology of the dielectric layer inside the trench has a crucial impact on the electrical performance of the device, especially the gate-source leakage current (IGSS).

[0003] Existing typical manufacturing processes usually include the following steps:

[0004] Trenches are formed by etching on a substrate covered with a hard mask;

[0005] A field oxide layer (Field SiO2, i.e., the first dielectric layer) is deposited on the inner wall of the trench and then filled with a first layer of polysilicon (PolyO).

[0006] The first layer of polysilicon is etched back to position it at the bottom of the trench.

[0007] The field oxide layer on the sidewalls is etched back using a wet etching process to reduce the height of the field oxide layer, so as to reserve filling space for the subsequent control gate and its isolation dielectric layer.

[0008] The interphase oxide (IPO) layer of polysilicon is filled using a high-density plasma (HDP) deposition process.

[0009] However, in actual production, the wet etching process described above has significant side effects. Since the field oxide layer is typically formed using chemical vapor deposition (CVD), its structure is relatively loose, resulting in a fast etching rate. During the etching of the field oxide layer, the wet etching solution easily penetrates downwards along the interface between the polysilicon and the field oxide layer, leading to over-etching of the field oxide layer at the bottom of the polysilicon.

[0010] like Figure 1 As shown in the diagram of the sidewall field SiO2 morphology in the prior art, this unintended "side-hole" effect results in an undesirable morphology of the field oxide layer after etching, with concave ends and a convex middle near the top of the polysilicon. This morphology leads to an abnormally large aspect ratio in the local trench, exceeding the filling capacity of subsequent HDP processes.

[0011] like Figure 2As shown in the prior art (morphology after HDP deposition), due to the increased aspect ratio, the HDP oxide layer cannot completely fill the tiny gaps on the sides of the polysilicon, thus forming voids within the inter-polysilicon oxide (IPO). During subsequent cleaning or etching steps, acid can penetrate these voids, further corroding the dielectric layer and causing localized thinning of the IPO (e.g., ...). Figure 3 (As shown). This defect significantly reduces the insulation performance between the upper and lower gates, ultimately causing an abnormal increase in the gate-source leakage current (IGSS) parameter of the device, leading to product failure.

[0012] Therefore, the industry urgently needs an optimized process that can protect the dielectric layer structure at the bottom of the polysilicon while wet etching the field oxide layer (first dielectric layer), avoiding the formation of filling voids, thereby improving the IGSS yield of the product. Summary of the Invention

[0013] This invention aims to solve the technical problem in power semiconductor manufacturing where lateral etching of the sidewall field oxide layer during wet etching leads to voids in the subsequent dielectric filling, resulting in an abnormally high gate-source leakage current.

[0014] A method for improving gate-source leakage current in semiconductor device manufacturing, the method comprising the following steps:

[0015] Step 1: Provide a semiconductor basic structure, which includes a trench, a first dielectric layer located on the inner wall of the trench, and a first conductive material filling the lower part of the trench. The first dielectric layer is located between the first conductive material and the sidewall of the trench, and the top surface of the first conductive material is lower than the opening plane of the trench.

[0016] Step 2: Perform thermal oxidation treatment on the semiconductor base structure to grow a second dielectric layer on the exposed surface of the first conductive material, wherein the second dielectric layer is mainly formed by the oxidation of the material on the surface of the first conductive material;

[0017] Step 3: Perform wet etching on the first dielectric layer, wherein the second dielectric layer protects the first dielectric layer on the side of the first conductive material from excessive lateral etching by utilizing the difference in etching rate between the second dielectric layer and the first dielectric layer in the wet etching solution.

[0018] Step 4: Deposit a third dielectric layer in the trench, which fills the trench after wet etching.

[0019] Preferably, in the semiconductor base structure described in step one, the trench is formed in the semiconductor substrate, and the surface of the semiconductor substrate is covered with a pad layer and a hard mask layer located on the pad layer; steps two, three and four are all performed with the pad layer and the hard mask layer remaining on the surface of the semiconductor substrate.

[0020] Preferably, prior to step one, the method further includes the step of forming the first conductive material and etching it back, such that the top surface of the first conductive material is lower than the opening plane of the trench.

[0021] Preferably, in step one, the first dielectric layer is a silicon oxide layer formed by chemical vapor deposition, and the first conductive material is polycrystalline silicon.

[0022] Preferably, in step two, the thermal oxidation treatment causes the second dielectric layer to cover the top corner of the first conductive material and extend from the top surface to the junction gap between the first conductive material and the first dielectric layer, so as to block the longitudinal etching path of the etching solution in step three.

[0023] Preferably, in step two, the second dielectric layer is a thermally oxidized silicon layer, which is grown on the top surface and edge of the polycrystalline silicon, and the etching rate of the second dielectric layer in the wet etching solution is lower than the etching rate of the first dielectric layer in the wet etching solution.

[0024] Preferably, in step three, the wet etching reduces the top height of the first dielectric layer; during this process, the second dielectric layer covers the top of the first conductive material, preventing the etching solution from penetrating into the interface gap between the first conductive material and the first dielectric layer, thereby preventing the formation of microgrooves or voids on both sides of the first conductive material.

[0025] Preferably, in step four, the third dielectric layer is a polycrystalline silicon interphase oxide layer, formed using a high-density plasma chemical vapor deposition process.

[0026] Preferably, in step four, after the third dielectric layer has been deposited to a predetermined thickness that meets the device design requirements, it is subjected to annealing.

[0027] Preferably, the method is used for the fabrication of a power split gate trench device, wherein the first dielectric layer is a field plate oxide layer and the first conductive material is a lower gate polysilicon layer.

[0028] As described above, the method for improving gate-source leakage current of the present invention has the following beneficial effects:

[0029] By adding an additional thermal oxidation process before the wet etching back of the sidewall dielectric layer, self-alignment protection is achieved without adding a mask by utilizing the etching rate difference between the dense protective layer formed by thermal growth and the loose dielectric layer formed by vapor deposition. This method effectively blocks the vertical and lateral penetration of the etching solution along the material interface, completely solving the inverted conical structure problem caused by the hollowing out of the side oxide layer of the first conductive material in traditional processes. The improved morphology ensures that the third dielectric layer and its polysilicon interphase oxide layer can achieve void-free, high-density filling. Experiments show that this method avoids the thinning of the insulating layer and the formation of leakage paths caused by dielectric filling defects, resulting in a significant optimization of the device's gate-source leakage current (IGSS) performance, ensuring the yield and reliability of power semiconductor products from the perspective of physical structural accuracy. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure after wet etching of the sidewall dielectric layer in the prior art;

[0031] Figure 2 The diagram shows a structural schematic of voids generated after high-density plasma deposition in the prior art.

[0032] Figure 3 This is a schematic diagram of the leakage path caused by a thin dielectric layer in the prior art.

[0033] Figure 4 The diagram shown is a schematic representation of a semiconductor basic structure provided in one embodiment of the present invention.

[0034] Figure 5 The diagram shown is a schematic representation of the structure of the first conductive material after being etched back in one embodiment of the present invention.

[0035] Figure 6 The diagram shown is a schematic representation of the structure after the formation of the second dielectric layer in one embodiment of the present invention.

[0036] Figure 7 The diagram shown is a schematic representation of the structure of the first dielectric layer after wet etching in one embodiment of the present invention.

[0037] Figure 8 The diagram shown is a structural schematic of the third dielectric layer after its formation in one embodiment of the present invention.

[0038] Figure 9 The diagram shows the experimental results comparing the cross-sectional morphology of semiconductor devices before and after applying the method of this invention. Detailed Implementation

[0039] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] Reference Figure 4 As shown, the present invention provides a method for improving gate-source leakage current for semiconductor device manufacturing, the method comprising the following steps:

[0041] Step 1: Provide a semiconductor basic structure, which includes a trench, a first dielectric layer 104 located on the inner wall of the trench, and a first conductive material 105 filled in the lower part of the trench. The first dielectric layer 104 is located between the first conductive material 105 and the sidewall of the trench, and the top surface of the first conductive material 105 is lower than the trench opening plane.

[0042] The semiconductor substrate is built on a semiconductor substrate 101, which may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer serving as the active layer. The active layer and the bulk semiconductor typically comprise the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0043] In some embodiments, in the basic structure of step one, a trench is formed in a semiconductor substrate 101, and the surface of the semiconductor substrate 101 is covered with a pad layer 102 and a hard mask layer 103 located on the pad layer 102; steps two, three, and four are all performed with the pad layer 102 and the hard mask layer 103 remaining on the surface of the semiconductor substrate 101. (Refer to...) Figure 4As shown, the pad layer 102 is selected from silicon dioxide, silicon oxynitride, or high dielectric materials such as alumina, hafnium oxide, tantalum oxide, or zirconium oxide formed by atomic layer deposition. The pad layer 102 can be grown by thermal oxidation or chemical vapor deposition. The hard mask layer 103 is selected from silicon nitride, silicon carbide, silicon carbide nitride, amorphous carbon layer, oxygen-doped silicon carbide, or metal mask materials. The hard mask layer 103 is formed by low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition. The hard mask layer 103 serves as an etching mask to define the trench locations and, together with the pad layer 102, acts as a stop layer for the chemical mechanical polishing step in subsequent steps to prevent mechanical wear or chemical contamination on the surface of the substrate 101.

[0044] In some embodiments, prior to step one, the method further includes forming a first conductive material 105 and etching it back, such that the top surface of the first conductive material 105 is lower than the trench opening plane. (Refer to...) Figure 5 As shown, the first conductive material 105 fills the bottom of the trench. Specifically, during formation, the entire trench is first filled and the surface of the hard mask layer 103 is covered by low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition. Then, redundant material above the hard mask layer 103 is removed using chemical mechanical polishing. Finally, back etching is performed using reactive ion etching or inductively coupled plasma etching. The etching gas is selected from chlorine-, bromine-, or fluorine-containing gases, such as chlorine, hydrogen bromide, sulfur hexafluoride, and combinations thereof. By controlling the etching bias and processing time, the top of the first conductive material 105 is recessed to a preset depth, ensuring that the top surface of the first conductive material 105 is exposed for subsequent processes.

[0045] In some embodiments, in step one, the first dielectric layer 104 is a silicon oxide layer formed by chemical vapor deposition, and the first conductive material 105 is polycrystalline silicon. The deposition method of the first dielectric layer 104 is selected from atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, high aspect ratio process, or thermal decomposition deposition process using tetraethyl orthosilicate as a precursor. In addition to polycrystalline silicon, the first conductive material 105 can also be replaced by doped amorphous silicon, monocrystalline silicon, tungsten, aluminum, titanium, cobalt, nickel, hafnium nitride, titanium nitride, tantalum nitride, or silicides of the above metals.

[0046] In some embodiments, the method is used for fabricating a power split-gate trench device, wherein the first dielectric layer 104 is a field plate oxide layer, and the first conductive material 105 is a lower gate polysilicon layer. The field plate oxide layer helps to regulate the electric field distribution in the drift region and improve the device breakdown voltage.

[0047] Step 2: Perform thermal oxidation treatment on the semiconductor base structure to grow a second dielectric layer 106 on the exposed surface of the first conductive material 105. The second dielectric layer 106 is mainly formed by oxidation of the surface material of the first conductive material 105. (Refer to...) Figure 6As shown, the thermal oxidation process involves placing the wafer in a vertical furnace tube or a rapid thermal annealing chamber and introducing an oxidizing atmosphere. The oxidizing atmosphere can be oxygen, ozone, nitrous oxide, water vapor, or free radical oxygen generated through hydroxyl synthesis. The thermal oxidation method is selected from dry oxygen oxidation, wet oxygen oxidation, in-situ steam growth, rapid thermal oxidation, free radical oxidation, or plasma-assisted oxidation. Under high-temperature conditions, silicon atoms in the first conductive material 105 react chemically with the oxidant. Since the first dielectric layer 104 and other oxide surfaces do not consume silicon atoms, the second dielectric layer 106 achieves self-aligned growth only on the surface of the first conductive material 105. The generated second dielectric layer 106 can tightly and continuously cover the top surface and corner edges of the first conductive material 105.

[0048] In some embodiments, step two is specifically implemented after the etching of the first conductive material 105 and before the wet etching back of the first dielectric layer 104, in order to improve the aspect ratio when the third dielectric layer 107 is subsequently deposited. Introducing a thermal oxidation process at this node ensures that the second dielectric layer 106 forms a highly chemically stable barrier before the wet chemical solution comes into contact with the interface gaps.

[0049] In some embodiments, in step two, the second dielectric layer 106 is a thermally oxidized silicon layer grown on the top and edges of the polysilicon. The etching rate of the second dielectric layer 106 in the wet etching solution is lower than that of the first dielectric layer 104 in the wet etching solution. This is because the thermally oxidized second dielectric layer 106 has a significantly higher molar density and stronger chemical bonds compared to the first dielectric layer 104 formed by deposition. In the same wet etching environment containing hydrofluoric acid or ammonium fluoride, the first dielectric layer 104 is rapidly removed, while the second dielectric layer 106 exhibits a lower etching rate, thus enabling it to function as a local masking layer.

[0050] Step 3: Perform wet etching on the first dielectric layer 104. Utilizing the difference in etching rates between the second dielectric layer 106 and the first dielectric layer 104 in the wet etching solution, the second dielectric layer 106 protects the first dielectric layer 104 on the side of the first conductive material 105 from excessive lateral etching. (Refer to...) Figure 7 As shown, wet etching is performed in an automated wet cleaning tank or a single-wafer rotary cleaning device. The chemical solution is selected from hydrofluoric acid, ammonium fluoride, nitric acid, sulfuric acid, or combinations thereof. Due to the physical shielding and chemical kinetic resistance of the second dielectric layer 106, the chemical solution preferentially falls back along the vertical direction of the trench sidewall and cannot penetrate laterally into the junction of the first conductive material 105 apex corner.

[0051] In some embodiments, in step three, wet etching reduces the top height of the first dielectric layer 104. During this process, the second dielectric layer 106 covers the top of the first conductive material 105, preventing the etching solution from drilling into the interface gap between the first conductive material 105 and the first dielectric layer 104, thereby preventing the formation of microgrooves or voids on both sides of the first conductive material 105. By controlling the etching time and the concentration of the etching solution, the height of the first dielectric layer 104 is precisely reduced to a preset node. Because the lateral drilling path is blocked, the cross-sectional morphology of the first dielectric layer 104 after its reduction is a gentle slope or quasi-plane, avoiding local high aspect ratio suspended structures and providing a smooth interface for subsequent filling processes.

[0052] Step 4: Deposit a third dielectric layer 107 within the trench. The third dielectric layer fills the trench after wet etching. (Refer to...) Figure 8 As shown, the deposition hardware is selected from high-density plasma chemical vapor deposition (PDCVD) equipment, atomic layer deposition (ALD) systems, fluidized bed chemical vapor deposition (FCVD) equipment, or spin coating equipment. The filling process achieves a bottom-up growth pattern, ensuring that the material layer uniformly fills all the space between the top surface of the first dielectric layer 104 and the hard mask layer 103.

[0053] In some embodiments, in step four, the third dielectric layer 107 is a polysilicon interphase oxide layer, formed using a high-density plasma chemical vapor deposition (PDCVD) process. Utilizing the characteristic of simultaneous deposition and physical sputtering in a high-density plasma device, hanging objects at the trench opening can be effectively removed, achieving complete filling of the remaining trench volume without any pores. Besides the polysilicon interphase oxide layer, the third dielectric layer 107 can also be replaced with phosphosilicate glass, boron-doped phosphosilicate glass, fluorosilicone glass, spin-coated glass, a low-dielectric-constant dielectric, or a composite layer.

[0054] In some embodiments, in step four, after the third dielectric layer 107 has been deposited to a predetermined thickness that meets the device design requirements, it is subjected to annealing. Annealing can further physically densify the filled third dielectric layer 107, increase chemical stability, and eliminate charge trapping centers or interface states generated by the plasma deposition process, thereby improving the overall voltage withstand characteristics of the thin film.

[0055] Reference Figure 9 As shown, a comparative analysis of semiconductor cross-sections before and after the application of this invention is performed. Figure 9 The left side shows the process before optimization. Due to severe lateral drilling of the first dielectric layer 104, deep grooves that are difficult to fill appeared in the morphology, which in turn caused voids to be generated at the top edge of the first conductive material 105 after the third dielectric layer was deposited. Figure 9The right side shows that after implementing the method of the present invention, the second dielectric layer 106 maintains the complete outline of the first dielectric layer 104, thereby enabling the third dielectric layer 107 to achieve a completely dense deposition. Experiments confirm that this method has a significant effect on microstructure reshaping.

[0056] The technical effects of the method implemented through the above steps are as follows: By adding a second dielectric layer 106 grown by thermal oxidation, the morphological evolution path of the first dielectric layer 104 during the wet etching process is precisely controlled. Utilizing the high density of the second dielectric layer 106 and its etching selectivity with the deposited layers, the vertical penetration of the etching solution along the material interface is successfully blocked, solving the problem of abnormally large local aspect ratios within the trenches. This solution completely eliminates physical voids or micro-gaps in the subsequent polysilicon inter-oxide layer filling process, thus avoiding localized thinning defects caused by further erosion of the dielectric layer by the subsequent wet etching solution through these voids. Reflected in electrical performance, this morphological improvement eliminates potential leakage paths within the device, solves the electric field distortion caused by the thinning of the insulating dielectric, and significantly improves the device's resistance to external electrical stress. Testing confirms that this series of methods can stabilize the gate-source leakage current index of the product within a low threshold range, significantly narrowing the dispersion of parameter distribution, and significantly improving the yield and reliability consistency of power semiconductor products without increasing the number of mask layers.

[0057] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0058] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving gate-source leakage current, characterized in that, At least including: Step 1: Provide a semiconductor basic structure, the basic structure including a trench, a first dielectric layer located on the inner wall of the trench, and a first conductive material filling the lower part of the trench, the first dielectric layer being located between the first conductive material and the sidewall of the trench, and the top surface of the first conductive material being lower than the opening plane of the trench; Step 2: Perform thermal oxidation treatment on the semiconductor base structure to grow a second dielectric layer on the exposed surface of the first conductive material, wherein the second dielectric layer is mainly formed by the oxidation of the material on the surface of the first conductive material; Step 3: Perform wet etching on the first dielectric layer, wherein the second dielectric layer protects the first dielectric layer on the side of the first conductive material from excessive lateral etching by utilizing the difference in etching rate between the second dielectric layer and the first dielectric layer in the wet etching solution. Step 4: Deposit a third dielectric layer in the trench, the third dielectric layer filling the trench after wet etching.

2. The method for improving gate-source leakage current according to claim 1, characterized in that: In the semiconductor basic structure described in step one, the trench is formed in the semiconductor substrate, and the surface of the semiconductor substrate is covered with a pad layer and a hard mask layer located on the pad layer; steps two, three and four are all performed with the pad layer and the hard mask layer remaining on the surface of the semiconductor substrate.

3. The method for improving gate-source leakage current according to claim 1, characterized in that: Prior to step one, the method further includes the step of forming the first conductive material and etching it back, such that the top surface of the first conductive material is lower than the opening plane of the trench.

4. The method for improving gate-source leakage current according to claim 1, characterized in that: In step one, the first dielectric layer is a silicon oxide layer formed by chemical vapor deposition, and the first conductive material is polycrystalline silicon.

5. The method for improving gate-source leakage current according to claim 1, characterized in that: In step two, the thermal oxidation treatment causes the second dielectric layer to cover the top corner of the first conductive material and extend from the top surface to the interface gap between the first conductive material and the first dielectric layer, so as to block the longitudinal etching path of the etching solution in step three.

6. The method for improving gate-source leakage current according to claim 4, characterized in that: In step two, the second dielectric layer is a thermally oxidized silicon layer, which is grown on the top surface and edge of the polycrystalline silicon. The etching rate of the second dielectric layer in the wet etching solution is lower than that of the first dielectric layer in the wet etching solution.

7. The method for improving gate-source leakage current according to claim 1, characterized in that: In step three, the wet etching reduces the top height of the first dielectric layer. During this process, the second dielectric layer covers the top of the first conductive material, preventing the etching solution from penetrating into the interface gap between the first conductive material and the first dielectric layer, thereby preventing the formation of microgrooves or voids on both sides of the first conductive material.

8. The method for improving gate-source leakage current according to claim 1, characterized in that: In step four, the third dielectric layer is a polycrystalline silicon interphase oxide layer, which is formed using a high-density plasma chemical vapor deposition process.

9. The method for improving gate-source leakage current according to claim 8, characterized in that: In step four, after the third dielectric layer has been deposited to the predetermined thickness that meets the device design requirements, it is then annealed.

10. The method for improving gate-source leakage current according to any one of claims 1 to 9, characterized in that: The method is used for the fabrication of power split gate trench devices, wherein the first dielectric layer is a field plate oxide layer and the first conductive material is a lower gate polysilicon layer.

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