Semiconductor device and method of forming the same

Abstract

The method includes: patterning a first opening through a first dielectric layer, a first source / drain region, and a second dielectric layer to expose a second source / drain region; forming a first dielectric liner along sidewalls of the first opening with the second source / drain region exposed; forming a first metal-semiconductor alloy region in the first opening along the second source / drain region; depositing a first conductive material to fill a remaining portion of the first opening; patterning a second opening through the first dielectric layer to expose the first source / drain region; forming a second dielectric liner along sidewalls of the second opening with the first source / drain region exposed; forming a second metal-semiconductor alloy region in the second opening along the first source / drain region; and depositing a second conductive material to fill a remaining portion of the second opening. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum part size, allowing more components to be integrated into a given area. As the semiconductor industry further moves towards increased device density, higher performance, and lower costs, challenges from manufacturing and design have led to stacked device configurations, such as stacked transistors, including complementary field-effect transistors (CFETs). While the minimum part size decreases, additional components are introduced. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming a semiconductor device, comprising: patterning a first opening through a first dielectric layer, a first source / drain region, and a second dielectric layer to expose a second source / drain region; forming a first dielectric pad along the sidewall of the first opening, wherein the second source / drain region is exposed; forming a first metal-semiconductor alloy region in the first opening along the second source / drain region; depositing a first conductive material to fill the remaining portion of the first opening; patterning a second opening through the first dielectric layer to expose the first source / drain region; forming a second dielectric pad along the sidewall of the second opening, wherein the first source / drain region is exposed; forming a second metal-semiconductor alloy region in the second opening along the first source / drain region; and depositing a second conductive material to fill the remaining portion of the second opening.

[0005] Other embodiments of this application provide a method for forming a semiconductor device, comprising: etching a first opening through a plurality of layers to expose a first epitaxial region disposed over a semiconductor substrate, the first epitaxial region comprising a first semiconductor material, the plurality of layers comprising: a first dielectric layer disposed over the first epitaxial region; a second epitaxial region disposed over the first dielectric layer, the second epitaxial region comprising a second semiconductor material; and a second dielectric layer disposed over the second epitaxial region; forming a first dielectric pad along the surface of the first opening; etching to remove a bottom segment of the first dielectric pad; depositing a silicon-germanium material over the first epitaxial region; filling the first opening disposed over the silicon-germanium material with a first conductive material; etching a second opening through the second dielectric layer to expose the second epitaxial region; forming a second dielectric pad along the surface of the second opening; etching to remove a bottom segment of the second dielectric pad; and filling the second opening disposed over the second epitaxial region with a second conductive material, the first conductive material being electrically connected to the second conductive material.

[0006] Some embodiments of this application provide a semiconductor device, including: a first dielectric layer disposed above a substrate and below a second dielectric layer; a first source / drain region located within the first dielectric layer, the first source / drain region including a first semiconductor layer having a first element and a second semiconductor layer having the first element, wherein the concentration of the first element in the first semiconductor layer varies in the direction toward the substrate, and wherein, in a cross-sectional view, the thickness of the first source / drain region is different from the width of the first source / drain region; a second source / drain region located within the second dielectric layer; and a first source / drain contact electrically coupled to the first source / drain region. The first source / drain contact extends to the first upper surface of the first source / drain region and through the first dielectric layer and the second source / drain region, the first source / drain contact being separated from the second source / drain region by a first dielectric pad; a second source / drain contact electrically coupled to the second upper surface of the second source / drain region and extending through the second dielectric layer; a first nanostructure adjacent to the first source / drain region; a second nanostructure adjacent to the second source / drain region; a first gate structure located around the first nanostructure; and a second gate structure located above the first gate structure and around the second nanostructure. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A perspective view of an exemplary stacked transistor according to some embodiments is shown.

[0009] Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A and Figure 14B This is a view of an intermediate stage in the fabrication of stacked transistors according to some embodiments.

[0010] Figure 15A and Figure 15B This is a view of an intermediate stage in the fabrication of stacked transistors according to some embodiments.

[0011] Figure 16A and Figure 16B This is a view of an intermediate stage in the fabrication of stacked transistors according to some embodiments.

[0012] Figure 17A and Figure 17B This is a view of an intermediate stage in the fabrication of stacked transistors according to some embodiments.

[0013] Figure 18 This is a view of an intermediate stage in the fabrication of stacked transistors according to some embodiments. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0016] Stacked transistor structures and methods for forming them are provided. Stacked transistor structures (such as CFETs) and methods for forming them are provided. The stacked transistor structure comprises two transistors vertically stacked and having opposite types (e.g., vertically stacked n-type and p-type transistors). Therefore, the source / drain regions of the vertically stacked transistors can also be vertically stacked. Furthermore, source / drain region contacts can be formed to the upper and / or lower source / drain regions. For example, several source / drain contacts can be formed to couple the lower source / drain region to the upper source / drain region. These contacts can be dual source / drain contacts, comprising a lower contact and an upper contact coupled to each other. The embodiments discussed herein allow for improved regrowth of epitaxial material on the source / drain regions, greater specificity and tuning of dopants, seamless filling to form source / drain contacts, and greater control and versatility in the formation and shape of the lower and upper source / drain contacts. According to various embodiments, the source / drain regions and source / drain contacts are formed to achieve better adjustment and improved yield, resulting in better performance and reliability of the stacked transistors.

[0017] Figure 1 Examples of stacked transistors 10 (including FETs 10U and 10L) according to some embodiments are shown. Figure 1It is a 3D view, and for clarity, some components of the stacked transistors have been omitted.

[0018] The stacked transistor comprises multiple vertically stacked FETs. For example, the stacked transistor may include a lower nanostructure FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type). When the stacked transistor is a CFET, the second device type of the upper nanostructure FET 10U is opposite to the first device type of the lower nanostructure FET 10L. The nanostructure FETs 10U and 10L include a semiconductor nanostructure 26 (including a lower semiconductor nanostructure 26L and an upper semiconductor nanostructure 26U), wherein the semiconductor nanostructure 26 serves as a channel region for the nanostructure FET. The lower semiconductor nanostructure 26L is used for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26U is used for the upper nanostructure FET 10U. In other embodiments, the stacked transistor may also be adapted to other types of transistors (e.g., finFETs, etc.).

[0019] A gate dielectric 78 surrounds the corresponding semiconductor nanostructure 26. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectric 78. Source / drain regions 62 (including a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U) are disposed on opposite sides of the gate dielectric 78 and the corresponding gate electrode 80. Each of the source / drain regions 62 may refer to either a source or a drain, individually or collectively, depending on the context. Isolation components (not shown) may be formed to separate the desired source / drain regions 62 and / or the desired gate electrode 80.

[0020] Figure 1 Reference cross sections used in later figures are also shown. Cross section A-A' is a vertical cross section parallel to the longitudinal axis of the semiconductor nanostructure 26 of the stacked transistor and in the direction of current, for example, between the source / drain regions 62 of the stacked transistor. Cross section B-B' is a vertical cross section perpendicular to cross section A-A' and extends through the source / drain regions 62 of the stacked transistor. For clarity, the following figures may refer to these reference cross sections.

[0021] Figures 2 to 18 Stacked transistors (such as) according to some embodiments are shown. Figure 1 A cross-sectional view of an intermediate stage in the formation of (schematic representation). In the following discussion, unless otherwise stated, the figures with numbers followed by the letter "A" show the process along the... Figure 1 A vertical section view of a section similar to the vertical reference section A-A' in the diagram. The attached diagram with a number followed by the letter "B" shows a section along the same... Figure 1A vertical section diagram of a section similar to the vertical reference section B-B' in the diagram. Furthermore, Figure 18 The vertical section B-B' is shown.

[0022] exist Figure 2 The wafer is provided, and the wafer includes a device layer 30 formed over a substrate 20. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, which may be doped (e.g., having p-type or n-type dopants) or undoped. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, carbon-doped silicon, III-V compound semiconductors; or combinations thereof.

[0023] Semiconductor strips 28 are formed extending upward from semiconductor substrate 20. Each semiconductor strip 28 includes a semiconductor strip 20' (a patterned portion of semiconductor substrate 20, also referred to as semiconductor fin 20') and a multilayer stack 22. The stacked components of the multilayer stack 22 are referred to hereinafter as nanostructures. Specifically, the multilayer stack 22 includes a pseudo-nanostructure 24A, one or more pseudo-nanostructures 24B, a lower semiconductor nanostructure 26L, and an upper semiconductor nanostructure 26U. Pseudo-nanostructures 24A and 24B can be further collectively referred to as pseudo-nanostructure 24, and the lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U can be further collectively referred to as semiconductor nanostructure 26.

[0024] The pseudo-nanostructure 24A is formed of a first semiconductor material, and the pseudo-nanostructure 24B is formed of a second semiconductor material different from the first semiconductor material. The first and second semiconductor materials can be selected from candidate semiconductor materials of the substrate 20. The first and second semiconductor materials have high etch selectivity towards each other. Therefore, in subsequent processes, the pseudo-semiconductor layer 24B can be removed at a faster rate than the pseudo-semiconductor layer 24A.

[0025] Semiconductor nanostructure 26 (including lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U) is formed of one or more third semiconductor materials. The third semiconductor material can be selected from candidate semiconductor materials of the substrate 20. The lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U can be formed of the same semiconductor material or different semiconductor materials. Furthermore, the first and second semiconductor materials of the pseudo-nanostructure 24 exhibit high etch selectivity towards the third semiconductor material of the semiconductor nanostructure 26. Therefore, the pseudo-nanostructure 24 can be selectively removed in subsequent process steps without significantly removing the semiconductor nanostructure 26. In some embodiments, the pseudo-nanostructure 24A is formed of or includes silicon-germanium, the semiconductor nanostructure 26 is formed of silicon, and the pseudo-nanostructure 24B can be formed of germanium or silicon-germanium having a higher percentage of germanium atoms than the pseudo-nanostructure 24A.

[0026] The lower semiconductor nanostructure 26L will provide the channel region for the lower nanostructure FET used in the CFET. The upper semiconductor nanostructure 26U will provide the channel region for the upper nanostructure FET used in the CFET. The semiconductor nanostructure 26, located directly above / below (e.g., in contact with) the pseudo-nanostructure 24B, can be used for isolation and may or may not be used as the channel region for the CFET. The pseudo-nanostructure 24B will then be replaced by an isolation structure defining the boundary between the lower and upper nanostructure FETs.

[0027] To form the semiconductor strip 28, layers of a first semiconductor material, a second semiconductor material, and a third semiconductor material (arranged as shown and described above) can be deposited over the semiconductor substrate 20. These layers can be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited using processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). A patterning process can then be applied to the layers of the first, second, and third semiconductor materials and the semiconductor substrate 20 to define the semiconductor strip 28, which includes a semiconductor strip 20', a pseudo-nanostructure 24, and a semiconductor nanostructure 26.

[0028] Semiconductor fins and nanostructures can be patterned using any suitable method. For example, the patterning process can include one or more photolithography processes, including dual patterning or multi-patterning processes. Typically, dual or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a smaller spacing than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed and patterned using a photolithography process over a substrate. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as an etch mask for the patterning process to etch layers of a first semiconductor material, a second semiconductor material, and a third semiconductor material, and the semiconductor substrate 20. Etching can be performed using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic.

[0029] Similarly, Figure 2 As shown, an isolation region 32, such as a shallow trench isolation (STI) region 32, is formed over the substrate 20 and between adjacent semiconductor strips 28. The STI region 32 may include a dielectric pad and a dielectric material above the dielectric pad. Each of the dielectric pad and the dielectric material may include an oxide such as silicon oxide, a nitride such as silicon nitride, or a combination thereof. Forming the STI region 32 may include: depositing a dielectric layer; and performing a planarization process such as a chemical mechanical polishing (CMP) process, a mechanical polishing process, etc., to remove excess portions of the dielectric material. The deposition process may include ALD, high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. In some embodiments, the STI region 32 includes silicon oxide formed by an FCVD process, followed by an annealing process. The dielectric layer is then recessed to define the STI region 32. The dielectric layer may be recessed such that the upper portion of the semiconductor strip 28 (including the multilayer stack 22) protrudes above the remaining STI region 32.

[0030] After forming the STI region 32, a dummy gate stack 42 can be formed over the upper portion of the semiconductor strip 28 (the portion protruding above the STI region 32) and along the sidewalls of the upper portion of the semiconductor strip 28. Forming the dummy gate stack 42 may include forming a dummy dielectric layer 36 on the semiconductor strip 28. The dummy dielectric layer 36 may be formed or include, for example, silicon oxide, silicon nitride, combinations thereof, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 38 is formed over the dummy dielectric layer 36. The dummy gate layer 38 may be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques, and then planarized, for example, by a CMP process. The material of the dummy gate layer 38 may be conductive or non-conductive and may be selected from the group including amorphous silicon, polycrystalline silicon, poly-SiGe, etc. A mask layer 40, including, for example, silicon nitride, silicon oxynitride, etc., is formed over the planarized dummy gate layer 38. Next, the mask layer 40 can be patterned using photolithography and etching processes to form a mask, which is then used to etch and pattern the dummy gate layer 38, and possibly etch and pattern the dummy dielectric layer 36. The remaining portions of the mask layer 40, the dummy gate layer 38, and the dummy dielectric layer 36 form the dummy gate stack 42.

[0031] exist Figure 3 In this process, a gate spacer 44 and a source / drain recess 46 are formed. First, the gate spacer 44 is formed over the multilayer stack 22 and on the exposed sidewalls of the dummy gate stack 42. The gate spacer 44 can be formed by conformally forming one or more dielectric layers and then anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by deposition processes such as CVD, ALD, etc. Fin spacers 45 (see...) can also be formed. Figure 4B It is part of forming the gate spacer 44.

[0032] Subsequently, source / drain recesses 46 are formed in semiconductor strip 28. The source / drain recesses 46 are formed by etching and can extend through the multilayer stack 22 and into semiconductor strip 20'. The bottom surface of the source / drain recesses 46 can be located above, below, or flush with the top surface of isolation region 32. During the etching process, gate spacers 44 and dummy gate stacks 42 mask portions of semiconductor strip 28. Etching can include a single etching process or multiple etching processes. When the source / drain recesses 46 reach the desired depth, a timing etching process can be used to stop the etching of the source / drain recesses 46.

[0033] Figure 4A and Figure 4B The various subsequent processing steps are shown. Figure 4A The accompanying diagram, with a number followed by the letter "A", shows the A-A' section of the structure, and Figure 4B The accompanying figure, with a number followed by the letter "B", illustrates the B-B' cross-section of the structure. Specifically, internal spacers 54 and a dielectric isolation layer 56 are formed. Forming the internal spacers 54 and the dielectric isolation layer 56 may include an etching process that laterally etches the pseudo-nanostructure 24A and removes the pseudo-nanostructure 24B. The etching process may be isotropic and selective for the material of the pseudo-nanostructure 24, such that the pseudo-nanostructure 24 is etched at a faster rate than the semiconductor nanostructure 26. The etching process may also be selective for the material of the pseudo-nanostructure 24B, such that the pseudo-nanostructure 24B is etched at a faster rate than the pseudo-nanostructure 24A. In this way, the pseudo-nanostructure 24B can be completely removed between the lower semiconductor nanostructure 26L (collectively referred to as the lower semiconductor nanostructure 26L) and the upper semiconductor nanostructure 26U (collectively referred to as the upper semiconductor nanostructure 26U), without completely removing the pseudo-nanostructure 24A.

[0034] In some embodiments, where the pseudo-nanostructure 24B is formed of germanium or silicon-germanium with a high percentage of germanium atoms, the pseudo-nanostructure 24A is formed of silicon-germanium with a low percentage of germanium atoms, and the semiconductor nanostructure 26 is formed of germanium-free silicon, the etching process may include a dry etching process using chlorine gas, with or without plasma. Because the pseudo-gate stack 42 surrounds the sidewalls of the semiconductor nanostructure 26 (see...), Figure 2 Therefore, the dummy gate stack 42 can support the upper semiconductor nanostructure 26U, preventing it from collapsing when the dummy nanostructure 24B is removed. Furthermore, although the sidewalls of the dummy nanostructure 24A are shown as straight after etching, the sidewalls can be concave or convex.

[0035] An internal spacer 54 is formed on the sidewall of the recessed pseudo-nanostructure 24A, and a dielectric isolation layer 56 is formed between the upper semiconductor nanostructure 26U (collectively referred to as the upper semiconductor nanostructure 26U) and the lower semiconductor nanostructure 26L (collectively referred to as the lower semiconductor nanostructure 26L). As will be described in more detail later, source / drain regions will subsequently be formed in the source / drain recess 46, and the pseudo-nanostructure 24A will be replaced with a corresponding gate structure. The internal spacer 54 serves as an isolation component between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the internal spacer 54 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes (such as etching processes for forming the gate structure). On the other hand, the dielectric isolation layer 56 is used to isolate the upper semiconductor nanostructure 26U (collectively referred to as the upper semiconductor nanostructure 26L) from the lower semiconductor nanostructure 26L (collectively referred to as the lower semiconductor nanostructure 26L). In addition, the intermediate semiconductor nanostructure (the semiconductor nanostructure 26 in contact with the dielectric isolation layer 56) and the dielectric isolation layer 56 can define the boundary between the lower nanostructure FET and the upper nanostructure FET.

[0036] The internal spacer 54 and dielectric isolation layer 56 can be formed by conformally depositing an insulating material in the source / drain trench 46, on the sidewalls of the pseudo-nanostructure 24, and between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L, and then etching the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon oxycarbonate, silicon oxycarbonate, silicon oxynitride, etc. Other low dielectric constant (low k) materials with a k value of less than about 3.5 can be used. The insulating material can be formed by a deposition process, such as ALD, CVD, etc. The etching of the insulating material can be anisotropic or isotropic. The insulating material (when etched) has a portion retained in the sidewalls of the pseudo-nanostructure 26A (thus forming the internal spacer 54) and a portion retained between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L (thus forming the dielectric isolation layer 56).

[0037] like Figure 4A and Figure 4B As further shown, a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U are formed. The lower epitaxial source / drain region 62L is formed in the lower portion of the source / drain recess 46. The lower epitaxial source / drain region 62L is in contact with the lower semiconductor nanostructure 26L, but not with the upper semiconductor nanostructure 26U. An internal spacer 54 electrically insulates the lower epitaxial source / drain region 62L from the pseudo-nanostructure 24A, which will be replaced with a replacement gate in a subsequent process.

[0038] The lower epitaxial source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon doped with n-type dopants such as phosphorus or arsenic. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material may include silicon or silicon-germanium doped with p-type dopants such as boron or indium. The lower epitaxial source / drain region 62L may be in-situ doped and may or may not be implanted with the corresponding p-type or n-type dopants. During the epitaxial process of the lower epitaxial source / drain region 62L, the exposed surfaces (e.g., sidewalls) of the upper semiconductor nanostructure 26U may be masked to prevent undesirable epitaxial growth on the upper semiconductor nanostructure 26U. After growing the lower epitaxial source / drain region 62L, the mask on the upper semiconductor nanostructure 26U can then be removed. The resulting epitaxial source / drain region 62 can include multiple semiconductor layers. For example, the first semiconductor layer includes a first element (e.g., silicon, germanium, boron, phosphorus, etc.), and the second semiconductor layer also includes the first element, wherein the concentration of the first element in the semiconductor layers varies in the direction toward the substrate. Furthermore, in situations such as... Figure 4B In the cross-section shown, the thickness of the epitaxial source / drain region 62 may be different from the width of the epitaxial source / drain region 62.

[0039] Due to the epitaxial process used to form the lower epitaxial source / drain regions 62L, the upper surface of the lower epitaxial source / drain regions 62L has small planes that extend laterally outward beyond the sidewalls of the multilayer stack 22. In some embodiments, adjacent lower epitaxial source / drain regions 62L remain separated after the epitaxial process is completed. In other embodiments, these small planes cause adjacent lower epitaxial source / drain regions 62L of the same FET to merge.

[0040] A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed above the lower epitaxial source / drain region 62L. The first CESL 66 can be formed from a dielectric material with high etch selectivity relative to the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and can be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 can be formed from a dielectric material, which can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 68 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0041] The formation process may include: depositing a conformal CESL layer; depositing material for the first ILD 68; and a subsequent planarization process and then an etch-back process. In some embodiments, the first ILD 68 is first etched, leaving the first CESL 66 unetched. An anisotropic etching process is then performed to remove the portion of the first CESL 66 above the recessed first ILD 68. After recessing, the sidewalls of the upper semiconductor nanostructure 26U are exposed.

[0042] Then, an upper epitaxial source / drain region 62U is formed in the upper portion of the source / drain recess 46. The upper epitaxial source / drain region 62U can be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 26U. The material of the upper epitaxial source / drain region 62U can be selected from the same group of candidate materials used to form the lower epitaxial source / drain region 62L, depending on the desired conductivity type of the upper epitaxial source / drain region 62U. In embodiments where the stacked transistor is a CFET, the conductivity type of the upper epitaxial source / drain region 62U can be opposite to that of the lower epitaxial source / drain region 62L. For example, the upper epitaxial source / drain region 62U can be doped in opposite ways to the lower epitaxial source / drain region 62L. Alternatively, the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L can have the same conductivity type. The upper epitaxial source / drain region 62U may be doped in situ with n-type or p-type dopants and / or may be implanted with n-type or p-type dopants. Adjacent upper epitaxial source / drain regions 62U may remain separated after the epitaxial process, or they may be merged.

[0043] After forming the epitaxial source / drain region 62U, a second CESL 70 and a second ILD 72 are formed. The materials and formation methods can be similar to those of the first CESL 66 and the first ILD 68, respectively, and will not be discussed in detail here. The formation process may include: depositing layers for the second CESL 70 and the second ILD 72; and performing a planarization process to remove excess portions of the corresponding layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacer 44, and the mask 40 (if present) or the dummy gate 38 are substantially coplanar (within process variations). Therefore, the top surface of the mask 40 (if present) or the dummy gate 38 is exposed through the second ILD 72. In the illustrated embodiment, the mask 40 is retained after the removal process. In other embodiments, the mask 40 is removed, thereby exposing the top surface of the dummy gate 38 through the second ILD 72.

[0044] exist Figure 5A and Figure 5BIn this process, a gate replacement process is performed to replace the dummy gate stack 42 and the dummy nanostructure 24A with the gate stack 76. The gate replacement process includes first removing the remaining portions of the dummy gate stack 42 and the dummy nanostructure 24A. The dummy gate stack 42 is removed in one or more etching processes, thereby defining a trench between the gate spacers 44 and exposing the upper portion of the semiconductor strip 28. The remaining portions of the dummy nanostructure 24A are then removed by etching, such that the trench extends between the semiconductor nanostructures 26. In the etching process, the material of the dummy nanostructure 24A is etched at a rate faster than the material of the semiconductor nanostructure 26, the dielectric isolation layer 56, and the internal spacers 54. The etching can be isotropic. For example, when the dummy nanostructure 24A is formed of silicon germanium and the semiconductor nanostructure 26 is formed of silicon, the etching process can include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0045] Then, a gate dielectric 78 is deposited in the recesses between the gate spacers 44 and on the exposed semiconductor nanostructure 26. The gate dielectric 78 is conformally formed on the exposed surface of the recesses (removed gate stack 42 and pseudo nanostructure 24A) including the semiconductor nanostructure 26 and the gate spacers 44. In some embodiments, the gate dielectric 78 encapsulates all (e.g., four) sides of the semiconductor nanostructure 26. Specifically, the gate dielectric 78 may be formed on the top surface of the fin 20'; the top, sidewalls, and bottom surfaces of the semiconductor nanostructure 26; and the sidewalls of the gate spacers 44. The gate dielectric 78 may include oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers thereof, etc. The gate dielectric 78 may include high dielectric constant (high k) materials having a k value greater than about 9.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric 78 may include molecular beam deposition (MBD), ALD, PECVD, etc., followed by a planarization process (e.g., CMP) to remove the portion of the gate dielectric 78 located above the second ILD 72. Although a single-layer gate dielectric 78 is shown, the gate dielectric 78 may include multiple layers, such as an interface layer and an upper high-k dielectric layer.

[0046] A lower gate electrode 80L is formed on a gate dielectric 78 surrounding the lower semiconductor nanostructure 26L. For example, the lower gate electrode 80L encapsulates the lower semiconductor nanostructure 26L. The lower gate electrode 80L can be formed of a metallic material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, or multilayers thereof. Although a single-layer gate electrode is shown, the lower gate electrode 80L may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0047] The lower gate electrode 80L is formed of a material suitable for the device type of the lower nanostructure FET. For example, the lower gate electrode 80L may include one or more work function adjustment layers formed of a material suitable for the device type of the lower nanostructure FET. In some embodiments, the lower gate electrode 80L includes an n-type work function adjustment layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, etc. In some embodiments, the lower gate electrode 80L includes a p-type work function adjustment layer, which may be formed of titanium nitride, tantalum nitride, tungsten nitride, combinations thereof, etc. Additionally or optionally, the lower gate electrode 80L may include a dipole inducing element suitable for the device type of the lower nanostructure FET. Acceptable dipole inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0048] The lower gate electrode 80L can be formed by: conformally depositing one or more gate electrode layers; or by recessing the gate electrode layers. Any acceptable etching process, such as dry etching, wet etching, or combinations thereof, can be performed to recess the gate electrode layers. The etching can be isotropic. Etching the lower gate electrode 80L can expose the upper semiconductor nanostructure 26U.

[0049] In some embodiments, an isolation layer (not explicitly shown) may optionally be formed on the lower gate electrode 80L. The isolation layer serves as an isolation component between the lower gate electrode 80L and the subsequently formed upper gate electrode 80U. The isolation layer may be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, etc.) and subsequently recessing the dielectric material to expose the upper semiconductor nanostructure 26U.

[0050] Then, an upper gate electrode 80U is formed on the isolation layer (if present) or lower gate electrode 80L described above. The upper gate electrode 80U is disposed between the upper semiconductor nanostructures 26U. In some embodiments, the upper gate electrode 80U encapsulates the upper semiconductor nanostructures 26U. The upper gate electrode 80U may be formed from the same candidate materials and candidate processes used to form the lower gate electrode 80L. The upper gate electrode 80U is formed from a material suitable for the device type of the upper nanostructure FET. For example, the upper gate electrode 80U may include one or more work function adjustment layers (e.g., n-type work function adjustment layers and / or p-type work function adjustment layers) formed from a material suitable for the device type of the upper nanostructure FET. Although a single-layer gate electrode 80U is shown, the upper gate electrode 80U may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0051] Furthermore, a removal process is performed to make the top surfaces of the upper gate electrode 80U and the second ILD 72 flush. The removal process used to form the gate dielectric 78 can be the same as the removal process used to form the upper gate electrode 80U. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc., can be utilized. After the planarization process, the top surfaces of the upper gate electrode 80U, the gate dielectric 78, the second ILD 72, and the gate spacer 44 are substantially coplanar (within process variations). Each corresponding pair of gate dielectric 78 and gate electrode 80 (including the upper gate electrode 80U and / or the lower gate electrode 80L) can be collectively referred to as a “gate structure” 76 (including the upper gate structure 76U and the lower gate structure 76L). Each gate structure 76 extends along three sides (e.g., the top surface, sidewalls, and bottom surface) of the channel region of the semiconductor nanostructure 26 (see Figure 1 The lower gate structure 76L may also extend along the sidewalls and / or top surface of the semiconductor fin 20'.

[0052] In some embodiments (see example) Figures 14A to 17A A gate mask 81 may be formed over the gate stack 42. The formation process may include: recessing the gate stack 76; filling the resulting recess with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, or combinations thereof; and performing a planarization process to remove excess dielectric material over the second ILD 72. In some embodiments, the gate mask 81 is formed in a later processing step or may be omitted.

[0053] like Figure 5B As further shown, a contact via 74 is formed having contact spacers 75 disposed on its sidewalls to at least partially extend through the device layer 30. As an example of forming the contact via 74, an opening can be formed through a combination of photolithography and etching processes through the second ILD 72, the second CESL 70, the first ILD 68, the first CESL 66, the STI region 32, and any other intermediate layers. The contact spacers 75 can be deposited along the sidewalls of the opening using a suitable dielectric material. The contact via 74 is then formed in the opening and can include multiple layers (not shown separately), such as pads (e.g., diffusion barrier layers, adhesive layers, etc.) and conductive material. The pads can include titanium, titanium nitride, tantalum, tantalum nitride, etc., or combinations thereof. The conductive material can be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A planarization process, such as CMP, can be performed to remove excess material from the top surface of the second ILD 72. The remaining pads and conductive material form the contact via 74.

[0054] In some embodiments, the contact spacer 75 may include silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, combinations thereof, etc., and may be formed by conformally depositing an insulating material layer via CVD, ALD, etc. The lateral portions of the insulating material layer may then be etched away using an anisotropic etching process such as plasma-based dry etching to form the contact spacer 75. A conductive material, including cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc., may then be formed in the opening. A planarization process, such as CMP, may be implemented to remove excess material from the top surface of the second ILD 72.

[0055] As shown, the contact via 74 and contact spacer 75 can be formed to pass through the first CESL 66, the first ILD 68, the second CESL 70, the second ILD 72, and the STI region 32. As shown in the following figures, the contact via 74 can provide electrical connections to the back-side interconnect structure 134 and / or the front-side interconnect structure 120 (e.g., via subsequently formed upper source / drain contacts). In this way, an interconnection between the front-side interconnect structure 120 and the back-side interconnect structure 134 can be achieved.

[0056] Figures 6A to 14B The diagram illustrates the formation of source / drain contacts 96 (e.g., contact plugs) and front-side interconnect structures 120 according to some embodiments to be electrically coupled to upper epitaxial source / drain regions 62U and lower epitaxial source / drain regions 62L. Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A and Figure 14A The A-A' section of the structure is shown, and Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B and Figure 14B The B-B' section of the structure is shown. As described in more detail below, a lower source / drain contact opening 82L is formed to the lower epitaxial source / drain region 62L, a lower source / drain contact 96L is formed in the lower source / drain contact opening 82L, an upper source / drain contact opening 82U is formed to the upper epitaxial source / drain region 62U, and an upper source / drain contact 96U is formed in the upper source / drain contact opening 82U.

[0057] exist Figure 6A and Figure 6BIn this configuration, a third ILD 106 can be formed above the second ILD 72 and the upper gate structure 76U, and a lower source / drain contact opening 82L is formed through the third ILD 106, the second ILD 72, the upper epitaxial source / drain region 62U, and the first ILD 68 to the lower epitaxial source / drain region 62L. In some embodiments, a third CESL 104 can be formed prior to the formation of the third ILD 106. The third CESL 104 can be formed from a dielectric material with high etch selectivity relative to the etching of the third ILD 106, such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, etc., which can be formed by any suitable deposition process, such as CVD, ALD, etc. The third ILD 106 can be formed using flowable CVD, ALD, etc., and the material can include PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method, such as CVD, PECVD, etc.

[0058] For example, the lower source / drain contact opening 82L is formed to expose (and optionally extend to) the lower epitaxial source / drain region 62L. Specifically, the lower source / drain contact opening 82L may extend through the third ILD 106, the third CESL 104, the second ILD 72, the second CESL 70, the upper epitaxial source / drain region 62U above, the first ILD 68 and / or the first CESL 66 to expose the lower epitaxial source / drain region 62L and partially extend into the lower epitaxial source / drain region 62L.

[0059] In some embodiments, the lower source / drain contact opening 82L can be formed by a combination of sequential photolithography and etching processes. According to some embodiments, the lower source / drain contact opening 82L (and the lower source / drain contact 96L) is formed before the upper source / drain contact opening 82U (and the upper source / drain contact 96U) is formed.

[0060] According to various embodiments, the lower source / drain contact opening 82L can have a high aspect ratio. For example, the aspect ratio of the lower source / drain contact opening 82L can be as high as about 8 to about 15. Furthermore, the width (e.g., diameter) of the lower source / drain contact opening 82L can be in the range of about 4 nm to about 15 nm, wherein the depth is in the range of about 32 nm to about 225 nm.

[0061] exist Figure 7A and Figure 7BIn this configuration, a first dielectric pad 84 is formed along the sidewall of the lower source / drain contact opening 82L. The first dielectric pad 84 can be made of a similar material to that described above for the bonding contact spacer 75 and formed using a similar process. For example, the first dielectric pad 84 can include silicon nitride, including silicon oxynitride, silicon carbonitride, etc., and can be formed by conformally depositing an insulating material layer using CVD, ALD, etc. The lateral portions of the insulating material layer can then be etched away using an anisotropic etching process such as plasma-based dry etching to form the first dielectric pad 84.

[0062] As shown, in some embodiments, the surface of the lower epitaxial source / drain region 62L can be exposed after an etching process. Furthermore, the upper portion of the first dielectric pad 84 can be recessed from the top surface of the structure (e.g., the third ILD 106). In other embodiments (not specifically shown), portions of the first dielectric pad 84 can be retained, allowing the upper portion to be substantially flush with the top surface of the structure (e.g., the third ILD 106).

[0063] exist Figure 8A and Figure 8B In the middle, a lower metal-semiconductor alloy region 88L is formed along the exposed surface of the lower epitaxial source / drain region 62L. The lower metal-semiconductor alloy region 88L will be located at the interface between the lower epitaxial source / drain region 62L and the subsequently formed lower source / drain contact 96L (see...). Figure 13A and Figure 13B The lower metal-semiconductor alloy region 88L can be a silicide region formed by metal silicides (e.g., nickel silicide (NiSi), titanium silicide (TiSi), tungsten silicide (WSi), molybdenum silicide (MoSi), ruthenium silicide (RuSi), zirconium silicide (ZrSi), antimony silicide (SbSi), cobalt silicide (CoSi), palladium silicide (PdSi), etc.), a germanium region formed by metal germanides (e.g., nickel germanide (NiGe), titanium germanide (TiGe), tungsten germanide (WGe), molybdenum germanide (MoGe), ruthenium germanide (RuGe), zirconium germanide (ZrGe), antimony germanide (SbGe), cobalt germanide (CoGe), palladium germanide (PdGe), etc.), or a silicon-germanium region formed by metal silicides and metal germanides. It should be noted that, for simplicity, the metal-semiconductor alloy region 88 may sometimes be broadly referred to as a silicide region or a metal silicide region to include the silicides, germanides and / or silicongerides listed above.

[0064] The lower metal-semiconductor alloy region 88L can be formed by depositing metal in the lower source / drain contact opening 82L (e.g., as indicated above) and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material (e.g., silicon, silicon-germanium, germanium, etc.) of the lower epitaxial source / drain region 62L to form a low-resistance metal-semiconductor alloy, such as nickel, titanium, tungsten, molybdenum, ruthenium, zirconium, antimony, cobalt, palladium, tantalum, platinum, other noble metals, other refractory metals, rare earth metals, or alloys thereof.

[0065] Furthermore, the metal can be deposited using deposition processes such as ALD, CVD, PVD, etc. Following the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the lower source / drain opening 82L (such as from the surface of the lower metal-semiconductor alloy region 88L) used for the lower source / drain contact 96L. In some embodiments, the lower metal-semiconductor alloy region 88L (e.g., comprising silicon-germanium epitaxial material) is formed of MoSiGe, RuSiGe, NiSiGe, PtSiGe, PdSiGe, or NbSiGe, wherein the metal is deposited by CVD or PVD, followed by a thermal annealing process at a temperature ranging from 400°C to 1000°C. Therefore, the lower metal-semiconductor alloy region 88L can be close to the silicon valence band.

[0066] Optionally, the lower epitaxial source / drain region 62L may be implanted with dopant and activated by a thermal annealing process. For example, in an embodiment where the lower source / drain region 62L comprises silicon-germanium epitaxial material, the implantation process may include a boron dopant, followed by annealing at a temperature ranging from 800°C to 1200°C. Optionally, in an embodiment where the lower source / drain region 62L comprises silicon epitaxial material, the implantation process may include phosphorus and / or arsenic dopant, followed by annealing at a temperature ranging from 800°C to 1200°C. In either case, implantation increases the dopant concentration to improve the performance of the lower epitaxial source / drain region 62L and reduces resistance with the lower metal-semiconductor alloy region 88L.

[0067] According to some embodiments, the implantation process can be performed before the formation of the lower metal-semiconductor alloy region 88L. In other embodiments, the implantation process can occur simultaneously with (e.g., interleaved with) the formation of the lower metal-semiconductor alloy region 88L or after its formation. As noted above, since the upper epitaxial source / drain region 62U is covered and protected by the first dielectric pad 84, the implantation process for the lower epitaxial source / drain region 62L can be specific to the conductivity type of the lower transistor in the stacked transistor.

[0068] The presence of a first dielectric pad 84 along the sidewall of the lower source / drain contact opening 82L provides an advantage. For example, during the formation of the lower metal-semiconductor alloy region 88L, the first dielectric pad 84 acts as a protective barrier for the upper epitaxial source / drain region 62U. Therefore, the materials and process conditions used to form the lower metal-semiconductor alloy region 88L can be selected to improve the electrical connection between the lower epitaxial source / drain region 62L and the subsequently formed lower source / drain contact 96L. Furthermore, the implantation process (if implemented) can utilize different dopants and process conditions than those subsequently used in the implantation process for the upper epitaxial source / drain region 62U (if implemented).

[0069] exist Figure 9A and Figure 9B In this process, a lower source / drain contact 96L is formed in the lower source / drain contact opening 82L to electrically couple to the lower epitaxial source / drain region 62L. For example, a first conductive material is deposited to fill the remaining portion of the lower source / drain contact opening 82L. In some embodiments, the first conductive material may be a metal, such as ruthenium, tungsten, molybdenum, cobalt, copper, copper alloys, silver, gold, aluminum, nickel, combinations thereof, etc., and may be formed by plating processes, PVD, CVD, ALD, etc. A removal process may be performed to remove excess first conductive material from the top surface of the gate spacer 44 and the third ILD 106. The remaining first conductive material forms the lower source / drain contact 96L in the lower source / drain contact opening 82L. In some embodiments, a planarization process such as CMP, etch-back process, combinations thereof is utilized. After the planarization process, the top surfaces of the gate spacer 44, the third ILD 106, and the lower source / drain contact 96L are substantially coplanar (within process variations).

[0070] According to various embodiments, the lower metal-semiconductor alloy region 88L can serve as a seed layer in the deposition of a first conductive material to form the lower source / drain contact 96L. The first conductive material can fill the lower source / drain contact opening 82L from the bottom upwards, such as from the lower metal-semiconductor alloy region 88L and upwards toward the upper portion of the lower source / drain contact opening 82L. Specifically, the first conductive material is deposited above and on itself the lower metal-semiconductor alloy region 88L at a rate greater than that along the first dielectric pad 84 along the sidewall. Therefore, the first conductive material can fill the lower source / drain contact opening 82L to form the lower source / drain contact 96L as substantially seamless or without voids caused by shrinkage. The resulting lower source / drain contact 96L can be formed with higher yield and higher performance and reliability.

[0071] exist Figure 10A and Figure 10BIn this process, a fourth ILD 142 can be formed above the third ILD 106, and a first upper source / drain contact opening 82UA and a second upper source / drain contact opening 82UB are formed through the fourth ILD 142, the third ILD 106, and the second ILD 72 to the upper epitaxial source / drain region 62U. In some embodiments, a fourth CESL 140 can be formed prior to the formation of the fourth ILD 142. The fourth CESL 140 can be formed from a dielectric material with high etch selectivity relative to the etching of the fourth ILD 142, such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, etc., which can be formed by any suitable deposition process, such as CVD, ALD, etc. The fourth ILD 142 can be formed using flowable CVD, ALD, etc., and the material can include PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method, such as CVD, PECVD, etc.

[0072] For example, an upper source / drain contact opening 82U is formed to expose (and optionally extend to) the upper epitaxial source / drain region 62U. Specifically, the upper source / drain contact opening 82U may extend through the fourth ILD 142, the third ILD 106, and the second CESL 70 to expose the upper epitaxial source / drain region 62U and partially extend into it. The first upper source / drain contact opening 82UA will subsequently accommodate a first upper source / drain contact 96UA connected to the corresponding lower source / drain contact 96L. The second upper source / drain contact opening 82UB will subsequently accommodate a second upper source / drain contact 96UB that may or may not be connected to the corresponding contact via 74. The upper source / drain contact opening 82U may be formed similarly as described above in conjunction with the lower source / drain contact opening 82L, such as using one or more photolithography and / or etching processes.

[0073] As shown, the first upper source / drain contact opening 82UA can expose the sidewalls of the lower source / drain contacts 96L and / or portions of their corresponding first dielectric pads 84. As discussed in more detail below, the correspondence between the first upper source / drain contact 96UA and the lower source / drain contact 96L can be collectively referred to as the dual source / drain contact 96D. Therefore, the corresponding upper epitaxial source / drain region 62U and lower epitaxial source / drain region 62L can be electrically coupled through the subsequently formed dual source / drain contact 96D (see...). Figure 13A and Figure 13B ).

[0074] As further shown, some of the second upper source / drain contact openings 82UB can expose the sidewalls of the contact vias 74. Therefore, the corresponding upper epitaxial source / drain region 62U can be electrically coupled to other integrated circuit components via the subsequently formed upper source / drain contacts 96UB and the corresponding contact vias 74. Although not specifically shown, other second upper source / drain contact openings 82UB can expose the corresponding upper epitaxial source / drain region 62U without exposing either the contact vias 74 or the lower source / drain contacts 96L. Furthermore, the first upper source / drain contact opening 82UA can expose part or all of the upper surface of the corresponding lower source / drain contact 96L. Similarly, the second upper source / drain contact openings 82UB can expose part or all of the upper surface of the corresponding contact vias 74.

[0075] exist Figure 11A and Figure 11B In this process, a second dielectric pad 90 is formed along the sidewall of the upper source / drain contact opening 82U. The second dielectric pad 90 can be formed from a similar material to that described above in conjunction with the first dielectric pad 84 and using a similar process. The second dielectric pad 90 can be made of the same or different material as the first dielectric pad 84. For example, the second dielectric pad 90 can include silicon nitride, including silicon oxynitride, silicon carbonitride, etc., and can be formed by conformally depositing an insulating material layer via CVD, ALD, etc. The lateral portions of the insulating material layer can then be etched away using an anisotropic etching process such as plasma-based dry etching to form the second dielectric pad 90.

[0076] As shown, in some embodiments, the surface of the upper epitaxial source / drain region 62U can be exposed after an etching process. Furthermore, the upper portion of the second dielectric pad 90 can be recessed from the top surface of the structure (e.g., the fourth ILD 142). In other embodiments (not specifically shown), portions of the second dielectric pad 90 can be retained, allowing the upper portion to be substantially flush with the top surface of the structure (e.g., the fourth ILD 142). Any of these phenomena may also occur at the top surface of the lower source / drain contact 96L and the contact via 74.

[0077] exist Figure 12A and Figure 12B In the middle, an upper metal-semiconductor alloy region 88U is formed along the exposed surface of the upper epitaxial source / drain region 62U. The upper metal-semiconductor alloy region 88U will be located at the interface between the upper epitaxial source / drain region 62U and the subsequently formed upper source / drain contact 96U (see...). Figure 13A and Figure 13BThe upper metal-semiconductor alloy region 88U can be formed from a similar material and through a similar process as described above in conjunction with the lower metal-semiconductor alloy region 88L. For example, the upper metal-semiconductor alloy region 88U can be a silicide region formed from metal silicides (e.g., NiSi, TiSi, WSi, MoSi, RuSi, ZrSi, SbSi, CoSi, PdSi, etc.), a germanide region formed from metal germanides (e.g., NiGe, TiGe, WGe, MoGe, RuGe, ZrGe, SbGe, CoGe, PdGe, etc.), or a silicon-germanide region formed from both metal silicides and metal germanides. As noted above, for simplicity, the metal-semiconductor alloy region 88 can sometimes be broadly referred to as a silicide region or a metal silicide region to include the silicides, germanides, and / or silicon-germanides listed above.

[0078] The upper metal-semiconductor alloy region 88U can be formed by depositing metal in the upper source / drain contact opening 82U (e.g., as indicated above) and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material (e.g., silicon, silicon-germanium, germanium, etc.) of the upper epitaxial source / drain region 62U to form a low-resistance metal-semiconductor alloy, such as nickel, titanium, tungsten, molybdenum, ruthenium, zirconium, antimony, cobalt, palladium, tantalum, platinum, other noble metals, other refractory metals, rare earth metals, or alloys thereof.

[0079] Furthermore, the metal can be deposited using deposition processes such as ALD, CVD, PVD, etc. Following the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the upper source / drain opening 82U (before forming the upper source / drain contact 96U) (e.g., from the surface of the upper metal-semiconductor alloy region 88U). In some embodiments, the upper metal-semiconductor alloy region 88U (e.g., comprising silicon epitaxial material) is formed of TiSi, MoSi, RuSi, NiSi, PtSi, PdSi, NbSi, or combinations thereof, wherein the metal is deposited by CVD or PVD, followed by a thermal annealing process at a temperature ranging from 400°C to 1000°C.

[0080] Optionally, the upper epitaxial source / drain region 62U may be implanted with dopants and activated by a thermal annealing process. For example, in embodiments where the upper epitaxial source / drain region 62U comprises silicon epitaxial material, the implantation process may include phosphorus and / or arsenic dopants, followed by annealing at a temperature ranging from 800°C to 1200°C. Optionally, in embodiments where the upper source / drain region 62U comprises silicon-germanium epitaxial material, the implantation process may include boron dopants, followed by annealing at a temperature ranging from 800°C to 1200°C. In either case, implantation increases the dopant concentration to improve the performance of the upper epitaxial source / drain region 62U and reduces resistance with the upper metal-semiconductor alloy region 88U.

[0081] According to some embodiments, the implantation process can be performed before the formation of the upper metal-semiconductor alloy region 88U. In other embodiments, the implantation process can occur simultaneously with (e.g., interleaved with) the formation of the upper metal-semiconductor alloy region 88U or after its formation. As noted above, since the lower epitaxial source / drain region 62L is covered and protected by the lower source / drain contact 96L, the implantation process for the upper epitaxial source / drain region 62U can be specific to the conductivity type of the upper transistor of the stacked transistor.

[0082] In some embodiments, the upper metal-semiconductor alloy region 88U may include titanium (e.g., including TiSi). For example, depositing one or more metals (e.g., including titanium) over the upper epitaxial source / drain region 62U may also cause those metals (e.g., titanium) to be deposited over other exposed surfaces, such as the metal surfaces of the lower source / drain contacts 96L and / or contact vias 74. After forming the upper metal-semiconductor alloy region 88U, a metal nitride layer 92 (e.g., titanium nitride) is formed. Subsequent cleaning steps to remove unsiliconized metal may not remove the metal nitride layer 92 or may remove some of the metal nitride layer 92.

[0083] It should be understood that the interface between the metal nitride layer 92 and the adjacent conductive material can have a non-negligible resistance (e.g., relatively high metal-to-metal resistance) under various operating conditions (e.g., including standard condition sets). The adjacent conductive material may include the first conductive material of the lower source / drain contact 96L, the conductive material of the contact via 74, or the second conductive material of the subsequently formed upper source / drain contact 96U. However, in some embodiments, the implantation process described above (if performed after the formation of the upper metal-semiconductor alloy region 88U) may result in dopant (e.g., phosphorus and / or arsenic) implantation, damage, and / or destruction of the metal nitride layer 92. The interface between the damaged metal nitride layer 92 and the adjacent conductive material may be reduced (e.g., reduced to a relatively low metal-to-metal resistance) under the same conditions (e.g., operating conditions, such as standard condition sets). Optionally, a processing process can be implemented to remove the metal nitride layer 92. For example, a treatment using chlorine gas can help pull back or remove the metal nitride layer 92. Alternatively or additionally, the subsequently deposited conductive material may include the same material, such as the same metal nitride, to reduce the resistance caused by the metal nitride layer 92.

[0084] The previously described process steps, implemented above the lower epitaxial source / drain region 62L via the lower source / drain contact opening 82L, and the formation of the lower source / drain contact 96L, offer advantages. For example, during the formation of the upper metal-semiconductor alloy region 88U, the lower source / drain contact 96L similarly protects the lower epitaxial source / drain region 62L (and the lower metal-semiconductor alloy region 88L). Therefore, the materials and process conditions used to form the upper metal-semiconductor alloy region 88U can be selected to improve the electrical connection between the upper epitaxial source / drain region 62U and the subsequently formed upper source / drain contact 96U. Furthermore, the implantation process (if implemented) can utilize different dopants and process conditions than those previously used in the implantation process (if implemented) for the lower epitaxial source / drain region 62L.

[0085] exist Figure 13A and Figure 13BIn this process, an upper source / drain contact 96U is formed in the upper source / drain contact opening 82U to electrically couple to the upper epitaxial source / drain region 62U. For example, a second conductive material is deposited to fill the remaining portion of the upper source / drain contact opening 82U. In some embodiments, the second conductive material can be a metal, such as ruthenium, tungsten, molybdenum, cobalt, copper, copper alloys, silver, gold, aluminum, nickel, combinations thereof, etc., and can be formed by plating processes, PVD, CVD, ALD, etc. A removal process can be performed to remove excess second conductive material from the top surface of the fourth ILD 142. The remaining second conductive material forms the upper source / drain contact 96U in the upper source / drain contact opening 82U. In some embodiments, a planarization process such as CMP, etch-back process, combinations thereof is utilized. After the planarization process, the top surfaces of the fourth ILD 142 and the upper source / drain contact 96U are substantially coplanar (within process variations).

[0086] As noted above, the upper source / drain contact 96U may include a first upper source / drain contact 96UA and a second upper source / drain contact 96UB. The first upper source / drain contact 96UA is formed above some of the first upper epitaxial source / drain region 62UA and the lower source / drain contact 96L and is electrically connected to some of the first upper epitaxial source / drain region 62UA and the lower source / drain contact 96L. The second upper source / drain contact 96UB is formed above some of the second upper epitaxial source / drain region 62UB and the optional contact via 74 and is electrically connected to some of the second upper epitaxial source / drain region 62UB and the optional contact via 74. In both types, the portion of the upper source / drain contact 96U located within the fourth ILD 142 can be directly disposed above or on the upper surface of the lower source / drain contact 96L or contact via 74 (e.g., and placed thereon). Furthermore, another portion of the upper source / drain contact 96U extending into the upper epitaxial source / drain region 62U can extend along the corresponding lower source / drain contact 96L or contact via 74. As shown, the second dielectric pad 90 can be interposed between small portions, large portions, or all of the upward and downward boundaries.

[0087] exist Figure 14A and Figure 14BIn this process, a fifth CESL 108 and a fifth ILD 110 can be formed above the fourth ILD 142, and then a gate contact 112 and a source / drain via 114 are formed to contact the upper gate electrode 80U and the source / drain contact 96, respectively. As an example of forming the gate contact 112 and the source / drain via 114, openings for the gate contact 112 and the source / drain via 114 are formed through the fifth ILD 110 and the fifth CESL 108. The openings can be formed using acceptable photolithography and etching techniques. Pads (not shown separately), such as diffusion barrier layers and adhesive layers, and conductive materials are formed in the openings. Pads can include titanium, titanium nitride, tantalum, tantalum nitride, etc. Conductive materials can be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A planarization process, such as CMP, can be implemented to remove excess material from the top surface of the fifth ILD 110. The remaining padding and conductive material form the gate contact 112 and the source / drain via 114 in the opening. The gate contact 112 and the source / drain via 114 can be formed in different processes or in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the gate contact 112 and the source / drain via 114 can be formed in a different cross-section, which avoids short circuits in the contacts.

[0088] A front-side interconnect structure 120 is formed on device layer 30. The front-side interconnect structure 120 includes a dielectric layer 122 and a layer of conductive components 124 located within the dielectric layer 122. The dielectric layer 122 may include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 122 may also include a passivation layer formed of a non-low-k and dense dielectric material above the low-k dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, or combinations thereof. The dielectric layer 122 may also include a polymer layer.

[0089] Conductive components 124 may include wires and vias, which can be formed using an inlay process. Conductive components 124 may include metal wires and metal vias, which include diffusion barriers and copper-containing material above the diffusion barriers. Aluminum pads electrically connected to the metal wires and vias may also be present above the metal wires and vias. In some embodiments, contacts to the lower gate stack 76L and the lower epitaxial source / drain region 62L may be fabricated via the back side of device layer 30 (e.g., the side opposite to the front interconnect structure 120).

[0090] Although not specifically shown, according to various embodiments, contacts to the lower gate stack 76L and the lower epitaxial source / drain region 62L can be fabricated on the back side of device layer 30 (e.g., the side opposite to the front interconnect structure 120). For example, device layer 30 would be situated between the front interconnect structure 120 and the back interconnect structure (not specifically shown). The back interconnect structure can be electrically coupled via contacts and is substantially similar to the front interconnect structure 120 as described above.

[0091] Figures 15A to 18 Various additional embodiments and depictions relating to the formation of the lower source / drain contact 96L and the upper source / drain contact 96U (e.g., including a dual source / drain contact 96D) are shown. It should be noted that components discussed in connection with these embodiments may be used in conjunction with any other embodiments described above or below, where appropriate and suitable. It should be understood that forming the source / drain contact 96 (and other illustrated components) in the following embodiments may include similar processes and materials as described above, unless otherwise stated.

[0092] Figure 15A and Figure 15B Exemplary illustrations are provided for how some of the components described above can be formed as a result of practical and / or process design choices (e.g., tooling or methods). For example, the formation of an opening such as source / drain contact opening 82 can be tapered, such that the upper portion of the opening is wider than the body. Thus, source / drain contact 96 can be formed to have a similar shape.

[0093] exist Figure 16A and Figure 16B In this configuration, the lower source / drain contact 96L can be formed to partially fill the lower source / drain contact opening 82L. For example, the lower source / drain contact 96L can be formed to have an uppermost surface that is lower than the uppermost surface of the upper epitaxial source / drain region 62U through which the lower source / drain contact opening 84L and the lower source / drain contact 96L extend. The first upper source / drain contact opening 82UA includes a portion within the third ILD 106 and the fourth ILD 142 that is directly disposed above or on (e.g., and placed thereon) the upper surface of the lower source / drain contact 96L. Furthermore, there may be little to no upward and downward boundaries between the first upper source / drain contact 96UA and the corresponding lower source / drain contact 96L.

[0094] exist Figure 17A and Figure 17B In the middle, in the formation of the lower metal-semiconductor alloy 88L (see Figure 8A and Figure 8BPrior to this, a first epitaxial regeneration process can be performed to form a lower epitaxial regeneration layer 86L on the lower epitaxial source / drain region 62L. This process is particularly useful when the lower epitaxial source / drain region 62L is over-etched during the formation of the lower source / drain contact opening 82L. According to some embodiments, the first epitaxial regeneration process may include a low-temperature epitaxial growth process. In embodiments where the lower epitaxial source / drain region 62L corresponds to a p-type lower transistor, the lower epitaxial regeneration layer 86L may include SiB, SiGe, SiGeB, or combinations thereof, and is deposited at a temperature between 350°C and 400°C. In embodiments where the lower epitaxial source / drain region 62L corresponds to an n-type lower transistor, the lower epitaxial regeneration layer 86L may include SiP, SiAs, or combinations thereof, and is deposited at a temperature between 350°C and 400°C. Deposition temperatures below 400°C are used to reduce the thermal budget while protecting other parts of the stacked transistor structure.

[0095] As further shown, in the formation of the upper metal-semiconductor alloy region 88U (see...) Figure 12A and Figure 12B Prior to this, a second epitaxial regeneration process can be performed to form an upper epitaxial regeneration layer 86U on the upper epitaxial source / drain region 62U. This process is particularly useful when over-etching the upper epitaxial source / drain region 62U during the formation of the upper source / drain contact opening 82U. According to some embodiments, the second epitaxial regeneration process may include a low-temperature epitaxial growth process. In embodiments where the upper epitaxial source / drain region 62U corresponds to an n-type lower transistor, the upper epitaxial regeneration layer 86U may include SiP, SiAs, or combinations thereof, and is deposited at a temperature between 350°C and 400°C. In embodiments where the upper epitaxial source / drain region 62U corresponds to a p-type upper transistor, the upper epitaxial regeneration layer 86U may include SiB, SiGe, SiGeB, or combinations thereof, and is deposited at a temperature between 350°C and 400°C. Deposition temperatures below 400°C are used to reduce the thermal budget while protecting other parts of the stacked transistor structure.

[0096] In some embodiments (not specifically shown), a first epitaxial regeneration process is performed on the lower epitaxial source / drain region 62L, while the second epitaxial regeneration process may not be performed on the upper epitaxial source / drain region 62U. In other embodiments (not specifically shown), a second epitaxial regeneration process is performed on the upper epitaxial source / drain region 62U, while the first epitaxial regeneration process may not be performed on the lower epitaxial source / drain region 62L.

[0097] exist Figure 18In this embodiment, a metal nitride layer 92 (e.g., titanium nitride) can be formed and retained on the exposed sidewall surfaces of one or both of the lower source / drain contacts 96L and contact vias 74. In such an embodiment, the processes described above (e.g., implantation processes) affecting the metal nitride layer 92 can reduce the interfacial resistance with respect to the upper surface portion of the metal nitride layer 92, while the sidewall portions of the metal nitride layer 92 remain substantially intact. Therefore, the upper surface portion of the metal nitride layer 92 can have a lower interfacial resistance with adjacent conductive components, while the sidewall surface portions of the metal nitride layer 92 can have a higher interfacial resistance with adjacent conductive components.

[0098] In some embodiments (not specifically shown), a metal nitride layer 92 may be formed on the exposed surfaces (e.g., top and / or sidewall surfaces) of the lower source / drain contact 96L, while the contact via 74 remains substantially free of the metal nitride layer 92. This may occur depending on the difference between the metal used to form the upper metal-semiconductor alloy region 88U and the first conductive material of the lower source / drain contact 96L and the conductive material of the contact via 74.

[0099] Various advantages are achieved during the formation of the source / drain contacts 96 of the stacked transistor. Specifically, implantation and epitaxial regeneration processes can be selected with greater specificity based on different materials for the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L. Furthermore, the deposition of the first conductive material into the lower source / drain contact opening 82L can be performed more efficiently and with reduced voids, resulting in a substantially seamless lower source / drain contact 96L. Therefore, the epitaxial source / drain regions 62 and the source / drain contacts 96 are formed with greater flexibility and improved yield, resulting in higher performance and reliability of the stacked transistor.

[0100] In one embodiment, the method includes: patterning a first opening through a first dielectric layer, a first source / drain region, and a second dielectric layer to expose a second source / drain region; forming a first dielectric pad along a sidewall of the first opening, wherein the second source / drain region is exposed; forming a first metal-semiconductor alloy region in the first opening along the second source / drain region; depositing a first conductive material to fill the remaining portion of the first opening; patterning a second opening through the first dielectric layer to expose the first source / drain region; forming a second dielectric pad along a sidewall of the second opening, wherein the first source / drain region is exposed; forming a second metal-semiconductor alloy region in the second opening along the first source / drain region; and depositing a second conductive material to fill the remaining portion of the second opening. In another embodiment, patterning the second opening includes exposing a sidewall of the first conductive material. In another embodiment, the second dielectric pad is formed along a portion of the exposed sidewall of the first conductive material. In another embodiment, the method further includes forming a first semiconductor material to regenerate a second source / drain region before forming the first metal-semiconductor alloy region, wherein the first metal-semiconductor alloy region is formed along the first semiconductor material of the second source / drain region. In another embodiment, the method further includes forming a second semiconductor material to regenerate the first source / drain region before forming the second metal-semiconductor alloy region, wherein the second metal-semiconductor alloy region is formed along the second semiconductor material of the first source / drain region. In another embodiment, the first semiconductor material comprises a silicon-germanium epitaxial layer, and wherein the second semiconductor material comprises a silicon epitaxial layer. In another embodiment, forming the first metal-semiconductor alloy region includes forming a metal nitride layer over a first conductive material. In another embodiment, after depositing the second conductive material, the metal nitride layer is interposed between the first conductive material and the second conductive material.

[0101] In one embodiment, the method includes: etching a first opening through multiple layers to expose a first epitaxial region disposed over a semiconductor substrate, the first epitaxial region comprising a first semiconductor material; the multiple layers comprising: a first dielectric layer disposed over the first epitaxial region; a second epitaxial region disposed over the first dielectric layer, the second epitaxial region comprising a second semiconductor material; and a second dielectric layer disposed over the second epitaxial region; forming a first dielectric pad along a surface of the first opening; etching to remove a bottom segment of the first dielectric pad; depositing a silicon-germanium material over the first epitaxial region; filling the first opening disposed over the silicon-germanium material with a first conductive material; etching a second opening through a second dielectric layer to expose a second epitaxial region; forming a second dielectric pad along a surface of the second opening; etching to remove a bottom segment of the second dielectric pad; and filling the second opening disposed over the second epitaxial region with a second conductive material, the first conductive material being electrically connected to the second conductive material. In another embodiment, the method further includes, prior to filling the first opening: depositing one or more first metals over the first epitaxial region; and performing a first annealing to convert at least a portion of the one or more first metals into a first metal-semiconductor alloy. In another embodiment, the method further includes, before filling the second opening: depositing one or more second metals over the first epitaxial region; and performing a second annealing to convert at least a portion of the one or more second metals into a second metal-semiconductor alloy. In another embodiment, the one or more second metals include titanium, wherein, after performing the second annealing, a titanium-containing layer is formed along the surface of the first conductive material, and wherein the interface between the titanium-containing layer and the first conductive material has a first resistance under a set of standard conditions. In another embodiment, the method further includes, before filling the second opening, performing a dopant implantation process via the second metal-semiconductor alloy, wherein, after performing the implantation process, the interface between the titanium-containing layer and the first conductive material has a second resistance under a set of standard conditions, and wherein the second resistance is less than the first resistance. In another embodiment, the first semiconductor material includes silicon-germanium, wherein the second semiconductor material includes silicon, and wherein the titanium-containing layer includes titanium nitride.

[0102] In an embodiment, the semiconductor device includes: a first dielectric layer disposed above a substrate and below a second dielectric layer; a first source / drain region located within the first dielectric layer, the first source / drain region including a first semiconductor layer having a first element and a second semiconductor layer having a first element, wherein the concentration of the first element in the first semiconductor layer varies in the direction toward the substrate, and wherein the thickness of the first source / drain region in a cross-sectional view is different from the width of the first source / drain region; a second source / drain region located within the second dielectric layer; and a first source / drain contact electrically coupled to the first dielectric layer. A first upper surface of a source / drain region extends through a first dielectric layer and a second source / drain region; a first source / drain contact is separated from the second source / drain region by a first dielectric pad; a second source / drain contact is electrically coupled to a second upper surface of the second source / drain region and extends through the second dielectric layer; a first nanostructure is adjacent to the first source / drain region; a second nanostructure is adjacent to the second source / drain region; a first gate structure is located around the first nanostructure; and a second gate structure is located above the first gate structure and around the second nanostructure. In another embodiment, the first source / drain contact is electrically coupled to the second source / drain contact. In another embodiment, a third upper surface of the first source / drain contact is flush with the inner region of the second source / drain region. In another embodiment, the first source / drain contact extends through the entire thickness of the second dielectric layer. In another embodiment, the semiconductor device further includes: a contact via extending from the substrate through a first dielectric layer and a second dielectric layer; a third source / drain region located within the second dielectric layer; and a third source / drain contact electrically coupled to a fourth upper surface of the third source / drain region and extending through the second dielectric layer. In another embodiment, the third source / drain contact is electrically coupled to the contact via.

[0103] Some embodiments of this application provide a method for forming a semiconductor device, comprising: patterning a first opening through a first dielectric layer, a first source / drain region, and a second dielectric layer to expose a second source / drain region; forming a first dielectric pad along the sidewall of the first opening, wherein the second source / drain region is exposed; forming a first metal-semiconductor alloy region in the first opening along the second source / drain region; depositing a first conductive material to fill the remaining portion of the first opening; patterning a second opening through the first dielectric layer to expose the first source / drain region; forming a second dielectric pad along the sidewall of the second opening, wherein the first source / drain region is exposed; forming a second metal-semiconductor alloy region in the second opening along the first source / drain region; and depositing a second conductive material to fill the remaining portion of the second opening.

[0104] In some embodiments, patterning the second opening includes exposing the sidewalls of the first conductive material. In some embodiments, the second dielectric pad is formed along a portion of the exposed sidewalls of the first conductive material. In some embodiments, the method further includes forming a first semiconductor material to regrow the second source / drain region before forming the first metal-semiconductor alloy region, wherein the first metal-semiconductor alloy region is formed along the first semiconductor material of the second source / drain region. In some embodiments, the method further includes forming a second semiconductor material to regrow the first source / drain region before forming the second metal-semiconductor alloy region, wherein the second metal-semiconductor alloy region is formed along the second semiconductor material of the first source / drain region. In some embodiments, the first semiconductor material includes a silicon-germanium epitaxial layer, and wherein the second semiconductor material includes a silicon epitaxial layer. In some embodiments, forming the first metal-semiconductor alloy region includes forming a metal nitride layer over the first conductive material. In some embodiments, after depositing the second conductive material, the metal nitride layer is interposed between the first conductive material and the second conductive material.

[0105] Other embodiments of this application provide a method for forming a semiconductor device, comprising: etching a first opening through a plurality of layers to expose a first epitaxial region disposed over a semiconductor substrate, the first epitaxial region comprising a first semiconductor material, the plurality of layers comprising: a first dielectric layer disposed over the first epitaxial region; a second epitaxial region disposed over the first dielectric layer, the second epitaxial region comprising a second semiconductor material; and a second dielectric layer disposed over the second epitaxial region; forming a first dielectric pad along the surface of the first opening; etching to remove a bottom segment of the first dielectric pad; depositing a silicon-germanium material over the first epitaxial region; filling the first opening disposed over the silicon-germanium material with a first conductive material; etching a second opening through the second dielectric layer to expose the second epitaxial region; forming a second dielectric pad along the surface of the second opening; etching to remove a bottom segment of the second dielectric pad; and filling the second opening disposed over the second epitaxial region with a second conductive material, the first conductive material being electrically connected to the second conductive material.

[0106] In some embodiments, the method further includes, before filling the first opening: depositing one or more first metals over the first epitaxial region; and performing a first annealing to convert at least a portion of the one or more first metals into a first metal-semiconductor alloy. In some embodiments, the method further includes, before filling the second opening: depositing one or more second metals over the first epitaxial region; and performing a second annealing to convert at least a portion of the one or more second metals into a second metal-semiconductor alloy. In some embodiments, the one or more second metals include titanium, wherein, after performing the second annealing, a titanium-containing layer is formed along the surface of the first conductive material, and wherein the interface between the titanium-containing layer and the first conductive material has a first resistance under a set of standard conditions. In some embodiments, the method further includes, before filling the second opening, performing a dopant implantation process through the second metal-semiconductor alloy, wherein, after performing the implantation process, the interface between the titanium-containing layer and the first conductive material has a second resistance under the set of standard conditions, and wherein the second resistance is less than the first resistance. In some embodiments, the first semiconductor material includes silicon-germanium, wherein the second semiconductor material includes silicon, and wherein the titanium-containing layer includes titanium nitride.

[0107] Some embodiments of this application provide a semiconductor device, including: a first dielectric layer disposed above a substrate and below a second dielectric layer; a first source / drain region located within the first dielectric layer, the first source / drain region including a first semiconductor layer having a first element and a second semiconductor layer having the first element, wherein the concentration of the first element in the first semiconductor layer varies in the direction toward the substrate, and wherein, in a cross-sectional view, the thickness of the first source / drain region is different from the width of the first source / drain region; a second source / drain region located within the second dielectric layer; and a first source / drain contact electrically coupled to the first source / drain region. The first source / drain contact extends to the first upper surface of the first source / drain region and through the first dielectric layer and the second source / drain region, the first source / drain contact being separated from the second source / drain region by a first dielectric pad; a second source / drain contact electrically coupled to the second upper surface of the second source / drain region and extending through the second dielectric layer; a first nanostructure adjacent to the first source / drain region; a second nanostructure adjacent to the second source / drain region; a first gate structure located around the first nanostructure; and a second gate structure located above the first gate structure and around the second nanostructure.

[0108] In some embodiments, the first source / drain contact is electrically coupled to the second source / drain contact. In some embodiments, the third upper surface of the first source / drain contact is flush with the inner region of the second source / drain region. In some embodiments, the first source / drain contact extends through the entire thickness of the second dielectric layer. In some embodiments, the semiconductor device further includes: a contact via extending from the substrate through the first dielectric layer and the second dielectric layer; a third source / drain region located within the second dielectric layer; and a third source / drain contact electrically coupled to a fourth upper surface of the third source / drain region and extending through the second dielectric layer. In some embodiments, the third source / drain contact is electrically coupled to the contact via.

[0109] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: Patterning is performed through a first opening in the first dielectric layer, the first source / drain region, and the second dielectric layer to expose the second source / drain region; A first dielectric pad is formed along the sidewall of the first opening, wherein the second source / drain region is exposed; A first metal-semiconductor alloy region is formed in the first opening along the second source / drain region; Deposit a first conductive material to fill the remaining portion of the first opening; Pattern a second opening through the first dielectric layer to expose the first source / drain region; A second dielectric pad is formed along the sidewall of the second opening, wherein the first source / drain region is exposed; A second metal-semiconductor alloy region is formed in the second opening along the first source / drain region; and A second conductive material is deposited to fill the remaining portion of the second opening.

2. The method according to claim 1, wherein, Patterning the second opening includes exposing the sidewalls of the first conductive material.

3. The method according to claim 2, wherein, The second dielectric pad is formed along a portion of the exposed sidewall of the first conductive material.

4. The method of claim 1, further comprising, prior to forming the first metal-semiconductor alloy region, forming a first semiconductor material to regrow the second source / drain region, wherein, The first metal-semiconductor alloy region is formed along the first semiconductor material of the second source / drain region.

5. The method of claim 4, further comprising, prior to forming the second metal-semiconductor alloy region, forming a second semiconductor material to regenerate the first source / drain region, wherein, The second metal-semiconductor alloy region is formed along the second semiconductor material of the first source / drain region.

6. The method according to claim 5, wherein, The first semiconductor material includes a silicon-germanium epitaxial layer, and the second semiconductor material includes a silicon epitaxial layer.

7. The method according to claim 1, wherein, Forming the first metal-semiconductor alloy region includes forming a metal nitride layer over the first conductive material.

8. The method according to claim 7, wherein, After the second conductive material is deposited, the metal nitride layer is positioned between the first conductive material and the second conductive material.

9. A method for forming a semiconductor device, comprising: A first opening is etched through multiple layers to expose a first epitaxial region disposed above a semiconductor substrate, the first epitaxial region comprising a first semiconductor material, the multiple layers comprising: A first dielectric layer is disposed above the first epitaxial region; A second epitaxial region is disposed above the first dielectric layer, and the second epitaxial region includes a second semiconductor material; and A second dielectric layer is disposed above the second epitaxial region; A first dielectric pad is formed along the surface of the first opening; Etching to remove the bottom segment of the first dielectric pad; Silicon-germanium material is deposited above the first epitaxial region; The first opening disposed above the silicon-germanium material is filled with a first conductive material; A second opening is etched through the second dielectric layer to expose the second epitaxial region; A second dielectric pad is formed along the surface of the second opening; Etching to remove the bottom segment of the second dielectric pad; and The second opening disposed above the second epitaxial region is filled with a second conductive material, wherein the first conductive material is electrically connected to the second conductive material.

10. A semiconductor device, comprising: The first dielectric layer is disposed above the substrate and below the second dielectric layer; A first source / drain region is located within the first dielectric layer. The first source / drain region includes a first semiconductor layer having a first element and a second semiconductor layer having the first element, wherein the concentration of the first element in the first semiconductor layer varies in the direction toward the substrate, and wherein, in a cross-sectional view, the thickness of the first source / drain region is different from the width of the first source / drain region. The second source / drain region is located within the second dielectric layer; A first source / drain contact is electrically coupled to a first upper surface of the first source / drain region and extends through the first dielectric layer and the second source / drain region. The first source / drain contact is separated from the second source / drain region by a first dielectric pad. The second source / drain contact is electrically coupled to the second upper surface of the second source / drain region and extends through the second dielectric layer; The first nanostructure is adjacent to the first source / drain region; The second nanostructure is adjacent to the second source / drain region; A first gate structure is located around the first nanostructure; and The second gate structure is located above the first gate structure and around the second nanostructure.

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