Infrared focal plane chip and preparation method thereof

Abstract

This invention relates to the field of infrared focal plane array (FLAS) chip technology, specifically to an infrared FLAS chip and its fabrication method. The FLAS chip includes a readout circuit and a photosensitive substrate. A pixel array, comprising multiple pixels, is disposed on the photosensitive substrate. Each pixel is flip-chip connected to the readout circuit via interconnect units. At least some interconnect units include bumps and limiting connection components. The limiting connection components include a dielectric film and a slotted connector. A through-hole is formed in the dielectric film, and the slotted connector is disposed within the through-hole. The bumps are inserted into the slotted connector and soldered to it. One of the bumps and the limiting connection components is disposed on a corresponding pixel, and the other is disposed on the readout circuit. This invention effectively prevents the bumps from slipping or misaligning during flip-chip soldering. Furthermore, the limiting connection components do not encroach on the pixel area and are unaffected by pixel pitch, making it particularly suitable for infrared FLAS chips with ultra-small pixel pitches. The use of a dielectric film allows for precise fabrication of the through-hole, avoiding pattern distortion.

Description

Technical Field

[0001] This invention relates to the field of infrared focal plane array chip technology, and specifically to an infrared focal plane array chip and its fabrication method. Background Technology

[0002] Existing cooled infrared focal plane array devices typically consist of a photosensitive material chip array and a readout circuit interconnected via indium bumps. In traditional techniques, indium bumps are located at both ends of the photosensitive array and the readout circuit. During the flip-soldering interconnection, the bumps at both ends are soldered in a top-to-top contact manner. As pixel size decreases, the top size of the indium bumps also decreases, making it easy for the indium bumps at both ends to slip and misalign horizontally during flip-soldering, leading to interconnection failure. Currently, metal layers of specific shapes and heights are fabricated on the chip or circuit surface as limiting structures to suppress lateral displacement of the indium bumps. However, due to the low precision of metal forming, these limiting structures require a certain amount of space. Furthermore, with the trend towards ultra-high resolution and ultra-small pixel pitch in focal plane infrared detectors, the chip pattern linewidth is decreasing, significantly increasing the difficulty of photolithography. Fabricating flip-soldering metal limiting structures on existing ultra-small pixel pitch (<10μm) chips often results in pattern distortion, and the fabricated limiting structures also affect subsequent indium bump photolithography processing and cause difficulties in peeling off. Summary of the Invention

[0003] The purpose of this invention is to provide an infrared focal plane array chip and its fabrication method, which can at least solve some of the defects in the prior art.

[0004] To achieve the above objectives, the technical solution of the present invention is an infrared focal plane array chip, comprising a readout circuit and a photosensitive substrate. A pixel array is disposed on the photosensitive substrate, the pixel array comprising multiple pixels, each pixel being flip-chip connected to the readout circuit via interconnect units. At least a portion of the interconnect units include bumps and limiting connection components. The limiting connection component includes a dielectric film and a grooved connector. A through-hole is disposed on the dielectric film, the grooved connector is disposed in and abuts the through-hole, and the bump is inserted into and soldered to the grooved connector. One of the bump and the limiting connection component is disposed on the corresponding pixel, and the other is disposed on the readout circuit.

[0005] As one implementation method, the planar dimension of the pixel is a, the design line width of the groove connector is b, the opening line width of the through-limiting hole is c, and a / 3 < c < b < a.

[0006] As one implementation method, the depth of the through-hole is h, the height of the groove connector is h1, the height of the protrusion is h2, the solder joint spacing between the pixel and the readout circuit is K, and h1 < 1 / 2h, 2h < h2 < K*(a / b).2 .

[0007] As one implementation method, h is in the range of 1~3μm and K is in the range of 3~15μm.

[0008] As one implementation, the pixel or the readout circuit is provided with an electrode, and the slotted connector is disposed on the electrode.

[0009] As one embodiment, the thickness of the dielectric film is 1-3 μm.

[0010] As one embodiment, the through-hole is an inverted trapezoidal structure, and the inclination angle of the sidewall of the through-hole is 60-85°.

[0011] The present invention also provides a method for fabricating an infrared focal plane array chip according to any one of the above claims, comprising the following steps:

[0012] S1. A pixel array is fabricated on a photosensitive substrate to form multiple pixels. A limiting connection component is fabricated on one of the pixels and the readout circuit, and a bump is fabricated on the other.

[0013] S2. Extend the protrusion into the groove of the corresponding limiting connection component and weld the protrusion to the groove.

[0014] As one implementation method, the method for fabricating a pixel array on a photosensitive substrate to form multiple pixels, and fabricating limiting connection components on the pixels is as follows:

[0015] 1) A dielectric film is grown and patterned on the surface of a photosensitive substrate; the patterned dielectric film is used as a mask to etch the substrate to complete the fabrication of the pixel array, forming multiple mesa-shaped pixels with dielectric films on their surfaces;

[0016] Alternatively, a dielectric film can be grown on the surface of a photosensitive substrate, and the pixel array can be fabricated by ion implantation to form multiple planar pixels with a dielectric film on the surface.

[0017] 2) Etch the dielectric film on the surface of each pixel to create through-hole limiting holes, and prepare groove-shaped connectors on the surface of the through-hole limiting holes to form limiting connection components.

[0018] As one implementation method, the method of fabricating a pixel array on a photosensitive substrate to form multiple pixels and fabricating a limiting connection component on a readout circuit is as follows:

[0019] A pixel array is fabricated on a photosensitive substrate to form multiple pixels;

[0020] A dielectric film is grown on the surface of the readout circuit, and then the dielectric film is etched to form multiple through-holes corresponding to multiple pixels. A groove-shaped connector is then prepared on the surface of each through-hole to form a limiting connection assembly.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] (1) The present invention sets a limiting connection component on one of the pixel and the readout circuit to limit and connect the protrusion set on the other of the pixel and the readout circuit. This not only effectively prevents the protrusion from slipping and misaligning during flip soldering, but also the through limiting hole structure does not occupy the pixel area and is not affected by the pixel pitch. It is especially suitable for infrared focal plane chips with ultra-small pixel pitch.

[0023] (2) The limiting connection component of the present invention uses a dielectric film to prepare a through limiting hole, which can be precisely controlled in size and position by photolithography and etching processes to avoid pattern distortion. Moreover, this structure will not affect the subsequent photolithography processing and stripping of the bumps, thereby significantly improving the consistency and reliability of flip interconnect.

[0024] (3) The present invention can prepare through-holes at the chip end, using the hard mask during the fabrication of mesa-type pixels or the protective layer during the fabrication of planar pixels as the dielectric film to prepare through-holes and grow groove-type connectors, which can eliminate the step of removing the hard mask or protective layer and grow bumps at the circuit end. Alternatively, through-holes can be prepared at the circuit end, using the insulating layer on the surface of the readout circuit as the dielectric film to prepare through-holes and grow groove-type connectors, and grow bumps at the chip end. Then, the two ends are interconnected by reverse soldering in a concave-convex structure. This not only effectively solves the bottleneck in the preparation of reverse soldering limiting structures for ultra-small pixel pitch cooled infrared focal plane chips, but also provides a flexible process. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A flowchart illustrating the fabrication process of an infrared focal plane array chip according to one embodiment of the present invention;

[0027] Figure 2 A structural diagram of another embodiment of the infrared focal plane chip provided in this invention;

[0028] In the figure: 1. Photosensitive substrate; 2. Dielectric film; 3. Passivation layer; 4. Through-hole limiting hole; 5. Groove connector; 6. Bump; 7. Readout circuit. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0031] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0032] like Figures 1-2 As shown, this embodiment provides an infrared focal plane array chip, including a readout circuit 7 and a photosensitive substrate 1. A pixel array is disposed on the photosensitive substrate 1, comprising multiple pixels. Each pixel is flip-chip connected to the readout circuit 7 via an interconnect unit. At least a portion of the interconnect units include bumps 6 and limiting connection components. The limiting connection components include a dielectric film 2 and a grooved connector 5. A through-hole 4 is disposed on the dielectric film 2, and the grooved connector 5 is disposed in and abuts the through-hole 4. The bumps 6 are inserted into the grooved connector 5 and soldered to it. One of the bumps 6 and the limiting connection component is disposed on the corresponding pixel, and the other is disposed on the readout circuit 7.

[0033] This embodiment uses a limiting connection component on one of the pixels and the readout circuit 7 to limit and connect the bump 6 on the other. This effectively prevents the bump from slipping or misaligning during flip-chip bonding. Furthermore, the limiting connection component does not encroach on the pixel area and is unaffected by the pixel pitch, making it particularly suitable for infrared focal plane array chips with ultra-small pixel pitches. In addition, the limiting connection component in this embodiment uses a dielectric film 2 to fabricate a through-hole 4, allowing for precise control of its size and position height through photolithography and etching processes, avoiding pattern distortion. This structure does not affect subsequent photolithography processing and stripping of the bump, thus significantly improving the consistency and reliability of flip-chip interconnects.

[0034] In some embodiments, the protrusion 6 is disposed on the readout circuit 7, and the limiting connection component is disposed on the corresponding pixel. Specifically, a dielectric film 2 is disposed on the surface of each pixel, a through-hole 4 is disposed on the dielectric film 2, the groove-shaped connector 5 is disposed in the through-hole 4, and the readout circuit 7 is provided with protrusions 6 corresponding one-to-one with each pixel. Figure 1 As shown, the through-hole 4 penetrates the dielectric film 2 on the pixel surface along the thickness direction and exposes the pixel. The groove-shaped connector 5 covers the pixel surface inside the through-hole 4, the inner wall of the through-hole 4, and extends to the surrounding surface of the dielectric film 2. Furthermore, a passivation layer 3 is provided on the surface of the dielectric film 2 and the side of the pixel.

[0035] In other embodiments, the protrusion 6 is disposed on the corresponding pixel, and the limiting connection component is disposed on the readout circuit 7. Specifically, a dielectric film 2 is disposed on the surface of the readout circuit 7, and a plurality of through-limiting holes 4 corresponding one-to-one with the pixels are disposed on the dielectric film 2. Each through-limiting hole 4 is provided with the groove-shaped connector 5, and each pixel is provided with the protrusion 6. Figure 2 As shown, the through-hole 4 penetrates the dielectric film 2 on the surface of the readout circuit 7 along the thickness direction, exposing the readout circuit 7. The slot-shaped connector 5 covers the surface of the readout circuit 7 within the through-hole 4, the inner wall of the through-hole 4, and extends to the surrounding surface of the dielectric film 2. Furthermore, a passivation layer 3 is provided on the surface of the pixel.

[0036] In some embodiments, the planar dimension of the pixel is 'a', the design linewidth of the slotted connector 5 is 'b', and the opening linewidth of the through-hole limiting hole 4 is 'c', where a / 3 < c < b < a. The planar dimension of the pixel is the two-dimensional planar dimension of the side of the pixel facing the readout circuit 7; the design linewidth 'b' of the slotted connector 5 is the maximum peripheral dimension of the slotted connector 5 in the direction parallel to the plane of the photosensitive substrate 1; the opening linewidth 'c' of the through-hole limiting hole 4 is the dimension of the through-hole limiting hole 4 at the opening plane on the surface of the dielectric film 2, and a, b, and c are dimensions in the same direction. By designing a / 3 < c < b < a, it is ensured that the top dimension of the slotted connector 5 is larger than the opening dimension of the through-hole limiting hole 4, so that the limiting groove and the slotted connector 5 achieve optimal dimensional matching, thereby ensuring a reliable connection between the slotted connector 5 and the protrusion 6.

[0037] Furthermore, the depth of the through-hole 4 is h, the height of the groove connector 5 is h1, the height of the protrusion 6 is h2, the solder joint spacing between the pixel and the readout circuit 7 is K, and h1 < 1 / 2h, 2h < h2 < K*(a / b). 2 The depth h of the through-hole 4 is consistent with the thickness of the dielectric film 2. By designing the height h1 of the groove-shaped connector 5 to be less than half the depth h of the through-hole 4, space is reserved for the insertion of the protrusion 6, thereby ensuring a reliable connection between the groove-shaped connector 5 and the protrusion 6; by designing 2h < h2 < K*(a / b) 2 This ensures that the bump 6 has sufficient height after insertion into the through-hole 4, guaranteeing optimal solder joint positioning and interconnection. Preferably, h is in the range of 1~3μm, and K is in the range of 3~15μm.

[0038] In some embodiments, electrodes are provided on the pixel or the readout circuit 7, and the slotted connector 5 is disposed on the electrodes. Specifically, the electrodes cover the surface of the pixel or readout circuit 7 within the through-hole 4, the inner wall of the through-hole 4, and extend to the surface of the surrounding dielectric film 2. They can be made of materials such as aluminum, gold, or platinum, and fabricated using processes such as photolithography, vapor deposition, and etching to form ohmic contacts; the slotted connector 5 covers the electrodes.

[0039] In some embodiments, the thickness of the dielectric film 2 is 1-3 μm. Specifically, when the pixel is a mesa-type pixel, the photosensitive substrate can be a superlattice, and the dielectric film 2 can be made of materials such as SiO2, Al2O3, or Si3N4, with a thickness of 1-3 μm to meet the depth requirements of the through-hole 4; when the pixel is a planar pixel, the photosensitive substrate is generally mercury cadmium telluride, and the dielectric film can be made of materials such as ZnS; when the dielectric film 2 is disposed on the readout circuit, the dielectric film 2 can be made of materials such as SiO2, Al2O3, or Si3N4.

[0040] In some embodiments, the through-hole 4 is an inverted trapezoidal structure, and the inclination angle of the sidewall of the through-hole 4 is 60-85°. In this embodiment, the groove-shaped connector 5 matches the shape of the through-hole 4, and the protrusion 6 is a frustum. By designing the through-hole 4 as an inverted trapezoidal structure and limiting the inclination angle of the sidewall of the through-hole 4, it is beneficial to guide the protrusion 6 into the through-hole 4 during the reverse welding process and to increase the contact area between the protrusion 6 and the groove-shaped connector 5, thereby ensuring the best reverse welding limiting and interconnection effect. The opening size of the through-hole 4 is specifically determined according to the pixel plane size and the size of the protrusion 6, which can satisfy the insertion of the protrusion 6 or at least the top part can be inserted into the through-hole 4 to ensure the reliable connection between the protrusion 6 and the concave-convex point.

[0041] This embodiment also provides a method for fabricating an infrared focal plane array chip, comprising the following steps:

[0042] S1. A pixel array is fabricated on a photosensitive substrate 1 to form multiple pixels. A limiting connection component is fabricated on one of the pixels and the readout circuit, and a bump 6 is fabricated on the other.

[0043] S2. Extend the protrusion 6 into the grooved connector 5 of the corresponding limiting connection component, and weld the protrusion 6 to the grooved connector 5.

[0044] In some embodiments, the method for fabricating a pixel array on a photosensitive substrate 1 to form multiple pixels, and fabricating limiting connection components on the pixels is as follows:

[0045] 1) A dielectric film 2 is grown and patterned on the surface of a photosensitive substrate 1; the patterned dielectric film 2 is used as a mask to etch the substrate 1 to complete the fabrication of the pixel array, forming multiple mesa-shaped pixels with dielectric film 2 on the surface;

[0046] Alternatively, a dielectric film 2 can be grown on the surface of the photosensitive substrate 1, and the pixel array can be fabricated by ion implantation to form multiple planar pixels with the dielectric film 2 on the surface.

[0047] 2) The dielectric film 2 is etched to create a through-hole 4, and a groove-shaped connector 5 is prepared on the surface of the through-hole 4 to form a limiting connection assembly.

[0048] Existing infrared focal plane array chip fabrication processes include hard mask or protective layer, pixel array fabrication, passivation, electrode fabrication, and indium bump fabrication. The hard mask or protective layer is usually removed after the pixel array is fabricated. In this embodiment, after the pixel array is fabricated, the hard mask used in the fabrication of mesa-type pixels or the protective layer used in the fabrication of planar-type pixels in the existing process is retained as dielectric film 2. Through-holes 4 are fabricated on dielectric film 2 by selective etching. This not only eliminates the step of removing the hard mask or protective layer and simplifies the overall process flow, but also allows for the fabrication of through-holes 4 on dielectric film 2 through photolithography and etching processes. The size and position of through-holes 4 can be precisely controlled, improving consistency and ensuring the reliability of interconnection.

[0049] In other embodiments, the method for fabricating a pixel array on the photosensitive substrate 1 to form multiple pixels and fabricating a limiting connection component on the readout circuit 7 is as follows:

[0050] A pixel array is fabricated on a photosensitive substrate 1 to form multiple pixels;

[0051] A dielectric film 2 is grown on the surface of the readout circuit 7, and then the dielectric film 2 is etched to form multiple through-limiting holes 4 corresponding to multiple pixels. A groove-shaped connector 5 is then prepared on the surface of each through-limiting hole 4 to form a limiting connection assembly.

[0052] Specifically, the through-hole 4 is fabricated by etching the dielectric film 2 as a flip-soldering limiting structure. The method is as follows: first, photoresist is coated and patterned on the dielectric film 2. Then, using the patterned photoresist as a mask, the dielectric film 2 is etched using a dry or wet etching process. The etching of the dielectric film 2 is stopped when the pixel or readout circuit 7 is exposed. After that, the photoresist is removed, and the through-hole 4 is formed on the dielectric film 2.

[0053] This embodiment can use the hard mask from the fabrication of mesa-type pixels or the protective layer from the fabrication of planar pixels as dielectric film 2 to prepare through-hole 4 at the chip end, or deposit an insulating layer as dielectric film 2 at the circuit end to prepare through-hole 4. This not only provides a flexible process, but also effectively solves the bottleneck in the fabrication of flip-soldering limiting structures for ultra-small pixel pitch cooled infrared focal plane chips. Furthermore, the dielectric film 2 at the chip end is the hard mask or protective layer retained during pixel fabrication, eliminating the step of removing the hard mask or protective layer and simplifying the process flow.

[0054] Furthermore, in step S1, after the pixel array fabrication is completed, a passivation layer 3 is grown on the pixel surface with the dielectric film 2, such as... Figure 1 As shown, or a passivation layer 3 can be grown on the surface of the pixel, such as Figure 2 As shown.

[0055] In some embodiments, after the through-hole 4 is prepared, an electrode is first prepared on the surface of the through-hole 4, and then a groove-shaped connector 5 is prepared on the surface of the electrode. For example... Figure 1 As shown, after the through-hole 4 is fabricated, a metal layer is first deposited on the surface of the pixel or readout circuit 7 inside the through-hole 4, the inner wall of the through-hole 4, and the surface of the dielectric film 2 around the through-hole 4. An electrode is then formed by etching. A groove-shaped connector 5 is then deposited on the electrode surface. The remaining hole depth after fabricating the electrode and groove-shaped connector 5 inside the through-hole 4 is not less than 0.5 μm to ensure the limiting effect of the through-hole 4.

[0056] In this embodiment, both the groove connector 5 and the protrusion 6 can be made of indium. The protrusion 6, the groove connector 5, and the pixel height are determined based on the pixel pitch and the depth of the through-hole 4.

[0057] The preparation method of the present invention will be described in detail below through a specific embodiment.

[0058] like Figure 1 As shown, this embodiment also provides a method for fabricating an infrared focal plane array chip, including the following steps:

[0059] 1) A SiO2 layer is grown on the surface of the photosensitive substrate 1 as a dielectric film 2, and it is patterned by photolithography and etching processes;

[0060] 2) Using the patterned dielectric film 2 as a mask, the photosensitive substrate 1 is etched by dry or wet etching process to form multiple pixels with dielectric film 2 on their surfaces that are isolated from each other. Then, ZnS is grown on the surface of the pixels with dielectric film 2 as a passivation layer 3.

[0061] 3) Coat the dielectric film 2 with photoresist and pattern it. Then, using the patterned photoresist as a mask, use dry or wet etching process to etch the dielectric film 2 on the pixel surface. Stop etching when the pixel is reached, remove the photoresist, and form a through-hole 4 with an inverted trapezoidal structure on the pixel.

[0062] 4) A metal layer is deposited on the surface of the through-hole 4 and the surface of the dielectric film 2 by vapor deposition, and patterned by stripping or etching process, thereby forming an electrode covering the pixel in the through-hole 4, the inner wall of the through-hole 4, and the surface of the dielectric film 2 around the through-hole 4.

[0063] 5) Indium is electroplated on the electrode surface to prepare a groove-shaped connector 5, and indium is electroplated on the surface of the readout circuit 7 to make multiple bumps 6 corresponding to the pixels one by one;

[0064] 6) Invert the readout circuit 7 so that the protrusion 6 of the readout circuit 7 is inserted into the through-limiting hole 4 on the pixel, and perform reverse soldering interconnection by hot-press bonding or reflow soldering process.

[0065] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An infrared focal plane array chip, comprising a readout circuit and a photosensitive substrate, wherein a pixel array is disposed on the photosensitive substrate, the pixel array comprising a plurality of pixels, and each pixel is flip-chip connected to the readout circuit via an interconnect unit; characterized in that: At least a portion of the interconnecting units include a bump and a limiting connection assembly. The limiting connection assembly includes a dielectric film and a grooved connector. The dielectric film has a through-hole, and the grooved connector is disposed in and fits into the through-hole. The bump is inserted into the grooved connector and welded to it. One of the bump and the limiting connection assembly is disposed on the corresponding pixel, and the other is disposed on the readout circuit.

2. The infrared focal plane array chip as described in claim 1, characterized in that: The planar dimension of the pixel is a, the design line width of the groove connector is b, and the opening line width of the through-hole is c, and a / 3 < c < b < a.

3. The infrared focal plane array chip as described in claim 2, characterized in that: The depth of the through-hole is h, the height of the groove connector is h1, the height of the protrusion is h2, the solder joint spacing between the pixel and the readout circuit is K, and h1 < 1 / 2h, 2h < h2 < K*(a / b). 2 .

4. The infrared focal plane array chip as described in claim 3, characterized in that: h is in the range of 1~3μm, and K is in the range of 3~15μm.

5. The infrared focal plane array chip as described in claim 1, characterized in that: The pixel or the readout circuit is provided with an electrode, and the slotted connector is disposed on the electrode.

6. The infrared focal plane array chip as described in claim 1, characterized in that: The thickness of the dielectric film is 1-3 μm.

7. The infrared focal plane array chip as described in claim 1, characterized in that: The through-hole is an inverted trapezoidal structure, and the inclination angle of the sidewall of the through-hole is 60-85°.

8. A method for fabricating an infrared focal plane array chip according to any one of claims 1-7, characterized in that, Includes the following steps: S1. A pixel array is fabricated on a photosensitive substrate to form multiple pixels. A limiting connection component is fabricated on one of the pixels and the readout circuit, and a bump is fabricated on the other. S2. Extend the protrusion into the groove of the corresponding limiting connection component and weld the protrusion to the groove.

9. The method for fabricating an infrared focal plane array chip as described in claim 8, characterized in that, The method for fabricating a pixel array on a photosensitive substrate to form multiple pixels, and then fabricating limiting connection components on the pixels is as follows: 1) A dielectric film is grown and patterned on the surface of a photosensitive substrate; the patterned dielectric film is used as a mask to etch the substrate to complete the fabrication of the pixel array, forming multiple mesa-shaped pixels with dielectric films on their surfaces; Alternatively, a dielectric film can be grown on the surface of a photosensitive substrate, and the pixel array can be fabricated by ion implantation to form multiple planar pixels with a dielectric film on the surface. 2) Etch the dielectric film on the surface of each pixel to create through-hole limiting holes, and prepare groove-shaped connectors on the surface of the through-hole limiting holes to form limiting connection components.

10. The method for fabricating an infrared focal plane array chip as described in claim 8, characterized in that, The method for fabricating a pixel array on a photosensitive substrate to form multiple pixels and fabricating a limiting connection component on the readout circuit is as follows: A pixel array is fabricated on a photosensitive substrate to form multiple pixels; A dielectric film is grown on the surface of the readout circuit, and then the dielectric film is etched to form multiple through-holes corresponding to multiple pixels. A groove-shaped connector is then prepared on the surface of each through-hole to form a limiting connection assembly.

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