Flip chip silver mirror light emitting diode chip and method of manufacturing the same

Abstract

The application provides a flip silver mirror light emitting diode chip and a preparation method thereof. The flip silver mirror light emitting diode chip comprises, from bottom to top, a substrate, an epitaxial layer, a current spreading layer, a first SiO2 film layer and a first semiconductor layer; the epitaxial layer comprises, from bottom to top, an N-type semiconductor layer, an active light emitting layer and a P-type semiconductor layer, and an N-type semiconductor layer conductive step is further arranged on the top of the N-type semiconductor layer; and an isolation groove is arranged outside the epitaxial layer; wherein the included angle between the sidewall of the first SiO2 film layer and the top of the N-type semiconductor layer is an acute angle, the angle β of the isolation groove is between 88° and 90°, the bottom width L of the isolation groove is between 2 um and 4 um, and the distance L1 between the projection of the sidewall of the isolation groove in the horizontal plane and the projection of the sidewall of the active light emitting layer in the horizontal plane is between 2 um and 5 um.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a flip-chip silver mirror light-emitting diode chip and its fabrication method. Background Technology

[0002] Light-emitting diode (LED) chips are widely used in both lighting and display fields due to their energy efficiency and high performance.

[0003] In recent years, improving the brightness of light-emitting diode (LED) chips has been a continuous goal for every industry professional.

[0004] In existing technologies, most flip-chip LEDs use inorganic Bragg mirrors as the reflective layer. Inorganic Bragg mirrors are brittle and easily break. Therefore, the isolation groove angle of existing flip-chip LEDs is generally between 45° and 55°. Later, people proposed using Ag metal as the reflective layer, but the isolation groove still followed the previous preparation method, and the angle remained at 45°-55°. Because Ag metal is used as the reflective layer, there is no problem of the Bragg reflective layer breaking at the isolation groove. Therefore, this invention proposes a preparation method that makes the isolation groove angle vertical, thereby effectively increasing the light-emitting area of ​​the silver mirror flip-chip LED, thereby increasing the luminous brightness. Summary of the Invention

[0005] Based on this, the purpose of the present invention is to provide a flip-chip silver mirror light-emitting diode chip and its preparation method, which can effectively solve the shortcomings of the prior art.

[0006] A flip-chip silver mirror light-emitting diode chip, comprising: The substrate, epitaxial layer, current spreading layer, first SiO2 thin film layer and first semiconductor layer are arranged sequentially from bottom to top; The epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer arranged sequentially from bottom to top. An N-type semiconductor layer conductive step is also provided on the top of the N-type semiconductor layer, and an isolation trench is provided on the outside of the epitaxial layer. The angle between the sidewall of the first SiO2 thin film layer and the top of the N-type semiconductor layer is an acute angle. The angle β of the isolation trench is between 88° and 90°. The bottom width L of the isolation trench is between 2um and 4um. The distance L1 between the projection of the sidewall of the isolation trench onto the horizontal plane and the projection of the sidewall of the active light-emitting layer onto the horizontal plane is between 2um and 5um.

[0007] Furthermore, an Al2O3 protective layer is provided on the isolation groove.

[0008] Furthermore, the first semiconductor layer includes a reflective metal layer, a second insulating layer, a conductive metal layer, a third insulating layer, and a pad layer sequentially disposed on the first SiO2 thin film layer.

[0009] Furthermore, P-type and N-type second insulating layer vias are provided on the second insulating layer, the conductive metal layer includes a P-type conductive metal layer and an N-type conductive metal layer, and the pad layer includes a P-type pad and an N-type pad.

[0010] Furthermore, a first SiO2 thin film layer through-hole and a first insulating protective layer are also provided on the first SiO2 thin film layer.

[0011] On the other hand, the present invention also provides a method for fabricating a flip-chip silver mirror light-emitting diode, comprising: S1. A substrate is provided, and an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer are sequentially prepared on the substrate as epitaxial layers. A current spreading layer is prepared on the epitaxial layers, and conductive steps of the N-type semiconductor layer are prepared on the current spreading layer and the epitaxial layers. S2. A first SiO2 thin film layer is deposited on the conductive steps of the current spreading layer and the N-type semiconductor layer using a first PECVD process. In the first PECVD process, the temperature of the reaction chamber decreases linearly, with the temperature ranging from 200℃ to 300℃ and the rate of linear decrease ranging from 0.5℃ / min to 1℃ / min. The angle between the sidewall of the first SiO2 thin film layer and the top of the N-type semiconductor layer is an acute angle. S3. Coat photoresist on the first SiO2 thin film layer, expose and develop it to remove part of the photoresist and expose the first SiO2 thin film layer under the photoresist. Then use BOE etching solution to remove the exposed first SiO2 thin film layer down to the N-type semiconductor layer conductive step at the bottom of the first SiO2 thin film layer. Then use ICP process to etch away the exposed N-type semiconductor layer conductive step to form an isolation trench. The ICP process specifically includes a first etching cycle step repeated several times, a second etching cycle step repeated several times, and a third etching cycle step repeated several times. The etching depth of the first etching cycle step is 1 / 2 of the depth of the isolation trench, the etching depth of the second etching cycle step is 1 / 4 of the depth of the isolation trench, and the etching depth of the third etching cycle step is 1 / 4 of the depth of the isolation trench. The first etching cycle step includes a first sub-step, a second sub-step, and a third sub-step. The second etching cycle step includes a fourth sub-step, a fifth sub-step, and a sixth sub-step. The third etching cycle step includes a seventh sub-step, an eighth sub-step, and a ninth sub-step. The angle β of the isolation trench is between 88° and 90°, the bottom width L of the isolation trench is between 2µm and 4µm, and the distance L1 between the projection of the sidewall of the isolation trench on the horizontal plane and the projection of the sidewall of the active light-emitting layer on the horizontal plane is 2µm to 5µm. In the first sub-step, the etching power is between 800W and 1200W, the etching power is between 400W and 600W, the etching time t1 is between 80s and 100s, the reaction gases are Cl2 and BCl3, the flow rate of Cl2 is between 20Scc / min and 40Scc / min, and the flow rate of BCl3 is between 10Scc / min and 15Scc / min. In the second sub-step, the etching power is between 200W and 300W, the etching power is off, the passivation time t2 is between 5s and 10s, the ratio of passivation time t2 to etching time t1 is between 1:20 and 1:10, the reaction gases are N2O and N2, the flow rate of N2O is between 30Scc / min and 50Scc / min, and the flow rate of N2 is between 80Scc / min and 100Scc / min; In the third sub-step, the etching power is between 200W and 300W, the etching power is turned off, the passivation time t3 is consistent with the passivation time t2, the passivation time t3 is between 5s and 10s, the reaction gas is CHF3, and the flow rate is between 20Scc / min and 30Scc / min. The fourth sub-step is completely identical to the first sub-step; In the fifth sub-step, the etching power is between 300W and 400W, the etching power is off, the passivation time t5 is greater than the passivation time t2, the passivation time t5 is between 8s and 20s, the ratio of passivation time t5 to etching time t1 is greater than the ratio of passivation time t2 to etching time t1, the ratio of passivation time t5 to etching time t1 is between 1:10 and 1:5, the reaction gases are N2O and N2, the flow rate of N2O is between 30Scc / min and 50Scc / min, the flow rate of N2 is between 80Scc / min and 100Scc / min, and the etching power in the fifth sub-step is greater than the etching power in the second sub-step. In the sixth sub-step, the etching power is between 300W and 400W, the etching power is off, the passivation time t6 is consistent with the passivation time t5, the passivation time t6 is between 8s and 20s, the reaction gas is CHF3, and the flow rate is between 20Scc / min and 30Scc / min. The seventh sub-step is completely identical to the first sub-step; In the eighth sub-step, the etching power is between 400W and 500W, the etching power is off, the passivation time t8 is greater than the passivation time t5, the passivation time t8 is between 20s and 50s, the ratio of the passivation time t8 to the etching time t1 is greater than the ratio of the passivation time t5 to the etching time t1, the ratio of the passivation time t8 to the etching time t1 is between 1:4 and 1:2, the reaction gases are N2O and N2, the flow rate of N2O is between 30Scc / min and 50Scc / min, the flow rate of N2 is between 80Scc / min and 100Scc / min, and the etching power in the eighth sub-step is greater than the etching power in the fifth sub-step. In the ninth sub-step, the etching power is between 400W and 500W, the etching power is off, the passivation time t9 is consistent with the passivation time t8, the passivation time t9 is between 20s and 50s, the reaction gas is CHF3, and the flow rate is between 20Scc / min and 30Scc / min. S4. Prepare an isolation trench protective layer on the remaining photoresist and the isolation trench; S5. Prepare a first SiO2 thin film layer through hole and a first insulating protective layer on the first SiO2 thin film layer; S6. Prepare a first semiconductor layer on the first SiO2 thin film layer.

[0012] Furthermore, step S4 specifically includes: An Al2O3 film is prepared on the surface of the remaining photoresist and the isolation trench using the ALD process as a protective layer for the isolation trench. Then, the Al2O3 film and photoresist on the photoresist are removed using the lift-off process.

[0013] Furthermore, step S5 specifically includes: Photoresist is then applied onto the first SiO2 thin film layer. After exposure and development, a portion of the photoresist is removed, exposing the first SiO2 thin film layer beneath it. The exposed portion of the first SiO2 thin film layer is then removed using BOE etching solution to form a via in the first SiO2 thin film layer. The photoresist is then removed, and the remaining first SiO2 thin film layer serves as a first insulating protective layer to protect the conductive steps of the N-type semiconductor layer.

[0014] Furthermore, the first semiconductor layer includes a reflective metal layer, a second insulating layer, a conductive metal layer, a third insulating layer, and a pad layer sequentially disposed on the first SiO2 thin film layer.

[0015] Furthermore, P-type and N-type second insulating layer vias are provided on the second insulating layer, the conductive metal layer includes a P-type conductive metal layer and an N-type conductive metal layer, and the pad layer includes a P-type pad and an N-type pad.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: By setting the isolation trench angle β between 88° and 90°, which is close to vertical, compared with the traditional 45°-55° inclined isolation trench, the vertical sidewall significantly increases the effective area available for light emission within the unit projected area of ​​the chip, thereby improving the overall light emission area. The increase in light emission area directly leads to an increase in light output power, and the chip brightness is significantly improved under the same injection current conditions. At the same time, by setting the bottom width L of the isolation trench between 2um and 4um, and setting the distance L1 between the projection of the isolation trench sidewall on the horizontal plane and the projection of the active light-emitting layer sidewall on the horizontal plane between 2um and 5um, it is ensured that the isolation trench does not damage the active light-emitting layer, thus ensuring the reliability and yield of the device. Attached Figure Description

[0017] Figure 1 This is a cross-sectional schematic diagram of the flip-chip silver mirror light-emitting diode chip in Embodiment 1 of the present invention; Figure 2 This is a flowchart illustrating the fabrication method of the flip-chip silver mirror light-emitting diode chip in Embodiment 2 of the present invention; Explanation of key component symbols:

[0018] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0019] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0020] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0022] Example 1 Please see Figure 1 Embodiment 1 of the present invention provides a flip-chip silver mirror light-emitting diode chip, comprising: The substrate 10, epitaxial layer, current spreading layer 12, first SiO2 thin film layer 13 and first semiconductor layer are arranged sequentially from bottom to top; The epitaxial layer includes an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 arranged sequentially from bottom to top. An N-type semiconductor layer conductive step 114 is also provided on the top of the N-type semiconductor layer 111, and an isolation trench 115 is provided on the outside of the epitaxial layer. The angle between the sidewall of the first SiO2 thin film layer 13 and the top of the N-type semiconductor layer 111 is an acute angle. The angle β of the isolation trench 115 is between 88° and 90°. The bottom width L of the isolation trench 115 is between 2 μm and 4 μm. The distance L1 between the projection of the sidewall of the isolation trench 115 onto the horizontal plane and the projection of the sidewall of the active light-emitting layer 112 onto the horizontal plane is between 2 μm and 5 μm.

[0023] Furthermore, the first semiconductor layer includes a reflective metal layer 15, a second insulating layer, a conductive metal layer, a third insulating layer 18, and a pad layer sequentially disposed on the first SiO2 thin film layer 13.

[0024] Furthermore, a P-type second insulating layer through-hole 161 and an N-type second insulating layer through-hole 162 are provided on the second insulating layer, the conductive metal layer includes a P-type conductive metal layer 171 and an N-type conductive metal layer 172, and the pad layer includes a P-type pad 191 and an N-type pad 192.

[0025] It should be noted that the angle between the sidewall of the first SiO2 thin film layer 13 and the top of the N-type semiconductor layer 111 is determined by the rate of temperature decrease of SiO2 deposition. The sidewall cross-section of the first SiO2 thin film layer 13 is not a straight line, but an arc-shaped and discontinuous one.

[0026] Understandably, the angle between the sidewall of the first SiO2 thin film layer 13 and the top of the N-type semiconductor layer 111 is set to an acute angle. This is beneficial for fabricating a vertically oriented isolation trench 115. By setting the angle β of the isolation trench 115 to between 88° and 90°, which is close to vertical, compared with the traditional 45°-55° inclined isolation trench, the vertical sidewall significantly increases the effective area available for light emission within the unit projected area of ​​the chip, thereby improving the overall light-emitting area. The increase in light-emitting area directly leads to an increase in light output power, and the chip brightness is significantly improved under the same injection current conditions. At the same time, by setting the bottom width L of the isolation trench 115 to between 2um and 4um, and setting the distance L1 between the projection of the sidewall of the isolation trench 115 on the horizontal plane and the projection of the sidewall of the active light-emitting layer 112 on the horizontal plane to between 2um and 5um, it is ensured that the isolation trench 115 does not damage the active light-emitting layer 112, thus ensuring device reliability and yield.

[0027] Furthermore, an Al2O3 protective layer 14 is provided on the isolation groove 115.

[0028] Understandably, the isolation trench protective layer 14 can effectively prevent the sidewalls of the isolation trench 115 from being damaged by etching, corrosion or metal deposition in subsequent processes, avoid the risk of leakage or short circuit, and improve the long-term stability and reliability of the chip.

[0029] It should be noted that, because the angle β of the isolation groove 115 is set between 88° and 90°, the protective layer 14 of the isolation groove is made of SiN or SiO2 material on the sidewall at such a large angle, and its protective ability on the sidewall is weaker than that of the protective layer 14 of Al2O3 material.

[0030] Furthermore, a first SiO2 thin film layer through-hole 131 and a first insulating protective layer 132 are also provided on the first SiO2 thin film layer 13.

[0031] Understandably, the first SiO2 thin film layer via 131 provides a contact window for the reflective metal layer 15, and the first insulating protective layer 132 can effectively prevent the sidewalls of the N-type semiconductor layer conductive step 114 from being etched or contaminated in subsequent processes, reducing the risk of leakage current and improving the chip manufacturing yield and long-term reliability.

[0032] Example 2 Please see Figure 2 Embodiment 2 of the present invention also provides a method for fabricating a flip-chip silver mirror light-emitting diode, comprising: S1. Provide a substrate 10, and sequentially prepare an N-type semiconductor layer 111, an active light-emitting layer 112 and a P-type semiconductor layer 113 as an epitaxial layer on the substrate 10. Prepare a current spreading layer 12 on the epitaxial layer, and prepare an N-type semiconductor layer conductive step 114 on the current spreading layer 12 and the epitaxial layer. Specifically, in this embodiment, step S1 includes: First, a substrate 10 is provided. Then, on the substrate 10, the N-type semiconductor layer 111, the active light-emitting layer 112, and the P-type semiconductor layer 113 are sequentially prepared from bottom to top using MOCVD process as epitaxial layers. Then, indium tin oxide is deposited on the surface of the epitaxial layer as the current spreading layer 12 using magnetron sputtering process. Then, photoresist is coated on the surface of the current spreading layer 12. Then, exposure and development are used to remove part of the photoresist, exposing the current spreading layer 12 below the photoresist. Then, indium tin oxide etchant is used to remove the exposed current spreading layer. Then, inductively coupled plasma etching process is used to remove the P-type semiconductor layer 113 and the active light-emitting layer 112 below the P-type semiconductor layer 113 until the N-type semiconductor layer 111 is exposed. Then, the photoresist is removed to form the N-type semiconductor layer conductive step 114. S2. A first SiO2 thin film layer 13 is deposited on the current spreading layer 12 and the conductive step 114 of the N-type semiconductor layer using a first PECVD process. In the first PECVD process, the temperature of the reaction chamber decreases linearly, with the temperature ranging from 200℃ to 300℃ and the rate of linear decrease ranging from 0.5℃ / min to 1℃ / min. The angle between the sidewall of the first SiO2 thin film layer 13 and the top of the N-type semiconductor layer 111 is an acute angle. It should be noted that the first SiO2 thin film layer 13 can be used as a mask for the subsequent fabrication of the isolation trench 115. This is because during the first PECVD process, the angle between the sidewall of the first SiO2 thin film layer 13 and the top of the N-type semiconductor layer 111 is determined by the rate at which the SiO2 deposition temperature decreases. Since the temperature of the reaction chamber decreases linearly, after BOE etching, the cross-section of the sidewall of the first SiO2 thin film layer 13 is not a straight line. Instead, the cross-section of the sidewall of the first SiO2 thin film layer 13 is arc-shaped and discontinuous. That is, the angle between the sidewall of the first SiO2 thin film layer 13 and the top of the N-type semiconductor layer 111 is an acute angle. This is beneficial for the subsequent fabrication of the vertically oriented isolation trench 115. S3. Photoresist is coated, exposed, and developed on the first SiO2 thin film layer 13. Part of the photoresist is removed to expose the first SiO2 thin film layer 13 underneath. Then, BOE etching solution is used to remove the exposed first SiO2 thin film layer 13 down to the N-type semiconductor layer conductive step 114 at the bottom of the first SiO2 thin film layer 13. After that, ICP process is used to etch away the exposed N-type semiconductor layer conductive step 114 to form an isolation trench 115. The ICP process specifically includes a first etching cycle step repeated several times, a second etching cycle step repeated several times, and a third etching cycle step repeated several times. The etching depth of the first etching cycle step is 1 / 2 of the depth of the isolation trench, the etching depth of the second etching cycle step is 1 / 4 of the depth of the isolation trench, and the etching depth of the third etching cycle step is 1 / 4 of the depth of the isolation trench. The first etching cycle step includes a first sub-step, a second sub-step, and a third sub-step. The second etching cycle step includes a fourth sub-step, a fifth sub-step, and a sixth sub-step. The third etching cycle step includes a seventh sub-step, an eighth sub-step, and a ninth sub-step. The angle β of the isolation trench 115 is between 88° and 90°, the bottom width L of the isolation trench 115 is between 2µm and 4µm, and the distance L1 between the projection of the sidewall of the isolation trench 115 on the horizontal plane and the projection of the sidewall of the active light-emitting layer 112 on the horizontal plane is 2µm to 5µm. It should be noted that the number of cycles in the first etching cycle step, the second etching cycle step, and the third etching cycle step are adjusted according to the specific etching depth. Specifically, in this embodiment, the depth of the isolation trench is 6 μm, the number of cycles in the first etching cycle step is 13, the etching depth of the first etching cycle step is 3 μm, the number of cycles in the second etching cycle step is 4, the etching depth of the second etching cycle step is 1.5 μm, the number of cycles in the third etching cycle step is 4, and the etching depth of the third etching cycle step is 1.5 μm; In the first sub-step, the etching power is between 800W and 1200W, the etching power is between 400W and 600W, the etching time t1 is between 80s and 100s, the reaction gases are Cl2 and BCl3, the flow rate of Cl2 is between 20Scc / min and 40Scc / min, and the flow rate of BCl3 is between 10Scc / min and 15Scc / min. Specifically in this embodiment, in the first sub-step, the etching power is 800W, the etching power is 400W, the etching time t1 is 100s, the reaction gases are Cl2 and BCl3, the flow rate of Cl2 is 30Scc / min, and the flow rate of BCl3 is 10Scc / min. It should be noted that the first sub-step is an etching process, in which semiconductor materials are etched using a mixture of Cl2 and BCl3 gases; In the second sub-step, the etching power is between 200W and 300W, the etching power is off, the passivation time t2 is between 5s and 10s, the ratio of passivation time t2 to etching time t1 is between 1:20 and 1:10, the reaction gases are N2O and N2, the flow rate of N2O is between 30Scc / min and 50Scc / min, and the flow rate of N2 is between 80Scc / min and 100Scc / min; Specifically in this embodiment, in the second sub-step, the etching power is 200W, the etching power is off, the passivation time t2 is 10s, the ratio of passivation time t2 to etching time t1 is 1:10, the reaction gases are N2O and N2, the flow rate of N2O is 30Scc / min, and the flow rate of N2 is 80Scc / min. It should be noted that the second sub-step is a passivation process, in which N2O and N2 passivation gas react with the sidewall surface of the isolation trench 115 formed by etching in the first sub-step to generate GaO. x / GaN x O y Inert protective layer; In the third sub-step, the etching power is between 200W and 300W, the etching power is off, the passivation time t3 is consistent with the passivation time t2, the passivation time t3 is between 5s and 10s, the reaction gas is CHF3, and the flow rate is between 20Scc / min and 30Scc / min. Specifically in this embodiment, in the third sub-step, the etching power is 200W, the etching power is turned off, the passivation time t3 is consistent with the passivation time t2, the passivation time t3 is 10s, the reaction gas is CHF3, and its flow rate is 20Scc / min. It should be noted that the third sub-step is a polymer passivation process, in which CHF3 forms a fluorocarbon polymer protective film on the sidewalls and bottom of the isolation trench 115 formed by etching in the second sub-step. The fourth sub-step is completely identical to the first sub-step; In the fifth sub-step, the etching power is between 300W and 400W, the etching power is off, the passivation time t5 is greater than the passivation time t2, the passivation time t5 is between 8s and 20s, the ratio of passivation time t5 to etching time t1 is greater than the ratio of passivation time t2 to etching time t1, the ratio of passivation time t5 to etching time t1 is between 1:10 and 1:5, the reaction gases are N2O and N2, the flow rate of N2O is between 30Scc / min and 50Scc / min, the flow rate of N2 is between 80Scc / min and 100Scc / min, and the etching power in the fifth sub-step is greater than the etching power in the second sub-step. Specifically, in this embodiment, in the fifth sub-step, the etching power is 300W, the etching power is off, the passivation time t5 is greater than the passivation time t2, the passivation time t5 is 20s, the ratio of passivation time t5 to etching time t1 is greater than the ratio of passivation time t2 to etching time t1, the ratio of passivation time t5 to etching time t1 is 1:5, the reaction gases are N2O and N2, the flow rate of N2O is 30Scc / min, the flow rate of N2 is 80Scc / min, and the etching power in the fifth sub-step is greater than the etching power in the second sub-step. In the sixth sub-step, the etching power is between 300W and 400W, the etching power is off, the passivation time t6 is consistent with the passivation time t5, the passivation time t6 is between 8s and 20s, the reaction gas is CHF3, and the flow rate is between 20Scc / min and 30Scc / min. Specifically in this embodiment, in the sixth sub-step, the etching power is 300W, the etching power is turned off, the passivation time t6 is consistent with the passivation time t5, the passivation time t6 is 20s, the reaction gas is CHF3, and its flow rate is 20Scc / min. The seventh sub-step is completely identical to the first sub-step; In the eighth sub-step, the etching power is between 400W and 500W, the etching power is off, the passivation time t8 is greater than the passivation time t5, the passivation time t8 is between 20s and 50s, the ratio of the passivation time t8 to the etching time t1 is greater than the ratio of the passivation time t5 to the etching time t1, the ratio of the passivation time t8 to the etching time t1 is between 1:4 and 1:2, the reaction gases are N2O and N2, the flow rate of N2O is between 30Scc / min and 50Scc / min, the flow rate of N2 is between 80Scc / min and 100Scc / min, and the etching power in the eighth sub-step is greater than the etching power in the fifth sub-step. Specifically, in this embodiment, in the eighth sub-step, the etching power is 400W, the etching power is off, the passivation time t8 is greater than the passivation time t5, the passivation time t8 is 50s, the ratio of passivation time t8 to etching time t1 is greater than the ratio of passivation time t5 to etching time t1, the ratio of passivation time t8 to etching time t1 is between 1:2, the reaction gases are N2O and N2, the flow rate of N2O is 30Scc / min, the flow rate of N2 is 80Scc / min, and the etching power of the eighth sub-step is greater than the etching power of the fifth sub-step. In the ninth sub-step, the etching power is between 400W and 500W, the etching power is off, the passivation time t9 is consistent with the passivation time t8, the passivation time t9 is between 20s and 50s, the reaction gas is CHF3, and the flow rate is between 20Scc / min and 30Scc / min. Specifically in this embodiment, in the ninth sub-step, the etching power is 400W, the etching power is turned off, the passivation time t9 is consistent with the passivation time t8, the passivation time t9 is 50s, the reaction gas is CHF3, and its flow rate is 20Scc / min. It should be noted that CF4 can also be used as a reaction gas in the third, sixth, and ninth sub-steps.

[0033] S4. Prepare an isolation trench protective layer 14 on the remaining photoresist and the isolation trench 115; Furthermore, step S4 specifically includes: An Al2O3 film is prepared on the surface of the remaining photoresist and the isolation trench 115 using the ALD process as an isolation trench protective layer 14. Then, the Al2O3 film and photoresist on the photoresist are removed using the lift-off process. It should be noted that, because the angle β of the isolation groove 115 is set between 88° and 90°, the protective layer 14 of the isolation groove is made of SiN or SiO2 material on the sidewall at such a large angle, and its protective ability on the sidewall is weaker than that of the protective layer 14 of Al2O3 material.

[0034] S5. A first SiO2 thin film layer through-hole 131 and a first insulating protective layer 132 are prepared on the first SiO2 thin film layer 13. Furthermore, step S5 specifically includes: Photoresist is then applied to the first SiO2 thin film layer 13, followed by exposure and development to remove part of the photoresist, exposing the first SiO2 thin film layer 13 beneath it. The exposed part of the first SiO2 thin film layer 13 is then removed using BOE etching solution to form a first SiO2 thin film layer via 131. The photoresist is then removed, and the remaining first SiO2 thin film layer 13 serves as a first insulating protective layer 132 to protect the side of the N-type semiconductor layer conductive step 114. S6. A first semiconductor layer is prepared on the first SiO2 thin film layer 13; Furthermore, the first semiconductor layer includes a reflective metal layer 15, a second insulating layer, a conductive metal layer, a third insulating layer 18, and a pad layer sequentially disposed on the first SiO2 thin film layer 13.

[0035] Furthermore, a P-type second insulating layer through-hole 161 and an N-type second insulating layer through-hole 162 are provided on the second insulating layer, the conductive metal layer includes a P-type conductive metal layer 171 and an N-type conductive metal layer 172, and the pad layer includes a P-type pad 191 and an N-type pad 192.

[0036] Specifically, in this embodiment, step S6 includes: A negative photoresist is coated on the first SiO2 thin film layer 13, and then exposed and developed to remove part of the photoresist. Then, an electron beam evaporation process is used to sequentially deposit Ag metal with a thickness of 1200Å-2000Å, Ti metal with a thickness of 500Å-1000Å, Ni metal with a thickness of 500Å-1000Å, Ni metal with a thickness of 500Å-1000Å, Ni metal with a thickness of 500Å-1000Å, and Ti metal with a thickness of 30Å-50Å. Then, a lift-off process is used to remove the metal and photoresist on the photoresist to form the reflective metal layer 15. Next, an Al2O3 film is deposited on the reflective metal layer 15 and the areas not covered by the reflective metal layer 15 using the ALD process. Then, a SiO2 film is deposited on the Al2O3 film using the PECVD process. The Al2O3 film and the SiO2 film together constitute the second insulating layer. Then, photoresist is coated on the surface of the second insulating layer. Then, exposure and development are performed to remove part of the photoresist, exposing the second insulating layer under this part of the photoresist. Then, the photoresist is removed to form the P-type second insulating layer via 161 and the N-type second insulating layer via 162. Next, negative photoresist is coated in the second insulating layer, the P-type second insulating layer via 161, and the N-type second insulating layer via 162. Then, exposure and development are performed to remove part of the photoresist. Then, an electron beam evaporation process is used to sequentially deposit Al metal with a thickness of 1200Å-2000Å, Ti metal with a thickness of 500Å-1000Å, Pt metal with a thickness of 500Å-1000Å, Pt metal with a thickness of 500Å-1000Å, Ti metal with a thickness of 500Å-1000Å, Au metal with a thickness of 8000Å-10000Å, and Ti metal with a thickness of 30Å-50Å as the conductive metal layer. Then, a lift-off process is used to remove the metal and photoresist on the photoresist to form the P-type conductive metal layer 171 and the N-type conductive metal layer 172. Next, SiO2 thin films are deposited as the third insulating layer 18 on the P-type conductive metal layer 171, the N-type conductive metal layer 172 and the areas not covered by the conductive metal layer using a PECVD process. Next, a negative photoresist is coated on the surface of the third insulating layer 18. Then, exposure and development are used to remove part of the photoresist, exposing the third insulating layer 18 underneath. Then, the exposed third insulating layer 18 is removed using BOE etching solution. Then, an electron beam evaporation process is used to sequentially deposit Al metal with a thickness of 10000Å-16000Å, Ti metal with a thickness of 500Å-1000Å, Pt metal with a thickness of 500Å-1000Å, Ni metal with a thickness of 5000Å-10000Å, and Au metal with a thickness of 200Å-500Å as the pad layer. Then, a lift-off process is used to remove the metal and photoresist on top of the photoresist, forming P-type pad 191 and N-type pad 192.

[0037] Example 3 A flip-chip silver mirror light-emitting diode (LED) chip differs from the flip-chip silver mirror LED chip prepared in Example 2 in that: Specifically, in this embodiment, the depth of the isolation trench is 6 μm, the number of cycles in the first etching cycle step is 10, the etching depth of the first etching cycle step is 3 μm, the number of cycles in the second etching cycle step is 2, the etching depth of the second etching cycle step is 1.5 μm, the number of cycles in the third etching cycle step is 2, and the etching depth of the third etching cycle step is 1.5 μm; Specifically in this embodiment, in the first sub-step, the etching power is 1200W, the etching power is 600W, the etching time t1 is 80s, the reaction gases are Cl2 and BCl3, the flow rate of Cl2 is 40Scc / min, and the flow rate of BCl3 is 15Scc / min. Specifically in this embodiment, in the second sub-step, the etching power is 300W, the etching power is off, the passivation time t2 is 5s, the ratio of passivation time t2 to etching time t1 is 1:16, the reaction gases are N2O and N2, the flow rate of N2O is 50Scc / min, and the flow rate of N2 is 100Scc / min. Specifically in this embodiment, in the third sub-step, the etching power is 300W, the etching power is turned off, the passivation time t3 is consistent with the passivation time t2, the passivation time t3 is 5s, the reaction gas is CHF3, and its flow rate is 30Scc / min. Specifically, in this embodiment, in the fifth sub-step, the etching power is 400W, the etching power is off, the passivation time t5 is greater than the passivation time t2, the passivation time t5 is 8s, the ratio of passivation time t5 to etching time t1 is greater than the ratio of passivation time t2 to etching time t1, the ratio of passivation time t5 to etching time t1 is 1:10, the reaction gases are N2O and N2, the flow rate of N2O is 50Scc / min, the flow rate of N2 is 100Scc / min, and the etching power of the fifth sub-step is greater than the etching power of the second sub-step. Specifically in this embodiment, in the sixth sub-step, the etching power is 400W, the etching power is turned off, the passivation time t6 is consistent with the passivation time t5, the passivation time t6 is 8s, the reaction gas is CHF3, and its flow rate is 30Scc / min. Specifically, in this embodiment, in the eighth sub-step, the etching power is 500W, the etching power is off, the passivation time t8 is greater than the passivation time t5, the passivation time t8 is 20s, the ratio of passivation time t8 to etching time t1 is greater than the ratio of passivation time t5 to etching time t1, the ratio of passivation time t8 to etching time t1 is between 1:4, the reaction gases are N2O and N2, the flow rate of N2O is between 50Scc / min, the flow rate of N2 is between 100Scc / min, and the etching power of the eighth sub-step is greater than the etching power of the fifth sub-step. Specifically, in this embodiment, in the ninth sub-step, the etching power is between 500W, the etching power is off, the passivation time t9 is consistent with the passivation time t8, the passivation time t9 is 20s, the reaction gas is CHF3, and its flow rate is 30Scc / min.

[0038] Example 4 A flip-chip silver mirror light-emitting diode (LED) chip differs from the flip-chip silver mirror LED chip prepared in Example 2 in that: Specifically, in this embodiment, the depth of the isolation trench is 6 μm, the number of cycles in the first etching cycle step is 12, the etching depth of the first etching cycle step is 3 μm, the number of cycles in the second etching cycle step is 3, the etching depth of the second etching cycle step is 1.5 μm, the number of cycles in the third etching cycle step is 3, and the etching depth of the third etching cycle step is 1.5 μm; Specifically in this embodiment, in the first sub-step, the etching power is 1000W, the etching power is 500W, the etching time t1 is 90s, the reaction gases are Cl2 and BCl3, the flow rate of Cl2 is 45Scc / min, and the flow rate of BCl3 is 13Scc / min. Specifically in this embodiment, in the second sub-step, the etching power is 250W, the etching power is off, the passivation time t2 is 7s, the ratio of passivation time t2 to etching time t1 is 7:90, the reaction gases are N2O and N2, the flow rate of N2O is 40Scc / min, and the flow rate of N2 is 90Scc / min. Specifically in this embodiment, in the third sub-step, the etching power is 250W, the etching power is turned off, the passivation time t3 is consistent with the passivation time t2, the passivation time t3 is 7s, the reaction gas is CHF3, and its flow rate is 25Scc / min. Specifically, in this embodiment, in the fifth sub-step, the etching power is 350W, the etching power is off, the passivation time t5 is greater than the passivation time t2, the passivation time t5 is 14s, the ratio of passivation time t5 to etching time t1 is greater than the ratio of passivation time t2 to etching time t1, the ratio of passivation time t5 to etching time t1 is 7:45, the reaction gases are N2O and N2, the flow rate of N2O is between 40Scc / min, the flow rate of N2 is between 90Scc / min, and the etching power of the fifth sub-step is greater than the etching power of the second sub-step. Specifically in this embodiment, in the sixth sub-step, the etching power is 350W, the etching power is turned off, the passivation time t6 is consistent with the passivation time t5, the passivation time t6 is 14s, the reaction gas is CHF3, and its flow rate is 25Scc / min. Specifically, in this embodiment, in the eighth sub-step, the etching power is 450W, the etching power is off, the passivation time t8 is greater than the passivation time t5, the passivation time t8 is 35s, the ratio of passivation time t8 to etching time t1 is greater than the ratio of passivation time t5 to etching time t1, the ratio of passivation time t8 to etching time t1 is between 7:18, the reaction gases are N2O and N2, the flow rate of N2O is between 40Scc / min, the flow rate of N2 is between 90Scc / min, and the etching power of the eighth sub-step is greater than the etching power of the fifth sub-step. Specifically, in this embodiment, in the ninth sub-step, the etching power is between 450W, the etching power is off, the passivation time t9 is consistent with the passivation time t8, the passivation time t9 is 35s, the reaction gas is CHF3, and its flow rate is 25Scc / min.

[0039] Comparative Example 1 A flip-chip silver mirror light-emitting diode (LED) chip differs from the flip-chip silver mirror LED chip prepared in Example 2 in that: In step S3, the ICP process specifically includes an etching process, with an etching power of 1000W for the upper etching step and 500W for the lower etching step, and the reaction gases being Cl2 and BCl3.

[0040] Based on the flip-chip silver mirror light-emitting diodes (LEDs) prepared in Examples 2, 3, 4, and Comparative Example 1, the luminous brightness of the 1320µm*1320µm flip-chip silver mirror LEDs prepared in Examples 2, 3, 4, and Comparative Example 1 was tested by passing a test current of 700mA through them. The corresponding test results are shown in the table below:

[0041] It should be noted that, in order to ensure the reliability of the verification results, when comparing the isolation cell angle and chip luminous brightness of the flip-chip silver mirror light-emitting diode chips prepared in the above embodiments 2, 3, 4 and Comparative Example 1, the other processes and parameters should be kept consistent except for the above-mentioned parameters.

[0042] In summary, the flip-chip silver mirror light-emitting diode chip and its fabrication method in the above embodiments of the present invention, by setting the ICP process to a first etching cycle step, a second etching cycle step, and a third etching cycle step, which are repeated several times, wherein the first etching cycle step includes a first sub-step, a second sub-step, and a third sub-step; the second etching cycle step includes a fourth sub-step, a fifth sub-step, and a sixth sub-step; and the third etching cycle step includes a seventh sub-step, an eighth sub-step, and a ninth sub-step, abandons the traditional single-parameter cycle mode and adopts three... The etching cycle is designed in a progressive manner. The three etching cycles work together to precisely control the verticality of the sidewalls through layered etching and passivation. Each etching cycle includes three sub-steps: etching, self-passivation, and polymer passivation. The passivation power, passivation time, and the ratio of passivation to etching time gradually increase in each etching cycle, forming a layered control logic of shallow etching, weak passivation, medium etching, medium passivation, deep etching, and strong passivation. The first etching cycle etches half the depth of the isolation trench. With lower power and shorter passivation time, the initial trench outline is constructed. At the same time, the GaO formed by self-passivation is utilized. x / GaN xAn inert protective layer and a fluorocarbon polymer protective film formed by polymer passivation prevent excessive etching of the sidewalls. The second etching cycle etches 1 / 4 of the depth, increasing passivation power and time to strengthen sidewall protection and reduce sidewall tilt. The third etching cycle etches the remaining depth, further increasing passivation power and the passivation-to-etching time ratio, achieving precise sidewall shaping and ultimately stabilizing the isolation trench angle at 88-90°, approaching a vertical state. Unlike traditional single passivation methods, this invention incorporates three sub-steps—etching, self-passivation, and polymer passivation—in each etching cycle. Each etching cycle is followed by self-passivation and polymer passivation. The two-step passivation protection involves a self-passivated inert protective layer that directly adheres to the GaN sidewalls, preventing continuous erosion of the sidewalls by etching gases. The fluorocarbon polymer film formed by polymer passivation further covers the sidewalls and trench bottom, filling in minor defects and preventing excessive etching of the trench bottom. This synergistic effect of dual passivation not only ensures the perpendicularity of the isolation trench angle but also guarantees smooth, burr-free, and undamaged trench walls, reducing gaps and defects during subsequent insulating layer coverage. This provides a fundamental dual passivation mechanism to enhance the chip's insulation performance and reliability, ensuring the integrity and flatness of the trench walls. This is achieved through the conductive steps between the current spreading layer 12 and the N-type semiconductor layer. A first SiO2 thin film layer is deposited on layer 114 using a first PECVD process. During the first PECVD process, the temperature of the reaction chamber decreases linearly, resulting in an acute angle between the sidewall of the first SiO2 thin film layer and the top of the N-type semiconductor layer. This serves as a mask for the subsequent ICP process, further assisting in controlling the verticality of the isolation trench, thus synergizing with the ICP process to ensure the isolation trench angle is precisely between 88° and 90°. Simultaneously, the first SiO2 thin film layer also provides insulation protection, further protecting the conductive steps of the N-type semiconductor layer and reducing damage during etching. By keeping the isolation trench angle β between 88° and... With a 90° angle, close to vertical, compared to the traditional 45°-55° inclined isolation trench, the vertical sidewall significantly increases the effective area for light emission per unit projected area of ​​the chip, thereby improving the overall light-emitting area. The increase in light-emitting area directly leads to an increase in light output power, and the chip brightness is significantly improved under the same injection current conditions. At the same time, by setting the bottom width L of the isolation trench between 2um and 4um, and setting the distance L1 between the projection of the isolation trench sidewall on the horizontal plane and the projection of the active light-emitting layer sidewall on the horizontal plane between 2um and 5um, it is ensured that the isolation trench does not damage the active light-emitting layer, thus guaranteeing device reliability and yield.

[0043] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0044] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A flip-chip silver mirror light-emitting diode chip, characterized in that, include: The substrate, epitaxial layer, current spreading layer, first SiO2 thin film layer and first semiconductor layer are arranged sequentially from bottom to top; The epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer arranged sequentially from bottom to top. An N-type semiconductor layer conductive step is also provided on the top of the N-type semiconductor layer, and an isolation trench is provided on the outside of the epitaxial layer. The angle between the sidewall of the first SiO2 thin film layer and the top of the N-type semiconductor layer is an acute angle. The angle β of the isolation trench is between 88° and 90°. The bottom width L of the isolation trench is between 2um and 4um. The distance L1 between the projection of the sidewall of the isolation trench onto the horizontal plane and the projection of the sidewall of the active light-emitting layer onto the horizontal plane is between 2um and 5um.

2. The flip-chip silver mirror light-emitting diode chip according to claim 1, characterized in that, An Al2O3 protective layer is provided on the isolation groove.

3. The flip-chip silver mirror light-emitting diode chip according to claim 1, characterized in that, The first semiconductor layer includes a reflective metal layer, a second insulating layer, a conductive metal layer, a third insulating layer, and a pad layer sequentially disposed on the first SiO2 thin film layer.

4. The flip-chip silver mirror light-emitting diode chip according to claim 3, characterized in that, The second insulating layer has P-type and N-type second insulating layer vias, the conductive metal layer includes a P-type conductive metal layer and an N-type conductive metal layer, and the pad layer includes a P-type pad and an N-type pad.

5. The flip-chip silver mirror light-emitting diode chip according to claim 1, characterized in that, The first SiO2 thin film layer also has a first SiO2 thin film layer through hole and a first insulating protective layer.

6. A method for fabricating a flip-chip silver mirror light-emitting diode, characterized in that, include: S1. A substrate is provided, and an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer are sequentially prepared on the substrate as epitaxial layers. A current spreading layer is prepared on the epitaxial layers, and conductive steps of the N-type semiconductor layer are prepared on the current spreading layer and the epitaxial layers. S2. A first SiO2 thin film layer is deposited on the conductive steps of the current spreading layer and the N-type semiconductor layer using a first PECVD process. In the first PECVD process, the temperature of the reaction chamber decreases linearly, with the temperature ranging from 200℃ to 300℃ and the rate of linear decrease ranging from 0.5℃ / min to 1℃ / min. The angle between the sidewall of the first SiO2 thin film layer and the top of the N-type semiconductor layer is an acute angle. S3. Coat photoresist on the first SiO2 thin film layer, expose and develop it to remove part of the photoresist and expose the first SiO2 thin film layer under the photoresist. Then use BOE etching solution to remove the exposed first SiO2 thin film layer down to the N-type semiconductor layer conductive step at the bottom of the first SiO2 thin film layer. Then use ICP process to etch away the exposed N-type semiconductor layer conductive step to form an isolation trench. The ICP process specifically includes a first etching cycle step repeated several times, a second etching cycle step repeated several times, and a third etching cycle step repeated several times. The etching depth of the first etching cycle step is 1 / 2 of the depth of the isolation trench, the etching depth of the second etching cycle step is 1 / 4 of the depth of the isolation trench, and the etching depth of the third etching cycle step is 1 / 4 of the depth of the isolation trench. The first etching cycle step includes a first sub-step, a second sub-step, and a third sub-step. The second etching cycle step includes a fourth sub-step, a fifth sub-step, and a sixth sub-step. The third etching cycle step includes a seventh sub-step, an eighth sub-step, and a ninth sub-step. The angle β of the isolation trench is between 88° and 90°, the bottom width L of the isolation trench is between 2µm and 4µm, and the distance L1 between the projection of the sidewall of the isolation trench on the horizontal plane and the projection of the sidewall of the active light-emitting layer on the horizontal plane is 2µm to 5µm. In the first sub-step, the etching power is between 800W and 1200W, the etching power is between 400W and 600W, the etching time t1 is between 80s and 100s, the reaction gases are Cl2 and BCl3, the flow rate of Cl2 is between 20Scc / min and 40Scc / min, and the flow rate of BCl3 is between 10Scc / min and 15Scc / min. In the second sub-step, the etching power is between 200W and 300W, the etching power is off, the passivation time t2 is between 5s and 10s, the ratio of passivation time t2 to etching time t1 is between 1:20 and 1:10, the reaction gases are N2O and N2, the flow rate of N2O is between 30Scc / min and 50Scc / min, and the flow rate of N2 is between 80Scc / min and 100Scc / min; In the third sub-step, the etching power is between 200W and 300W, the etching power is turned off, the passivation time t3 is consistent with the passivation time t2, the passivation time t3 is between 5s and 10s, the reaction gas is CHF3, and the flow rate is between 20Scc / min and 30Scc / min. The fourth sub-step is completely identical to the first sub-step; In the fifth sub-step, the etching power is between 300W and 400W, the etching power is off, the passivation time t5 is greater than the passivation time t2, the passivation time t5 is between 8s and 20s, the ratio of passivation time t5 to etching time t1 is greater than the ratio of passivation time t2 to etching time t1, the ratio of passivation time t5 to etching time t1 is between 1:10 and 1:5, the reaction gases are N2O and N2, the flow rate of N2O is between 30Scc / min and 50Scc / min, the flow rate of N2 is between 80Scc / min and 100Scc / min, and the etching power in the fifth sub-step is greater than the etching power in the second sub-step. In the sixth sub-step, the etching power is between 300W and 400W, the etching power is off, the passivation time t6 is consistent with the passivation time t5, the passivation time t6 is between 8s and 20s, the reaction gas is CHF3, and the flow rate is between 20Scc / min and 30Scc / min. The seventh sub-step is completely identical to the first sub-step; In the eighth sub-step, the etching power is between 400W and 500W, the etching power is off, the passivation time t8 is greater than the passivation time t5, the passivation time t8 is between 20s and 50s, the ratio of the passivation time t8 to the etching time t1 is greater than the ratio of the passivation time t5 to the etching time t1, the ratio of the passivation time t8 to the etching time t1 is between 1:4 and 1:2, the reaction gases are N2O and N2, the flow rate of N2O is between 30Scc / min and 50Scc / min, the flow rate of N2 is between 80Scc / min and 100Scc / min, and the etching power in the eighth sub-step is greater than the etching power in the fifth sub-step. In the ninth sub-step, the etching power is between 400W and 500W, the etching power is off, the passivation time t9 is consistent with the passivation time t8, the passivation time t9 is between 20s and 50s, the reaction gas is CHF3, and the flow rate is between 20Scc / min and 30Scc / min. S4. Prepare an isolation trench protective layer on the remaining photoresist and the isolation trench; S5. Prepare a first SiO2 thin film layer through hole and a first insulating protective layer on the first SiO2 thin film layer; S6. Prepare a first semiconductor layer on the first SiO2 thin film layer.

7. The method for fabricating a flip-chip silver mirror light-emitting diode according to claim 6, characterized in that, Step S4 specifically includes: An Al2O3 film is prepared on the surface of the remaining photoresist and the isolation trench using the ALD process as a protective layer for the isolation trench. Then, the Al2O3 film and photoresist on the photoresist are removed using the lift-off process.

8. The method for fabricating a flip-chip silver mirror light-emitting diode according to claim 6, characterized in that, Step S5 specifically includes: Photoresist is then applied onto the first SiO2 thin film layer. After exposure and development, a portion of the photoresist is removed, exposing the first SiO2 thin film layer beneath it. The exposed portion of the first SiO2 thin film layer is then removed using BOE etching solution to form a via in the first SiO2 thin film layer. The photoresist is then removed, and the remaining first SiO2 thin film layer serves as a first insulating protective layer to protect the conductive steps of the N-type semiconductor layer.

9. The method for fabricating a flip-chip silver mirror light-emitting diode according to claim 6, characterized in that, The first semiconductor layer includes a reflective metal layer, a second insulating layer, a conductive metal layer, a third insulating layer, and a pad layer sequentially disposed on the first SiO2 thin film layer.

10. The method for fabricating a flip-chip silver mirror light-emitting diode according to claim 9, characterized in that, The second insulating layer has P-type and N-type second insulating layer vias, the conductive metal layer includes a P-type conductive metal layer and an N-type conductive metal layer, and the pad layer includes a P-type pad and an N-type pad.

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