Neuromorphic device and reconfigurable synapse neuromorphic array

Abstract

This invention provides a neuromorphic device and a reconfigurable synaptic neuromorphic array. The neuromorphic device comprises a main transistor M1 and a control transistor M2. The control transistor M2 includes a P-type semiconductor substrate, a first source region, a first drain region, and a first gate electrode formed on the upper surface of the substrate. The main transistor M1 includes a deep N-well region formed in the substrate, a floating body region formed on the upper surface of the deep N-well region, a shallow P-well region formed around the floating body region, a second source region, a second drain region, and a second gate electrode formed on the upper surface of the floating body region. A body contact region formed on the upper surface of the shallow P-well region is electrically connected to the first drain region, thereby regulating the switching of the neuromorphic device between synaptic and neuronal modes by applying a mode control voltage to the first gate electrode. This invention combines a dual-transistor collaborative control architecture to achieve dynamic switching between synaptic and neuronal modes with a single device, and features a simple structure and high stability.

Description

Technical Field

[0001] This invention relates to the field of neuromorphic computing technology, and in particular to a neuromorphic device and a reconfigurable synaptic neuromorphic array. Background Technology

[0002] In the field of neuromorphic computing, traditional multi-transistor solutions typically require a large number of transistors to work together to implement neuron and synapse functions, resulting in low chip area utilization and difficulty in meeting the needs of high-density integration of large-scale neural networks. At the same time, the complex multi-transistor architecture requires cumbersome peripheral control ionization and numerous interface circuits, which not only increases the design difficulty of the chip, but also introduces additional signal transmission delays and power consumption overhead, further restricting the overall computing power and energy efficiency of neuromorphic systems.

[0003] While novel electronic devices such as memristors, widely used in existing technologies, possess some programmable synaptic weights, their cycle durability is typically less than 10^5 cycles due to the intrinsic properties of the functional materials, making it difficult to meet the requirements for long-term stable operation. Furthermore, these devices cannot achieve real-time dynamic reconfiguration of neuronal and synaptic functions, resulting in insufficient system flexibility and difficulty in adapting to diverse and dynamic neuromorphic computing tasks, significantly limiting the expansion and large-scale application of neuromorphic computing.

[0004] To address the aforementioned issues, this invention proposes an innovative neuromorphic device and array architecture that effectively improves the integration, reliability, and flexibility bottlenecks of existing solutions, providing core technical support for the practical and large-scale implementation of neuromorphic computing. Summary of the Invention

[0005] This application provides a neuromorphic device and a reconfigurable synaptic neuromorphic array.

[0006] In a first aspect, this application provides a neuromorphic device, including a dual transistor unit that can switch between synaptic mode and neuron mode, the dual transistor unit being composed of a main transistor M1 and a control transistor M2;

[0007] The control transistor M2 includes: P-type semiconductor substrate; The first source region and the first drain region of the N-type are formed alternately on the upper surface of the P-type semiconductor substrate; The first gate electrode is formed on the upper surface of the P-type semiconductor substrate between the first source region and the first drain region through a first gate insulating film; The main transistor M1 includes: A deep N-well region is formed inside the P-type semiconductor substrate; A floating body region is formed on the upper surface of the deep N-well region; A shallow P-well region is formed around the periphery of the floating body region. The P-type doping concentration of the shallow P-well region is higher than that of the floating body region. Together with the deep N-well region, the floating body region is electrically isolated from the P-type semiconductor substrate. The second source region and the second drain region of the N-type are formed alternately on the upper surface of the floating body region; The second gate electrode is formed on the upper surface of the floating body region between the second source region and the second drain region through a second gate insulating film; A body contact region is formed on the upper surface of the shallow P-well region. The body contact region is electrically connected to the first drain region of the control transistor M2, and the first source region of the control transistor M2 is connected to a reference potential. The neuromorphic device is configured to control the switching between synaptic and neuron modes by applying a mode control voltage to the first gate electrode to adjust the equivalent resistance of the floating body region.

[0008] In conjunction with the first aspect, in one possible implementation, the bulk contact region is a heavily doped P-type doped region.

[0009] In conjunction with the first aspect, in one possible implementation, when the mode control voltage is less than a first preset threshold, the equivalent resistance increases, and the neuromorphic device operates in the synaptic mode; In the synaptic mode, the main transistor M1 is configured as follows: In response to a positive voltage pulse applied to the second drain region of the main transistor M1, its threshold voltage decreases and its channel conductance increases, resulting in a long-term enhancement of the synaptic weight. In response to a negative voltage pulse applied to the second drain region of the main transistor M1, its threshold voltage increases and its channel conductance decreases, corresponding to long-term suppression of synaptic weights.

[0010] In conjunction with the first aspect, in one possible implementation, the floating body region is configured as follows: Based on the voltage pulse applied to the second drain region, different numbers of stable charge states are accumulated, corresponding to multi-level distinguishable channel conductance, to simulate multi-level synaptic weights.

[0011] In conjunction with the first aspect, in one possible implementation, when the mode control voltage is greater than the second preset threshold, the equivalent resistance decreases, and the neuromorphic device operates in the neuron mode; wherein the second preset threshold is greater than the first preset threshold. In the neuron mode, the charge in the floating body region is dynamically discharged through an equivalent resistance to simulate the leakage-integration-ignition behavior of a neuron.

[0012] In conjunction with the first aspect, in one possible implementation, a plurality of shallow trench isolation regions are further included. Each of the shallow trench isolation regions is formed on the periphery of the body contact region, the second source region and the second drain region of the main transistor M1, and the first source region and the first drain region of the control transistor M2, for the purpose of achieving electrical isolation between the body contact region, the active regions of the main transistor M1 and the control transistor M2.

[0013] In conjunction with the first aspect, in one possible implementation, the body contact area shares the shallow trench isolation area on the same side as the main transistor M1.

[0014] In conjunction with the first aspect, in one possible implementation, the first preset threshold is 0.2V and the second preset threshold is 0.8V.

[0015] Secondly, this application provides a reconfigurable synaptic neuromorphic array, including a plurality of neuromorphic devices arranged in an array, wherein the neuromorphic devices are as described in any of the preceding claims. The second gate electrode of the main transistor M1 of each of the neuromorphic devices arranged along the first direction is connected to the corresponding word line. In each of the neuromorphic devices arranged along the second direction, the second drain region of the main transistor M1 is connected to the corresponding bit line, and the second source region is connected to the corresponding source line. The first gate electrode of each of the neuromorphic devices arranged along the first direction is connected to the corresponding mode control voltage line, and the first source region is connected to the reference potential line.

[0016] In conjunction with the second aspect, in one possible implementation, the word line and the mode control voltage line are configured to apply control signals synchronously to collaboratively control the operating mode of the target neuromorphic device selected by the word line and the mode control voltage line.

[0017] Compared with existing technologies, the advantages of this invention are as follows: First, the dual-mode neuromorphic device of this invention has a simplified structure and higher integration and reliability. The main transistor M1 and control transistor M2 are integrated on the same P-type semiconductor substrate. Through the structural design of the deep N-well region, the functional area of ​​the main transistor M1 located above it is electrically isolated from the P-type semiconductor substrate located below it. The P-type semiconductor substrate above the deep N-well region constitutes the floating body region of the main transistor M1. A shallow P-well region with a high P-type doping concentration is formed around the floating body region. Utilizing its high doping characteristics, the sidewalls of the floating body region are electrically isolated from the P-type semiconductor substrate. Thus, through the rational design of the deep N-well region and the shallow P-well region, an independent floating body region is formed, which can effectively prevent charge leakage from the floating body region to the substrate, ensuring the stability of charge storage and the accuracy of synaptic weight control. Second, the volume contact area formed on the upper surface of the shallow P-well region is electrically connected to the control transistor M2 to adjust the equivalent resistance, thereby dynamically controlling the operating mode of the device. This design avoids direct contact between the floating body region and external metal lines, significantly reducing the risk of signal crosstalk. Simultaneously, it achieves seamless, low-power switching between synaptic and neuron modes, enabling a single device to perform both synaptic weight storage and neuron pulse firing functions, greatly improving the flexibility and energy efficiency of system integration. Thirdly, based on the aforementioned dual-mode neuromorphic device, an M×N array of reconfigurable synaptic neuromorphic arrays is constructed. Through optimized circuit interconnect design, synchronous mode control logic, and phased workflow design, multiple breakthroughs are achieved in integration density, functional flexibility, computational performance, and system power consumption. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a dual-mode neuromorphic device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the architecture of a reconfigurable synaptic neuromorphic array in an embodiment of the present invention. Detailed Implementation

[0019] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0021] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. Furthermore, the technical features involved in the different embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0022] To facilitate understanding of the proposed solution, the relevant concepts of floating-body NMOS transistors will be explained below.

[0023] A floating-body NMOS transistor is a MOSFET device with an electrically isolated body region from the substrate and no fixed bias in the body region. Its core feature is that the body region forms an electrically "floating node," allowing for specific functional modulation through the accumulation and release of charge within the body region. The core working principle is as follows: when the voltage applied to the drain of the floating-body NMOS transistor exceeds the critical threshold voltage, electrons in its channel are accelerated and collide with each other under the influence of a strong electric field, generating a large number of electron-hole pairs. Electrons are collected by the drain, while holes accumulate in the electrically isolated floating body region, causing the body region potential Vb to rise. This increased body region potential further reduces the threshold voltage Vth of the floating-body NMOS transistor, ultimately leading to an abnormal increase in the drain current Id with increasing drain voltage Vd, forming a distinct "kink" on the Id-Vd characteristic curve. This phenomenon is the physical basis for the neural / synaptic function of the floating-body NMOS transistor. It should be noted that the above-mentioned critical threshold voltage is the drain critical voltage that triggers severe impact ionization at the drain terminal and causes the Id-Vd characteristic curve to become kinked. The specific value of this parameter is closely related to the device structure and process parameters of the floating body MOS transistor, such as the channel length, substrate material, and doping concentration.

[0024] To achieve controllable regulation of the charge state in the body region and further realize flexible switching between neuronal and synaptic functions, a floating-body bias control transistor can be introduced based on the floating-body NMOS transistor. The core function of this floating-body bias control transistor is to adjust the equivalent resistance Rb of the body region to control the charge discharge rate within the body region, thereby realizing the dynamic switching of the device between neuronal and synaptic modes. The neuromorphic device and reconfigurable synaptic neuromorphic array based on the floating-body NMOS transistor of this application will be described in detail below.

[0025] Example 1 Combination Figure 1 As shown, this embodiment provides a dual-mode neuromorphic device compatible with standard processes. The device is fabricated using a 180nm standard bulk silicon NMOS process, requiring no special process modification and exhibiting excellent process compatibility and mass production feasibility. The device integrates a dual-transistor unit capable of dynamically switching between synaptic and neuron modes. This dual-transistor unit consists of a main transistor M1 and a control transistor M2, both of which have structures and electrical characteristics adapted to the 180nm bulk silicon NMOS process.

[0026] The main transistor M1, as the core functional device, is responsible for pulse firing in neuronal mode and conductance modulation and weight storage in synaptic mode. Its body region adopts a floating design, forming the floating body region 12 of the main transistor M1. This floating body region 12 serves as the core area for charge storage and dynamic potential control, and is a key structure for realizing dual-mode switching and neuromorphic functions. The control transistor M2 is an auxiliary control device. Its core function is to precisely adjust the equivalent resistance Rb of the floating body region 12 of the main transistor M1. By applying a mode control voltage Vg2 to the first gate electrode 24 of the control transistor M2, its on / off state is changed, thereby dynamically adjusting the operating mode of the neuromorphic device.

[0027] Specifically, the bottom layer of the neuromorphic device is a P-type semiconductor substrate 21, which serves as the physical support substrate for the entire neuromorphic device. It is typically grounded, providing a stable electrical reference potential for the entire device. Simultaneously, the P-type semiconductor substrate 21 also serves as the body region of the control transistor M2. Its upper surface is ion-implanted to form a heavily doped N-type first source region 22 and a first drain region 23 at intervals. On the upper surface of the P-type semiconductor substrate 21 between the first source region 22 and the first drain region 23, a gate oxide dielectric is deposited to form a first gate insulating film. Polysilicon is deposited and patterned on top of the first gate insulating film to form the first gate electrode 24 of the control transistor M2, thus constituting the complete control transistor M2.

[0028] Inside the P-type semiconductor substrate 21, a deep N-well region 11 is formed using a high-energy ion implantation process. This deep N-well region 11 serves as a core isolation structure, electrically isolating the functional area of ​​the main transistor M1 above it from the P-type semiconductor substrate 21 below. The main transistor M1 is constructed entirely above the deep N-well region 11 and mainly consists of a floating body region 12, a shallow P-well region 13, a second source region 14, a second drain region 15, and a second gate electrode 16. The P-type semiconductor substrate 21, located above the deep N-well region 11, constitutes the floating body region 12 of the main transistor M1. The shallow P-well region 13 continuously surrounds the peripheral sidewalls of the floating body region 12, and its bottom is in physical contact with the upper surface of the deep N-well region 11, thus forming an isolation structure enclosing the floating body region 12 together with the deep N-well region 11. The P-type doping concentration of the shallow P-well region 13 is higher than that of the floating body region 12 to suppress charge leakage from the floating body region 12 to the P-type semiconductor substrate 21. Thus, the deep N-well region 11 achieves electrical isolation between the bottom of the floating body region 12 and the P-type semiconductor substrate 21 through the PN junction barrier; the shallow P-well region 13, through its high doping characteristics, can effectively block the leakage of charge in the floating body region 12 to the P-type semiconductor substrate 21, thereby achieving electrical isolation between the side of the floating body region 12 and the P-type semiconductor substrate 21.

[0029] To ensure isolation, the upper surface of the deep N-well region 11 must substantially cover the bottom of the floating body region 12, while the shallow P-well region 13 is arranged around the sidewall of the floating body region 12 and must cover the entire sidewall of the floating body region 12. This ensures that the deep N-well region 11 and the shallow P-well region 13 together fully enclose the bottom and sidewall of the floating body region 12, preventing the floating body region 12 from directly contacting the P-type semiconductor substrate 21.

[0030] It is understood that the P-type doping concentration of the floating body region 12 can be the same as that of the P-type semiconductor substrate 21, or it can be set differently according to design requirements; that is, the floating body region 12 can be directly formed by the P-type semiconductor substrate 21 above the deep N-well region 11, or it can be formed by P-type doping on the basis of the P-type semiconductor substrate 21 above the deep N-well region 11. This application does not make specific limitations on this.

[0031] The isolation design of the deep N-well region 11 and the shallow P-well region 13 effectively prevents latch-up and provides an independent and stable electrical operating environment for the main transistor M1. On the other hand, it constructs a closed charge storage space for the floating body region 12, preventing charge leakage to the P-type semiconductor substrate 21 and ensuring the stability of charge storage and the reliability of synaptic weight regulation.

[0032] On the upper surface of the floating body region 12, a heavily doped N-type second source region 14 and a second drain region 15 are formed alternately by ion implantation, constituting the two electrodes of the conductive channel of the main transistor M1. On the upper surface of the floating body region 12 between the second source region 14 and the second drain region 15, a gate oxide dielectric is deposited to form a second gate insulating film. Polysilicon is deposited and patterned on top of the second gate insulating film to form the second gate electrode 16 of the main transistor M1. At the same time, a heavily doped P-type body contact region 17 is also prepared on the upper surface of the shallow P-well region 13. The doping concentration of the body contact region 17 is higher than that of the shallow P-well region 13, which can form a good ohmic contact with the external metal line. It is a key structure for realizing the electrical conduction between the floating body region 12 and the control transistor M2.

[0033] This device achieves electrical isolation between the bottom of the floating body region 12 and the P-type semiconductor substrate 21 through the design of the deep N-well region 11; through the design of the shallow P-well region 13, not only can the sidewall of the floating body region 12 be electrically isolated from the P-type semiconductor substrate 21, but the equivalent resistance Rb of the floating body region 12 can also be indirectly adjusted through the shallow P-well region 13, avoiding direct contact between the floating body region 12 and the external metal line, further improving the charge storage stability and dual-mode switching accuracy.

[0034] The upper surface of the shallow P-well region 13 of the main transistor M1 is heavily doped with a P-type body contact region 17. The body contact region 17 is electrically connected to the first drain region 23 of the control transistor M2, and the first source region 22 of the control transistor M2 is connected to the reference potential, thus forming a complete equivalent resistance Rb control link. By applying a mode control voltage Vg2 to the first gate electrode 24 of the control transistor M2, the equivalent resistance Rb of the floating body region 12 of the main transistor M1 can be controlled, thereby realizing the control of the charge accumulation and discharge rate in the floating body region 12, and ultimately realizing the switching of the neuromorphic device between synaptic mode and neuron mode. The specific switching rules are as follows: When the mode control voltage Vg2 applied to the first gate electrode 24 is greater than 0.8V, the control transistor M2 is turned on, and the equivalent resistance Rb of the floating body region 12 of the main transistor M1 is reduced. The low Rb accelerates the accumulation and discharge rate of charge in the floating body region 12, making the entire device exhibit steep threshold switching characteristics (on / off ratio greater than 10³), simulating the "all-or-none" pulse firing behavior of a neuron. When the mode control voltage Vg2 applied to the first gate electrode 24 is less than 0.2V, the control transistor M2 is turned off, and the equivalent resistance Rb of the floating body region 12 of the main transistor M1 increases significantly. The high Rb slows down the injection / recombination process of the body region charge, and the channel conductance can be finely controlled to stably realize multi-level discrete conductance states. Each level of conductance state corresponds to a different synaptic weight value, simulating the long-term enhancement and long-term suppression of synaptic weights.

[0035] In neuron mode, the charge in floating body region 12 is dynamically discharged through the equivalent resistance Rb to simulate the leakage-integration-ignition behavior of a neuron. The specific process is as follows: When the drain voltage Vd applied to the second drain region 15 of the main transistor M1 is in the low range, the electric field of the second drain region 15 is weak, the impact ionization effect is weak, and the drain current Id rises slowly with the drain voltage Vd. This process corresponds to the slow integration and accumulation of the neuron's input signal to the anterior synapse. When the drain voltage Vd exceeds the critical threshold voltage, the strong electric field of the second drain region 15 triggers violent impact ionization. The generated holes accumulate rapidly and raise the potential Vb of the floating body region, causing the threshold voltage Vth of the main transistor M1 to drop sharply. The drain current Id surges suddenly, forming a kink. This process corresponds to the instantaneous ignition behavior of the neuron after the integral reaches the trigger threshold. The steepness of the current change at the kink determines the steepness of the neuron's threshold. By controlling the equivalent resistance Rb of the floating body region 12, charge discharge can be accelerated, making the kink steeper, simulating a "none-or-nothing" switching characteristic closer to that of a biological neuron, and adapting to the functional requirements of neurons in neuromorphic computing.

[0036] In synaptic operation mode, the neuromorphic device uses the channel conductance of the main transistor M1 as a physical representation of synaptic weight. Different steady-state channel conductance values ​​correspond to different levels of synaptic weight, thus simulating biological synaptic weight at the electrical level. This device utilizes the impact ionization effect generated by the second drain region 15 under pulse excitation to achieve long-term plasticity control of synaptic weight, specifically including two operating states: long-term enhancement (LTP) and long-term suppression (LTD). The control mechanism is as follows: When a positive voltage pulse is applied to the second drain region 15 of the main transistor M1 (example parameters: Vd=+5V, Tp=500µs), strong collisional ionization occurs in the second drain region 15 under the influence of the high electric field, generating a large number of electron-hole pairs. Among them, holes are injected into the floating body region 12, causing the body region potential Vb to rise, which in turn reduces the threshold voltage Vth of the main transistor M1. Under the condition of fixed gate bias, the conductivity of the conductive channel carriers is enhanced, the channel current increases, and the channel conductance is improved, corresponding to the long-term enhancement of synaptic weight (LTP). When a negative voltage pulse is applied to the second drain region 15 of the main transistor M1 (example parameter: Vd = -3V), the second drain region 15 induces hot electrons to be injected into the floating body region 12 under the action of the reverse bias electric field. The injected hot electrons recombine with the original holes in the floating body region 12, neutralizing some of the positive charge, resulting in a decrease in the body region potential Vb and an increase in the threshold voltage Vth of the main transistor M1. Under the condition of fixed gate bias, the conductivity of the conductive channel weakens, the channel current decreases, and the channel conductance decreases, corresponding to the long-term suppression (LTD) of the synaptic weight.

[0037] Furthermore, the outer walls of the active regions of this device, namely the body contact region 17, the first source region 22 and the first drain region 23, and the second source region 14 and the second drain region 15, are surrounded by shallow trench isolation regions made of silicon dioxide insulating medium. This can achieve electrical isolation between the body contact region, the main transistor M1 and the active regions of the control transistor M2, effectively prevent carrier diffusion and signal crosstalk, and further ensure the independence of floating body charge storage and the reliability of dual-mode switching.

[0038] In summary, this embodiment of the dual-mode neuromorphic device integrates the main transistor M1 and the control transistor M2 on the same common substrate. Through the structural design of deep N-well and shallow P-well regions, reliable electrical isolation between the floating body region of the main transistor M1 and the P-type semiconductor substrate is achieved, constructing a precisely controllable floating body region. Combined with the dual-transistor collaborative control architecture, the device combines structural simplicity with functional flexibility, providing high-performance core device support for the practical application and large-scale deployment of neuromorphic computing systems.

[0039] It should be noted that the core working mechanism and dual-transistor collaborative control architecture of the PMOS dual-mode neuromorphic device are basically the same as those of the aforementioned NMOS device, with the only difference being the inversion characteristics in substrate type, doping polarity, voltage direction, and carrier type. Specifically, the PMOS dual-mode neuromorphic device integrates the main transistor M1 and the control transistor M2 on the same N-type semiconductor substrate. Through the structural design of deep P-well and shallow N-well regions, reliable electrical isolation between the floating body region of the main transistor M1 and the N-type semiconductor substrate is achieved, constructing a precisely controllable floating body region. This allows for flexible selection based on actual circuit design requirements, providing diversified high-performance core device support for the diversified integration, practical application, and large-scale deployment of neuromorphic computing systems.

[0040] Example 2 Combination Figure 2 As shown, this embodiment provides a reconfigurable synaptic neuromorphic array. Taking a 4×4 array of neuromorphic devices as an example, the specific description is as follows: the first direction of the array is the column direction, and the second direction is the row direction. This reconfigurable synaptic neuromorphic array is constructed based on the aforementioned dual-mode neuromorphic device, possessing high configurability and high-density integration characteristics. The circuit connections and collaborative control logic of each neuromorphic device's operating mode are as follows: The second gate electrode 16 of the main transistor M1 of each column of neuromorphic devices is connected to the corresponding word line WL, and the word line WL controls the opening and relationship of the main transistor M1 of the corresponding column; the second drain region 15 of the main transistor M1 of each row of neuromorphic devices is connected to the corresponding bit line BL, and its second source region 14 is connected to the corresponding source line SL; the first gate electrode 24 of the control transistor M2 of each column of neuromorphic devices is connected to the corresponding mode control voltage line. The mode control voltage line adopts an independent wiring design, which can realize the independent control of the working mode of each column of neuromorphic devices in the array and support the configuration of modes column by column; the first source region 22 of the control transistor M2 of each column of neuromorphic devices is grounded, and its first drain region 23 is electrically connected to the body contact region 17 of the corresponding main transistor M1, forming a complete mode control link.

[0041] Specifically, the second gate electrode 16 of the main transistor M1 of the first neuromorphic device is connected to the first column word line WL1, the second gate electrode 16 of the main transistor M1 of the second neuromorphic device is connected to the second column word line WL2, the second gate electrode 16 of the main transistor M1 of the third neuromorphic device is connected to the third column word line WL3, and the second gate electrode 16 of the main transistor M1 of the fourth neuromorphic device is connected to the fourth column word line WL4. The second drain regions 15 of the main transistors M1 in the first row of neuromorphic devices are connected to the first row bit line BL1, and their second source regions 14 are connected to the first row source line SL1. The second drain regions 15 of the main transistors M1 in the second row of neuromorphic devices are connected to the second row bit line BL2, and their second source regions 14 are connected to the second row source line SL2. The second drain regions 15 of the main transistors M1 in the third row of neuromorphic devices are connected to the third row bit line BL3, and their second source regions 14 are connected to the third row source line SL3. The second drain regions 15 of the main transistors M1 in the fourth row of neuromorphic devices are connected to the fourth row bit line BL4, and their second source regions 14 are connected to the fourth row source line SL4. The first gate electrodes 24 of the control transistors M2 in the first to fourth columns of neuromorphic devices are respectively connected to the dedicated mode control voltage lines of each column, enabling independent mode control for each column of devices.

[0042] The word line WL and the mode control voltage line are configured to apply control signals synchronously to collaboratively control the operating mode of the target neuromorphic device selected by both the word line WL and the mode control voltage line. When the mode control voltage line applies a voltage less than a first preset threshold, in conjunction with the gating signal of the word line, the target neuromorphic device operates in synaptic mode to perform synaptic weight updates, reads, or simulated multiply-accumulate operations. When the mode control voltage line applies a voltage greater than a second preset threshold, in conjunction with the gating signal of the word line WL, the target neuromorphic device operates in neuron mode to perform neuronal leakage-integration-ignition pulse firing operations. The first preset threshold is 0.2V, the second preset threshold is 0.8V, and the second preset threshold is greater than the first preset threshold.

[0043] The working process of this reconfigurable synaptic neuromorphic array is divided into a configuration phase and a computation phase. The specific operations of each phase are as follows: Configuration phase: The mode control voltage Vg2 is applied to the mode control voltage line of the array. According to the actual computing task requirements, the working mode of each column of neuromorphic devices in the array is precisely set. After the mode configuration is completed, the computing phase can be entered. The configuration process can be completed in nanoseconds and supports dynamic reconfiguration at runtime.

[0044] Computation phase: The array executes the corresponding operations for the neuron and synapse columns according to the configured working mode, as follows: Neuron row operation: The input pulse is applied to the neuron unit through the bit line BL. The neuron unit integrates the input pulse. When the integrated voltage exceeds the critical threshold voltage, the pulse is transmitted to the next layer of synaptic row through the source line SL. The typical firing delay of this neuron row operation is <100ns, and it supports pulse frequencies up to MHz, which can meet the needs of high-speed computing.

[0045] Synaptic array operation: The input voltage is applied to the synaptic unit through the bit line BL. The synaptic unit outputs a corresponding current to the source line SL according to its own conductance value (corresponding to the synaptic weight). The output currents of multiple synaptic units can be simulated and accumulated on the source line SL to complete the vector-matrix multiplication and addition operation. The conductance state of the synaptic unit can be programmed to at least 16 levels (4-bit precision), and the multiplication and addition (MAC) operation accuracy reaches ±5%, ensuring the accuracy of the calculation.

[0046] In summary, this embodiment of the reconfigurable synaptic neuromorphic array, constructed as an M×N array architecture based on the aforementioned dual-mode neuromorphic devices, achieves multiple breakthroughs in integration density, functional flexibility, computational performance, and system power consumption through optimized circuit interconnect design, synchronous mode control logic, and phased workflow design. Firstly, the array uses a single dual-transistor device as the basic unit, abandoning traditional redundant structures. Combined with the orderly routing of word lines, bit lines, and mode control voltage lines, it significantly improves chip area utilization and possesses beneficial high-density integration characteristics, adapting to the integration requirements of large-scale neural networks. Secondly, through the collaborative addressing mechanism of word lines and mode control voltage lines, target devices can be precisely selected and column-by-column independent configuration of operating modes can be achieved. This supports nanosecond-level dynamic switching of synaptic and neuron modes and allows for flexible adjustment of the operating modes of each column according to the computational needs of different neural network layers and the design requirements of hybrid computing architectures. This enables adaptation to diverse neuromorphic computing tasks and effectively solves the technical problems of traditional arrays having fixed functions and poor scenario adaptability. Third, by adopting a bit-line input and source-line output signal transmission method, the pulse output of a neuron row can be directly transmitted to the next layer of synapse rows through the source line, realizing direct cascading within the array. This significantly reduces the delay and loss of signal transmission across modules, improving the array's signal transmission efficiency and cascading scalability. Fourth, the array adopts a phased workflow of "configuration + computation," with clear control logic and no need for complex external control circuits. The coordinated control of word lines, bit lines, and mode control voltage lines can achieve device selection and mode switching solely through voltage signals, effectively reducing the system's design complexity and operating power consumption.

[0047] It should be emphasized that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any way. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention shall still fall within the scope of the technical solution of the present invention.

Claims

1. A neuromorphic device, characterized in that, It includes a dual-transistor unit that can switch between synaptic and neuron modes, the dual-transistor unit consisting of a main transistor M1 and a control transistor M2; The control transistor M2 includes: P-type semiconductor substrate; The first source region and the first drain region of the N-type are formed alternately on the upper surface of the P-type semiconductor substrate; The first gate electrode is formed on the upper surface of the P-type semiconductor substrate between the first source region and the first drain region through a first gate insulating film; The main transistor M1 includes: A deep N-well region is formed inside the P-type semiconductor substrate; A P-shaped floating body region is formed on the upper surface of the deep N-well region; A shallow P-well region is formed around the periphery of the floating body region. The P-type doping concentration of the shallow P-well region is higher than that of the floating body region. Together with the deep N-well region, the floating body region is electrically isolated from the P-type semiconductor substrate. The second source region and the second drain region of the N-type are formed alternately on the upper surface of the floating body region; The second gate electrode is formed on the upper surface of the floating body region between the second source region and the second drain region through a second gate insulating film; A body contact region is formed on the upper surface of the shallow P-well region. The body contact region is electrically connected to the first drain region of the control transistor M2, and the first source region of the control transistor M2 is connected to a reference potential. The neuromorphic device is configured to control the switching between synaptic and neuron modes by applying a mode control voltage to the first gate electrode to adjust the equivalent resistance of the floating body region.

2. The neuromorphic device according to claim 1, characterized in that, The bulk contact region is a heavily doped P-type doped region.

3. The neuromorphic device according to claim 1, characterized in that, When the mode control voltage is less than the first preset threshold, the equivalent resistance increases, and the neuromorphic device operates in the synaptic mode; In the synaptic mode, the main transistor M1 is configured as follows: In response to a positive voltage pulse applied to the second drain region of the main transistor M1, its threshold voltage decreases and its channel conductance increases, resulting in a long-term enhancement of the synaptic weight. In response to a negative voltage pulse applied to the second drain region of the main transistor M1, its threshold voltage increases and its channel conductance decreases, corresponding to long-term suppression of synaptic weights.

4. The neuromorphic device according to claim 3, characterized in that, The floating body region is configured as follows: Based on the voltage pulse applied to the second drain region, different numbers of stable charge states are accumulated, corresponding to multi-level distinguishable channel conductance, to simulate multi-level synaptic weights.

5. The neuromorphic device according to claim 3, characterized in that, When the mode control voltage is greater than the second preset threshold, the equivalent resistance decreases, and the neuromorphic device operates in the neuron mode; wherein, the second preset threshold is greater than the first preset threshold; In the neuron mode, the charge in the floating body region is dynamically discharged through an equivalent resistance to simulate the leakage-integration-ignition behavior of a neuron.

6. The neuromorphic device according to claim 1, characterized in that, It also includes several shallow trench isolation regions, each of which is formed on the periphery of the body contact region, the second source region and the second drain region of the main transistor M1, and the first source region and the first drain region of the control transistor M2, to achieve electrical isolation between the active regions of the body contact region, the main transistor M1 and the control transistor M2.

7. The neuromorphic device according to claim 6, characterized in that, The body contact area shares the same shallow trench isolation area on the same side as the main transistor M1.

8. The neuromorphic device according to claim 5, characterized in that, The first preset threshold is 0.2V, and the second preset threshold is 0.8V.

9. A reconfigurable synaptic neuromorphic array, characterized in that, It includes multiple neuromorphic devices arranged in an array, wherein the neuromorphic devices are the neuromorphic devices as described in any one of claims 1-8; The second gate electrode of the main transistor M1 of each of the neuromorphic devices arranged along the first direction is connected to the corresponding word line. The second drain regions of the main transistors M1 of each of the neuromorphic devices arranged along the second direction are connected to the corresponding bit lines, and the second source regions are connected to the corresponding source lines. The first gate electrode of each of the neuromorphic devices arranged along the first direction is connected to the corresponding mode control voltage line, and the first source region is connected to the reference potential line. The first direction and the second direction are intersected.

10. The reconfigurable synaptic neuromorphic array according to claim 9, characterized in that, The word line and the mode control voltage line are configured to apply control signals synchronously to collaboratively control the operating mode of the target neuromorphic device selected by the word line and the mode control voltage line.

Images