Cmos-compatible graphene structures, interconnects, and methods of fabrication

Abstract

The invention relates to CMOS compatible graphene structures, interconnects and methods of manufacture. MLG (multi-layer graphene) device layer structures are connected with vias. The structure includes an M1 MLG interconnect device layer on a dielectric layer. An interlayer dielectric separates the M1 MLG interconnect device layer. An M2 MLG interconnect device layer is on the interlayer dielectric. A metal via penetrates the M2 MLG interconnect device layer, the interlayer dielectric and the M1 MLG interconnect device layer and forms an edge contact through the thickness of the M1 MLG and M2 MLG layers. A method of forming MLG layers by diffusion of carbon from a solid phase graphene precursor through a catalyst layer to deposit MLG on a dielectric or metal layer via application of mechanical pressure at a diffusion temperature.

Description

[0001] This application is a divisional application of patent application No. 202180077379.4, filed on December 1, 2021, entitled "CMOS Compatible Graphene Structure, Interconnector and Manufacturing Method".

[0002] Statement of Government Interests

[0003] This invention was made with government support under contract number W911NF-18-1-0366 granted by the U.S. Army Research Office. The government holds certain rights to this invention.

[0004] Priority claims and citations of related applications

[0005] Pursuant to 35 USC §119 and all applicable laws and treaties, this application claims priority to the prior U.S. Provisional Application Serial No. 63 / 123,587, filed on December 10, 2020. Technical Field

[0006] The field of this invention is semiconductor devices and their manufacture. In particular, this invention relates to interconnects (interconnects) and the formation of interconnects in integrated circuits (ICs). Background Technology

[0007] Interconnects are critical components in all ICs. They are the conductive paths that connect numerous transistors in digital, analog, or radio frequency (RF) ICs, and are key factors determining their performance (speed), energy conversion (power), and reliability (lifetime). The semiconductor industry currently uses copper (Cu) as the primary interconnect metal in most ICs, including various microprocessors. However, with scaling, the resistivity of Cu increases significantly due to the "size effect" (increased grain boundary and surface scattering, and the influence of arbitrarily high-resistivity barrier layers that are difficult to thin), leading to increased self-heating and reduced current carrying capacity (or reliability). (K. Banerjee et al., "Global (interconnect) warming," IEEE Circuits and Devices Magazine, Vol. 17, No. 5, pp. 16-32, 2001). Therefore, the industry has been searching for solutions to replace Cu with another type of interconnect that extends performance properties beyond Cu.

[0008] Cobalt (Co) has recently been introduced as a potential alternative to the narrowest Cu wires due to its higher melting point than Cu. When wiring dimensions approach sub-20 nm, conventional (i.e., bulk or 3D) conductors such as Cu, Co, and noble metals such as ruthenium (Ru) suffer from significant size effects, leading to a nonlinear increase in resistivity. This increases RC delay and self-heating (SH), reduces electromigration (EM) reliability, and thus limits their performance, current carrying capacity, and energy efficiency.

[0009] Graphene, particularly multilayer graphene (MLG) and doped multilayer graphene (DMLG), is a promising candidate to replace Cu due to its lower resistivity (for doped MLG) and significantly higher melting point than conventional metals including Cu and Co. Graphene belongs to the broader family of two-dimensional (2D) van der Waals materials. (PAjayan, P. Kim, K. Banerjee, “Two-dimensional van der Waals materials,” Physics Today, 69, 9-38, 2016). Graphene is also an excellent barrier material for preventing the diffusion of Cu and other metals. Graphene can also be used as a seed layer for growing other electronic materials, including gallium nitride (GaN), and for fabricating various material heterostructures, including 2D-2D or 3D-2D structures, for a wide range of micro / nanoelectronic applications.However, back-end process (BEOL) CMOS process compatibility is crucial for using any form of graphene (including monolayer (1L), few-layer graphene (FLG), MLG, and DMLG) for interconnects (interconnects) and other BEOL structures in CMOS integrated circuits. These interconnects and other BEOL structures include barrier / capping layers for Cu (or other conventional metal) interconnects (K. Agashiwala, J. Jiang, K. Parto, D. Zhang, CH Yeh, K. Banerjee, “Demonstration of CMOS-compatible multi-level graphene interconnects with metal vias,” IEEE Transactions on Electron Devices, Vol. 68, No. 4, pp. 2083–2091, 2021), on-chip sensors (J. Kang, Y. Matsumoto, X. Li, J. Jiang, X. Xie, K. Kawamoto, M. Kenmoku, JH Chu, W. Liu, J. Mao, K. Ueno and K. Banerjee, "On-chip..."). Intercalated-graphene inductors for next-generation radio frequency electronics, *Nature Electronics*, 1 (1), 46-51, 2018, or for monolithic-3D integration (Jiang, K. Parto, W. Cao, and K. Banerjee, “Ultimate monolithic-3D integration with 2D materials: Rationale, prospects, and challenges,” IEEE Journal of the Electron Devices Society, Vol. 7, pp. 878-887, 2019). Monolayers or FLGs can also be used as canvas layers for the regionally selective fabrication of low-contact-resistance lateral heterojunction transistors (graphene-2D-semiconductor-graphene) and other active devices.CH. Yeh, W. Cao, A. Pal, K. Parto, and K. Banerjee, “Area-selective-CVD technology enabled top-gated and scalable 2D-heterojunction transistors with dynamically tunable schottky barrier,” IEEE International Electron Devices Meeting (IEDM), San Francisco, December 7-11, 2019, pp. 23.4.1-23.4. FLG can also be used to construct highly transparent electrodes for solar cells and other optical devices. W. Liu, J. Kang and K. Banerjee, “Characterization of FeCl3 intercalation doped CVD few-layer graphene,” IEEE Electron Device Letters, Vol. 37, No. 9, pp. 1246-1249, September 2016. Previous efforts sought to make graphene compatible with CMOS structures, but suffered from several drawbacks discussed below.

[0010] Two prior publications disclosed simulation results demonstrating that graphene nanoribbons can outperform Cu interconnects through intercalation (embedding) doping. The proposed doping methods are impractical for CMOS fabrication because they rely on impractical (toxic) AsF5 doping. These publications are: Banerjee et al., “Graphene nano-ribbon (GNR) interconnects: A genuine contender or a delusive dream,” IEDM Technical Digest, pp. 201-204, 2008; Banerjee et al., “Modeling, analysis and design of graphene nano-ribbon interconnects,” IEEE TED, Vol. 56, No. 8, pp. 1567-1578, 2009.

[0011] Another publication discloses the CVD growth of doped graphene interconnects from transferred graphene at 900 °C–1100 °C. High-temperature CVD and transfer are incompatible with state-of-the-art IC fabrication processes. This publication is by Banerjee et al., “Intercalation doped multilayer-graphene-nanoribbons for next generation interconnects,” Nano Letters, Vol. 17, No. 3, pp. 1482–1488, 2017.

[0012] Others have proposed forming mechanical exfoliation to create graphene nanoribbon interconnects. Exfoliation is not suitable for large-scale fabrication. Furthermore, the nanoribbons are undoped, thus providing conductivity that is not comparable to current Cu interconnects. This exfoliation method is disclosed in Meindl et al., “Resistivity of graphene nanoribbon interconnects,” IEEE Electron Device Letters, Vol. 30, No. 6, pp. 611-613, 2009.

[0013] U.S. Patent No. 8,952,258 discloses a wound graphene tape carried around a conductive interconnect component. The carrier is a metal. This is a hybrid structure requiring a metal component and is unlikely to match the conductivity of Cu because conductivity is limited by the contact resistance between graphene and the metal. The current-carrying capacity of any such hybrid structure is also limited by the relatively low melting point of the metal component.

[0014] U.S. Patent No. 9,257,391 also discloses a hybrid metal-graphene interconnect structure. This interconnect also requires a barrier layer in the trenches. The barrier material is selected from tantalum, tantalum nitride, and graphene seed materials selected from ruthenium, nickel, palladium, iridium, and copper. The same disadvantages discussed in the previous paragraph also apply.

[0015] U.S. Patent No. 9,159,615 discloses graphene interconnects requiring an underlying catalyst film and interconnect trenches. The disclosed manufacturing method includes a high-temperature (>800°C) graphene growth process that is incompatible with CMOS BEOL processes.

[0016] U.S. Patent No. 9,202,743 discloses a graphene connector in a trench lined with a Ru or Ta liner, together with a filler metal in elemental form or an alloy comprising one or more of copper, aluminum, silver, gold, calcium, platinum, tin, lithium, zinc, nickel, and tungsten. The graphene formation process is low-temperature CVD, which is known to produce low-quality graphene.

[0017] U.S. Patent No. 9,209,136 discloses a hybrid metal / graphene interconnect. Graphene is formed on a metal such as copper (Cu), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt), or palladium (Pd). Growing graphene on a metal surface requires high temperatures (incompatible with CMOS BEOL).

[0018] U.S. Patent No. 9,761,532 also discloses a hybrid metal-graphene interconnect structure. The hybrid structure includes an interfacial bonding layer between a non-metallic material layer and a graphene layer, or between a metal layer and a graphene layer. The disclosed process is a high-temperature graphene growth process (>700°C) limited to a few memory device applications. The same disadvantages discussed above regarding hybrid methods also apply.

[0019] U.S. Patent No. 10,079,209 discloses a method for manufacturing graphene films. In this method, a catalyst metal film is formed on a substrate. A graphene film is formed on the catalyst metal film. The metal catalyst film is removed via an oxidant. The graphene film is then transferred onto the substrate. This transfer process is incompatible with CMOS fabrication and can increase film defect density and overall manufacturing cost.

[0020] Jiang et al., “CMOS-compatible doped-multilayer-graphene interconnects for next-generation VLSI,” 2018 IEEE International Electron Devices Meeting (IEDM), described a method for forming MLG graphene interconnects in a single device layer. This method involves diffusing carbon from graphite powder through a nickel catalyst layer. The paper does not disclose any techniques for forming multiple device layers or interconnecting MLGs in different device layers. The use of graphite powder makes this process difficult to integrate in commercial CMOS fabrication fabs, where extremely small particle counts are a critical requirement. Secondly, it is difficult to bring arbitrary powders into fully automated commercial tools.

[0021] Figure 1 A conventional dual damascene (DD) process is shown for forming a metal (wire)-via-metal (wire) structure. This process has been scaled down to a sub-20 nm linewidth. The structure suffers from the previously discussed “size effect,” which increases self-heating (SH), reduces electromigration (EM) reliability, and thus limits the interconnect current carrying capacity. Figure 3A and 3BThe diagram illustrates the current congestion and SH effect that occur when a via line contacts layer M1 at its bottom and layer M2 at its top. This is primarily due to current redistribution caused by the resistance of the edge contact (edge ​​contact) between the via and the metal line. Furthermore, void formation during the filling of highly scaled trenches and via holes during DD processes exacerbates reliability and variability issues. It should be noted that MLG lines cannot follow the DD process flow. As described in later sections, a subtractive etching (SE) process scheme must be used for MLG lines.

[0022] Representative publications attempting to use graphene [1-3] and other materials [4-6] for monolayer interconnects include: [1] J. Jiang et al., “Intercalation doped multilayer-graphene-nanoribbons for next-generation interconnects,” Nano Letters, 17(3), pp. 1482-1488, 2017; [2] J. Jiang et al., “CMOS-compatible doped-multilayer-graphene interconnects for next-generation VLSI,” IEEE IEDM, pp. 34.5.1-34.5.4, 2018; [3] J. Jiang et al., “Characterization of self-heating and current-carrying capacity of intercalation doped graphene-nanoribbon interconnects,” IEEE Int. ReliabilityPhysics Symp. (IRPS), 2017, pp. 6-B.1-6-B.6; [4] C.-K. Hu et al., “Future On-chip interconnect metallization and electromigration,” IEEE Int. Reliability Physics Symp. (IRPS), pp. 4F.1.1-4F.1.4, 2018; [5] SJ Yoon et al., “Largegrain ruthenium for alternative interconnects,” IEEE Electron Device Letters, Vol. 40, No. 1, pp. 91-94, 2019; [6] S. Dutta et al., “Sub-100 nm 2 “cobaltinterconnects,” IEEE Electron Device Letters, Vol. 39, No. 5, pp. 731-734, 2018. These processes [4-6] have achieved minor improvements in reducing resistivity and increasing current carrying capacity, but practical processes for fabricating multilayer MLGs with via interconnects for CMOS compatibility are still needed.

[0023] One publication discusses multilevel MLGs with carbon nanotube (CNT) vias. [8] J. Jiang, J. Kang, JH Chu and K. Banerjee, “All-carbon interconnect scheme integrating graphene-wires and carbon-nanotube-vias,” IEEE International Electron Devices Meeting (IEDM), San Francisco, December 2-6, 2017, pp. 14.3.1-14.3.4. Constructing carbon nanotube vias in this structure requires very high temperatures for non-CMOS compatible processes. Summary of the Invention

[0024] A preferred embodiment provides an MLG (multilayer graphene) device layer structure connected by vias. The structure includes an M1 MLG interconnect device layer on a dielectric layer. An interlayer dielectric separates the M1 MLG interconnect device layer. An M2 MLG interconnect device layer lies on the interlayer dielectric. Metal vias penetrate the M2 MLG interconnect device layer, the interlayer dielectric, and the M1 MLG interconnect device layer, forming edge contacts across the thickness of both the M1 and M2 MLG layers. The method involves directly growing MLG on the dielectric or metal layer by diffusing carbon from a solid-phase graphene precursor through a catalyst layer under mechanical pressure at a diffusion temperature. Attached Figure Description

[0025] Figure 1 (Prior art) illustrates a double damask (DD) process for conventional metal wires (as through holes);

[0026] Figure 2A-2C A preferred method for forming an MLG-Metalline Via-MLG structure in CMOS circuit fabrication using a subtractive etching process is shown;

[0027] Figure 3A and 3B (Prior art) illustrates the via layout and current density distribution for the M1-through-hole-M2 cross-section manufactured using a conventional double damask (DD) process; and

[0028] Figure 3C and 3D (Prior art) illustrates the via layout and current density distribution of an MLG-via-MLG cross section manufactured by a preferred subtractive etching (SE) process.

[0029] Figure 4A-B illustrates the method of the present invention for directly growing MLG on a metal substrate (e.g., Cu). Detailed Implementation

[0030] This invention provides multilayer graphene (MLG) and doped multilayer graphene structures, interconnects, and methods for fabricating MLG and DMG interconnects. In a preferred embodiment, MLG is grown directly on a dielectric (SiO2) substrate in a practical multilayer configuration at CMOS-compatible temperatures (e.g., 350°C) using a pressure-assisted solid-state precursor synthesis method, and is connected using metal vias to achieve edge contact between the MLG and the vias in a process that meets the thermal budget requirements of all processed ICs.

[0031] This invention provides a method for connecting an MLG with an “edge contact” configuration, which is the optimal way to connect to the MLG to minimize interface contact resistance, thereby minimizing the overall via resistance. This translates to faster signal propagation and clock distribution within the chip, and significantly lower resistive losses (IR drop) during on-chip power distribution.

[0032] Unlike Cu wires, which must be completely encapsulated by a high-resistivity refractory metal (which increases process complexity, cost, and the effective resistivity of the Cu wire), in the preferred manufacturing method, neither the wire (MLG or doped MLG) nor the metal via is required to have any diffusion barrier layer, since there is no carbon diffusion through any metal or dielectric.

[0033] The preferred growth technique currently shows ~10 mm 2 The uniform, large coverage area allows for easy scaling to 8-inch or 12-inch wafers / substrates. This demonstrates the significant potential of this process approach for direct integration into current CMOS processes.

[0034] Preferred methods (also demonstrated with some modifications) can also be used to grow MLG directly on metal substrates such as Cu. This can be used to explore the potential benefits of using MLG as a barrier / capping layer for Cu (and other metals), eliminating the need for highly refractory metals (which increase the effective resistivity of Cu interconnects as well as cost and process complexity).

[0035] Preferred multilevel MLG interconnects with through-hole structures exhibit <2% conductivity degradation over 1000 hours at room temperature without any encapsulation or barrier layers, and maintain 200 MA / cm at >100°C. 2Negligible electromigration (EM) (a typical reliability issue in interconnects) under current density stress (~50 times higher than that that nanoscale Cu can safely maintain). This makes this via approach the most reliable process for contacting transistors among all currently available materials and processes.

[0036] Compared to conventional dual-Damasc process solutions, the significantly higher current-carrying capacity of the preferred multi-level MLG interconnect structure allows for a significant reduction in MLG thickness, resulting in lower in-line capacitance. This significantly improves speed in ICs, reduces noise coupling, and lowers conversion energy or power consumption. This potential for power reduction in MLG interconnects is particularly important because up to two-thirds of the power consumption in modern microprocessors can be attributed to interconnect capacitance. The preferred interconnect structure of this invention enables faster, smaller, lighter, more flexible, more reliable, more energy-efficient, and more cost-effective ICs.

[0037] In the preferred method, MLG is grown directly on a dielectric (SiO2) substrate at 350°C in a multilayer configuration via pressure-assisted solid-phase diffusion and connected using metal vias, while meeting the thermal budget requirements of all IC processes.

[0038] The preferred approach is to connect the MLG with an "edge contact" configuration, which is the optimal way to connect the MLG to minimize interface contact resistance, and thus minimize the overall via resistance. This translates to faster signal propagation and clock distribution within the chip, and significantly lower resistive losses (IR drop) during on-chip power distribution.

[0039] Unlike Cu wires, which must be completely encapsulated by a high-resistivity refractory metal (which increases process complexity, cost, and the effective resistivity of the Cu wire), the preferred method avoids carbon diffusion through any metal or dielectric, and neither the wire (MLG or doped MLG) nor the metal via requires any diffusion barrier layer.

[0040] The preferred method was demonstrated experimentally to be ~10 mm 2 It provides uniform, large coverage, which can be easily scaled up to 8-inch or 12-inch wafers / substrates. This demonstrates that the method can be directly integrated into current state-of-the-art CMOS processes.

[0041] Preferred methods (as demonstrated experimentally) allow for the direct growth of MLG on metal substrates such as Cu. One application of this method is the use of MLG as a capping layer for Cu, eliminating the need for highly refractory metals (which increase the effective resistivity of Cu interconnects, as well as cost and process complexity).

[0042] Preferred device structures with multi-level MLG interconnects featuring metal vias exhibit <2% conductivity degradation over 1000 hours at room temperature without any encapsulation or barrier layers, and maintain 200 MA / cm at >100°C. 2 Negligible electromigration (EM) (a typical reliability issue in interconnects) under current density stress (~50 times higher than that that nanoscale Cu can safely maintain). This via structure significantly surpasses the most reliable current processes for contacting transistors using all currently available materials and processes.

[0043] Compared to conventional structures, the preferred multi-level MLG interconnect via structure offers significantly higher current carrying capacity. This allows for a significant reduction in MLG thickness compared to conventional dual-damasc process solutions, resulting in lower in-line capacitance. This significantly improves speed in ICs, reduces noise coupling, and lowers power consumption. The current multi-level MLG interconnect via structure's power consumption reduction is particularly important because up to two-thirds of the power consumption in modern microprocessors can be attributed to interconnect capacitance.

[0044] Preferred embodiments utilize different solid-phase graphene precursors. One solid-phase precursor is graphite powder. Another solid-phase precursor is graphite slurry. A further solid-phase graphite precursor is an amorphous carbon (a-carbon) layer. For high-volume CMOS fabrication, the method using deposited a-carbon layers offers significant advantages over graphite powder and graphite slurry.

[0045] The experiment deposited MLG on SiO2, a preferred and widely used dielectric. However, the method of the present invention for forming MLG can form MLG on dielectrics with any acceptable thermal requirements (~350-400°C).

[0046] Preferred embodiments of the invention will now be discussed in conjunction with experiments and accompanying drawings. In view of common knowledge in the art and the subsequent description of experiments, a broader understanding of the invention will be apparent to those skilled in the art.

[0047] Figure 2A-2B A preferred method for growing graphene directly on a dielectric at CMOS processing temperatures is shown, and Figure 2C A preferred method for forming an MLG-via-MLG structure is shown, wherein the MLG-via-MLG structure has edge contact between a metal via and two connected MLG layers. Figure 2A-2B The process in this technology can reliably grow large-area, uniform, and high-quality MLG at multiple levels (in multi-stages), and Figure 2CThe process connects multiple levels to edge-contact metal vias. Uniform MLG can be patterned into interconnect patterns (interconnect body patterns) via conventional mask etching techniques. For example, experiments have shown that MLG layers are patterned using a metal mask via oxygen ICP etching, which is then removed by wet etching.

[0048] exist Figure 2A In the first step, 20, the silicon dioxide layer on the silicon substrate is cleaned. SiO2, for example, 200 nm, will be used as the interlayer dielectric in the MLG-via-MLG structure to be formed. In step 22, a metal or alloy catalyst, such as nickel, is deposited. Other metals and alloys, such as Co, Fe, Cu, and Co-Ni alloys, can also be used for graphene growth. However, the thickness, quality, and area coverage of the resulting graphene are key factors (functions) in the selection of the metal catalyst. Nickel is the most likely and preferred choice. In the experiment, it was evaporated via electron beam at approximately 3 x 10⁻⁶ Å. -6 A 100 nm thick Ni layer is deposited under the chamber pressure of the Torr chamber. Thicknesses in the range of ~50 nm to ~200 nm can also be used. Generally, a higher metal catalyst thickness reduces the thickness of the resulting MLG layer, while a lower metal catalyst thickness increases the thickness of the resulting MLG (for the same growth time), because carbon atoms need to diffuse through the grains and grain boundaries of the metal catalyst and nucleate at the Ni / SiO2 interface. Low-temperature annealing (at temperatures below 450 °C, for example ~350 °C) for 2 hours in an H2 / Ar environment improves the quality of the deposited metal catalyst (Ni). Annealing can be performed in vacuum, Ar, H2, N2, O2, or a forming gas, but a combination of H2 / Ar is preferred because the presence of H2 with an inert Ar background helps to significantly improve metal quality (by increasing the metal grain size). Annealing just before the actual growth step significantly improves coverage and growth quality. Annealing is preferably performed at the same temperature used for other steps to not only reduce overall process complexity but also meet the thermal budget requirements of CMOS BEOL. The next step, 24, involves depositing a solid-phase graphene precursor, and as... Figure 2AThe three options shown are specifically, an amorphous carbon option, a graphene slurry option, and a graphene powder option. The powder can be uniformly sprinkled onto a wafer approximately 100 µm thick. In the experiment, amorphous carbon (~10-15 nm thick) was deposited via electron beam (E-beam) evaporation, which is the same technique used to deposit Ni metal catalysts. Typically, the relationship between the thickness of the amorphous carbon precursor and the thickness of the resulting MLG film is a function of the supersaturated concentration of carbon in the selected catalyst. A 1:1 ratio between the amorphous carbon film thickness and the resulting MLG thickness provides a reasonable guideline. The slurry is a solution of organic solvent and graphite powder, which can be uniformly distributed on the wafer and heated to evaporate the organic solvent. The resulting film is approximately ~10-20 nm thick.

[0049] This process is in Figure 2B Step 26 continues, where the formed graphene precursor is subjected to pressure and temperature sufficient to cause carbon diffusion through the Ni catalyst and form a graphene layer on SiO2. As an example, a mechanical pressure of ~65-80 psi is applied at a temperature of at least about 350°C for about 60 minutes to produce ~20 nm multilayer graphene (MLG). The mechanical pressure can be further increased for arbitrary graphene growth optimization. The minimum temperature for diffusion can be as low as ~200°C. The maximum temperature for attempting to complete diffusion can be as high as ~1000°C. However, CMOS compatibility requires the maximum temperature to be below 500°C. Then, oxygen cleaning in step 28 removes any excess graphene precursor, and then the metal catalyst is etched away in step 30 to leave a high-quality graphene layer on SiO2. Subtractive etching is performed in step 32 to pattern the MLG interconnects.

[0050] Figure 2C The process described in the text can be used to produce bottom 40 and top 42 MLG layers (which may be referred to as M1 and M2), which can also be patterned using conventional mask etching techniques. The M140 and M2 layers 42 are based on... Figure 2A-2B The process is performed directly on dielectric layers, such as SiO2 layers 44 and 46. Plasma-enhanced chemical vapor deposition (PECVD) is used in experiments for depositing SiO2, but the dielectric can be formed by any other technique. A dielectric with uniform coverage and thickness is typical, but the method of this invention is versatile enough to form MLGs on arbitrary surface topologies. An additional dielectric layer 48 may form part of the interconnect pattern of the M2 MLG layer 42. In step 50, dielectric layer 46 is formed as an intermediate dielectric layer, and as... Figure 2A-2BThe process is as described above for forming the top MLG M2 layer 42, followed by the formation of the additional dielectric 48. In step 52, an opening 54 is created through the layer down to the dielectric layer 44. In step 56, metal is deposited in the opening 54 to form a via 58, which advantageously allows the edge to contact the entire thickness of each of the bottom MLG M1 layer 40 and the top MLG M2 layer 42.

[0051] Several metals can be used for via 58. Density functional theory (DFT) simulations of Co, Ru, and W show that they have almost the same edge contact resistance as MLG. However, Co's higher activation energy and lower resistivity compared to Ru and W mean that it has greater tolerance to EM (electromigration) and SH (self-heating), making it a better choice and preferred metal for via 58 in multi-level MLG line-via structures.

[0052] This edge contact avoids current congestion at the top and bottom contacts. Figure 3A and 3B ),like Figure 3C and 3D As shown in the image. Compared to conventional DD processes, the edge contact structure exhibits a significant reduction in current congestion and SH effects, primarily due to current redistribution caused by the edge contact resistance between the via and the MLG line, as illustrated in... Figure 3B and 3D As shown in the figure. Compared to SE-Co and Ru, MLG offers higher conductivity and EM resistance, especially at smaller aspect ratios. Therefore, although the added edge contact resistance between MLG and the metal via increases the total via resistance, tests show that the FO4 delay remains constant relative to the (wrt) total via resistance.

[0053] The quality and via properties of the MLG layer were experimentally tested. Sharp G and 2D peaks were observed in the single-point Raman spectroscopy data. TEM images verified the uniform, high-quality growth. The top MLG M242 fabricated on the interlayer dielectric (ILD) 46 exhibited comparable quality and thickness to the bottom MLG 40, as evidenced by the experimentally observed single-point Raman spectra and uniform large-area Raman plots. XPS was used to determine the C1 content in the bottom MLG film, revealing precise peak positions (1202.3 eV) and atomic composition (~83%) corresponding to the C=C sp2 bonds, which can also be observed in conventionally CVD-grown MLGs. This confirms the high-quality growth of solid-phase MLGs without requiring the high and CMOS-incompatible temperatures (>800 °C) required for CVD-grown MLGs.

[0054] and Figure 2A-2CConsistent experimental fabrication demonstrated a two-stage SE (subtractive etch)-MLG interconnect structure using Co-doped vias, where a single damask process (single embedding process) was used to etch the vias through the wires and ILD. For both stages, the experimental structures comprised 20 nm thick MLG layers. Although unintentional, the use of FeCl3 solution in step 30 to remove the Ni catalyst provided surface doping of Fe at both the top and bottom MLG surfaces, which reduced the MLG resistivity. Via resistance was measured, and for the 20 nm thick Co-MLG edge contact, the minimum contact resistance was estimated to be 137 Ω-µm. This value also confirms the claim of partial surface doping of the MLG by FeCl3, as it falls between the theoretically estimated (by DFT) edge contact resistance values ​​for both Co-doped and undoped MLG. Constant current stress testing showed that the via-induced resistance increase was <2% over >40 hours, indicating negligible EM in the Co-doped vias and / or at the Co-MLG contacts.

[0055] Figures 4A-4B A preferred method for directly forming MLG on a Cu layer is shown. In step 60, a stack comprising SiO2 is formed on a silicon substrate, followed by a Cu layer, a thin amorphous carbon barrier layer, a nickel catalyst layer, and a solid-phase graphene precursor, which may be as follows: Figure 2A The graphite powder (as shown), amorphous carbon, or graphite slurry shown in the figure. The thin amorphous carbon layer prevents the Cu and Ni layers from interdiffusion and assists the graphene growth process by acting as an additional source of readily available carbon at the Cu interface, and is completely consumed during MLG growth. In step 64, as shown in the figure... Figure 2B In step 26, mechanical pressure is applied to induce carbon diffusion through the Ni catalyst and form a graphene layer on Cu. After the graphene layer forms, as... Figure 2B As shown in steps 28 and 30, any residual graphite or α-carbon on the nickel is cleaned, followed by nickel etching. Cleaning is performed using O2 plasma to remove any graphite formed on the Ni substrate. Ni etching removes the Ni catalyst metal layer via wet etching using a FeCl3 solution, but other material removal processes, including dry etching, can also be used. Subsequently, the MLG layer is etched via a subtractive process (e.g., a process using oxygen plasma to form the MLG interconnect). The MLG can be doped using various methods to modulate conductivity.

[0056] Experiments were also conducted to verify this. Figures 4A-4BThe method involved forming a 300 nm SiO2 layer on a Si wafer, upon which a 100 nm Cu, 2 nm amorphous carbon, and 100 nm Ni layer were deposited via electron beam deposition. A graphite precursor, such as 100 µm graphite powder, was then uniformly applied onto the resulting stack. Raman spectroscopy revealed the formation of high-quality MLG grown directly on Cu at ~350 °C, which was also confirmed by the layered structure visible in TEM images. In other experiments, patterned interconnect MLG layers contacting the edges of metal vias, as discussed above, were also formed. In example experiments, such as… Figure 2A-2B The bottom MLG is grown as described above, and then patterned with a metal mask via oxygen ICP etching, which is subsequently removed by wet etching. A 200 nm thick SiO2 ILD is deposited after defining contacts and pads (15 nm Ni / 150 nm Au) to connect the bottom MLG. The top MLG is patterned to form an area overlapping the bottom MLG, and then contacts and pads for the top MLG are patterned. Vias (ranging in width from 200 nm to 2 µm) are opened via three steps of oxygen-, CHF3-, and oxygen-ICP to etch the top MLG, ILD, and bottom MLG separately using a photoresist mask. The vias are filled at a slow deposition rate by thermal evaporation (<100°C) to deposit a ~220 nm thick Co layer, ensuring complete metal filling. Finally, the ILD on top of the bottom pads is etched to allow electrical contact. More advanced lithography techniques known in the art can be used to further scale the line / via width.

[0057] The present invention includes the following embodiments.

[0058] 1. A method for forming an MLG (multilayer graphene) device layer connected to vias directly on a dielectric or metal layer at CMOS (complementary metal-oxide-semiconductor) compatible process temperatures, comprising:

[0059] Provide a dielectric or metal layer;

[0060] A metal or metal alloy catalyst layer is deposited on the dielectric or metal layer;

[0061] Solid-phase graphene precursors are deposited on the catalyst layer; and

[0062] M1 MLG layer is formed by depositing MLG on the dielectric or metal layer by diffusing carbon from the graphene precursor through the catalyst layer by applying diffusion pressure at the diffusion temperature.

[0063] Remove the catalyst layer;

[0064] An interlayer dielectric is deposited on the M1 MLG layer;

[0065] An M2 MLG layer is formed on the interlayer dielectric by depositing a catalyst layer, depositing a solid-phase graphene precursor, and diffusing carbon.

[0066] Open a via through the entire M2 MLG, interlayer dielectric, and M1 MLG layers to form a via; and

[0067] Through-hole metal is deposited in the via to form an edge contact that extends through the thickness of both the M1 MLG layer and the M2 MLG layer.

[0068] 2. The method of claim 1, wherein the diffusion pressure is a pressure of ~65-80 psi and the diffusion temperature is at least about 200°C.

[0069] 3. The method described in any of the preceding items, wherein the graphene precursor is graphite powder.

[0070] 4. The method of any one of items 1-2, wherein the graphene precursor is amorphous carbon.

[0071] 5. The method of any one of items 1-2, wherein the graphene precursor is a graphite slurry.

[0072] 6. The method described in any of the preceding paragraphs, comprising annealing the catalyst at a temperature below 500°C prior to depositing the solid graphene precursor.

[0073] 7. The method described in any of the preceding items, wherein the through-hole metal is one of Co, Ru, and W.

[0074] 8. The method described in item 7, wherein the through-hole metal is Co.

[0075] 9. The method described in any of the preceding items, wherein the catalyst layer is Ni.

[0076] 10. The method described in any of the preceding items, wherein the dielectric layer and the interlayer dielectric comprise SiO2.

[0077] 11. A method for forming MLG (multilayer graphene) on a metal surface, the method comprising:

[0078] An amorphous carbon barrier layer is formed on the metal surface;

[0079] A metal or metal alloy catalyst layer is deposited on the amorphous carbon barrier layer;

[0080] Solid-phase graphene precursors are deposited on the catalyst layer; and

[0081] Carbon is diffused from the graphene precursor through the catalyst layer by applying diffusion pressure at a diffusion temperature to deposit MLG on the metal surface.

[0082] 12. The method of item 9, wherein the metal surface is Cu.

[0083] 13. The method of item 9 or 10, wherein the catalyst layer is Ni.

[0084] 14. The method described in item 1, wherein M1 MLG and M2 MLG layers are patterned and doped.

[0085] 15. An MLG (multilayer graphene) device layer structure connected to a through-hole, comprising:

[0086] M1 MLG interconnect device layer on the dielectric layer;

[0087] The interlayer dielectric separating the M1 MLG interconnect device layers;

[0088] The M2 MLG interconnect device layer on the interlayer dielectric; and

[0089] A metal via is formed through the M2 MLG interconnect device layer, the interlayer dielectric, and the M1 MLG interconnect device layer, with the metal via extending through the thickness of both the M1 MLG layer and the M2 MLG layer to form an edge contact.

[0090] 16. The device layer structure of item 15, wherein the M1 MLG layer and the M2 MLG layer are patterned.

[0091] 17. The device layer structure of claim 15 or 16, wherein the dielectric layer and the interlayer dielectric comprise SiO2.

[0092] 18. The device layer structure of any one of items 15-17, wherein the M1 MLG layer and the M2 MLG layer are doped.

[0093] While specific embodiments of the invention have been shown and described, it should be understood that other modifications, substitutions, and alternatives will be apparent to those skilled in the art. Such modifications, substitutions, and alternatives may be made without departing from the spirit and scope of the invention, as determined by the appended claims.

[0094] The various features of the present invention are set forth in the appended claims.

Claims

1. A method for forming an MLG multilayer graphene device layer connected to vias directly on a dielectric or metal layer at CMOS complementary metal-oxide-semiconductor compatible process temperatures, comprising: Provide a dielectric or metal layer; A metal or metal alloy catalyst layer is deposited on the dielectric or metal layer; The catalyst layer was annealed at a temperature below 500°C; And then A solid-phase graphene precursor is deposited on the catalyst layer; and M1 MLG layer is formed by depositing MLG on the dielectric or metal layer by diffusing carbon from the graphene precursor through the catalyst layer by applying mechanical diffusion pressure at the diffusion temperature. Remove the catalyst layer and any excess graphene precursor; Patterning, etching, and doping of the M1 MLG layer; An interlayer dielectric is deposited on the M1 MLG layer; An M2 MLG layer is formed on the interlayer dielectric by depositing a catalyst layer, annealing the catalyst layer, depositing a solid graphene precursor, and then diffusing carbon. Remove the remaining graphene precursor and catalyst layer; Patterning, etching, and doping of the M2 MLG layer; A via is formed by opening a via through the M2 MLG layer, the interlayer dielectric, and the M1 MLG layer; and Through-hole metal is deposited in the via to form an edge contact that extends through the thickness of both the M1 MLG layer and the M2 MLG layer.

2. The method of claim 1, wherein the diffusion pressure is ~10 -5 -10 5 The diffusion temperature is greater than 200°C and less than 500°C.

3. The method of any of the preceding claims, wherein the graphene precursor is graphite powder.

4. The method of any one of claims 1-2, wherein the graphene precursor is amorphous carbon.

5. The method of any one of claims 1-2, wherein the graphene precursor is a graphite slurry.

6. The method of any of the preceding claims, comprising annealing the catalyst layer and the solid graphene precursor directly after deposition of the solid graphene precursor at a temperature below 500°C.

7. The method of any of the preceding claims, wherein the through-hole metal is one of Co, Ru, and W.

8. The method of claim 7, wherein the through-hole metal is Co.

9. The method of claim 1, wherein the catalyst layer comprises Ni, Co or Cu.

10. The method of claim 1, wherein the dielectric layer and the interlayer dielectric comprise SiO2.

11. The method of claim 9, wherein the metal surface is Cu.

12. The method of claim 9 or 10, wherein the catalyst layer is Ni.

13. A method for forming MLG multilayer graphene on a metal surface, the method comprising: An amorphous carbon barrier layer is formed on the metal surface; A metal or metal alloy catalyst layer is deposited on the amorphous carbon barrier layer; A solid-phase graphene precursor is deposited on the catalyst layer; and Carbon is diffused from the graphene precursor through the catalyst layer by applying diffusion pressure at a diffusion temperature to deposit MLG on the metal surface.

14. The method of claim 13, wherein the diffusion pressure is ~10 -5 -10 5 The pressure is psi and the diffusion temperature is greater than 200°C and less than 500°C.

15. The method of claim 11, wherein the catalyst layer comprises Ni, Co, or Cu.

16. An MLG multilayer graphene device layer structure connected to a through-hole, comprising: M1 MLG interconnect device layer on the dielectric layer The M1 MLG interconnect device layer is patterned, etched, and doped. The interlayer dielectric separating the M1 MLG interconnect device layers, An M2 MLG interconnect device layer on the interlayer dielectric, wherein the M2 MLG interconnect device layer is patterned, etched, and doped; and A metal via is formed through the M2 MLG interconnect device layer, the interlayer dielectric, and the M1 MLG interconnect device layer, with the metal via penetrating the thicknesses of both the M1 MLG layer and the M2 MLG layer to form an edge contact.

17. The device layer structure of claim 16, wherein the through-hole metal comprises Co, Ru, or W.

18. The device layer structure of claim 16 or 17, wherein the dielectric layer and the interlayer dielectric comprise SiO2.

19. An MLG multilayer graphene device layer structure connected to a through-hole, comprising: M1 interconnect device layer on the dielectric layer The M1 interconnect device layer is patterned and etched; and The M1 interconnect device layer includes Cu, Co, or Ru; Interlayer dielectric on the M1 interconnect device layer; M2 MLG interconnect device layer on the interlayer dielectric, The M2 MLG interconnect device layer is patterned, etched, and doped; and A metal via is provided, passing through the M2 MLG interconnect device layer, the interlayer dielectric, and connected to the M1 interconnect device layer. The metal via extends through the thickness of the M2 MLG layer and the top surface to form an edge contact and / or form an edge contact with the M1 interconnect layer.

20. The device layer structure of claim 19, wherein the through-hole metal comprises Co, Ru, or W.

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