Method for reducing white pixels of a cmos image sensor
By doping nitrogen ions into CMOS image sensors and forming oxide-vacancy defect complexes, the problem of white pixels caused by metal impurity ions is solved, achieving a reduction in white pixels and an improvement in device performance, which is suitable for semiconductor integrated circuit manufacturing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUA HONG SEMICON WUXI LTD
- Filing Date
- 2022-11-30
- Publication Date
- 2026-06-05
AI Technical Summary
Existing technologies are difficult to effectively reduce white pixels in CMOS image sensors, especially in reducing metal impurity ion contamination. Traditional methods are prone to wafer thermal deformation and affect device performance.
The method to reduce white pixels by doping nitrogen ions into a polycrystalline silicon adsorption layer and forming an oxide-vacancy defect complex using an annealing process to promote the capture of metal impurity ions includes forming a sacrificial oxide layer, a polycrystalline silicon adsorption layer, ion implantation, and an annealing process.
It effectively reduces white pixels in CMOS image sensors, reduces metal impurity ion contamination, avoids wafer thermal deformation, improves device performance, and is suitable for a wide range of applications.
Smart Images
Figure CN115831995B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a method for reducing white pixels in CMOS image sensors. Background Technology
[0002] Currently, CMOS image sensor (CIS) devices are widely used in mobile phone cameras, and to meet broader demands, their performance requirements are constantly increasing. The main factor affecting CIS imaging quality is white pixels (WP), and the primary cause of white pixels is metal ion contamination during the manufacturing process.
[0003] The main method to reduce metal contamination in the manufacturing process is to reduce the introduction of metal impurity ions, such as using substrates with higher purity and controlling the introduction of metal elements by the working components at the machine end. However, while these measures can reduce metal contamination to some extent, further reductions in white pixels require other methods to reduce metal impurity ions. Currently, the traditional method for removing metal impurity ions is to improve the bottom microdefects (BMD) of the silicon wafer (e.g., Figure 1 (as shown), but it requires a large thermal budget, which can easily cause wafer thermal deformation and affect device performance. Therefore, it is difficult to meet the needs of a wide range of applications. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for reducing white pixels in CMOS image sensors, thereby solving the problem of white pixels caused by metal impurity ions in existing CMOS image sensors.
[0005] To achieve the above and other related objectives, the present invention provides a method for reducing white pixels in a CMOS image sensor, the method comprising:
[0006] A substrate is provided, the substrate comprising at least a semiconductor substrate, wherein a PN junction of a photodiode, a first isolation and a second isolation are formed therein, the first isolation being located above the photodiode, the second isolation being located on the side of the photodiode, and the first isolation containing metal impurity ions;
[0007] A sacrificial oxide layer is formed on the surface of the substrate, and a polycrystalline silicon adsorption layer is formed on the surface of the sacrificial oxide layer;
[0008] Nitrogen ions were implanted into the polycrystalline silicon adsorption layer using an ion implantation process.
[0009] The polycrystalline silicon adsorption layer implanted with the nitrogen ions is annealed using an annealing process;
[0010] Remove the sacrificial oxide layer and the polycrystalline silicon adsorption layer.
[0011] Optionally, the semiconductor substrate is of P-type conductivity, and the first isolation and the second isolation are P+ type isolations.
[0012] Optionally, the substrate includes an epitaxial layer, and the epitaxial layer is formed on the semiconductor substrate. In this case, the PN junction of the photodiode, the first isolation layer, and the second isolation layer are formed within the epitaxial layer.
[0013] Optionally, the epitaxial layer is of P-type conductivity, and the first isolation and the second isolation are P+ type isolations.
[0014] Optionally, the polycrystalline silicon adsorption layer is formed using an LPCVD deposition process.
[0015] Optionally, the thickness of the polycrystalline silicon adsorption layer is 300 angstroms to 400 angstroms.
[0016] Optionally, the nitrogen ion implantation dose is 2.0E8cm. -2 ~4.0E8cm -2 .
[0017] Optionally, the ion implantation energy of the ion implantation process is 4 keV to 6 keV.
[0018] Optionally, the annealing process conditions include: an annealing temperature of 700℃~1000℃, an annealing time of 20min~30min, and an annealing rate of 3~5℃ / min.
[0019] Optionally, the polycrystalline silicon adsorption layer can be removed using a dry etching process.
[0020] Optionally, the sacrificial oxide layer can be removed using a wet etching process.
[0021] As described above, the method for reducing white pixels in a CMOS image sensor according to the present invention involves doping a polycrystalline silicon adsorption layer with nitrogen ions. By utilizing the ability of nitrogen ions to effectively hinder dislocation movement, the polycrystalline silicon adsorption layer is promoted to form an oxide-vacancy defect complex at high temperature. This accelerates the capture of metal impurity ions by the polycrystalline silicon adsorption layer under the action of a local stress field, thereby achieving the purpose of reducing white pixels in the image sensor. Attached Figure Description
[0022] Figure 1 This is a schematic diagram of existing microscopic defects on the bottom of a silicon substrate.
[0023] Figure 2 The flowchart shown is a method for reducing white pixels in a CMOS image sensor according to the present invention.
[0024] Figure 3The diagram shown is a cross-sectional view of the substrate containing metal impurity ions, a photodiode, and P+ isolation according to the present invention.
[0025] Figure 4 The diagram shown is a cross-sectional view of the substrate surface after the formation of a sacrificial oxide layer and a polycrystalline silicon adsorption layer according to the present invention.
[0026] Figure 5 The diagram shown illustrates the ion implantation process of this invention.
[0027] Figure 6 The diagram shown illustrates the annealing process of this invention.
[0028] Figure 7 The diagram shown is a cross-sectional view of the present invention after the removal of the sacrificial oxide layer and the polycrystalline silicon adsorption layer.
[0029] Figure 8 The diagram shown is a cross-sectional view of the structure after the gate oxide layer is formed according to the present invention.
[0030] Figure 9 The diagram shown is a cross-sectional view of the substrate including the epitaxial layer according to the present invention.
[0031] Explanation of icon numbers
[0032] 10: Substrate; 11: Semiconductor substrate; 12: Photodiode; 13: First isolation layer; 14: Second isolation layer; 15: Metal impurity ions; 16: Epitaxial layer; 17: Shallow trench isolation structure; 18: Floating diffusion region; 20: Sacrificial oxide layer; 30: Polycrystalline silicon adsorption layer; 40: Gate oxide layer Detailed Implementation
[0033] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0034] Please see Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.
[0035] like Figure 1 As shown, this embodiment provides a method for reducing white pixels in a CMOS image sensor, the method comprising:
[0036] A substrate 10 is provided, the substrate 10 including at least a semiconductor substrate 11, and a PN junction of a photodiode 12, a first isolation 13 and a second isolation 14 are formed in the semiconductor substrate 11, the first isolation 13 is located above the photodiode 12, the second isolation 14 is located on the side of the photodiode 12, and the first isolation 13 contains metal impurity ions 15.
[0037] A sacrificial oxide layer 20 is formed on the surface of the substrate 10, and a polycrystalline silicon adsorption layer 30 is formed on the surface of the sacrificial oxide layer 20.
[0038] Nitrogen ions were implanted into the polycrystalline silicon adsorption layer 30 using an ion implantation process.
[0039] The polycrystalline silicon adsorption layer 30 doped with the nitrogen ions is annealed using an annealing process;
[0040] Remove the sacrificial oxide layer 20 and the polycrystalline silicon adsorption layer 30.
[0041] The method for reducing white pixels in a CMOS image sensor provided in this embodiment will be described in detail below with reference to the accompanying drawings.
[0042] like Figure 3 As shown, a substrate 10 is provided, the substrate 10 including at least a semiconductor substrate 11, and a PN junction of a photodiode 12, a first isolation 13 and a second isolation 14 are formed in the semiconductor substrate 11. The first isolation 13 is located above the photodiode 12, the second isolation 14 is located on the side of the photodiode 12, and the first isolation 13 contains metal impurity ions 15.
[0043] Specifically, the semiconductor substrate 11 is of P-type conductivity, and the first isolation 13 and the second isolation 14 are P+ type isolations.
[0044] In this embodiment, the semiconductor substrate is a silicon substrate. The second isolation 14 is located on both sides of the 12N-type region of the photodiode, with the second isolation 14 on the left side being attached to it and the second isolation 14 on the right side being at a certain distance from it.
[0045] Specifically, such as Figure 9 As shown, the substrate 10 includes an epitaxial layer 16, and the epitaxial layer 16 is formed on the semiconductor substrate 11. At this time, the PN junction of the photodiode 12, the first isolation 13 and the second isolation 14 are formed in the epitaxial layer 16.
[0046] More specifically, the epitaxial layer 16 is of P-type conductivity, and the first isolation layer 13 and the second isolation layer 14 are P+ type isolation layers.
[0047] In this embodiment, the photodiode 12 uses the P+ type isolation as the deep region isolation and the shallow trench isolation structure 17 (STI) for the shallow region isolation.
[0048] Furthermore, the semiconductor substrate 11 or the epitaxial layer 16 also includes a shallow trench isolation structure 17 formed by processes such as photolithography, etching and chemical vapor deposition, and a floating diffusion region 18 formed by ion implantation. The floating diffusion region 18 is located above the second isolation 14 on the right side of the photodiode 12N type region and is used as the drain of the polysilicon transport gate.
[0049] like Figure 4 As shown, a sacrificial oxide layer 20 is formed on the surface of the substrate 10, and a polycrystalline silicon adsorption layer 30 is formed on the surface of the sacrificial oxide layer 20.
[0050] Specifically, the polycrystalline silicon adsorption layer 30 is formed using an LPCVD deposition process.
[0051] As an example, the thickness of the polycrystalline silicon adsorption layer 30 is 300 angstroms to 400 angstroms.
[0052] like Figure 5 As shown, nitrogen ions are implanted into the polycrystalline silicon adsorption layer 30 using an ion implantation process.
[0053] Specifically, the nitrogen ion implantation dose is 2.0E8cm. -2 ~4.0E8cm -2 .
[0054] In this embodiment, by doping the polycrystalline silicon adsorption layer 30 with a low concentration of N ions, the formation of oxide-vacancy defect complexes in the polycrystalline silicon adsorption layer 30 can be effectively promoted.
[0055] Specifically, the ion implantation energy for the ion implantation process is 4 keV to 6 keV.
[0056] like Figure 6 As shown, the polycrystalline silicon adsorption layer 30 doped with the nitrogen ions is annealed using an annealing process;
[0057] Specifically, the annealing process conditions include: annealing temperature of 700℃~1000℃, annealing time of 20min~30min, and annealing speed of 3~5℃ / min.
[0058] In this embodiment, an annealing process is used. On the one hand, nitrogen ions promote the aggregation of oxygen elements in the polycrystalline silicon adsorption layer 30 and promote the combination of oxygen elements with vacancies to form oxide precipitates, thereby allowing metal impurity ions to be adsorbed at high temperatures. On the other hand, the high temperature used during annealing accelerates the migration rate of metal impurity ions.
[0059] like Figure 7 As shown, the sacrificial oxide layer 20 and the polycrystalline silicon adsorption layer 30 are removed.
[0060] Specifically, the polycrystalline silicon adsorption layer 30 is removed using a dry etching process.
[0061] Specifically, the sacrificial oxide layer 20 is removed using a wet etching process.
[0062] Furthermore, such as Figure 8 As shown, in this embodiment, after removing the sacrificial oxide layer 20, a gate oxide layer 40 is formed on the surface of the semiconductor substrate 11 using a standard CMOS process. Of course, if the substrate 10 includes the epitaxial layer 16, after removing the sacrificial oxide layer 20, a gate oxide layer 40 is formed on the surface of the epitaxial layer 16 using a standard CMOS process.
[0063] In this embodiment, at high temperature, nitrogen ions react with vacancies and oxygen in the silicon substrate to form oxide-vacancy defect complexes (NVO). (The atomic radius of N is smaller than that of Si; substituted N atoms easily create crystal micro-defects, which readily absorb interstitial oxygen atoms and form complexes through reaction.) These complexes promote the nucleation of oxygen deposits, thereby generating dislocation loops around the oxygen deposits. For the polycrystalline silicon adsorption layer, since polycrystalline silicon is primarily a silicon substrate, it contains numerous grain boundaries, which are themselves defects. The addition of doped N ions introduces even more defects, resulting in a large local stress field within the polycrystalline silicon adsorption layer. This accelerates the capture of metal impurity ions, thereby reducing white pixels in the CMOS image sensor. Furthermore, the method described above has minimal impact on the wafer itself in reducing white pixels in the CMOS image sensor.
[0064] In summary, the method for reducing white pixels in CMOS image sensors according to the present invention involves doping a polycrystalline silicon adsorption layer with nitrogen ions. Nitrogen ions effectively hinder dislocation movement, promoting the formation of oxide-vacancy defect complexes in the polycrystalline silicon adsorption layer at high temperatures. This, in turn, accelerates the capture of metal impurity ions by the polycrystalline silicon adsorption layer under a localized stress field, thereby reducing white pixels in the image sensor. Therefore, the present invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.
[0065] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for reducing white pixels in a CMOS image sensor, characterized in that, The method includes: A substrate is provided, the substrate comprising at least a semiconductor substrate, wherein a PN junction of a photodiode, a first isolation and a second isolation are formed therein, the first isolation being located above the photodiode, the second isolation being located on the side of the photodiode, and the first isolation containing metal impurity ions; A sacrificial oxide layer is formed on the surface of the substrate, and a polycrystalline silicon adsorption layer is formed on the surface of the sacrificial oxide layer; Nitrogen ions were implanted into the polycrystalline silicon adsorption layer using an ion implantation process. The polycrystalline silicon adsorption layer implanted with the nitrogen ions is annealed using an annealing process; The sacrificial oxide layer and the polycrystalline silicon adsorption layer are removed, and then a gate oxide layer is formed on the surface of the semiconductor substrate.
2. The method for reducing white pixels in a CMOS image sensor according to claim 1, characterized in that, The semiconductor substrate is of P-type conductivity, and the first isolation and the second isolation are P+ type isolations.
3. The method for reducing white pixels in a CMOS image sensor according to claim 1 or 2, characterized in that, The substrate includes an epitaxial layer, which is formed on the semiconductor substrate. In this case, the PN junction of the photodiode, the first isolation layer, and the second isolation layer are formed within the epitaxial layer.
4. The method for reducing white pixels in a CMOS image sensor according to claim 3, characterized in that, The epitaxial layer is of P-type conductivity, and the first and second isolations are P+ type isolations.
5. The method for reducing white pixels in a CMOS image sensor according to claim 1, characterized in that, The polycrystalline silicon adsorption layer was formed using an LPCVD deposition process.
6. The method for reducing white pixels in a CMOS image sensor according to claim 5, characterized in that, The thickness of the polycrystalline silicon adsorption layer is 300 angstroms to 400 angstroms.
7. The method for reducing white pixels in a CMOS image sensor according to claim 1, characterized in that, The nitrogen ion implantation dose is 2.0 E8cm. -2 ~4.0E8cm -2 .
8. The method for reducing white pixels in a CMOS image sensor according to claim 7, characterized in that, The ion implantation energy for the ion implantation process is 4 keV to 6 keV.
9. The method for reducing white pixels in a CMOS image sensor according to claim 1, characterized in that, The conditions for the annealing process include: annealing temperature of 700℃~1000℃, annealing time of 20min~30min, and annealing speed of 3~5℃ / min.
10. The method for reducing white pixels in a CMOS image sensor according to claim 1, characterized in that, The polycrystalline silicon adsorption layer was removed using a dry etching process.
11. The method for reducing white pixels in a CMOS image sensor according to claim 10, characterized in that, The sacrificial oxide layer was removed using a wet etching process.