A top-down hierarchical logic rewriting method

Abstract

The application provides a top-down layered logic rewriting method, which comprises: a top-layer rewriting operation, including: performing XMG-based logic rewriting on a target circuit to convert the target circuit into a top-layer-rewritten XMG network, wherein XMG represents an XOR-majority-inverter graph; a fine-grained layer rewriting operation, including: dividing, by using a type-aware division strategy, the top-layer-rewritten XMG network into an XOR sub-circuit and a majority decision sub-circuit according to vertex types; performing XAG-based logic rewriting on the XOR sub-circuit to obtain an XAG sub-circuit, wherein XAG represents an XOR-and-inverter graph; performing MIG-based logic rewriting on the majority decision sub-circuit to obtain a MIG sub-circuit, wherein MIG represents a majority-decision-inverter graph; and a post-optimization operation, including: merging the XAG sub-circuit and the MIG sub-circuit into a unified XMG network, and performing XMG-based logic rewriting on the unified XMG network to obtain a final XMG network.

Description

Technical Field

[0001] This invention relates to the field of automated chip design, specifically to the field of logic synthesis, and more specifically, to a top-down hierarchical logic rewriting method. Background Technology

[0002] As chip scale continues to increase, efficient electronic design automation (EDA) tools have become essential for successful chip design, significantly shortening design cycles and accelerating time-to-market. Logic synthesis, a crucial stage in the EDA front-end flow, plays a fundamental role in chip design. The logic synthesis process mainly includes two stages: a logic optimization stage, which abstracts circuit functions into a Boolean network structure independent of physical implementation; and a process mapping stage, which transforms the abstract Boolean network structure into an optimized circuit implementation based on a given standard cell library.

[0003] During the logic optimization phase, Boolean networks can be represented in various forms. The main existing representations include: And-Inverter Graphs (AIG), Majority-Inverter Graphs (MIG), Xor-And-Inverter Graphs (XAG), and Xor-Majority-Inverter Graphs (XMG). Among these, XMG has attracted widespread attention due to its powerful logical expression capabilities and flexibility, making it particularly suitable for emerging computing paradigms such as quantum computing and in-memory computing (IMC).

[0004] Given the inherent computational complexity of logic optimization, finding the global optimum for any Boolean network type is often computationally infeasible. Therefore, heuristic logic optimization techniques are widely adopted due to their effectiveness in practical applications and robust empirical performance. Among these techniques, logic rewriting, as a classic logic optimization method, simplifies the Boolean network by extracting a window and applying local transformations. The algorithm traverses each node in the circuit diagram according to a certain topological order, searching for its local window and extracting the corresponding Boolean truth table. The tool then maps the computed Boolean function to a standard NPN (Negation-Permutation-Negation) equivalence class, the optimal representation of which is recorded in a library, thereby updating the window.

[0005] However, although some Boolean network types theoretically possess stronger expressive power, logical rewriting of them may result in less compact network structures compared to networks generated from types with lower expressive power. The implementation mechanism of logical rewriting and its inherent greedy nature limit its optimization capabilities to some extent. In practice, logical rewriting performs optimization by expanding sub-circuits and searching for more compact replacement structures. Although XMG has stronger expressive power, it may not expose more replaceable sub-circuits during optimization, thus limiting the effectiveness of logical rewriting in this representation.

[0006] In recent years, advancements in logic optimization have increasingly focused on integrating multiple complementary logic optimization techniques to improve the quality and effectiveness of logic synthesis. In particular, data-driven methods based on supervised learning have achieved significant progress in circuit size reduction and delay optimization through the combination of classic techniques such as resubstitution, resynthesis, reconstruction, and logic rewriting. However, existing work primarily focuses on improving overall optimization performance. While it incorporates logic rewriting as a component of a broader optimization framework, it does not emphasize improving more fine-grained techniques such as logic rewriting itself.

[0007] Therefore, it is necessary to address the limitation of optimization capabilities in complex Boolean networks when logic rewriting is performed in existing technologies.

[0008] It should be noted that the background information presented here is only for illustrating relevant information about the present invention to aid in understanding the technical solution of the present invention, and does not imply that the relevant information is necessarily prior art. The relevant information was submitted and disclosed together with the present invention, and should not be considered prior art unless there is evidence that the relevant information was disclosed before the filing date of the present invention. Summary of the Invention

[0009] Therefore, the purpose of this invention is to overcome the shortcomings of the prior art and provide a hierarchical logic rewriting method.

[0010] The objective of this invention is achieved through the following technical solution:

[0011] According to a first aspect of the present invention, a hierarchical logic rewriting method is provided, comprising: a top-level rewriting operation, including: performing XMG-based logic rewriting on a target circuit to convert the target circuit into a top-level rewritten XMG network, wherein XMG represents an XOR-majority decision-inverter diagram; a fine-grained layer rewriting operation, including: employing a type-aware partitioning strategy to partition the top-level rewritten XMG network into XOR sub-circuits and majority decision sub-circuits according to vertex types; performing XAG-based logic rewriting on the XOR sub-circuits to obtain XAG sub-circuits, where XAG represents an XOR-AND-inverter diagram; performing MIG-based logic rewriting on the majority decision sub-circuits to obtain MIG sub-circuits, where MIG represents a majority decision-inverter diagram; and a post-optimization operation, including: merging the XAG sub-circuits and MIG sub-circuits into a unified XMG network, and performing XMG-based logic rewriting on the unified XMG network to obtain a final XMG network. This scheme achieves at least the following beneficial technical effects: It fully leverages the advantages of various Boolean network representations, constructing a top-down hierarchical logic rewriting framework for XMG networks, achieving several effects: First, by constructing a top-down hierarchical logic rewriting architecture, it unifies circuit representation at the top level using the strongest expressive power of XMG. At the fine-grained level, it applies customized XAG and MIG rewriting rules to XOR-dense and majority-decision-dense regions respectively. This allows for precise implementation of customized rewriting techniques tailored to the structural characteristics of each sub-circuit, thereby achieving targeted enhancement of optimization effects. Second, after merging the optimized sub-circuits into a unified Boolean network (a unified XMG network), it performs XMG-based rewriting as a post-optimization process. This post-optimization operation can effectively correct suboptimal vertex allocations generated during sub-circuit merging by restoring vertices to more suitable Boolean network types when necessary, eliminating redundant logic and ultimately obtaining a more compact and efficient circuit implementation.

[0012] Optionally, the type-aware partitioning strategy includes: dividing the rewritten XMG network into XOR partitions and majority decision partitions according to vertex type, and setting the redistribution condition of vertices in the majority decision partition to meet the redistribution state only; cutting the edges between the XOR partition and the majority decision partition to form multiple connected components within the majority decision partition; identifying connected components with a vertex size greater than or equal to a preset threshold, and setting the redistribution condition of all vertices within them to not meet the redistribution state; and performing multi-round label propagation optimization on vertices that meet the redistribution state based on the complete topology of the rewritten XMG network, including: each round iterating... In the iteration, for each vertex to be optimized, the majority neighbor label type of its one-hop neighbors under the complete topology is counted. When the label of the vertex to be optimized is inconsistent with its majority neighbor label type, if the majority neighbor label type is XOR logic, the label of the vertex to be optimized is updated to AND logic; otherwise, the label of the vertex to be optimized is updated to the majority neighbor label type. The iteration terminates when the preset termination condition is met. After the iteration terminates, the partition is updated, and the vertices whose labels are changed to AND logic are moved from the majority decision partition to the XOR partition. The vertices and edges in the updated XOR partition form an XOR sub-circuit, and the vertices and edges in the updated majority decision partition form a majority decision sub-circuit. This scheme achieves at least the following beneficial technical effects: It effectively decomposes Boolean networks into several sub-circuits through a type-aware rapid partitioning strategy, enabling precise implementation of customized rewriting techniques tailored to the structural characteristics of each sub-circuit; it reallocates vertex types within controlled small-scale partitions using a label propagation algorithm, fully utilizing the structural context information of the vertex's local neighborhood, rather than relying solely on isolated vertex types for partitioning. This updates vertices to be optimized that have a majority neighbor label type of XOR logic to AND logic, allowing vertices originally belonging to the majority-determined partition to be transformed into AND logic and assigned to the XOR partition when surrounded by XOR logic neighbors. This supports XAG-based logic rewriting, effectively solving the technical challenge of determining precise partitioning boundaries due to the equivalence of logic primitives in different forms, promoting the formation of meaningful local sub-circuits, and significantly improving the quality of subsequent logic rewriting.

[0013] Optionally, the method further includes: after changing the label to a logical vertex from the majority-decision partition to the XOR partition, and before performing an XAG-based logical rewrite, performing the following transformation:

[0014]

[0015] in, Indicates the majority decision gate, This represents three Boolean input signals. The scheme represents AND logic. It achieves at least the following beneficial technical effects: by converting the majority decision vertices deemed suitable for inclusion in the XOR partition through label propagation into XAG-compatible AND logic structures, this sub-circuit can fully utilize the optimization opportunities unique to XAG rewriting rules, achieving finer logic simplification for XOR-dense local structures, improving the adaptability of fine-grained layer rewriting to specific circuit characteristics and the quality of subsequent rewriting operations.

[0016] Optionally, AIG-based logic rewriting is not used in either the top-level rewriting operation or the fine-grained layer rewriting operation, where AIG stands for AND-Inverter Graph. This approach achieves at least the following beneficial technical effects: Considering that AIG-based rewriting schemes have limited expressive power (weaker than MIG and XAG) and relatively high computational overhead, excluding them from consideration in the layered architecture avoids the huge computational overhead caused by introducing AIG-based logic rewriting, thus achieving a balance between improving logic rewriting quality and maintaining reasonable computational costs.

[0017] Optionally, the preset termination conditions include a first termination condition and a second termination condition. The iteration terminates when at least one of the first and second termination conditions is met, wherein: the first termination condition is that no vertex label changes in this iteration; the second termination condition is that the number of iterations has reached the maximum iteration threshold at the start of this iteration. This scheme can achieve at least the following beneficial technical effects: it ensures that the label propagation algorithm converges within a finite number of steps through a dual termination mechanism, strictly limits the time complexity of the redistribution process to O(V) level, avoids runtime inflation caused by infinite iteration, and guarantees the computational efficiency of the overall partitioning strategy.

[0018] Optionally, the post-optimization operation includes: performing XMG-based logic rewriting on the unified XMG network to restore suboptimal vertex assignments generated during the merging process to better Boolean network types, resulting in a more compact and efficient final XMG network. This scheme can achieve at least the following beneficial technical effects: by introducing post-XMG rewriting as an optimization process after sub-circuit merging, vertices can be restored to more suitable Boolean network types when necessary, effectively correcting suboptimal vertex assignments caused by rigid type partitioning during sub-circuit merging, eliminating redundant logic, and ultimately obtaining a more compact and efficient circuit implementation.

[0019] Optionally, the process of restoring suboptimal vertex assignments generated during the merging process to a better Boolean network type includes: identifying vertices in the unified XMG network that have been converted to XAG and MIG representations due to fine-grained layer rewriting operations, but whose corresponding original XMG representations are more compact, to obtain the suboptimal vertices to be restored; utilizing the native logic operations of XMG, restoring the suboptimal vertices to be restored in the unified XMG network to an XMG-compatible structure, thereby eliminating the additional intermediate vertices introduced by the fine-grained layer rewriting operations, and obtaining the final XMG network. This scheme can achieve at least the following beneficial technical effects: by directionally identifying and restoring the native, better vertex representations of XMG, it avoids the situation where fine-grained rewriting sacrifices global structural compactness in pursuit of local optima, thus obtaining a final circuit structure with a more compact structure and higher execution efficiency.

[0020] According to a second aspect of the present invention, a computer device / apparatus / system is provided, including a memory, a processor, and a computer program / instructions stored in the memory, wherein the processor executes the computer program / instructions to implement the steps of the method described in the first aspect.

[0021] According to a third aspect of the present invention, a computer program product is provided, comprising a computer program / instructions that, when executed by a processor, implement the steps of the method described in the first aspect. Attached Figure Description

[0022] The embodiments of the present invention will be further described below with reference to the accompanying drawings, wherein:

[0023] Figure 1 This is a flowchart illustrating the hierarchical logic rewriting method according to an embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of the modular overall process of the hierarchical logic rewriting method according to an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of a tag propagation algorithm according to an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the invention.

[0027] As mentioned in the background section, there is a need to address the limitation of optimization capabilities in complex Boolean networks when logic rewriting is performed in existing technologies. This is because: a single Boolean network representation (such as AIG, MIG, XAG, or XMG) is difficult to fully exploit the optimization potential of a hybrid structure combining XOR logic and majority decision logic when repeatedly applied, and the structural advantages across representations cannot be synergistically utilized; simultaneously, existing technologies struggle to form meaningful sub-circuit partitions in complex, interwoven Boolean networks, and rewriting strategies lack precise adaptation mechanisms to local circuit features, thus limiting the effectiveness of subsequent optimization steps.

[0028] To address this issue, this application systematically solves the problem of limited optimization capabilities in complex Boolean networks through the construction of a top-down hierarchical optimization architecture. Specifically: In the top-level rewriting stage, the target circuit is uniformly transformed using the strongest expressive power of XMG (Exclusive Orb-Most Decision-Inverter Graph), preserving all information of the hybrid structure of XOR logic and majority decision logic, thus breaking through the upper limit of the expressive power of a single representation. In the fine-grained layer rewriting stage, a type-aware partitioning strategy is used to adaptively decompose the XMG network into XOR sub-circuits and majority decision sub-circuits. Customized rewriting based on XAG (Exclusive Orb-AND-Inverter Graph) is performed on XOR-dense regions, utilizing the algebraic properties of XOR chains to achieve deep compression; customized rewriting based on MIG (Most Decision-Inverter Graph) is performed on majority decision-dense regions, leveraging the inherent structural advantages of majority decision gates; and targeted enhancement of optimization effects is achieved through precise matching of local circuit features. In the post-optimization stage, the rewritten sub-circuits are merged into a unified XMG network, and XMG rewriting is performed again to correct suboptimal vertex allocations generated during the merging process, eliminate redundant intermediate nodes introduced by fine-grained rewriting, and restore the compactness of the global structure. This layered architecture, through the design of "unification first, decomposition then fusion," allows the structural advantages of multiple Boolean network representations to work synergistically. Compared to repeated rewriting of a single representation, it significantly improves the optimization capability and execution efficiency of complex Boolean networks.

[0029] For ease of understanding and reference, the following explanations are provided for some of the abbreviations used in this application:

[0030] AIG (And-Inverter Graph) represents the And-Inverter Graph.

[0031] MIG (Majority-Inverter Graph) represents the majority-inverter graph.

[0032] XAG (Xor-And-Inverter Graph) represents the XOR-AND-Inverter Graph.

[0033] XMG (Xor-Majority-Inverter Graph) stands for XOR-Majority-Inverter Graph.

[0034] MAJ (Majority) represents majority decision.

[0035] XOR (Exclusive OR) represents the unique OR operation.

[0036] AND (Logical AND) means AND.

[0037] NOT (Logical NOT / Negation) represents NOT, and is also called an inverter.

[0038] NPN (Negation-Permutation-Negation) stands for Negation-Permutation-Negation.

[0039] LPA (Label Propagation Algorithm) represents the label propagation algorithm.

[0040] NDP (Node Depth Product) represents the node depth product.

[0041] IMC (In-Memory Computing) represents in-memory computing.

[0042] The inventors first conducted an in-depth analysis of the properties of various Boolean network representations and studied the most suitable representation for integration into this application, aiming to achieve a balance between improving logic rewriting quality and maintaining reasonable computational costs. Subsequently, addressing the technical challenge of high-quality circuit partitioning, this application proposes a hierarchical logic rewriting method based on a type-aware partitioning strategy. This type-aware partitioning strategy can perform precise partitioning operations based on the internal logical characteristics of the circuit. To make the objectives, technical solutions, and advantages of this application clearer, the following further describes this application from the aspects of Boolean network representation analysis, overall workflow, and experimental results.

[0043] I. Analysis of Boolean Network Representation

[0044] Based on the different logical functions represented by the vertices of a Boolean network, Boolean networks are generally classified into four types: And-Inverter (AIGs), Majority-Inverter (MIGs), Xor-And-Inverter (XAGs), and Xor-Majority-Inverter (XMGs). Each type of Boolean network is defined by a set of atomic logical operations, specifically including the NOT operation (…). ), and operations ( XOR operation ) and most decision operations ( ).

[0045] Specifically, AIG consists of AND and NOT operations; MIG uses majority decision and NOT operations; XAG uses XOR, AND, and NOT operations; while XMG combines XOR, majority decision, and NOT operations, as shown in Table 1.

[0046] Table 1

[0047]

[0048] It is worth noting that MIG and XAG exhibit stronger logical expression capabilities than AIG. This is because most decision-making logic can be implemented by fixing one of the inputs to 0, i.e., ... Based on the above characteristics, an inclusion relationship can be established between Boolean networks. From the perspective of expressive power, XMG has the strongest expressive power, followed by XAG and MIG, and the expressive power of XAG and MIG is strictly stronger than that of AIG, thus forming the following inclusion hierarchy structure:

[0049] ,

[0050] While employing multiple network representations has the potential to improve the quality of XMG rewriting optimization, this strategy inevitably leads to significant computational overhead.

[0051] Based on the above analysis, in order to achieve a balance between logic rewriting quality and computational efficiency, this application designates XMG-based rewriting as the top-level optimization scheme, serving as the basis for subsequent fine-grained optimization. Following this, for each sub-circuit obtained by the subsequent partitioning method of this application, MIG-based and XAG-based logic rewriting are implemented at the fine-grained level, respectively. It should be noted that, considering the limited expressive power and relatively high computational overhead of the AIG-based rewriting scheme, this application will exclude it from consideration in the layered architecture.

[0052] II. Overall Workflow

[0053] See Figure 1 This invention provides a hierarchical logic rewriting method, including steps S1, S2, and S3. To better understand this invention, each step is described in detail below with reference to specific embodiments.

[0054] Step S1: Top-level rewrite operation, including: performing an XMG-based logic rewrite on the target circuit to convert the target circuit into an XMG network rewritten at the top level, where XMG stands for XOR-majority decision-inverter diagram.

[0055] According to one embodiment of the present invention, see Figure 2 For a target circuit in the form of an AIG network, XMG rewriting is performed at the top level to obtain a top-level rewritten XMG network. For example, XMG-based logic rewriting can be applied using identities. as well as The target circuit is converted into an XMG network. This represents two Boolean input signals. This represents XOR logic. This indicates an inverter (not logic gate). Representation and Logic This indicates that the majority decision-making gate is selected.

[0056] To illustrate, first, the target circuit is read in AIG (AND-Inverter Diagram) format. The AIG network consists of AND logic vertices and inverter edges, and only supports two atomic operations: AND logic and NOT logic.

[0057] Although AIG networks do not natively support XOR operations, complex AND-NOT cascade structures can achieve equivalent XOR functionality. Therefore, it is possible to first identify the XOR logic implemented in the target circuit through AND-NOT cascade structures, such as identifying... The logical structure is then converted into an XOR vertex. ,Right now This formula eliminates redundant intermediate AND-NOT vertices, directly expressing XOR logic using atomic operations of XMG, thereby significantly compressing vertex depth and reducing network complexity.

[0058] Subsequently, since the XMG (Exclusive OR Majority Decision Inverter Graph) has a significantly stronger expressive power than AIG (i.e., AIG ⊂ XMG), the AND logic in the AIG network needs to be converted to an XMG-compatible structural form. Based on the degenerate property of majority decision operations, when one input of the majority decision gate is fixed at logic 0, its output is equivalent to AND logic, i.e. Therefore, the AND logic vertices in the AIG network can be transformed into majority decision vertices with three inputs, and the third input can be fixedly connected to the logic constant 0, thus obtaining the majority decision vertex representation in the XMG network.

[0059] After the above processing, the target circuit in the form of an AIG network is completely converted into a top-level rewritten XMG network. The top-level rewritten XMG network only contains XOR vertices, majority decision vertices, and inverter edges, laying a unified topological foundation for subsequent type-aware partitioning and fine-grained layer rewriting. At the same time, the top-level XMG rewriting makes full use of the strongest expressive power of XMG, retains all the logical information of the original circuit, and reduces functional loss during the conversion process.

[0060] Step S2: Fine-grained layer rewriting operation, including: using a type-aware partitioning strategy, dividing the XMG network rewritten from the top layer into XOR sub-circuits and majority decision sub-circuits according to vertex type; for the XOR sub-circuit, performing XAG-based logic rewriting to obtain the XAG sub-circuit, where XAG represents an XOR-AND-inverter diagram; for the majority decision (MAJ) sub-circuit, performing MIG-based logic rewriting to obtain the MIG sub-circuit, where MIG represents a majority decision-inverter diagram.

[0061] According to one embodiment of the present invention, the type-aware partitioning strategy includes: dividing the top-level rewritten XMG network into XOR partitions and majority decision partitions according to vertex type; setting the redistribution condition of vertices in the majority decision partition to meet the redistribution state only; cutting the edges between the XOR partition and the majority decision partition to form multiple connected components within the majority decision partition; identifying connected components with vertex sizes greater than or equal to a preset threshold, and setting the redistribution condition of all vertices within these components to not meet the redistribution state; and performing multi-round label propagation optimization on vertices meeting the redistribution state based on the complete topology of the top-level rewritten XMG network, including... In each iteration, for each vertex to be optimized, the majority neighbor label type among its one-hop neighbors in the complete topology is counted. When the label of the vertex to be optimized is inconsistent with its majority neighbor label type, if the majority neighbor label type is XOR logic, the label of the vertex to be optimized is updated to AND logic; otherwise, the label of the vertex to be optimized is updated to the majority neighbor label type. The iteration terminates when a preset termination condition is met. After the iteration terminates, the partitions are updated, and vertices whose labels are changed to AND logic are moved from the majority decision partition to the XOR partition. The vertices and edges in the updated XOR partition form an XOR sub-circuit, and the vertices and edges in the updated majority decision partition form a majority decision sub-circuit. Preferably, the preset termination condition includes a first termination condition and a second termination condition. The iteration terminates when at least one of the first termination condition and the second termination condition is met, wherein: the first termination condition is: no vertex label changes after this iteration; the second termination condition is: at the beginning of this iteration, the number of iterations has reached the maximum number of iterations threshold.

[0062] To effectively address the technical challenge of determining high-quality partitioning boundaries, this embodiment proposes a novel circuit partitioning strategy: a type-aware partitioning strategy. After XMG-based logic rewriting, the top-level rewritten XMG network contains only XOR vertices and Majority Decision (MAJ) vertices, which are widely distributed and intricately intertwined throughout the network. This presents a technical challenge in distinguishing the boundaries between the two networks. As mentioned earlier, some MAJ vertices can be considered equivalent transformations of AND vertices, thus enabling their use in logic rewriting within XAG networks. Therefore, conventional partitioning methods based solely on vertex types cannot capture meaningful structural information, thereby limiting the effectiveness of subsequent logic rewriting steps.

[0063] To overcome the aforementioned shortcomings, this embodiment proposes a type-aware partitioning strategy. It uses vertex type as the initial partitioning criterion, followed by a refinement step based on the Label Propagation Algorithm (LPA). (See [link to relevant documentation]). Figure 3This involves reallocating vertex types and fully exploring further optimization space. The reallocation operation is selectively performed within smaller partitions to enhance the coherence of local structures while maintaining the overall partition hierarchy. The illustrative implementation steps of this type-aware partitioning strategy are as follows:

[0064] In the initial stage, the rewritten XMG network is divided into two partitions according to vertex type (XOR vertices are assigned to the XOR partition, and majority decision vertices are assigned to the majority decision partition), and the state of all vertices is marked as meeting the redistribution condition. For vertices identified as belonging to the XOR partition, this application believes that their inherent logical semantics are not suitable for further transformation or simplification within the current framework. Therefore, this embodiment explicitly defines its transformation conditions as follows: In other words, the redistribution condition of vertices in the XOR partition is set to not meet the redistribution state, thus excluding them from subsequent transformation processes. This approach reflects the inherent compactness of XOR components, which typically do not consider transforming their logical semantics to maintain their structural efficiency.

[0065] Subsequently, the edges between the XOR partition and the majority decision partition are cut (i.e., the connecting edges between the majority decision vertex and the XOR vertex are cut) to form multiple connected components within the majority decision partition. Used to assist Boolean networks with a The vertices are then subjected to a breadth-first traversal to obtain their connected components. The size of the visited connected components is then determined. Reaching the preset threshold At that time, the redistribution eligibility marker will be updated accordingly. The condition for redistributing all vertices in a connected component whose vertex size is greater than or equal to a preset threshold is set to a non-redistribution state.

[0066] Next, based on the preset label propagation algorithm, multiple rounds of label propagation optimization are performed on the vertices that meet the redistribution state, and a flag is set. To characterize whether the vertex label has changed in this iteration, such as This indicates that no vertex labels have changed. This indicates that vertex labels have changed; initialization is performed before the start of each round. When the flag bit True ( And the number of iterations At that time, a type-aware reallocation process is executed iteratively. When the vertex When the qualification flag is true, the vertex type will be... The update is performed by assigning the most frequent label to its neighboring vertices. The formula for this update rule is as follows:

[0067] ,

[0068] in, Represents vertices In the The updated label in the next iteration. (Function) Used to generate tags The one-hot vector representation, where the value is 1 at the corresponding label position and 0 at other positions. For each vertex... If its current type is related to the set of its adjacent vertices If most types are inconsistent, the flag bit is triggered and pulled high. The update process terminates when no vertex type change occurs or the maximum number of iterations is reached.

[0069] Schematic, when a majority decision (MAJ) vertex is primarily surrounded by XOR (XOR) adjacent vertices, this embodiment updates its type to AND logic, thereby enabling the corresponding subcircuit to support XAG-based logic rewriting. Through this controlled refinement operation, this embodiment effectively promotes the formation of practically meaningful subcircuits and significantly improves the overall logic rewriting quality. After relocating vertices labeled as AND logic from the majority decision partition to the XOR partition, before performing XAG-based logic rewriting, the corresponding logic transformation operation is performed as follows: ,in, Indicates the majority decision gate, This represents three Boolean input signals. The representation is AND logic. Since the majority decision vertex is derived from the previous AND logic transformation, and the third input signal is 0, the majority decision vertex that is assigned to the XOR partition can be reversed into the AND logic vertex using a formula similar to the one above, to support subsequent XAG-based logic rewriting.

[0070] In the above implementation process, when the vertex Iterate and add to the collection In the process, once the conditions are met... If λ indicates that the size of the connected component is large, the algorithm will trigger an early termination mechanism. This early termination mechanism ensures that the time complexity of the vertex qualification check phase remains within the range specified by the algorithm. Level. For the redistribution process, given the maximum number of iterations. Since it is a constant, its time complexity is also limited to 1 / 2. Level. Therefore, the overall time complexity of the type-aware partitioning strategy in this embodiment is O(n log n). It has extremely high computational efficiency.

[0071] According to one embodiment of the present invention, for an XOR subcircuit, XAG-based logic rewriting is performed to obtain an XAG subcircuit. For example, after type-aware partitioning, the XOR subcircuit includes XOR vertices, AND vertices, and inverter edges. Since the atomic operation set of XAG (Exclusive Or-AND-Inverter Graph) is {XOR, AND, NOT}, it is naturally compatible with the vertex types of the XOR subcircuit, and the XAG rewriting rules can be directly applied without additional structural transformation. The XAG-based logic rewriting follows the classic window extraction and NPN equivalence class replacement paradigm: the algorithm traverses each vertex in the XOR subcircuit in topological order, extracts its local window, and calculates the corresponding Boolean truth table. Subsequently, the tool maps the truth table to the NPN equivalence class supported by XAG, queries the pre-built standard library for the optimal expression of the equivalence class in the XAG representation space, and replaces the original window structure with it. For example, for XOR-intensive subcircuits, this application applies XAG-specific XOR logic rewriting rules to deeply compress the XOR chain. For example, the application rules... This approach utilizes the algebraic properties of the XOR operation to eliminate redundant intermediate XOR vertices, reducing circuit depth. This rule fully leverages the reflexivity and associativity of XOR logic, achieving structural compactness while maintaining functional equivalence. Through a customized rewrite based on XAG, the XOR sub-circuit is optimized into an XAG sub-circuit. The XAG sub-circuit is expressed using the native vertex type of XAG, preserving the compactness of the XOR logic and laying the structural foundation for subsequent merging with MIG sub-circuits. Compared to uniformly using XMG rewriting, this customized strategy achieves finer local optimization for XOR-dense regions, significantly improving the overall quality of logic synthesis.

[0072] According to one embodiment of the present invention, for a majority-decision (MAJ) subcircuit, MIG-based logic rewriting is performed to obtain the MIG subcircuit. For example, after type-aware partitioning, the majority-decision subcircuit includes majority-decision vertices and inverter edges. Since the atomic operation set of MIG (majority-decision-inverter graph) is {MAJ, NOT}, which is compatible with the vertex types of the majority-decision subcircuit, MIG rewriting rules can be directly applied. The MIG-based logic rewriting follows the window extraction and NPN equivalence class replacement paradigm. Each vertex in the majority-decision subcircuit is traversed in topological order, its local window is extracted, and a Boolean truth table is computed. The tool maps the truth table to the NPN equivalence class supported by MIG, queries the optimal representation of the equivalence class in the MIG representation space from the pre-built standard library, and replaces the original window structure with it. The vertex depth and area are optimized by applying MIG-specific majority-decision logic rewriting rules. For example, the rules are applied... This rule fully leverages the inherent advantages of MIG in expressing majority decision functions, avoiding the structural redundancy introduced by the general representation of XMG. Through customized rewriting based on MIG, the majority decision sub-circuit is optimized into a MIG sub-circuit. The MIG sub-circuit is expressed using the native vertex type of MIG, preserving the compactness of the majority decision logic while laying the structural foundation for subsequent merging with XAG sub-circuits. Compared to uniformly using XMG rewriting, this customized strategy achieves more refined local optimization for the majority decision-intensive region, thus better improving the overall quality of logic synthesis.

[0073] Step S3: Post-optimization operation, including: merging the XAG sub-circuit and the MIG sub-circuit into a unified XMG network, and performing XMG-based logic rewriting on the unified XMG network to obtain the final XMG network.

[0074] According to one embodiment of the present invention, the post-optimization operation includes: performing an XMG-based logical rewrite on the unified XMG network to restore suboptimal vertex allocations generated during the merging process to a better Boolean network type, resulting in a final XMG network with a more compact structure and higher execution efficiency. The process of restoring suboptimal vertex allocations generated during the merging process to a better Boolean network type includes: identifying vertices in the unified XMG network that have been converted to XAG and MIG representations due to fine-grained layer rewrite operations, but whose corresponding original XMG representations are more compact, thus obtaining the suboptimal vertices to be restored; and using native XMG logical operations, restoring the suboptimal vertices to be restored in the unified XMG network to an XMG-compatible structure to eliminate the additional intermediate vertices introduced by the fine-grained layer rewrite operations, thus obtaining the final XMG network. For example, due to the rigid boundaries of type-aware partitioning and the local optimization characteristics of fine-grained layer rewrite, some suboptimal vertex allocations exist in the merged XMG network. Illustratively, some vertices are converted to XAG or MIG representations at the fine-grained layer, but their corresponding original XMG representations are more compact. For example, vertices rewritten and expanded into XOR-AND-OR structures by XAG rewriting, or majority decision vertices rewritten and expanded into nested structures by MIG rewriting, may introduce additional intermediate nodes, leading to a deterioration in the global node depth product metric. Therefore, a post-optimization is performed on the unified XMG network using XMG-based logical rewriting. The algorithm traverses the merged XMG network, identifies suboptimal vertices to be restored, and uses native XMG logical operations (XOR, MAJ, NOT) to restore them to an XMG-compatible compact structure, eliminating redundant intermediate vertices introduced by fine-grained layer rewriting. Through this post-optimization, a more compact and efficient XMG network is ultimately obtained.

[0075] III. Experimental Results

[0076] To comprehensively evaluate the optimization performance and execution efficiency of the hierarchical logic rewriting method proposed in this application, the inventors conducted systematic comparative experiments on benchmark circuit sets such as EPFL and IWLS'05. The EPFL benchmark set covers various complex Boolean networks, including arithmetic, control, and random circuits, while the IWLS'05 benchmark set contains large-scale industrial-grade circuit examples. Together, they constitute a representative test environment.

[0077] To ensure experimental transparency and address practical application considerations, this application specifies evaluation metrics and conducts an in-depth analysis of the sensitivity of key parameters. The experiment selects the Node Depth Product (NDP) as the primary evaluation metric. This metric comprehensively reflects the area and delay characteristics of the circuit and is defined as the product of the number of logic nodes and the circuit depth. A lower NDP indicates a better area-delay tradeoff. Simultaneously, the experiment records the running time of each method to evaluate computational efficiency.

[0078] The comparison method is set as follows:

[0079] Single representation repeated rewriting: including three repeated rewriting based solely on XMG (XMG³), and a combined strategy of performing two AIG / MIG / XAG rewritings followed by one XMG rewriting.

[0080] MixSyn method: An existing multi-representation hybrid synthesis method. This experiment has made adaptive modifications to it, namely, performing XAG rewriting first, then AIG / XAG rewriting, and finally XMG rewriting.

[0081] The method of this application is to adopt a top-down hierarchical logic rewriting method, including top-level XMG rewriting, type-aware partitioning, fine-grained XAG / MIG customized rewriting, and post-XMG optimization.

[0082] The experimental results are shown in Table 2:

[0083] Table 2

[0084]

[0085] Table 2 shows the results of rewriting using different logical representations, where the network type name represents the optimization method applied to the Boolean network as a whole, and the exponent represents the number of optimizations (e.g., ...). +XMG involves performing two AIG rewrites followed by one XMG rewrite. This experiment also modified MixSyn, performing one XAG rewrite first, then an AIG / XAG rewrite, and finally an XMG rewrite. The average ratio represents the ratio of the corresponding metrics of each method to the average of the unoptimized circuit (Origin).

[0086] The results show that applying different logical representations to the entire network for rewriting results in relatively poor optimization performance. Although some representations can provide better results than rewriting using XMG alone, their performance is still slightly inferior to the more fine-grained, partition-based rewriting method adopted in this application. This highlights the advantage of this application, namely, by combining multiple Boolean network representations and their corresponding rewriting methods in the XMG network, a broader optimization space can be explored. For example, for... This application generates substantially more compact circuit results than rewriting solely based on XMG by leveraging optimization opportunities unique to other representations. This demonstrates the flexibility of this application in adapting to specific circuit characteristics, an adaptability unattainable by rewriting methods that repeatedly apply a single representation. Essentially, the core advantage of this application lies in the diversity of rewriting paths it integrates. Overall, on NDP, compared to +XMG、 +XMG、 , The +XMG and MixSyn methods are implemented in this application respectively. , , , as well as Average NDP reduction.

[0087] Experimental results show that, in terms of final optimized performance, compared to the state-of-the-art rewriting methods, this application achieves a reduction of approximately 4.31% in the Node Depth Product (NDP) metric; simultaneously, it reduces runtime by 13.62%, strongly demonstrating that this application combines superior optimization quality with higher execution efficiency. Furthermore, it has been thoroughly validated on the EPFL and IWLS'05 benchmark sets that the hierarchical architecture of this invention is independent of specific circuit topologies and can achieve optimization on XOR-dominated, majority-dominated, and hybrid circuit structures, proving its generalization capability across circuit types.

[0088] In summary, this invention provides a top-down hierarchical logic rewriting framework for XMG networks. Through a three-layer architecture—a unified top-level XMG representation, fine-grained XAG / MIG-oriented rewriting, and post-XMG rewriting optimization—it fully leverages the structural advantages of various selected Boolean network representations to achieve better logic rewriting performance. Experiments show that the hierarchical logic rewriting framework of this application significantly outperforms existing single or simple combination rewriting strategies in simultaneously compressing circuit area and reducing critical path delay.

[0089] It should be noted that although the steps are described in a specific order above, it does not mean that the steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently, or even in a different order, as long as the required function can be achieved.

[0090] This invention can be a system, method, electronic device, computing device, computer program product and / or computer-readable medium.

[0091] Computer program products mainly refer to software products that implement various aspects of the present invention through computer programs, or hardware products that carry software that implements various aspects of the present invention.

[0092] Computer-readable storage media can be tangible devices that hold and store instructions for use by an instruction execution device. Computer-readable storage media can include, for example, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof.

[0093] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A hierarchical logic rewriting method, comprising: The top-level rewrite operation includes: performing an XMG-based logic rewrite on the target circuit to convert the target circuit into an XMG network rewritten at the top level, where XMG stands for XOR-majority-decision-inverter diagram; The fine-grained layer rewriting operation includes: using a type-aware partitioning strategy, dividing the XMG network rewritten from the top layer into XOR sub-circuits and majority decision sub-circuits according to vertex type; for the XOR sub-circuits, performing XAG-based logic rewriting to obtain XAG sub-circuits, where XAG represents an XOR-AND-inverter diagram; for the majority decision sub-circuits, performing MIG-based logic rewriting to obtain MIG sub-circuits, where MIG represents a majority decision-inverter diagram. The post-optimization operation includes: merging the XAG sub-circuit and the MIG sub-circuit into a unified XMG network, and performing XMG-based logic rewriting on the unified XMG network to obtain the final XMG network.

2. The method according to claim 1, characterized in that, The type-aware partitioning strategy includes: The XMG network rewritten at the top level is divided into XOR partitions and majority decision partitions according to vertex type. Only the redistribution condition of vertices in the majority decision partition is set to meet the redistribution state. Cut the edge between the XOR partition and the majority decision partition to form multiple connected components within the majority decision partition; Identify connected components whose vertex size is greater than or equal to a preset threshold, and set the redistribution condition of all vertices within them to a non-redistribution state. Based on the complete topology of the XMG network rewritten at the top level, multi-round label propagation optimization is performed on vertices that meet the redistribution state, including: in each iteration, for each vertex to be optimized, the majority neighbor label type of its one-hop neighbors under the complete topology is counted. When the label of the vertex to be optimized is inconsistent with its majority neighbor label type, if the majority neighbor label type is XOR logic, the label of the vertex to be optimized is updated to AND logic; otherwise, the label of the vertex to be optimized is updated to the majority neighbor label type. The iteration is terminated when the preset termination condition is met. After the iteration is terminated, the partition is updated, and the vertices with labels changed to AND logic are moved from the majority decision partition to the XOR partition. The vertices and edges in the updated XOR partition are used to form XOR sub-circuits, and the vertices and edges in the updated majority decision partition are used to form majority decision sub-circuits.

3. The method according to claim 2, characterized in that, The method further includes: after changing the label to a logical vertex from the majority-determined partition to the XOR partition, and before performing the XAG-based logical rewrite, performing the following transformation: in, Indicates the majority decision gate, This represents three Boolean input signals. Representation and logic.

4. The method according to claim 1, characterized in that, In both top-level rewrite operations and fine-grained rewrite operations, AIG-based logic rewrite is not used, where AIG stands for AND-Inverter Graph.

5. The method according to claim 2 or 3, characterized in that, The preset termination conditions include a first termination condition and a second termination condition. The iteration terminates when at least one of the first termination condition and the second termination condition is met, wherein: The first termination condition is: no vertex label has changed in this iteration; The second termination condition is: when the current iteration begins, the number of iterations has reached the maximum number of iterations threshold.

6. The method according to any one of claims 1-4, characterized in that, The post-optimization operation includes: The unified XMG network is rewritten using XMG-based logic to restore suboptimal vertex assignments generated during the merging process to a better Boolean network type, resulting in a final XMG network with a more compact structure and higher execution efficiency.

7. The method according to claim 6, characterized in that, The process of restoring suboptimal vertex assignments generated during the merging process to a better Boolean network type includes: Identify vertices in the unified XMG network that have been converted to XAG and MIG representations due to fine-grained layer rewriting operations, but whose corresponding original XMG representations are more compact, and obtain the suboptimal vertices to be recovered; By utilizing the native logic operations of XMG, the suboptimal vertices to be restored in the unified XMG network are restored to an XMG-compatible structure, thereby eliminating the extra intermediate vertices introduced by the fine-grained layer rewriting operations and obtaining the final XMG network.

8. A computer device / equipment / system, comprising a memory, a processor, and computer programs / instructions stored in the memory, characterized in that, The processor executes the computer program / instructions to implement the steps of the method according to any one of claims 1-7.

9. A computer program product comprising a computer program / instructions that, when executed by a processor, implement the steps of the method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, It stores a computer program / instruction thereon, which is executed by a processor to implement the steps of the method according to any one of claims 1-7.

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