Current detection method and driving module of three-phase permanent magnet motor

Abstract

The embodiment of the application discloses a current detection method of a three-phase permanent magnet motor and a driving module thereof, and the effective vector is ensured to be long enough in action time, and sampling is performed at a moment before the effective vector action time of the current ends, so that the sampled current is more stable and more accurate.

Description

Technical Field

[0001] This application relates to the field of electronic circuits, specifically to a current detection method and drive module for a three-phase permanent magnet motor. Background Technology

[0002] In existing technologies, to reconstruct the three-phase current from the bus current, PWM phase shifting is required to ensure a sufficiently long effective vector duration during PWM modulation, providing a sufficient sampling window for current sampling. A conventional sampling method involves capturing the turn-on edge of the switching transistors in the three-phase inverter circuit, then delaying the transient process before sampling. This allows for the acquisition of two-phase currents within one cycle. However, if external parameters such as temperature or load current change, causing transient variations, the sampling point based on the turn-on moment may still be in an oscillating state, leading to unstable sampling. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a current detection method and drive module for a three-phase permanent magnet motor to ensure that the sampled current is more stable and more accurate.

[0004] In a first aspect, embodiments of this application provide a current detection method for a three-phase permanent magnet motor, comprising: within a pulse width modulation period, determining whether the interval between adjacent falling edges in a three-phase PWM signal is less than a preset interval; when the interval between two adjacent falling edges is less than the preset interval, shifting at least one of the two PWM signals corresponding to the two adjacent falling edges to make the interval between the two adjacent falling edges the preset interval, and ensuring that the time interval between the falling edge of each phase PWM signal and the end or start time of the current pulse width modulation period is within a preset range, thereby making the time interval between adjacent falling edges greater than or equal to the preset interval; wherein, the current sampling circuit samples at the corresponding times of the second and third falling edges of the three-phase PWM signals within the current pulse width modulation period to obtain the phase current of two phases.

[0005] Optionally, when the interval between two adjacent falling edges is less than a preset interval, the interval between adjacent falling edges can be configured to the preset interval by keeping one phase of the PWM signal unchanged and shifting the other phase of the PWM signal.

[0006] Optionally, when the interval between two adjacent falling edges is less than a preset interval, the two PWM signals corresponding to the two adjacent falling edges are shifted so that the falling edge of one phase PWM signal is consistent with the preset cutoff start point or preset cutoff end point in the current pulse width modulation period, thereby making the interval between two adjacent falling edges the preset interval.

[0007] Optionally, by shifting the two PWM signals corresponding to two adjacent falling edges in opposite directions, the falling edge of one phase PWM signal is made to coincide with the preset cutoff start point or preset cutoff end point in the current pulse width modulation period, so that the interval between two adjacent falling edges is a preset interval.

[0008] Optionally, the preset cutoff start point is one of the endpoint values ​​corresponding to the preset interval, and the preset cutoff end point is the other endpoint value corresponding to the preset interval.

[0009] Optionally, the interval between adjacent falling edges in the three-phase PWM signal can be determined by comparing the pulse widths of the three-phase PWM signals.

[0010] Optionally, within each pulse width modulation cycle, the pulse widths of the three-phase PWM signals are compared to identify the first PWM signal with the largest pulse width, the second PWM signal with the second largest pulse width, and the third PWM signal with the smallest pulse width.

[0011] Determine whether the interval between the falling edge of the first PWM signal and the falling edge of the second PWM signal is less than a preset interval, and whether the interval between the falling edge of the second PWM signal and the falling edge of the third PWM signal is less than a preset interval.

[0012] Optionally, the duty cycle of the three-phase PWM signal in the current pulse width modulation period is calculated based on the phase current of the two phases sampled in the previous pulse width modulation period.

[0013] The three comparison values ​​corresponding to the three-phase modulation wave of the generated three-phase PWM signal are calculated based on the duty cycle.

[0014] The time interval between two adjacent falling edges is determined by comparing the three comparison values.

[0015] Optionally, the time interval between two adjacent falling edges can be determined by comparing whether the difference between two adjacent comparison values ​​is less than a threshold.

[0016] When the difference between two adjacent comparison values ​​is less than a threshold, at least one of the two adjacent comparison values ​​is adjusted so that the difference between the two adjacent comparison values ​​is the threshold, and each comparison value is less than or equal to a first preset value and greater than or equal to a second preset value, so that the difference between the adjacent comparison values ​​is greater than or equal to the threshold.

[0017] Optionally, the falling edges of the three-phase PWM signals are generated based on the adjusted three comparison values;

[0018] By changing the minimum comparison value, the intermediate comparison value, or the maximum comparison value in reverse by equal amounts, the rising edge of the corresponding phase PWM signal is generated, thereby achieving the translation of the PWM signal.

[0019] Optionally, ensuring that the interval between the falling edge of each phase PWM signal and the end or start time of the current pulse width modulation period is within a preset range includes: ensuring that the comparison value corresponding to the modulation wave of the falling edge of the PWM signal of the corresponding phase is less than or equal to a first preset value and greater than or equal to a second preset value.

[0020] Optionally, the three comparison values ​​are compared to obtain the maximum comparison value, the middle comparison value, and the minimum comparison value;

[0021] When the difference between the maximum comparison value and the intermediate comparison value is less than the threshold, it is determined whether the sum of the intermediate comparison value and the threshold is less than or equal to the first preset value; if it is less than or equal to the threshold, the intermediate comparison value remains unchanged, and the maximum comparison value is adjusted to the sum of the intermediate comparison value and the threshold; otherwise, the maximum comparison value is adjusted to the first preset value, and the difference between the maximum comparison value and the intermediate comparison value is adjusted to the threshold.

[0022] Optionally, the three comparison values ​​are compared to obtain the maximum comparison value, the middle comparison value, and the minimum comparison value;

[0023] When the difference between the intermediate comparison value and the minimum comparison value is less than the threshold, it is determined whether the difference between the intermediate comparison value and the threshold is greater than or equal to the second preset value; if it is greater than or equal to the threshold, the intermediate comparison value remains unchanged, and the minimum comparison value is adjusted to the difference between the intermediate comparison value and the threshold; otherwise, the minimum comparison value is adjusted to the second preset value, and the difference between the intermediate comparison value and the minimum comparison value is adjusted to the threshold.

[0024] Optionally, the adjusted three-phase PWM signals are delayed by the same amount of time to obtain three-phase delayed pulse signals;

[0025] Among them, the three-phase delayed pulse signal is used to control the switching transistors in the three-phase inverter circuit of the three-phase permanent magnet motor.

[0026] Optionally, the three-phase delay pulse signals are all used to control the high-side switching transistors in the three-phase inverter circuit, or all are used to control the low-side switching transistors in the three-phase inverter circuit.

[0027] Optionally, the delay time for the adjusted three-phase PWM signal is greater than or equal to the sampling and holding time of the ADC conversion circuit, wherein the ADC conversion circuit is used to perform analog-to-digital conversion on the signal sampled by the current sampling circuit.

[0028] Optionally, the current detection method further includes obtaining the phase current of the third phase based on the fact that the sum of the phase currents of two phases and the three phase currents is 0.

[0029] On the other hand, this application provides a three-phase permanent magnet motor drive module, including: a current sampling circuit for sampling the phase currents of at least two phases; an ADC conversion circuit for performing analog-to-digital conversion on the signals sampled by the current sampling circuit; a three-phase inverter circuit including three phase arms, each phase arm including a high-side switch and a low-side switch; and a control circuit for sampling and controlling the current sampling circuit according to the above-mentioned current detection method, and controlling the switches in the three-phase inverter circuit after the at least two phase currents sampled by the current sampling circuit are converted by the ADC conversion circuit.

[0030] Optionally, the current sampling circuit includes a sampling resistor and an amplifier circuit connected across the sampling resistor.

[0031] This application provides a current detection method, detection circuit, and drive module for a three-phase permanent magnet motor. By ensuring that the effective vector has a sufficiently long action time and sampling is performed before the effective vector action time ends, the current waveform is stable relative to the start of the effective vector action time, thereby ensuring that the sampled current is more stable and accurate. Attached Figure Description

[0032] The above and other objects, features, and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0033] Figure 1A This is a circuit diagram of a three-phase permanent magnet motor system according to an embodiment of this application;

[0034] Figure 1B This is a table showing the relationship between the current flowing through the sampling resistor and the phase current under different effective vector corresponding switch combinations in the embodiments of this application;

[0035] Figure 2 This is a schematic waveform diagram of the three-phase PWM signal of a three-phase permanent magnet motor according to an embodiment of this application;

[0036] Figure 3 This is a first flowchart of a current detection method for a three-phase permanent magnet motor according to an embodiment of this application;

[0037] Figure 4 These are two schematic waveform diagrams of the three-phase PWM signal of the three-phase permanent magnet motor according to an embodiment of this application;

[0038] Figure 5 This is a second flowchart of the current detection method for a three-phase permanent magnet motor according to an embodiment of this application;

[0039] Figure 6 This is a schematic waveform diagram of a single-phase PWM signal of a three-phase permanent magnet motor according to an embodiment of this application;

[0040] Figure 7 This is a third schematic waveform diagram of the three-phase PWM signal of the three-phase permanent magnet motor according to an embodiment of this application;

[0041] Figure 8 This is a fourth schematic waveform diagram of the three-phase PWM signal of a three-phase permanent magnet motor according to an embodiment of this application. Detailed Implementation

[0042] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0043] Those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

[0044] It should be understood that, in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic connection. When an element or circuit is said to be "connected" to another element, or when an element / circuit is said to be "connected" between two nodes, it can be a direct connection or a connection to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly connected" to another element, it means that there are no intermediate elements between them.

[0045] Unless the context explicitly requires it, words such as "including," "etc." throughout the application should be interpreted as having the meaning of "including but not limited to," rather than "exclusive" or "exhaustive."

[0046] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0047] Figure 1AFigure 1 shows a circuit diagram of a three-phase permanent magnet motor system according to the present invention. The three-phase permanent magnet motor system includes a three-phase permanent magnet motor, a current detection circuit 15, a control circuit 12, and a three-phase inverter circuit 14. The three-phase inverter circuit includes three-phase bridge arms, each bridge arm including a high-side switch and a low-side switch. The high-side and low-side switches are complementary in conduction. In practice, to prevent short circuits caused by direct conduction between the two switches, a short dead time is allowed when the high-side and low-side switches switch on and off, allowing both switches to be off. The current detection circuit 15 is used to detect the phase current flowing through at least two phases of the three-phase bridge arm.

[0048] The control circuit 12 is used to sample and control the current detection circuit according to the current detection method, and generate PWM (pulse width modulation) signals for the three-phase bridge arms: PWMa, PWMb, and PWMc based on the current of at least two phases sampled by the current detection circuit, thereby controlling the switching transistors in the three-phase inverter circuit.

[0049] The three-phase inverter circuit 14 includes switching transistors Q1 to Q6. Switches Q1 and Q2 serve as the high-side and low-side switches of phase a, respectively; switches Q3 and Q4 serve as the high-side and low-side switches of phase b, respectively; and switches Q5 and Q6 serve as the high-side and low-side switches of phase c, respectively. The switching transistors Q1 to Q6 are controlled by three-phase PWM signals. It is understood that each of the switching transistors Q1 to Q6 can have a freewheeling diode connected in parallel. Therefore, the control circuit 12 can control the conduction time of the switching transistors by controlling the pulse width of the PWM signal for each phase.

[0050] In pulse width modulation, the three-phase permanent magnet motor system in this embodiment uses space vector pulse width modulation (SVPWM). A space vector is formed based on the three-phase output voltage to control the six switching transistors in the three-phase bridge arms. Therefore, depending on the combination of switching transistors, there are six different effective vectors and two zero vectors, such as... Figure 1B As shown in the diagram, "ON" indicates that the corresponding switch is turned on, and "OFF" indicates that the corresponding switch is turned off. Different vectors correspond to different switch combinations, allowing the current detection circuit to sample the phase current flowing through the corresponding phase. Based on the relationship between the sampled phase current and the three-phase current of the motor, the current detection circuit can easily calculate the phase current of each phase, thereby reconstructing the three-phase currents Ia, Ib, and Ic.

[0051] like Figure 1AAs shown, the three-phase permanent magnet motor current detection circuit 15 includes a current sampling circuit 11 and an ADC conversion circuit 13. The current sampling circuit 11 includes a sampling resistor Rc and an amplifier circuit connected across the sampling resistor. The ADC conversion circuit 13 is used to perform analog-to-digital conversion on the signal sampled by the current sampling circuit. One end of the sampling resistor Rc is connected to the common connection point of the three-phase bridge arms, and the other end is connected to the negative terminal of the DC bus voltage Udc. In one embodiment, the amplifier circuit includes an operational amplifier.

[0052] Within one pulse width modulation cycle of SVPWM, there are two effective vectors. Two phase currents can be detected using these two different effective vectors. The remaining phase current is calculated using Kirchhoff's law that the sum of the three-phase currents is 0, i.e., Ia + Ib + Ic = 0, thus reconstructing the three-phase current. Current sampling requires time: from switch on-time to current stabilization, then to op-amp output establishment, and finally to ADC sampling. The duration of the effective vector must be greater than a preset interval to ensure the control module obtains accurate current information. However, conventional SVPWM modulation sometimes results in very short effective vector durations, such as... Figure 2 As shown, the three-phase PWM signals PWMA', PWMB' and PWMC' are used to control the bridge arms of phase a, phase b and phase c respectively. Within one pulse width modulation period, the time interval t between the falling edge of PWMB' and the falling edge of PWMC' is less than the preset interval t0. Therefore, it is necessary to phase shift the PWM signals so that the time interval between two adjacent falling edges is greater than or equal to the preset interval t0, thereby ensuring that the effective vector action time is long enough.

[0053] like Figure 3 As shown, this application proposes a current detection method for a three-phase permanent magnet motor. The detection method includes: within a pulse width modulation cycle, determining whether the interval between two adjacent falling edges in the three-phase PWM signal is less than a preset interval; when the interval between two adjacent falling edges is less than the preset interval, shifting at least one of the two PWM signals corresponding to the two adjacent falling edges to make the interval between the two adjacent falling edges the preset interval, and ensuring that the time interval between the falling edge of each phase PWM signal and the end or start time of the current pulse width modulation cycle is within a preset range, thereby making the time interval between adjacent falling edges greater than or equal to the preset interval; wherein, the current sampling circuit is sampled at the corresponding times of the second and third falling edges of the three-phase PWM signal in the current pulse width modulation cycle to obtain the phase current of two phases.

[0054] In one implementation, when the interval between two adjacent falling edges is less than a preset interval, the interval between adjacent falling edges is configured to the preset interval by keeping one phase of the PWM signal unchanged and shifting the other phase of the PWM signal. As an example, the rising and falling edges of the PWM signal are generated by comparing a carrier signal and a comparison value. Therefore, in one example of this embodiment, the control circuit can shift the PWM signal by simultaneously changing the magnitude of the comparison value corresponding to the rising and falling edges. PWM signal shifting only changes the positions of the falling and rising edges of the PWM signal, without changing the pulse width or duty cycle.

[0055] See again Figure 2 For example, such as Figure 2 The three-phase PWM signals, represented by solid lines (PWMA', PWMB', and PWMB'), are the signals before adjustment, while PWMA, represented by dashed lines, is the signal after adjustment. The time interval t between the falling edges of PWMA' and PWMB' is less than a preset interval t0. That is, before adjustment, the time interval t between the second and third falling edges is less than the preset interval t0. By keeping PWMB' corresponding to the second falling edge unchanged and only shifting PWMA' to the right to obtain PWMA, the time interval t between the second and third falling edges is adjusted to be equal to the preset interval t0. That is, after adjustment, the time interval between the falling edges of PWMB and PWMA' is equal to the preset interval t0, and the falling edges of all three adjusted PWM signals are within the preset interval.

[0056] In another implementation, when the interval between two adjacent falling edges is less than a preset interval, the two PWM signals corresponding to the two adjacent falling edges are shifted so that the falling edge of one phase of the PWM signal coincides with a preset cutoff start or preset cutoff end in the current pulse width modulation period, thereby making the interval between the two adjacent falling edges the preset interval. Specifically, this is achieved by shifting the two PWM signals corresponding to the two adjacent falling edges in opposite directions so that the falling edge of one phase of the PWM signal coincides with a preset cutoff start or preset cutoff end in the current pulse width modulation period, thus making the interval between the two adjacent falling edges the preset interval.

[0057] Specifically, the preset cutoff start point and preset cutoff end point are both endpoint values ​​corresponding to a preset interval; that is, the preset cutoff start point is one endpoint value corresponding to a preset interval, and the preset cutoff end point is the other endpoint value corresponding to the preset interval. By setting a preset interval corresponding to the preset cutoff start point and preset cutoff end point, where the left endpoint of the preset interval is the preset cutoff start point and the right endpoint is the preset cutoff end point, the interval between the falling edge of the shifted three-phase PWM signal and the start or end time of the pulse width modulation period is made to be within the preset interval, thereby maintaining a certain interval between the falling edge of the adjusted PWM signal and the start or end time of the pulse width modulation period.

[0058] More specifically, when the time interval between the third falling edge and the second falling edge is less than a preset interval, it is determined whether the sum of the time corresponding to the second falling edge and the preset interval is less than or equal to a preset cutoff point. If it is less than or equal to, the PWM signal corresponding to the second falling edge remains unchanged, and the PWM signal corresponding to the third falling edge is shifted so that the third falling edge is adjusted to the time corresponding to the sum of the time corresponding to the second falling edge and the preset interval. Otherwise, when the sum of the time corresponding to the second falling edge and the preset interval is greater than the preset cutoff point, the PWM signal corresponding to the third falling edge is shifted so that the third falling edge is adjusted to the time corresponding to the preset cutoff point, and the time interval between the second and third falling edges is equal to the preset interval by shifting the PWM signal corresponding to the second falling edge. During the adjustment process, the PWM signal corresponding to the third falling edge is shifted to the right, and the PWM signal corresponding to the second falling edge is shifted to the left.

[0059] like Figure 4 As shown, the solid lines represent the three-phase PWM signals: PWMA', PWMB', and PWMB' are the signals before adjustment, while the dashed lines represent PWMA and PWMB' are the signals after adjustment. Before adjustment, when the interval t between the second and third falling edges is less than the preset interval t0, the two PWM signals corresponding to the second and third falling edges, PWMA' and PWMB', are shifted so that the falling edge of PWMA' corresponding to the third falling edge coincides with the preset cutoff endpoint in the current pulse width modulation period, thus making the interval between the second and third falling edges the preset interval t0. Figure 4In the process, the sum of the time corresponding to the falling edge of PWMB' and the preset interval t0 is greater than the preset cutoff endpoint. Therefore, PWMA' corresponding to the third falling edge is shifted to the right to obtain PWMA, so that the falling edge of PWMA is adjusted to the time corresponding to the preset cutoff endpoint. At the same time, PWMB' is shifted to the left to obtain PWMB, so that the time interval between the second and third falling edges is equal to the preset interval t0, thus making the time interval between the falling edges of PWMA and PWMB equal to the preset interval t0.

[0060] Optionally, when the time interval between the second falling edge and the first falling edge is less than a preset interval, it is determined whether the difference between the time corresponding to the second falling edge and the preset interval is greater than or equal to a preset cutoff start point. If it is greater than or equal to, the PWM signal corresponding to the second falling edge remains unchanged, and the first falling edge is adjusted to the time corresponding to the sum of the time corresponding to the second falling edge and the preset interval by shifting the PWM signal corresponding to the first falling edge. Otherwise, when the difference between the time corresponding to the second falling edge and the preset interval is less than the preset cutoff start point, the PWM signal corresponding to the first falling edge is shifted to adjust the time corresponding to the first falling edge to the time corresponding to the preset cutoff start point, and the time interval between the second falling edge and the first falling edge is equal to the preset interval by shifting the PWM signal corresponding to the second falling edge. During the adjustment process, the PWM signal corresponding to the second falling edge is shifted to the right, and the PWM signal corresponding to the first falling edge is shifted to the left. As an example, the second and third falling edges of the three-phase PWM signals within the pulse width modulation period can be identified by comparing the pulse widths of the three-phase PWM signals, and it can be determined whether the interval between adjacent falling edges in the three-phase PWM signals is less than the preset interval. Within each pulse width modulation cycle, the pulse widths of the three-phase PWM signals are compared to identify the first PWM signal with the largest pulse width, the second PWM signal with the second largest pulse width, and the third PWM signal with the smallest pulse width. It is then determined whether the interval between the falling edges of the first PWM signal and the second PWM signal is less than a preset interval, and whether the interval between the falling edges of the second PWM signal and the third PWM signal is less than a preset interval.

[0061] like Figure 5As shown, as an example, the duty cycle of the three-phase PWM signal in the current pulse width modulation cycle is calculated based on the phase currents of the two phases sampled in the previous pulse width modulation cycle; three comparison values ​​are then calculated to generate the three-phase PWM signal based on the duty cycle. As another example, the method for generating the three-phase PWM signal is as follows: a counter counts upwards from 0 to the auto-reload value, then counts downwards back to 0, forming a symmetrical triangular wave carrier; the on / off state of the three-phase switching transistors is determined by comparing the counter value with the comparison values, ultimately achieving the output of a low-harmonic three-phase PWM signal. The rising and falling edges of the PWM signal are controlled by comparing the counter value and the comparison values. Therefore, the time interval between two adjacent falling edges can be determined by comparing the three comparison values ​​to see if it is less than a preset interval.

[0062] As an example, by controlling the comparison value used to generate the falling edge of the PWM signal to be less than or equal to a first preset value and greater than or equal to a second preset value, the interval between the falling edge of each phase PWM signal and the end or start time of the current pulse width modulation period is within a preset range.

[0063] like Figure 5 As shown, the magnitudes of three comparison values ​​corresponding to the three-phase modulation wave that generates the three-phase PWM signal are compared to obtain the maximum comparison value, the intermediate comparison value, and the minimum comparison value. It is then determined whether the difference between the maximum comparison value and the intermediate comparison value is less than a threshold. When the difference between the maximum comparison value and the intermediate comparison value is less than the threshold, it is determined whether the sum of the intermediate comparison value and the threshold is less than or equal to a first preset value. When it is less than or equal to the threshold, the intermediate comparison value remains unchanged, and the maximum comparison value is increased by the threshold, that is, the maximum comparison value is adjusted to the sum of the intermediate comparison value and the threshold. Otherwise, the maximum comparison value is adjusted to the first preset value, and the difference between the maximum comparison value and the intermediate comparison value is reduced to the threshold.

[0064] like Figure 5 As shown, it is determined whether the difference between the intermediate comparison value and the minimum comparison value is less than a threshold; when the difference between the intermediate comparison value and the minimum comparison value is less than the threshold, it is determined whether the difference between the intermediate comparison value and the threshold is greater than or equal to a second preset value; when it is greater than or equal to, the intermediate comparison value remains unchanged, and the minimum comparison value is reduced by the threshold, that is, the minimum comparison value is adjusted to the difference between the intermediate comparison value and the threshold; otherwise, the minimum comparison value is adjusted to the second preset value, and the difference between the intermediate comparison value and the minimum comparison value is adjusted to the threshold.

[0065] The falling edges of the three-phase PWM signals are generated by adjusting the difference between adjacent comparison values ​​to be greater than or equal to the threshold corresponding to the minimum, intermediate, or maximum comparison value. During the adjustment process, the rising edges of the corresponding phase PWM signals are generated by reversing the minimum, intermediate, or maximum comparison values ​​corresponding to the three falling edges, thereby achieving PWM signal shifting. Specifically, during the adjustment process, when the comparison value corresponding to the falling edge of a phase PWM signal increases, the comparison value is decreased by the same amount to generate the rising edge of the same phase PWM signal; conversely, when the comparison value corresponding to the falling edge of a phase PWM signal decreases, the comparison value is increased by the same amount to generate the rising edge of the same phase PWM signal, thus keeping the duty cycle unchanged and achieving shifting of the phase PWM signal.

[0066] like Figure 6 As shown, taking one phase PWM signal PWMA as an example, before adjustment, signal PWMA... ， Both the rising and falling edges of the PWMA signal are generated using the same comparison value CMP. During adjustment, the falling edge of the PWMA signal is generated by increasing the comparison value CMP by ΔS to obtain the comparison value CMP2, and the rising edge is generated by decreasing the comparison value CMP by ΔS to obtain the comparison value CMP1. CMP1 < CMP < CMP2, and CMP - CMP1 = CMP2 - CMP = ΔS; thus ensuring that the PWMA signal and the PWMA signal are consistent. ， The duty cycle of the signal is consistent, thus achieving control of PWMA. ， The rising and falling edges of the signal are both shifted by a time ∆t, thereby realizing the PWMA ， The signal is shifted by a time ∆t to obtain the PWMA signal.

[0067] It should be noted that, Figure 6 The example only demonstrates how to shift the PWM signal by inverting the comparison values ​​of the rising and falling edges. In other examples, the falling edge can be shifted by decreasing the comparison value CMP, and the rising edge can be shifted by increasing the comparison value CMP. In other examples, two or three phases of the PWM signal may be shifted during the adjustment process, which is not limited here.

[0068] In addition, the adjusted three-phase PWM signals need to be delayed by the same time to obtain three-phase delayed pulse signals. These three-phase delayed pulse signals are used to control the switching transistors in the three-phase inverter circuit of the three-phase permanent magnet motor. Either all three delayed pulse signals are used to control the high-side switching transistors in the three-phase inverter circuit, or all three are used to control the low-side switching transistors. The current sampling circuit samples the current at the corresponding moments of the second and third falling edges of the three-phase PWM signals within the current pulse width modulation period to obtain the phase current of two phases.

[0069] like Figure 7 As shown in the figure, as an example, signals PWMA, PWMB, and PWMC are adjusted three-phase PWM signals, and all are used to control the high-side switching transistors in the three-phase inverter circuit. PWMA, PWMB, and PWMC are delayed by the same delay time tdelay to obtain the first delayed pulse signal PWMA_1, the second delayed pulse signal PWMB_1, and the third delayed pulse signal PWMC_1. Among them, the first delayed pulse signal PWMA_1, the second delayed pulse signal PWMB_1, and the third delayed pulse signal PWMC_1 are used to control the switching transistors in the three-phase inverter circuit of the three-phase permanent magnet motor.

[0070] like Figure 7 The sampling time corresponding to the second falling edge in a pulse width modulation cycle (corresponding to the falling edge of the PWMB signal in the figure) is taken as sampling point 1, and the sampling time corresponding to the third falling edge in the same pulse width modulation cycle (corresponding to the falling edge of the PWMA signal in the figure) is taken as sampling point 2. The sampling resistor Rc in Figure 1 samples at the times corresponding to sampling point 1 and sampling point 2 respectively, so as to realize the sampling of phase current by delaying the effective vector action time by tdelay in advance, thereby ensuring that the sampled current is more stable and more accurate.

[0071] The above example uses three high-side switches in a three-phase inverter circuit as examples where the three-phase PWM signals are all part of the circuit, but this is not a limitation. Figure 8 As shown, this illustrates how the time interval between adjacent falling edges, after adjustment, is greater than or equal to a preset interval. This is used to control the three-phase delay pulse signals PWMA_1, PWMB_1, and PWMC_1 of the three high-side switches Q1, Q3, and Q5 in Figure 1. By controlling the time intervals t2 and t3 to be greater than or equal to the preset interval, the effective vector's duration is made sufficiently long. Figure 8As shown, a pulse width modulation cycle includes two effective vectors, used to detect the phase current Ia of phase a at time interval t2 or t6, and to detect the phase current Ic of phase c at time interval t3 or t5. From the above analysis, the sampling time corresponding to the falling edge of the PWMB signal is taken as sampling time S1, and the sampling time corresponding to the falling edge of the PWMA signal is taken as sampling time S2. The interval between sampling time S1 and the falling edge of the second delayed pulse signal PWMB_1, and the interval between sampling time S2 and the falling edge of the third delayed pulse signal PWMC_1, are maintained as the delay time tdelay. Figure 8 PWMB and PWMC are not shown in the figure, such as Figure 7 As shown, PWMB_1 and PWMC_1 are obtained by delaying PWMB and PWMC by the same delay time tdelay, respectively. Thus, sampling is performed at the sampling time S1 before the end of the effective vector, that is, at time S1 before the end of time interval t2 and at time S2 before the end of time interval t3, avoiding sampling at the beginning of the effective vector (as shown at time S11 and time S12 in the figure).

[0072] same, Figure 8 The diagram also illustrates the three-phase delayed pulse signals PWMA_L, PWMB_L, and PWMC_L used to control the three low-side switches Q2, Q4, and Q6 in Figure 1. By controlling the time intervals t5 and t6 to be greater than or equal to a preset interval, the effective vector's duration is made sufficiently long. As analyzed above, the interval between sampling time S3 and the falling edge of PWMB_L, and the interval between sampling time S4 ​​and the falling edge of PWMA_L, are maintained at a delay time tdelay. This ensures that sampling occurs at sampling times S3 and S4 before the effective vector's holding time ends, avoiding sampling at the beginning of the effective vector (e.g., ...). Figure 8 The sampling method, based on capturing the second and third falling edges of the three-phase PWM signal within the same pulse width modulation period corresponding to the three high-side or three low-side switches and sampling them in advance, ensures that the sampling point is at the moment before the high-side or low-side switches are turned off. This eliminates the need to shield the transient conduction process of the switches, ensuring that the current is stable at the time of sampling.

[0073] At the same time Figure 8It can be seen that, regardless of whether the signal is used to control the three-phase high-side switching transistor or the signal is used to control the three-phase low-side switching transistor, within the same pulse width modulation period, the second falling edge and the third falling edge correspond to the falling edge corresponding to the second and maximum pulse width signals, respectively. Therefore, the second and third falling edges within the same pulse width modulation period can also be determined by detecting and sorting the pulse widths.

[0074] In summary, this invention discloses a current detection method and detection circuit for a three-phase permanent magnet motor provided in this application embodiment. It can reconstruct the three-phase current by comparing the duty cycle, which can reduce the complexity of the algorithm. Furthermore, by sampling the phase current at the moment before the effective vector action time ends, the bus current is more stable at the sampling moment.

[0075] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A current detection method for a three-phase permanent magnet motor, characterized in that, include: Within a pulse width modulation cycle, determine whether the interval between two adjacent falling edges in the three-phase PWM signal is less than a preset interval; When the interval between two adjacent falling edges is less than the preset interval, at least one of the two PWM signals corresponding to the two adjacent falling edges is shifted to make the interval between the two adjacent falling edges the preset interval, and the time interval between the falling edge of each phase PWM signal and the end or start time of the current pulse width modulation period is within the preset range, so that the time interval between adjacent falling edges is greater than or equal to the preset interval. The current sampling circuit samples the two phase currents at the corresponding moments of the second and third falling edges of the three-phase PWM signals within the current pulse width modulation period.

2. The current detection method according to claim 1, characterized in that: When the interval between two adjacent falling edges is less than the preset interval, the interval between adjacent falling edges is configured to the preset interval by keeping one phase of the PWM signal unchanged and shifting the other phase of the PWM signal.

3. The current detection method according to claim 1, characterized in that: When the interval between two adjacent falling edges is less than the preset interval, the two PWM signals corresponding to the two adjacent falling edges are shifted so that the falling edge of one phase PWM signal is consistent with the preset cutoff start point or preset cutoff end point in the current pulse width modulation period, so that the interval between two adjacent falling edges is the preset interval.

4. The current detection method according to claim 3, characterized in that: By shifting the two PWM signals corresponding to two adjacent falling edges in opposite directions, the falling edge of one phase PWM signal is made to coincide with the preset cutoff start point or preset cutoff end point in the current pulse width modulation period, so that the interval between two adjacent falling edges is a preset interval.

5. The current detection method according to claim 3, characterized in that: The preset cutoff start point is one of the endpoint values ​​corresponding to the preset interval, and the preset cutoff end point is the other endpoint value corresponding to the preset interval.

6. The current detection method according to claim 1, characterized in that, Also includes: By comparing the pulse widths of the three-phase PWM signals, it is determined whether the interval between adjacent falling edges in the three-phase PWM signals is less than a preset interval.

7. The current detection method according to claim 6, characterized in that: Within each pulse width modulation cycle, the pulse widths of the three-phase PWM signals are compared to identify the first PWM signal with the largest pulse width, the second PWM signal with the second largest pulse width, and the third PWM signal with the smallest pulse width. Determine whether the interval between the falling edge of the first PWM signal and the falling edge of the second PWM signal is less than a preset interval, and whether the interval between the falling edge of the second PWM signal and the falling edge of the third PWM signal is less than a preset interval.

8. The current detection method according to claim 1, characterized in that, include: Based on the phase currents of the two phases sampled in the previous pulse width modulation cycle, calculate the duty cycle of the three-phase PWM signal in the current pulse width modulation cycle. The three comparison values ​​corresponding to the three-phase modulation wave of the generated three-phase PWM signal are calculated based on the duty cycle. The time interval between two adjacent falling edges is determined by comparing the three comparison values.

9. The current detection method according to claim 8, characterized in that: The time interval between two adjacent falling edges is determined by comparing whether the difference between two adjacent comparison values ​​is less than a threshold. When the difference between two adjacent comparison values ​​is less than a threshold, at least one of the two adjacent comparison values ​​is adjusted so that the difference between the two adjacent comparison values ​​is the threshold, and each comparison value is less than or equal to a first preset value and greater than or equal to a second preset value, so that the difference between the adjacent comparison values ​​is greater than or equal to the threshold.

10. The current detection method according to claim 9, characterized in that: The falling edges of the three-phase PWM signals are generated based on the adjusted three comparison values. By changing the minimum comparison value, the intermediate comparison value, or the maximum comparison value in reverse by equal amounts, the rising edge of the corresponding phase PWM signal is generated, thereby achieving the translation of the PWM signal.

11. The current detection method according to claim 8, characterized in that: Ensuring that the interval between the falling edge of each phase PWM signal and the end or start time of the current pulse width modulation period is within a preset range includes: ensuring that the comparison value corresponding to the modulation wave of the falling edge of the PWM signal of the corresponding phase is less than or equal to a first preset value and greater than or equal to a second preset value.

12. The current detection method according to claim 11, characterized in that: The three comparison values ​​are compared to obtain the maximum comparison value, the middle comparison value, and the minimum comparison value; When the difference between the maximum comparison value and the intermediate comparison value is less than the threshold, determine whether the sum of the intermediate comparison value and the threshold is less than or equal to the first preset value; When the value is less than or equal to the threshold, the intermediate comparison value remains unchanged, and the maximum comparison value is adjusted to the sum of the intermediate comparison value and the threshold. Otherwise, the maximum comparison value is adjusted to the first preset value, and the difference between the maximum comparison value and the intermediate comparison value is adjusted to the threshold.

13. The current detection method according to claim 11, characterized in that: The three comparison values ​​are compared to obtain the maximum comparison value, the middle comparison value, and the minimum comparison value; When the difference between the intermediate comparison value and the minimum comparison value is less than the threshold, it is determined whether the difference between the intermediate comparison value and the threshold is greater than or equal to the second preset value; if it is greater than or equal to the threshold, the intermediate comparison value remains unchanged, and the minimum comparison value is adjusted to the difference between the intermediate comparison value and the threshold; otherwise, the minimum comparison value is adjusted to the second preset value, and the difference between the intermediate comparison value and the minimum comparison value is adjusted to the threshold.

14. The detection method according to claim 1, characterized in that: The three-phase PWM signals that have been adjusted are delayed by the same amount of time to obtain three-phase delayed pulse signals; Among them, the three-phase delayed pulse signal is used to control the switching transistors in the three-phase inverter circuit of the three-phase permanent magnet motor.

15. The current detection method according to claim 14, characterized in that, The current detection method further includes: The three-phase delay pulse signals are all used to control the high-side switching transistors in the three-phase inverter circuit, or all used to control the low-side switching transistors in the three-phase inverter circuit.

16. The detection method according to claim 15, characterized in that: The time for delaying the adjusted three-phase PWM signal is greater than or equal to the sampling and holding time of the ADC conversion circuit, wherein the ADC conversion circuit is used to perform analog-to-digital conversion on the signal sampled by the current sampling circuit.

17. The current detection method according to claim 1, characterized in that, The current detection method further includes: The phase current of the third phase is obtained by considering that the sum of the phase currents of two phases and the three phase currents is zero.

18. A three-phase permanent magnet motor drive module, characterized in that, include: A current sampling circuit is used to sample the phase current of at least two phases; An ADC conversion circuit is used to perform analog-to-digital conversion on the signal sampled by the current sampling circuit. A three-phase inverter circuit includes three phase arms, each phase arm including a high-side switch and a low-side switch; A control circuit is used to sample and control the current sampling circuit according to the current detection method according to any one of claims 1 to 17, and to control the switching transistors in the three-phase inverter circuit after the current sampling circuit samples at least two phase currents and converts them through an ADC conversion circuit.

19. The motor drive module according to claim 18, characterized in that: The current sampling circuit includes a sampling resistor and an amplifier circuit connected across the sampling resistor.

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