Processing circuitry, control method and electronic device for data access

Abstract

A data access processing circuit, control method, and electronic device are disclosed. The circuit, used for data access between multiple functional modules and a system bus, includes: an arbitration circuit connected to the multiple functional modules, configured to receive access request signals and urgency signals sent by the multiple functional modules, determine a target functional module from the multiple functional modules based on the urgency signal, send a confirmation signal to the target functional module, and generate internal operation instructions based on the access request signals; and a conversion circuit connected to the arbitration circuit, the multiple functional modules, and the system bus, configured to receive the internal operation instructions, convert the internal operation instructions into bus operation instructions conforming to the system bus protocol and send them to the system bus, and transmit data corresponding to the bus operation instructions between the system bus and the target functional module. This application has the technical effect of improving data access processing efficiency.

Description

Technical Field

[0001] This application relates to the field of data access technology, and in particular to a data access processing circuit, control method, and electronic device. Background Technology

[0002] With the rapid development of integrated circuit technology, the design of System-on-Chip (SoC) is becoming increasingly complex, and the number of integrated functional modules is constantly increasing. In a chip system, each functional module typically needs to access external memory (such as DDR) or other peripherals through a bus interface. Currently, the Advanced eXtensible Interface (AXI) has become a widely adopted bus standard in the industry due to its high performance. However, the standard AXI bus protocol includes multiple channels for reading and writing addresses, data, and responses, resulting in a large number of interface signals with complex timing. When a system contains a large number of functional modules, connecting each module through a standard AXI interface would consume enormous wiring resources and increase the complexity of circuit design. Therefore, improving the processing efficiency of multi-channel data access is a crucial issue. Summary of the Invention

[0003] In view of this, embodiments of this application provide a data access processing circuit, control method, and electronic device, in order to improve the processing efficiency of data access by multiple functional modules in an integrated circuit.

[0004] In a first aspect, a data access processing circuit is provided for data access between multiple functional modules and a system bus, comprising: an arbitration circuit, connected to the multiple functional modules respectively, configured to receive access request signals and urgency signals sent by the multiple functional modules, determine a target functional module from the multiple functional modules according to the urgency signal, send a confirmation signal to the target functional module, and generate an internal operation instruction according to the access request signal; and a conversion circuit, connected to the arbitration circuit, the multiple functional modules, and the system bus respectively, configured to receive the internal operation instruction, convert the internal operation instruction into a bus operation instruction conforming to the system bus protocol and send it to the system bus, and transmit data corresponding to the bus operation instruction between the system bus and the target functional module.

[0005] The data access processing circuit described above optimizes interface efficiency when multiple modules share a bus through a specific architectural design. In this circuit, the arbitration circuit acts as the decision-making center for multiple access requests. An urgency signal is introduced, allowing each functional module to select the most pressing task as the target functional module based on its real-time operating status. The arbitration circuit then generates concise internal operation instructions, which are converted into bus operation instructions by a conversion circuit to establish a bridge between the system bus and the target functional module, completing the data access. This technical solution effectively improves data access processing efficiency, simplifies the interface design of each functional module, and eliminates the need for each module to independently maintain complex bus logic. Instead, it only requires providing data access requests and urgency signals, significantly reducing the design complexity of functional modules and the consumption of chip routing resources. Furthermore, it ensures timely responses to critical tasks or high-bandwidth-demand tasks, improving the overall system's data throughput efficiency and bus utilization.

[0006] Optionally, the arbitration circuit includes a write arbitration sub-circuit and a read arbitration sub-circuit; the conversion circuit includes a write conversion sub-circuit and a read conversion sub-circuit; wherein, when multiple functional modules are writing data, they form a write data channel with the write arbitration sub-circuit and the write conversion sub-circuit, and the write data channel is used to process write data transmission requests generated by multiple functional modules; when multiple functional modules are reading data, they form a read data channel with the read arbitration sub-circuit and the read conversion sub-circuit, and the read data channel is used to process read data transmission requests generated by multiple functional modules.

[0007] Optionally, when multiple functional modules are writing data, the urgency signal is used to characterize the urgency of the data to be transmitted by the functional modules; wherein, when the amount of data to be transmitted is greater than or equal to a preset data amount threshold, or when the data transmission of the functional module is in an uninterruptible state, a first-priority urgency signal is output; when the amount of data to be transmitted back up in the functional module is less than the preset data amount threshold, or when the data transmission of the functional module is in an intermittent state, a second-priority urgency signal is output; wherein, the first priority is higher than the second priority.

[0008] Optionally, the urgency signal is also used to characterize the bandwidth gap of the functional module, and is configured to be determined based on the data transmission difference between the actual data transmission amount and the predicted data transmission amount of the functional module within a preset time interval; wherein, when the data transmission difference indicates that the actual data transmission amount of the functional module is less than the predicted data transmission amount, the priority of the urgency signal is determined based on the magnitude of the difference.

[0009] Optionally, the internal operation instructions include: the module identifier, access address, and data length of the target functional module; the arbitration circuit is configured to package the access address, data length, and module identifier sent by the target functional module to generate internal operation instructions.

[0010] Optionally, when the access request signal is a write request signal, the conversion circuit is configured to parse the internal operation instruction, generate a write command bus operation instruction according to the system bus protocol, and send it to the system bus; when the system bus allows the target functional module to perform a write data operation based on the write command bus operation instruction, the conversion circuit sends a first control signal to the target functional module; the target functional module sends the data to be written to the system bus through the conversion circuit based on the first control signal.

[0011] Optionally, when the access request signal is a read request signal, the conversion circuit is configured to parse the internal operation instruction, generate a read command bus operation instruction according to the system bus protocol, and send it to the system bus; when the system bus allows the target functional module to perform a read data operation based on the read command bus operation instruction, the conversion circuit sends a second control signal to the target functional module; the target functional module obtains the data to be read from the system bus through the conversion circuit based on the second control signal.

[0012] Optionally, it also includes: a register configured to store bus control parameters corresponding to the functional module; a conversion circuit configured to look up the corresponding bus control parameters based on the module identifier in the internal operation instructions, and generate bus operation instructions in combination with the internal operation instructions; wherein, the system bus is an AXI bus.

[0013] In a second aspect, a data access control method is provided, applied to the data access processing circuit provided in the first aspect, comprising: receiving access request signals and urgency signals sent by multiple functional modules; in response to at least one urgency signal, determining a target functional module from the multiple functional modules and feeding back an acknowledgment signal to the target functional module; generating a bus operation command based on the access request signal of the target functional module and sending it to the system bus; and in response to the feedback signal of the system bus, transmitting data corresponding to the bus operation command between the system bus and the target functional module.

[0014] Thirdly, an electronic device is provided, including the data access processing circuitry provided in the first aspect. Attached Figure Description

[0015] The following is a brief introduction to the accompanying drawings used in the description of the embodiments of this application: Figure 1 This paper illustrates a system architecture diagram of multiple functional modules and an AXI bus provided in some embodiments of this application; Figure 2 This paper illustrates a system architecture diagram of multiple functional modules, an arbitrator, and an AXI bus provided in some embodiments of this application. Figure 3A schematic diagram of the structure of a data access processing circuit provided in some embodiments of this application is shown; Figure 4 A schematic diagram of the structure of another data access processing circuit provided in some embodiments of this application is shown; Figure 5 The diagram illustrates the signal interaction and data transmission of a multi-channel data access processing circuit provided in some embodiments of this application; Figure 6 A flowchart illustrating a data access control method provided in some embodiments of this application is shown. Detailed Implementation

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, examples of implementation methods of this application will be described below with reference to the accompanying drawings. The accompanying drawings described below are merely some embodiments of this application. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without creative effort. Adjustments and improvements made without departing from the concept of this application are all within the protection scope of this application.

[0017] To keep the drawings simple, each figure only schematically shows the parts relevant to the embodiment, and they do not represent the actual structure of the product. In addition, for the sake of clarity and ease of understanding, some figures only schematically show parts of components with the same structure or function, and there may actually be more or fewer components with the same structure or function.

[0018] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish and describe related objects, and should not be construed as indicating or implying the relative importance or order between related objects; furthermore, they do not represent the quantity of related objects. "Multiple" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between related objects, indicating an "or" relationship between them. "And / or" is used to describe the relationship between related objects, including any combination relationship between them, such as "a and / or b" including: "a alone," "b alone," or "a and b." "One or more" or "at least one" of multiple objects refers to any object or any combination of multiple objects, such as "one or more of a1, a2, a3" or "at least one of a1, a2, a3" including: "a1 alone," "a2 alone," "a3 alone," "a1 and a2," "a1 and a3," "a2 and a3," or "a1, a2 and a3."

[0019] In complex chip system designs, to meet the high data throughput requirements of applications such as multimedia processing and artificial intelligence computing, the system typically contains multiple functional subsystems, each integrating several specific functional modules. These modules frequently need to access external memory, such as dynamic random access memory, via the on-chip bus. To standardize these access behaviors, the AXI bus protocol is currently mainly used to implement the connection and scheduling between functional modules and memory. Furthermore, each functional module needs to independently maintain a complete set of AXI bus interface logic. Figure 1 This diagram illustrates a system architecture diagram of multiple functional modules and an AXI bus, provided in some embodiments of this application. In this system, to meet the connection and data access requirements of each functional module, each independent functional module is equipped with its own standard AXI bus interface. For example, based on the module's functional attributes, some functional modules (Module 4 to Module 6) are configured as AXI master interfaces (Master 4 to Master 6), while some functional modules (Module 1 to Module 3) are configured as AXI slave interfaces. Each functional module connects directly to the AXI bus through its own independent interface, thereby enabling data interaction and access. In a subsystem architecture, the AXI interfaces of multiple modules are typically aggregated into an arbitrator, and after arbitration, connected to the system bus through a common AXI port. Figure 2This diagram illustrates a system architecture diagram of multiple functional modules, an arbitrator, and an AXI bus provided in some embodiments of this application. The system includes functional subsystems (such as a first subsystem M1 and a second subsystem M2), each of which integrates multiple specific functional modules. Taking the first subsystem M1 as an example, it includes a fourth functional module Module4, a fifth functional module Module5, and a sixth functional module Module6. To avoid the excessive bus size and resource consumption caused by all module interfaces directly connecting to the system bus, this architecture adopts an interface aggregation optimization measure. For example, access requests initiated by the fourth functional module Module4 to the sixth functional module Module6 need to be arbitrated by the first arbitrator Arbiter1 within the subsystem. After obtaining authorization, they are then connected to the AXI bus through a single AXI interface. Similarly, the modules within the second subsystem M2 are also aggregated through the second arbitrator Arbiter2 before being connected to the system. In addition, the AXI bus also connects the first functional module Module1, the second functional module Module2, and the third functional module Module3 as slave devices. Although this design achieves interconnection, it exposes significant drawbacks in practical applications. To support high-performance transmission, the AXI protocol defines an extremely rich set of interface signals, including dozens of signal paths such as read address channels, read data channels, write address channels, and write data channels. When the number of modules is large, this channel redundancy leads to extremely complex internal wiring, severely consuming routing resources and hindering chip area optimization. Secondly, in terms of arbitration control for multi-access, the arbitrator struggles to perceive the actual operating status of each module. For example, it cannot distinguish whether a module urgently needs to write data due to severe backlog or is simply performing routine periodic access, nor can it determine whether the module's current actual bandwidth is significantly lower than its predicted requirements. This arbitration mechanism, lacking business awareness, can easily lead to critical tasks not receiving timely responses, while non-urgent tasks consume valuable bus bandwidth, thereby reducing the overall system efficiency. Therefore, this application provides a multi-data access processing circuit and method. By simplifying the structure between modules and the bus and introducing a dynamic priority mechanism based on transaction urgency and bandwidth gaps, it aims to improve the efficiency of data access between multiple functional modules within an integrated circuit and the system bus while reducing hardware design complexity.

[0020] Figure 3A schematic diagram of a data access processing circuit provided in some embodiments of this application is shown. This data access processing circuit 300 is used for data access between multiple functional modules and the system bus, and includes: an arbitration circuit 310, connected to multiple functional modules (e.g., the first functional module Module1 to the third functional module Module3 in the figure), configured to receive access request signals and urgency signals sent by the multiple functional modules, determine a target functional module from the multiple functional modules based on the urgency signal, send a confirmation signal to the target functional module, and generate internal operation instructions based on the access request signals; and a conversion circuit 320, connected to the arbitration circuit 310, the multiple functional modules, and the system bus 10, configured to receive the internal operation instructions, convert the internal operation instructions into bus operation instructions conforming to the system bus protocol and send them to the system bus 10, and transmit data corresponding to the bus operation instructions between the system bus 10 and the target functional module.

[0021] The data access processing circuit 300 can be integrated into the system-on-a-chip (SoC) as a bridge connecting multiple functional modules and the system bus 10, enabling efficient management of data access. The arbitration circuit 310 can establish connections with multiple functional modules (e.g., the first functional module Module1 to the third functional module Module3 shown in the figure). Functional modules can be any hardware unit within the chip that needs to access external memory or shared resources, such as a central processing unit (CPU), graphics processing unit (GPU), digital signal processor (DSP), direct memory access controller (DRAM), or video codec engine. The arbitration circuit 310 can receive access request signals from various functional modules, as well as urgency signals reflecting the current task priority status of each functional module. Based on the received urgency signals, the arbitration circuit 310 arbitrates among the requesting functional modules to determine the target functional module currently entitled to bus access, and sends a confirmation signal to the target functional module to complete the handshake response. In this application, the arbitration circuit 310 can generate internal operation instructions based on the access request signals sent by the target functional module and transmit these instructions to subsequent circuits. Internal operation instructions refer to intermediate control commands transmitted within the processing circuit 300 after arbitration integration. The internal operation instructions, not yet converted into a complex bus protocol format, encapsulate the key parameters required to complete a data access, such as the module identifier of the target functional module, the access address in the system memory, and the length of the data to be transmitted. The conversion circuit 320 can be connected to the arbitration circuit 310, multiple functional modules, and the system bus 10, serving as a protocol adapter and data path. The conversion circuit 320 receives the internal operation instructions from the arbitration circuit 310 and, according to the standard protocol specifications followed by the system bus 10, such as the AXI bus protocol, converts the internal operation instructions into bus operation instructions that meet timing requirements. These instructions can directly drive the system bus 10 to operate using standard protocol signals. For example, under the AXI protocol, these instructions correspond to control signals such as AWID, AWADDR, and AWLEN on the write address channel, or ARID, ARADDR, and ARLEN on the read address channel. Subsequently, the conversion circuit 320 sends these bus operation instructions to the system bus 10 to initiate the actual bus transmission transaction. The conversion circuit 320 can also establish a data transmission channel to transmit data corresponding to the aforementioned bus operation instructions between the system bus 10 and the target functional module. This data could include, for example, data that each functional module actually wants to write to or read from memory. Based on the module identifier in the internal operation instructions, the conversion circuit 320 can precisely move the data stream between the specific target functional module and the system bus 10, ensuring the correctness of the data routing.

[0022] The data access processing circuit 300 described above optimizes interface efficiency when multiple modules share a bus through a specific architecture design. In this processing circuit, the arbitration circuit 310 acts as the decision center for multiple access requests. An urgency signal is introduced, allowing each functional module to report its urgency level to the arbitration circuit 310 based on its real-time operating status, such as the data backlog in its internal FIFO or the current bandwidth demand gap. The arbitration circuit 310 can then flexibly select the most urgent task as the target functional module to respond to, generating concise internal operation instructions. The conversion circuit 320 then converts the arbitration result into bus operation instructions to establish a bridge between the system bus 10 and the target functional module, completing the data access. This technical solution effectively improves data access processing efficiency, simplifies the interface design of each functional module, and eliminates the need for each functional module to independently maintain complex bus logic. It only requires providing data access requests and urgency signals, significantly reducing the design difficulty of functional modules and the consumption of chip wiring resources. Furthermore, it ensures that critical tasks or high-bandwidth-demand tasks can receive timely responses, improving the overall system's data throughput efficiency and bus utilization.

[0023] Figure 4 A schematic diagram of another data access processing circuit provided in some embodiments of this application is shown. The arbitration circuit 310 includes a write arbitration sub-circuit 311 and a read arbitration sub-circuit 312; the conversion circuit includes a write conversion sub-circuit 321 and a read conversion sub-circuit 322; wherein, when multiple functional modules perform data writing, they form a write data channel with the write arbitration sub-circuit 311 and the write conversion sub-circuit 321, and the write data channel is used to process write data transmission requests generated by the multiple functional modules; when multiple functional modules perform data reading, they form a read data channel with the read arbitration sub-circuit 312 and the read conversion circuit 322, and the read data channel is used to process read data transmission requests generated by the multiple functional modules.

[0024] The arbitration circuit 310 and the conversion circuit 320 can adopt a read-write separation architecture. For example, the arbitration circuit 310 can be further divided into independent write arbitration sub-circuit 311 and read arbitration sub-circuit 312, and the conversion circuit 320 can be correspondingly divided into write conversion sub-circuit 321 and read conversion sub-circuit 322. This architecture allows multiple functional modules to process data writing and data reading through two parallel data channels respectively. When any one or more of the multiple functional modules need to write data to the system bus 10, they, together with the write arbitration sub-circuit 311 and the write conversion sub-circuit 321, form a write data channel. In this channel, the functional module that initiates the write request sends a write request signal and a write urgency signal reflecting the urgency of its write transaction to the write arbitration sub-circuit 311. The write arbitration sub-circuit 311 focuses on processing the write operation requests of all modules, dynamically determines the target functional module to obtain write bus control according to the priority of the write urgency signal, and feeds back a write confirmation signal. Subsequently, the write arbitration subcircuit 311 generates an internal write operation instruction containing the target functional module identifier, write address, and write data length, and sends it to the write conversion subcircuit 321. In response to this instruction, the write conversion subcircuit 321 converts it into write address channel and write data channel control signals conforming to a system bus protocol (such as the AXI protocol), and sends a data read signal to the target functional module, thereby transferring the data to be written to the system bus 10. Correspondingly, when multiple functional modules need to read data from the system bus, they form an independent read data channel with the read arbitration subcircuit 312 and the read conversion subcircuit 322. In this channel, the functional module initiating the read request sends a read request signal and a read urgency signal. The read arbitration subcircuit 312 operates independently of the write channel, determining the highest priority read task based on the read urgency signal, and generates an internal read operation instruction to be passed to the read conversion subcircuit 322. The read conversion sub-circuit 322 initiates a read operation to the system bus. After the system bus returns data, the read conversion sub-circuit 322 accurately routes the valid data and data validity signal to the target functional module that initiated the request, based on the module identifier in the instruction. The above implementation adopts a read-write separation architecture. Since the system bus, especially the AXI bus, supports parallel transmission of read and write channels, this application also separates the arbitration and conversion logic for read and write operations. This fully utilizes the full-duplex characteristics of the bus to achieve parallel processing of read and write operations. While writing a large amount of data, urgent read requests are not blocked, thus significantly improving the system's data throughput and bus bandwidth utilization. Independent arbitration logic allows read and write transactions to apply different scheduling strategies without interference, reducing the complexity of the arbitration logic. This parallel architecture effectively reduces access latency in high-concurrency scenarios, ensuring system response speed when multiple modules access the system.

[0025] In some embodiments of this application, when multiple functional modules are writing data, an urgency signal is used to characterize the urgency of the data to be transmitted by the functional modules; wherein, when the amount of data to be transmitted is greater than or equal to a preset data amount threshold, or when the data transmission of the functional module is in an uninterruptible state, a first priority urgency signal is output; when the amount of data to be transmitted backlogged by the functional module is less than the preset data amount threshold, or when the data transmission of the functional module is in an interruptible state, a second priority urgency signal is output; wherein, the first priority is higher than the second priority.

[0026] Taking a scenario where multiple functional modules write data as an example, the arbitration circuit no longer allocates bus usage rights based on a fixed priority configuration, but rather on the urgency signal reported by the functional modules in real time. The specific generation logic of this urgency signal is configured to reflect the urgency level of the current transaction to be transmitted by the functional module. Specifically, each functional module can be configured with a data buffer unit, such as a FIFO memory, to temporarily store data to be written. The functional module can monitor the amount of data to be transmitted accumulated in the data buffer unit in real time and compare this amount with a preset data volume threshold. Simultaneously, the functional module can also make a comprehensive judgment based on its own operating mode status, such as whether it is currently in a non-stop continuous operating state. When a functional module detects that the amount of data to be transmitted accumulated inside it is greater than or equal to the preset data volume threshold, it means that the data buffer unit is about to overflow, and failure to transmit in time may lead to data loss; or, when the functional module is in a non-stop state, such as a real-time video acquisition module or a continuous signal sampling module, where an interruption to its data stream may lead to system errors, the functional module will configure the output urgency signal as the first priority, such as a high level or a specific high-priority encoded value. At this point, the high urgency signal of the first priority will indicate to the arbitration circuit that the module urgently needs to occupy bus bandwidth. Conversely, when the functional module detects that the amount of backlogged data to be transmitted is less than a preset data amount threshold, indicating that the buffer space is relatively sufficient, or when the functional module is in a pauseable state, such as a non-real-time data processing module with a handshake pause mechanism, the functional module will configure the output urgency signal to the second priority, such as a low level or a low priority encoded value. Among them, the first priority is higher than the second priority. The above implementation can achieve accurate perception of the urgency of business by establishing a dynamic priority mechanism based on the amount of data backlog and the working status. For functional modules with serious data backlog or extremely high real-time requirements, the system can give them a higher bus selection advantage, thereby effectively preventing the risk of data buffer overflow or data loss due to bus congestion. For non-urgent tasks, bandwidth is actively relinquished when the bus is busy, thereby achieving optimal dynamic allocation of system bus resources among multiple modules and improving the overall robustness of the system.

[0027] In the above embodiments, each functional module can set a preset time interval, such as 1 microsecond, 1 millisecond, or any statistical period defined according to the system clock. Within this preset time interval, the functional module can monitor and statistically analyze two key values ​​in real time: one is the predicted amount of data that the functional module should theoretically transmit under normal working conditions, which depends on the module's service type, such as the bitrate or sampling rate of a video stream; the other is the actual amount of data that the functional module successfully transmits via the system bus. Subsequently, the functional module calculates the data transmission difference between the actual transmitted data amount and the predicted transmitted data amount. When the difference indicates that the actual transmitted data amount is less than the predicted transmitted data amount, it indicates that the functional module has not obtained sufficient bus bandwidth within the current statistical period, resulting in a bandwidth deficit. In this case, the system will determine the priority of the urgency signal based on the magnitude of the difference. The larger the difference, the more severe the bandwidth deficit, and the higher the priority of the urgency signal output by the functional module. For example, multiple levels of priority can be set, with a 50% gap being the highest priority and a 20% gap being the second highest priority. Conversely, if the actual transmission amount reaches or exceeds the predicted value, the lowest priority signal is output. By introducing a feedback adjustment mechanism based on bandwidth gaps, this application enables functional modules with strict bandwidth stability requirements, such as display refresh or real-time signal processing, to move beyond blind preemptive scheduling and instead quantitatively perceive the actual needs of each module. When excessive bus load causes some modules to fail to meet their expected bandwidth targets, the system can automatically increase their priority for compensation, thereby ensuring that the average bandwidth of critical modules meets design requirements over a period of time. This effectively avoids data interruptions caused by momentary bus congestion and significantly improves the system's capacity to handle complex multimedia services.

[0028] In some embodiments of this application, the internal operation instructions include: the module identifier, access address, and data length of the target functional module; the arbitration circuit is configured to package the access address, data length, and module identifier sent by the target functional module to generate the internal operation instructions.

[0029] Once the arbitration circuit determines the target functional module based on the urgency signal, it doesn't simply forward the signal; instead, it performs a packetization operation. The arbitration circuit can extract the access address from the signals sent by the target functional module, such as the starting physical address of the data read / write operation in memory and the data length, and combine this with the target functional module's unique identifier in the system to form an internal operation instruction. This packetization process can use bit concatenation or data packet assembly to integrate the key information from these three dimensions into a unified instruction word, which is then sent to the subsequent conversion circuit. For example, in a write operation, the instruction can be represented in the format {Module_ID, Write_Address, Write_Length}; in a read operation, the instruction can be represented in the format {Module_ID, Read_Address, Read_Length}.

[0030] In some embodiments of this application, when the access request signal is a write request signal, the conversion circuit is configured to parse the internal operation instruction, generate a write command bus operation instruction according to the system bus protocol, and send it to the system bus; when the system bus allows the target functional module to perform a write data operation based on the write command bus operation instruction, the conversion circuit sends a first control signal to the target functional module; the target functional module sends the data to be written to the system bus through the conversion circuit based on the first control signal.

[0031] In some embodiments of this application, when the access request signal is a read request signal, the conversion circuit is configured to parse the internal operation instruction, generate a read command bus operation instruction according to the system bus protocol, and send it to the system bus; when the system bus allows the target functional module to perform a read data operation based on the read command bus operation instruction, the conversion circuit sends a second control signal to the target functional module; the target functional module obtains the data to be read from the system bus through the conversion circuit based on the second control signal.

[0032] When the internal operation instruction sent by the arbitration circuit corresponds to a write request signal, the conversion circuit first parses the internal operation instruction, extracting information such as the write address, write data length, and module identifier. Subsequently, based on the system bus protocol, such as the write address channel specification of the AXI protocol, the conversion circuit uses the above information to generate standard write command bus operation instructions, which may include signals such as AWADDR, AWLEN, and AWID, and sends them to the system bus. During the write data transmission phase, when the system bus is ready to receive data based on the above write command bus operation instructions, or when the conversion circuit determines that data needs to be acquired according to the protocol timing, the conversion circuit sends a first control signal to the target functional module. This first control signal can specifically be a data read signal or a pop signal. The target functional module responds to this first control signal by outputting its internally buffered data to be written. The conversion circuit receives this data to be written and writes it out through the system bus, thus completing the data transfer.

[0033] Correspondingly, when the internal operation instruction sent by the arbitration circuit corresponds to a read request signal, the conversion circuit parses the internal operation instruction and uses the parsed read address, read data length, and module identifier to generate a standard read command bus operation instruction according to the system bus protocol and send it to the system bus. During the read data transmission phase, when the system bus responds to the read command and returns data via the read data channel, the conversion circuit receives the data. To correctly deliver the data to the target functional module, the conversion circuit sends a second control signal to the target functional module. This second control signal can specifically be a data valid signal. Based on the indication of this second control signal, the target functional module successfully obtains the data to be read from the system bus through the conversion circuit.

[0034] In some embodiments of this application, the system bus is further comprising: a register configured to store bus control parameters corresponding to the functional module; a conversion circuit configured to look up the corresponding bus control parameters based on the module identifier in the internal operation instruction, and generate a bus operation instruction in combination with the internal operation instruction; wherein the system bus is an AXI bus.

[0035] Registers can be integrated inside the conversion circuit or tightly coupled to it. These registers can pre-store bus control parameters corresponding one-to-one with each functional module. These bus control parameters can be static or semi-static attribute signals specified in the system bus protocol. For the same functional module, these parameters typically remain unchanged across multiple transmissions or only require low-frequency configuration by software. When the system bus is an Advanced Scalable Interface (AXI) bus, these bus control parameters specifically include, but are not limited to: burst transfer type (AxBURST), data transfer width (AxSIZE), and memory protection type (AxPROT). Under this architecture, the instruction generation logic of the conversion circuit is further optimized. When the conversion circuit receives an internal operation instruction from the arbitration circuit, it first parses out the module identifier of the target functional module contained within. Subsequently, using this module identifier as an index, the conversion circuit accesses the aforementioned register to find and read the bus control parameters pre-bound to the target functional module. Finally, the conversion circuit concatenates or combines the dynamic parameters (such as access address and data length) extracted from the internal operation instructions with the static parameters (such as burst type and caching strategy) read from the registers to construct a complete bus operation instruction that conforms to the AXI bus protocol specification, and sends it to the AXI bus.

[0036] The above implementation reduces the number of interaction signals between functional modules and conversion circuits through a register configuration mechanism. Functional modules do not need to send complex AXI protocol attribute signals with each request; they only need to focus on the address and data itself, thus simplifying the interface logic of the functional modules. Simultaneously, it provides the system with a degree of flexibility. Software drivers can dynamically adjust the access attributes of different modules by modifying register configuration values, such as changing the caching strategy or security level of a module, without modifying the hardware code or circuit structure, achieving a balance between simplified hardware interfaces and flexible software definition.

[0037] Figure 5This diagram illustrates the signal interaction and data transmission of a multi-channel data access processing circuit provided in some embodiments of this application. Taking the write data channel signal interaction process as an example, where the first functional module Module1 needs to write data to the system bus 10, the interaction process includes: when initiating a request, the first functional module Module1 sets the write request signal wreq1 to an active state and simultaneously outputs the corresponding write address waddr1, write data length wlen1, and write urgency signal wurgent1. In this process, the generation of the write urgency signal wurgent is crucial for control. To adapt to different business needs, the functional module can control the level of this signal from two dimensions: if the first functional module Module1 urgently needs to write data, for example, if there is too much data piled up to be written internally, or if the module is in an unstoppable continuous working mode, then a higher priority wurgent1 is output; if there is less data to be written or the module can be paused, then a lower priority wurgent1 is output. If the second functional module Module2 also sends a write urgency signal wurgent2 at this time, and the priority of wurgent2 is lower than that of wurgent1, then the first functional module Module1 will be selected as the target functional module. Another dimension is the amount of bandwidth shortfall. Based on the predicted working bandwidth requirement, the first functional module Module1 calculates the actual amount of data written within a preset time interval. If the actual amount written is much less than the predicted value, indicating a bandwidth shortfall, then a higher priority wurgent1 will be output; if the predicted value has been reached, then a lower priority wurgent1 will be output. The write arbitration sub-circuit 311 monitors the write request signals (wreq1-wreq3) and write urgency signals (wurgent1-wurgent3) sent by each functional module in real time. The write arbitration sub-circuit 311 makes a decision based on the level of the request signal wurgent (e.g., different levels such as 0 / 1 / 2), selects the functional module with the highest current priority (in this example, the first functional module Module1) to respond, and returns a write confirmation signal wack1 to that module. After receiving the acknowledgment signal wack1, the first functional module Module1 cancels the request signal wreq1 and resets the relevant signals, preparing to initiate the next transmission request. The write arbitration sub-circuit 311 packages the write address waddr1, write data length wlen1, and module identifier of the target functional module (i.e., the selected first functional module Module1) into a write internal operation instruction wcmd and sends it to the write conversion sub-circuit 321. The write conversion sub-circuit 321 converts the internal operation instruction wcmd into a write command conforming to the AXI bus protocol and sends it to the system bus 10.The write conversion sub-circuit 321 sends a data read signal pop1 to the first functional module Module1 according to the module identifier in the instruction. The first functional module Module1 responds to the pop1 signal and outputs the data to be written, data1. The write conversion sub-circuit 321 receives data1 and sends it to the system bus 10, thereby completing the data writing and transmission.

[0038] Taking the third functional module Module3's need to read data from system bus 10 as an example, when initiating a request, Module3 sets the read request signal rreq3 to an active state and simultaneously outputs the corresponding read address raddr3, read data length rlen3, and read urgency signal rurgent3. In this process, the generation of the read urgency signal rurgent is crucial for control. The read arbitration sub-circuit 312 makes a judgment based on the level of the request signal rurgent (e.g., different levels such as 0 / 1 / 2), selects the functional module with the highest current priority (Module3 in this example) to respond, and returns a read confirmation signal rack3 to that module. After receiving the confirmation signal rack3, Module3 cancels the request signal rreq3 and resets the relevant signals, preparing to initiate the next transmission request. The read arbitration sub-circuit 312 packages the read address raddr3, read data length rlen3 of the target functional module (i.e., the selected third functional module Module3), and the module identifier of that module to generate a read internal operation instruction rcmd, and sends it to the read conversion sub-circuit 322. The read conversion sub-circuit 322 converts the contents of the internal operation instruction rcmd into a read command conforming to the AXI bus protocol and sends it to the system bus 10. The read conversion sub-circuit 322 receives the data returned by the system bus 10 and, according to the module identifier in the instruction, sends a data valid signal valid3 and data data3 to the third functional module Module3. The third functional module Module3 responds to the valid3 signal and receives the data data3, thereby completing the data reading and transmission.

[0039] In the above embodiments, the signals shown in the figures are for illustrative purposes only. In practical applications, other handshake information can be added as needed, such as a bit width indication signal. That is, if the data bit width transmitted by each functional module is different, a wsize / rsize signal can be added to indicate the effective bit width of the data. Furthermore, for the numerous complex control signals in the AXI bus protocol, this application can configure the static parameters corresponding to each module in advance in the conversion circuit 320 by setting registers via software. When the conversion circuit receives wcmd or rcmd, it looks up the corresponding register configuration based on the module identifier and automatically completes the other control information required for AXI transmission.

[0040] Figure 6 A flowchart illustrating a data access control method provided in some embodiments of this application is shown. This data access control method is applied to the data access processing circuit provided in the above embodiments, and includes: S610: Receives access request signals and urgency signals from multiple functional modules; S620: In response to at least one urgency signal, determine the target functional module from multiple functional modules and send a confirmation signal back to the target functional module; S630: Generates bus operation instructions based on the access request signal of the target functional module and sends them to the system bus; S640: In response to feedback signals from the system bus, it transmits data corresponding to bus operation commands between the system bus and the target functional module.

[0041] The specific implementation method and beneficial effects of this data access control method can be found in the above-mentioned data access processing circuit, and will not be repeated here.

[0042] Based on the same technical concept, this application also provides an electronic device, including the data access processing circuit provided in the above embodiments.

[0043] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail or in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the above embodiments can be freely combined as needed.

Claims

1. A data access processing circuit, characterized in that, Used for data access between multiple functional modules and the system bus, including: An arbitration circuit, connected to the plurality of functional modules respectively, is configured to receive access request signals and urgency signals sent by the plurality of functional modules, determine the target functional module from the plurality of functional modules according to the urgency signal, send a confirmation signal to the target functional module, and generate internal operation instructions according to the access request signal. The conversion circuit, connected to the arbitration circuit, the plurality of functional modules and the system bus respectively, is configured to receive the internal operation instructions, convert the internal operation instructions into bus operation instructions conforming to the system bus protocol and send them to the system bus, and transmit data corresponding to the bus operation instructions between the system bus and the target functional module.

2. The data access processing circuit according to claim 1, characterized in that, The arbitration circuit includes: a write arbitration sub-circuit and a read arbitration sub-circuit; The conversion circuit includes: a write conversion sub-circuit and a read conversion sub-circuit; When writing data, the multiple functional modules form a write data channel with the write arbitration sub-circuit and the write conversion sub-circuit. The write data channel is used to process the write data transmission requests generated by the multiple functional modules. When the multiple functional modules read data, they form a read data channel with the read arbitration sub-circuit and the read conversion sub-circuit. The read data channel is used to process the read data transmission requests generated by the multiple functional modules.

3. The data access processing circuit according to claim 2, characterized in that, When multiple functional modules are writing data, the urgency signal is used to characterize the urgency of the data to be transmitted by the functional module. Specifically, when the amount of data to be transmitted is greater than or equal to a preset data amount threshold, or when the data transmission of the functional module is in an uninterruptible state, a first priority urgency signal is output. When the amount of data to be transmitted backlogged by the functional module is less than the preset data amount threshold, or when the data transmission of the functional module is in a pauseable state, a second priority urgency signal is output. The first priority is higher than the second priority.

4. The data access processing circuit according to claim 2, characterized in that, The urgency signal is also used to characterize the bandwidth gap of the functional module, and is configured to be determined based on the data transmission difference between the actual data transmission amount and the predicted data transmission amount of the functional module within a preset time interval. Specifically, when the data transmission difference indicates that the actual data transmission amount of the functional module is less than the predicted data transmission amount, the priority of the urgency signal is determined based on the magnitude of the difference.

5. The data access processing circuit according to claim 1, characterized in that, The internal operation instructions include: the module identifier, access address, and data length of the target functional module; The arbitration circuit is configured to package the access address, the data length, and the module identifier sent by the target functional module to generate the internal operation instruction.

6. The data access processing circuit according to claim 5, characterized in that, When the access request signal is a write request signal, the conversion circuit is configured to parse the internal operation instruction, generate a write command bus operation instruction according to the system bus protocol, and send it to the system bus. When the system bus allows the target functional module to perform a write data operation based on the write command bus operation instruction, the conversion circuit sends a first control signal to the target functional module; The target functional module sends the data to be written to the system bus through the conversion circuit based on the first control signal.

7. The data access processing circuit according to claim 5, characterized in that, When the access request signal is a read request signal, the conversion circuit is configured to parse the internal operation instruction, generate a read command bus operation instruction according to the system bus protocol, and send it to the system bus. When the system bus allows the target functional module to perform a read data operation based on the read command bus operation instruction, the conversion circuit sends a second control signal to the target functional module; The target functional module obtains the data to be read from the system bus through the conversion circuit based on the second control signal.

8. The data access processing circuit according to any one of claims 1 to 7, characterized in that, Also includes: The register is configured to store bus control parameters corresponding to the functional module; The conversion circuit is configured to look up the corresponding bus control parameters based on the module identifier in the internal operation instruction, and generate the bus operation instruction in combination with the internal operation instruction; The system bus is an AXI bus.

9. A data access control method, characterized in that, The processing circuitry applied to the data access according to any one of claims 1 to 8 includes: Receive access request signals and urgency signals sent by the multiple functional modules; In response to at least one of the urgency signals, the target functional module is determined from the plurality of functional modules, and a confirmation signal is fed back to the target functional module; The bus operation command is generated based on the access request signal of the target functional module and sent to the system bus; In response to the feedback signal of the system bus, data corresponding to the bus operation command is transmitted between the system bus and the target functional module.

10. An electronic device, characterized in that, It includes the data access processing circuitry as described in any one of claims 1 to 8.

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