Three-terminal tandem solar cell, method of manufacturing the same, and photovoltaic module

Abstract

This invention provides a three-terminal tandem solar cell, its fabrication method, and a photovoltaic module. The method includes: providing a silicon substrate; fabricating N-region and P-region structures spaced apart on the back surface of the silicon substrate; forming a mask layer on the surfaces of the N-region and P-region structures, as well as on the surface of the gap between the N-region and P-region structures; forming a textured surface on the entire light-facing surface of the silicon substrate; sequentially forming a silicon oxide layer and a front-side n-type doped polycrystalline silicon layer on the textured surface; and sequentially forming a composite layer and a top cell on the side of the front-side n-type doped polycrystalline silicon layer away from the silicon substrate. Therefore, the above method can protect the N-region and P-region while forming a textured front-side n-type doped polycrystalline silicon layer, thereby enhancing the light absorption of the cell while retaining the tunnel junction, ensuring contact and communication between the top and bottom cells.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, specifically to three-terminal tandem solar cells, their fabrication methods, and photovoltaic modules. Background Technology

[0002] Perovskite / crystalline silicon tandem solar cells are structures that combine crystalline silicon solar cells and perovskite solar cells. Through complementary advantages and synergistic effects, conversion efficiency is improved. The two types of cells stacked together can fully utilize light absorption and electron transport, achieving complementary effects and thus improving overall performance. In the fabrication of perovskite / TBC three-terminal tandem solar cells, to achieve efficient electrical connections and maximize cell performance, the crystalline silicon bottom cell needs to have a textured N-poly (n-type doped polycrystalline silicon) surface on the front side. This enhances light absorption while retaining the tunnel junction to ensure contact connectivity between the top and bottom cells. However, before N-poly deposition in existing TBC cells, the N-regions on both the front and back sides share a planar commonality. Due to equipment resources and technical difficulties, it is challenging to achieve single-sided chain texturing, i.e., it is difficult to maintain a planar back side while texturing the front side. Summary of the Invention

[0003] This invention aims to at least partially solve one of the technical problems in related technologies. Therefore, one objective of this invention is to provide a method for fabricating a three-terminal tandem solar cell, which can effectively achieve the effect of a textured surface on the front n-type doped polycrystalline silicon and a planar N-region and P-region on the back side.

[0004] In one aspect, the present invention provides a method for fabricating a three-terminal tandem solar cell. According to an embodiment of the present invention, the method for fabricating a three-terminal tandem solar cell includes: providing a silicon substrate having a light-facing side and a back-facing side disposed opposite to each other; fabricating N-region structures and P-region structures spaced apart on the back-facing side of the silicon substrate; forming a mask layer on the surfaces of the N-region structures and the P-region structures, and on the surface of the gap region between the N-region structures and the P-region structures; forming a textured surface on the entire light-facing side of the silicon substrate; sequentially forming a silicon oxide layer and a front-side n-type doped polycrystalline silicon layer on the surface of the textured surface; and sequentially forming a composite layer and a top cell on the side of the front-side n-type doped polycrystalline silicon layer away from the silicon substrate. Thus, by providing mask layers to protect the N-region and P-region structures on the back-facing side, and then texturing the light-facing side of the silicon substrate to form a textured surface structure, a front-side n-type doped polycrystalline silicon layer can be formed on the textured surface, thereby enhancing the light absorption of the cell while retaining the tunnel junction, ensuring contact and communication between the top cell and the bottom cell.

[0005] According to an embodiment of the present invention, the material of the mask layer includes silicon oxide.

[0006] According to an embodiment of the present invention, the mask layer is formed by plasma-enhanced chemical vapor deposition, and the thickness of the mask layer is 50-70 nm.

[0007] According to an embodiment of the present invention, a first phosphosilicate glass layer is provided between the N-region structure and the mask layer, and the first phosphosilicate glass layer and the mask layer on its surface constitute a first composite mask; a borosilicate glass layer is provided between the P-region structure and the mask layer, and the borosilicate glass layer and the mask layer on its surface constitute a second composite mask.

[0008] According to an embodiment of the present invention, the method for forming the textured surface on the light-facing side of the silicon substrate includes: firstly texturing the light-facing side of the silicon substrate with an alkaline texturing agent at a solution temperature of 70-80°C for a process time of 450-650s; and then acid washing the light-facing side of the silicon substrate with an acid bath to obtain the textured surface.

[0009] According to an embodiment of the present invention, a silicon oxide layer and a front-side n-type doped polysilicon layer are sequentially formed on the surface of the textured surface using a low-pressure chemical vapor deposition method, and a second phosphosilicate glass layer is formed on the surface of the front-side n-type doped polysilicon layer. During the formation of the silicon oxide layer, the oxygen flow rate is 27000-36000 sccm, the temperature is 590-615°C, the process time is 500-1800 s, the tube blanching time is 300-1000 s, and the thickness of the silicon oxide layer is 1.9-2.3 nm. During the formation of the front-side n-type doped polysilicon layer, the deposition temperature is 590-615°C, the process time is 1500-5000 s, and the thickness of the front-side n-type doped polysilicon layer is 100-200 nm.

[0010] According to an embodiment of the present invention, the method for preparing a three-terminal tandem solar cell further includes: removing the first composite mask, the second composite mask, and the second phosphosilicate glass layer by the same acid washing step.

[0011] According to an embodiment of the present invention, the top cell comprises a perovskite cell.

[0012] In another aspect of the present invention, a three-terminal tandem solar cell is provided. According to an embodiment of the present invention, the three-terminal tandem solar cell is prepared by the method described above, comprising: a silicon substrate having a light-facing surface and a back-lighting surface disposed opposite to each other, wherein the entire surface of the light-facing surface is textured; an N-region structure and a P-region structure, the N-region structure and the P-region structure being disposed at intervals on the surface of the back-lighting surface, wherein the surfaces of the N-region structure and the P-region structure away from the silicon substrate are planar; a silicon oxide layer disposed on the textured surface; a front-side n-type doped polycrystalline silicon layer disposed on the side of the silicon oxide layer away from the silicon substrate; a composite layer disposed on the side of the front-side n-type doped polycrystalline silicon layer away from the silicon substrate; and a top cell disposed on the side of the composite layer away from the silicon substrate. Therefore, the entire surface of the light-facing side has a textured structure, which can form a textured n-type doped polycrystalline silicon layer on the front side. This can enhance the light absorption of the battery while retaining the tunnel junction, ensuring that the top and bottom batteries are in contact and connected. At the same time, the surfaces of the N-region and P-region structures away from the silicon substrate are planar, which can effectively protect the battery performance of the bottom battery.

[0013] In another aspect, the present invention provides a photovoltaic module. According to an embodiment of the present invention, the photovoltaic module includes the aforementioned three-terminal tandem solar cell.

[0014] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0015] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a flowchart of the preparation of a three-terminal stacked battery in one embodiment of the present invention; Figure 2 This is a flowchart of the preparation of a three-terminal stacked battery in another embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a crystalline silicon bottom battery in another embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a three-terminal stacked battery in another embodiment of the present invention. Detailed Implementation

[0016] The present invention will be explained below with reference to embodiments. Those skilled in the art will understand that the following embodiments are for illustrative purposes only and should not be considered as limiting the scope of the invention. Where specific techniques or conditions are not specified in the embodiments, they are performed according to the techniques or conditions described in the literature in the field or according to the product instructions. Reagents or instruments whose manufacturers are not specified are all conventional products that can be obtained commercially.

[0017] The "range" disclosed in this application is defined by a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, which define the boundaries of a particular range. Ranges defined in this way can include or exclude endpoints and can be arbitrarily combined; that is, any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60-120 and 80-110 are listed for a specific parameter, it is expected that ranges of 60-110 and 80-120 are also included. Furthermore, if minimum range values ​​of 1 and 2 are listed, and if maximum range values ​​of 3, 4, and 5 are listed, then the following ranges are all expected: 1-3, 1-4, 1-5, 2-3, 2-4, and 2-5. In this application, unless otherwise stated, the numerical range "ab" represents a shortened representation of any combination of real numbers between a and b, where a and b are real numbers. For example, the numerical range "0-5" indicates that all real numbers between "0-5" have been listed in this article; "0-5" is simply a shortened representation of these numerical combinations. Furthermore, when a parameter is stated as an integer ≥2, it is equivalent to disclosing that the parameter is, for example, an integer such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0018] The present invention will now be described with reference to specific embodiments. It should be noted that these embodiments are merely descriptive and do not limit the present invention in any way.

[0019] The terms "first" and "second" used in this document are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature marked "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0020] In one aspect of the invention, a method for fabricating a three-terminal tandem solar cell is provided. According to an embodiment of the invention, referring to… Figure 1 and Figure 2 The method for preparing a three-terminal tandem solar cell includes: S100: Provides a silicon substrate 100, which has a light-facing surface 110 and a back-lighting surface 120 disposed opposite to each other.

[0021] In some embodiments, the silicon substrate can be polished with an alkaline solution beforehand to remove mechanical damage to the surface of the silicon substrate.

[0022] S200: An N-region structure 200 and a P-region structure 300 are respectively fabricated on the back surface 120 of the silicon substrate 100.

[0023] In some embodiments, the fabrication of the P-region structure 300 includes a P-region tunneling layer 310 and a p-type doped polysilicon layer 320. The fabrication method can employ low-pressure chemical vapor deposition (LPCVD). Specifically, the P-region tunneling layer and the polysilicon layer are sequentially formed in the P-region of the backlight surface using LCVD, and then the polysilicon layer is boron-expanded to form a p-type doped polysilicon layer. During the formation of the P-region tunneling layer 310, the oxygen flow rate is 27000-36000 sccm, and the temperature is 590-615°C. The deposition time is 500-1800s, and the tube-clogging time is 300-1000s. During the formation of the polycrystalline silicon layer, the deposition temperature is 545-565℃, the process time is 10000-12600s, and the silane flow rates for the three-stage gas inlet methods are 170-210 sccm, 410-470 sccm, and 600-640 sccm, respectively. The final thickness of the P-region tunneling layer is 1.9-2.3 nm, the thickness of the polycrystalline silicon layer (poly layer) is 230-360 nm, and the surface concentration is 2×10⁻⁶. 19 cm -3 -8×10 19 cm -3 During the boron diffusion process, the boron source flow rate is 200-300 sccm, the temperature is 835-885℃, the process time is 500-1500s, the advance step temperature is 945-955℃, and the advance time is 900-1200s; the oxidation temperature is 945-955℃, the oxygen flow rate is 5000-10000 sccm, and the oxidation time is 1400-1800s, ultimately forming a structure of p-type doped polycrystalline silicon layer 320 and borosilicate glass layer 330 (i.e., P-poly layer + BSG layer structure). The P-poly and N-type silicon substrate form a PN junction, wherein the thickness of the P-poly layer is 230-360nm, the thickness of the BSG layer is 45-55nm, and the sheet resistance is 80±5Ω.

[0024] Furthermore, the borosilicate glass layer in the N region and the gap region (gap region 400) of the backlight surface is removed by laser, while the borosilicate glass layer 330 in the P region is retained. The laser power is 40-50W, the overlap rate is 50-60%, the frequency is 500-600kHz, and the pulse width is 0.8-1.2μs.

[0025] Furthermore, the borosilicate glass layer formed on the light-facing surface and sides is removed using a wet chain machine.

[0026] Furthermore, alkaline washing is performed using a wet alkaline washing machine to remove the p-type doped polysilicon layers on the light-facing and side surfaces, as well as the p-type doped polysilicon layers in the Gap and N regions, leaving only the p-type doped polysilicon layer 320 and the borosilicate glass layer 330 in the P region. The temperature of the wet alkaline washing machine is 50-75℃, and the process time is 200-300s. At the same time, the thickness of the borosilicate glass layer 330 in the P region is reduced after passing through the alkaline washing machine, for example, the thickness can be reduced to 20±5nm.

[0027] In some embodiments, the N-region structure 200 includes an N-region tunneling layer 210 and an n-type doped polysilicon layer 220. The fabrication method can employ low-pressure chemical vapor deposition (LPCVD). Specifically, the N-region tunneling layer 210 and a polysilicon layer are sequentially formed in the N-region of the backlight surface using LCVD, followed by phosphorus diffusion of the polysilicon layer to form the n-type doped polysilicon layer 220. During the formation of the N-region tunneling layer 210, the oxygen flow rate is 27000-36000 sccm, and the temperature is 590-615℃. The process time is 500-1800 s, and the tube-blocking time is 300-1000 s. During the formation of the polycrystalline silicon layer, the deposition temperature is 590-615℃, the process time is 1500-5000 s, and the silane flow rates for the three-stage gas inlet method are 170-210 sccm, 410-470 sccm, and 600-640 sccm, respectively. The final thickness of the N-region tunneling layer is 1.9-2.3 nm, the thickness of the polycrystalline silicon layer (poly layer) is 180-280 nm, and the surface concentration is 2×10⁻⁶. 20 cm -3 -8×10 20 cm -3 During the phosphorus diffusion process, the phosphorus source flow rate is 900-1400 sccm, the temperature is 780-830℃, the process time is 960-1500s, the advance step temperature is 860-900℃, and the process time is 900-1300s; the oxidation temperature is 870℃, the oxygen flow rate is 1500-3000 sccm, and the oxidation time is 540-1000s, ultimately forming a structure of an n-type doped polycrystalline silicon layer 220 and a first phosphorosilicate glass layer 230 (i.e., an N-poly layer + a first PSG layer). The thickness of the N-poly layer is 100-280nm, the thickness of the PSG layer is 45-55nm, and the sheet resistance is 20±5Ω.

[0028] Furthermore, the first phosphosilicate glass layer between the P region and the Gap region (gap region 400) of the backlight surface is removed by laser, while the first phosphosilicate glass layer 230 of the N region is retained. The laser power is 30-50W, the overlap rate is 50-60%, the frequency is 500-600kHz, and the pulse width is 0.8-1.2μs.

[0029] Furthermore, the first phosphosilicate glass layer formed on the light-facing surface and the side surface is removed by a wet chain machine.

[0030] Furthermore, an alkaline washing process is performed using a wet alkaline washing tank to remove the n-type doped polysilicon layers on the light-facing and side surfaces, as well as the n-type doped polysilicon layers in the Gap and P regions, leaving only the n-type doped polysilicon layer 220 in the N region and the first phosphosilicate glass layer 230. The tank temperature of the wet alkaline washing tank is 50-75℃, and the process time is 200-300 seconds. Simultaneously, the thickness of the first phosphosilicate glass layer 230 in the N region decreases after passing through the alkaline tank, and the borosilicate glass layer 330 in the P region is also further thinned (e.g., ...). Figure 2 As shown), for example, the thickness can be reduced to 20±5nm, and the borosilicate glass layer 330 in the P region can be reduced to 10±5nm. In some embodiments, the first phosphosilicate glass layer 230 in the N region and the borosilicate glass layer 330 in the P region are even completely removed during the above process. Figure 1 As shown.

[0031] Specifically, by retaining a certain thickness of the first phosphorus silicate glass layer 230 in the N region and the borosilicate glass layer 330 in the P region, the n-type doped polysilicon layer and the p-type doped polysilicon layer can be better protected from etching.

[0032] As mentioned above, the thickness of both the borosilicate glass layer and the first phosphosilicate glass layer is reduced after passing through the alkaline bath. If the borosilicate glass layer and the first phosphosilicate glass layer of this thickness are directly used as protective masks to texturize the entire surface of the silicon substrate on the light-facing side, the texturing process is sufficient to etch away the aforementioned thinner glass layer, and further etch the n-type doped polycrystalline silicon layer and p-type doped polycrystalline silicon layer on the back-facing side, forming a micro-textured structure on its surface, making it impossible to maintain a flat surface. This will seriously affect the performance of the crystalline silicon bottom cell.

[0033] To address this technical problem, the present invention proposes forming a mask layer as a protective layer on the entire backlight surface.

[0034] S300: A mask layer 500 is formed on the surfaces of the N-region structure 200 and the P-region structure 300, as well as on the surface of the gap region 400 between the N-region structure 200 and the P-region structure 300. By forming mask layers in the N-region and P-region of the backlight side to protect the N-region and P-region structures, and then during the texturing of the light-facing side of the silicon substrate to form a textured structure, the planar structure of the n-type doped polysilicon layer and the p-type doped polysilicon layer on the backlight side can be protected while the textured n-type doped polysilicon layer on the front side can be formed. This not only enhances the light absorption of the cell on the light-facing side while retaining the tunnel junction to ensure the contact and communication between the top and bottom cells, but also protects the cell performance of the bottom cell, thereby improving the overall cell efficiency of the stacked cell.

[0035] According to some embodiments of the present invention, the material of the mask layer includes silicon oxide, such as silicon dioxide. Thus, there is no negative impact on the n-type doped polysilicon layer and the p-type doped polysilicon layer, and the protective effect is good.

[0036] According to some embodiments of the present invention, a mask layer 500 is formed by plasma-enhanced chemical vapor deposition. In some embodiments, during the deposition process, the deposition temperature is 520~560°C, the silane SiH4 flow rate is 915~945 sccm, the nitrous oxide (N2O) flow rate is 11000~13000 sccm, the discharge power is 10~18 kW, the pulse on / off ratio is (3~7):(115~135) ms, the time is 600-800 s, and the thickness of the resulting mask layer 500 is 50-70 nm. The resulting mask layer can effectively protect the N-region and P-region structures during the texturing process on the light-facing side.

[0037] Furthermore, in some embodiments, it is necessary to remove the mask layer formed around the light-facing side and the side using a wet chain machine, leaving only the mask layer 500 on the back side.

[0038] According to some embodiments of the present invention, with reference to Figure 2 A first phosphosilicate glass layer 230 is located between the N-region structure 200 and the mask layer 500, forming a first composite mask with the mask layer 500 on its surface. A borosilicate glass layer 330 is located between the P-region structure 300 and the mask layer 500, forming a second composite mask with the mask layer 500 on its surface. This design better protects the planar structure of the n-type doped polysilicon layer and the p-type doped polysilicon layer on the backlight surface. S400: A textured surface 111 is formed on the entire light-facing surface 110 of the silicon substrate 100.

[0039] According to some embodiments of the present invention, a method for forming a textured surface on the light-facing surface 110 of a silicon substrate 100 includes: firstly texturing the light-facing surface of the silicon substrate using an alkaline texturing agent at a solution temperature of 70-80°C for a process time of 450-650 s; then acid-washing the light-facing surface of the silicon substrate using an acid bath to obtain the textured surface 111. In this step, the thickness of the mask layer 500 is reduced, for example, to 20±5 nm.

[0040] In some specific embodiments, the alkaline texturing agent includes sodium hydroxide solution and texturing additives; pickling can be performed using hydrofluoric acid solution at a temperature of 55~75℃ for a process time of 40~60s.

[0041] S500: A silicon oxide layer 600 and a front-side n-type doped polysilicon layer 700 are sequentially formed on the surface of the textured surface 111.

[0042] According to some embodiments of the present invention, a silicon oxide layer 600 and a front-side n-type doped polysilicon layer 700 are sequentially formed on the surface of a textured surface using low-pressure chemical vapor deposition (LPCVD). A second phosphosilicate glass layer 710 is then formed on the surface of the front-side n-type doped polysilicon layer 700. During the formation of the silicon oxide layer 600, the oxygen flow rate is 27000-36000 sccm, the temperature is 590-615°C, the process time is 500-1800 s, and the tube-blocking time is 300-1000 s. The thickness of the silicon oxide layer is 1.9-2.3 nm. During the formation of the front-side n-type doped polysilicon layer 700, the deposition temperature is 590-615°C, the process time is 1500-5000 s, and the surface concentration is 2 × 10⁻⁶. 20 cm -3 -8×10 20 cm -3 A polycrystalline silicon layer is formed, and then phosphorus diffusion is performed on the polycrystalline silicon layer. During the phosphorus diffusion process, the phosphorus source flow rate is 900-1400 sccm, the temperature is 780-830℃, the process time is 960-1500s, the advance step temperature is 860-900℃, the process time is 900-1300s, the oxidation temperature is 850~890℃, the oxygen flow rate is 1500-3000 sccm, and the oxidation time is 540-1000s. Finally, a structure of front-side n-type doped polycrystalline silicon layer 700 + second phosphorosilicate glass layer 710 is formed. The thickness of the front-side n-type doped polycrystalline silicon layer is 100-200nm, the thickness of the second phosphorosilicate glass layer 710 is 45-55nm, and the sheet resistance is 30±5Ω.

[0043] Furthermore, in some embodiments, a second phosphosilicate glass layer formed on the backlight surface and sides is removed by a wet chain machine.

[0044] Furthermore, in some embodiments, the front n-type doped polysilicon layer deposited on the back and side surfaces is removed by wet alkaline washing.

[0045] According to some embodiments of the present invention, with reference to Figure 2 The method for preparing a three-terminal tandem solar cell further includes removing the first composite mask, the second composite mask, and the second phosphosilicate glass layer 710 through the same acid washing step. This allows the three-layer structure to be removed in a single process, improving process efficiency. In some specific embodiments, the first composite mask, the second composite mask, and the second phosphosilicate glass layer 710 are removed by acid washing in an acid washing tank, wherein the acid solution can be a hydrofluoric acid solution.

[0046] According to some embodiments of the present invention, the steps for fabricating a crystalline silicon bottom solar cell include: sequentially forming a passivation layer 1000 and an antireflection layer 1100 on the back surface, such as... Figure 3 As shown, the passivation layer 1000 can be formed by atomic layer deposition, and its material includes, but is not limited to, aluminum oxide, with a thickness of 5±0.8 nm; the antireflection layer 1100 can be formed by film deposition, and its material includes, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, etc. The antireflection layer can be formed by multiple sub-reflection layers, and the overall thickness of the antireflection layer is 84±6 nm, with a refractive index of 2.12±0.05.

[0047] Furthermore, the steps for fabricating a crystalline silicon bottom solar cell may also include: forming a first metal grid line 1210 and a second metal grid line 1220 on the backlight surface by screen printing; sintering at high temperature, whereby the first metal grid line 1210 forms an ohmic contact with the n-type doped polycrystalline silicon layer 220, and the second metal grid line 1220 forms an ohmic contact with the p-type doped polycrystalline silicon layer 320; collecting and discharging current, as shown below. Figure 3 As shown.

[0048] S600: A composite layer 800 and a top cell 900 are sequentially formed on the side of the front n-type doped polycrystalline silicon layer 700 away from the silicon substrate.

[0049] According to some embodiments of the present invention, the composite layer can be a transparent conductive layer, such as an ITO layer or an IZO layer. The thickness of the composite layer can be 5-10 nm, and the preparation method can be physical vapor deposition (PVD), such as magnetron sputtering.

[0050] According to some embodiments of the present invention, the top cell includes a perovskite cell.

[0051] In some embodiments, refer to Figure 4 In the direction away from the crystalline silicon base cell, the perovskite cell includes a first charge transport layer 910, a perovskite active layer 920, a second charge transport layer 930, a transparent conductive layer 940, an electrode 950, and an antireflection layer 960 formed sequentially.

[0052] In some embodiments, one of the first charge transport layer and the second charge transport layer is a hole transport layer, and the other is an electron transport layer. For example, if the first charge transport layer is a hole transport layer, then the second charge transport layer is an electron transport layer; conversely, if the first charge transport layer is an electron transport layer, then the second charge transport layer is a hole transport layer. There are no specific requirements regarding the materials used for the hole transport layer and the electron transport layer; those skilled in the art can flexibly choose according to existing technology and actual needs.

[0053] In some embodiments, the material structure of the perovskite active layer can be ABX3, wherein A is a monovalent cation, including but not limited to one or a mixture of several monovalent cations selected from cesium (Cs), rubidium (Rb), methylamino (CH3NH3), and formamidinyl (CH2(NH2)2); B is a divalent cation, including but not limited to one or a mixture of several divalent cations selected from lead (Pb) and tin (Sn); and X is a monovalent anion, including but not limited to one or a mixture of several monovalent anions selected from iodine (I), bromine (Br), chloride (Cl), fluorine (F), and thiocyanate (SCN). In some specific embodiments, the material structure of the perovskite light-absorbing layer can be Cs. x FA1 x Pb(I y Br1 y 3, x and y are 0~1 respectively.

[0054] In some embodiments, the material of the transparent conductive layer includes, but is not limited to, transparent conductive materials such as ITO and IZO.

[0055] In some embodiments, the electrode material includes, but is not limited to, conductive metals such as silver, tin, aluminum, and copper.

[0056] In some embodiments, the antireflective layer is made of materials including, but not limited to, magnesium fluoride (MgF2).

[0057] In another aspect, the present invention provides a three-terminal tandem solar cell. According to an embodiment of the present invention, the three-terminal tandem solar cell is prepared by the method described above, referring to… Figure 4The three-terminal tandem solar cell includes: a silicon substrate 100, which has a light-facing surface 110 and a back-lighting surface 120 disposed opposite to each other, and the entire surface of the light-facing surface is textured; an N-region structure 200 and a P-region structure 300, which are respectively disposed at intervals on the surface of the back-lighting surface 120, and the surfaces of the N-region structure 200 and the P-region structure 300 away from the silicon substrate 100 are planar; a silicon oxide layer 600, which is disposed on the textured surface; a front-side n-type doped polycrystalline silicon layer 700, which is disposed on the side of the silicon oxide layer 600 away from the silicon substrate 100; a composite layer 800, which is disposed on the side of the front-side n-type doped polycrystalline silicon layer 700 away from the silicon substrate 100; and a top cell 900, which is disposed on the side of the composite layer 800 away from the silicon substrate 100. Therefore, the entire surface of the light-facing side has a textured structure, which can form a textured n-type doped polycrystalline silicon layer on the front side. This can enhance the light absorption of the battery while retaining the tunnel junction, ensuring that the top and bottom batteries are in contact and connected. At the same time, the surfaces of the N-region and P-region structures away from the silicon substrate are planar, which can effectively protect the battery performance of the bottom battery.

[0058] In another aspect, the present invention provides a photovoltaic module. According to an embodiment of the present invention, the photovoltaic module includes the aforementioned three-terminal tandem solar cell.

[0059] Example Example 1 The TBC bottom cell fabrication process is as follows: 1. Polishing of N-type silicon substrates is performed using an alkaline solution. The alkaline solution consists of NaOH and polishing additives in a volume ratio of 11:3, with a NaOH concentration of 2.1%, a solution temperature of 67°C, and a process time of 250 seconds. 2. A P-region tunneling silicon oxide layer and a polycrystalline silicon layer were formed on the back surface of a silicon substrate using LPCVD: The oxygen flow rate for preparing the silicon oxide layer was 32000 sccm, the temperature was 600℃, the process time was 1000 s, and the tube blocking time was 650 s, resulting in a tunneling silicon oxide layer with a thickness of 2.1 nm. The polycrystalline silicon layer was deposited at a temperature of 550℃, a process time of 11500 s, and silane flow rates of 190, 440, and 620 sccm for the three-stage gas inlet method, respectively. The polycrystalline silicon layer had a thickness of 300 nm and a surface concentration of 6 × 10⁻⁶. 19 cm -3 ; 3. Boron diffusion: The boron diffusion source flow rate is 250 sccm, the temperature is 855℃, and the process time is 1000s; the advance step temperature is 950℃, and the process time is 1100s; the oxidation temperature is 950℃, the oxygen flow rate is 8000 sccm, and the oxidation time is 1600s, ultimately forming a structure of P-poly layer (boron-doped polycrystalline silicon layer) + BSG layer. The thickness of the P-poly layer is 300nm, the thickness of the BSG layer is 50nm, and the sheet resistance is 80. 4. Laser removal of the BSG layer in the N-region and Gap region on the back side, with a laser power of 45W, an overlap rate of 55%, a frequency of 550kHz, and a pulse width of 1.0μs; 5. The BSG layer formed on the sun-facing surface and sides is removed by a wet chain machine; 6. The P-poly layer on the light-facing and side surfaces, as well as the P-poly layers in the Gap and N regions, are removed by alkaline washing using a wet alkaline washing tank. The tank temperature of the wet alkaline washing tank is 60℃, and the process time is 250s. After passing through the alkaline tank, the thickness of the BSG layer in the P region becomes 20nm. 7. An N-region tunneling silicon oxide layer and a polycrystalline silicon layer were formed on the back surface of a silicon substrate using LPCVD: The oxygen flow rate for preparing the oxide layer was 31000 sccm, the temperature was 600℃, the process time was 1100 s, and the tube blocking time was 700 s, resulting in an N-region tunneling silicon oxide layer with a thickness of 2.2 nm. The polycrystalline silicon layer was deposited at 600℃ for 4000 s, with silane flow rates of 190, 440, and 620 sccm for the three-stage gas inlet method, resulting in a polycrystalline silicon layer thickness of 200 nm and a surface concentration of 5.6 × 10⁻⁶. 20 cm -3 ; 8. Phosphorus diffusion: The phosphorus diffusion flow rate is 1200 sccm, the temperature is 800℃, and the process time is 1200s; the advance step temperature is 880℃, and the process time is 1100s; the oxidation temperature is 870℃, the oxygen flow rate is 2200 sccm, and the oxidation time is 800s; finally, an N-poly layer (phosphorus-doped polycrystalline silicon layer) + PSG layer structure is formed, where the thickness of the N-poly layer is 200nm, the thickness of the PSG layer is 50nm, and the sheet resistance is 20. 9. Laser removal of the PSG layer in the P-region and Gap region on the back side, with a laser power of 40W, an overlap rate of 55%, a frequency of 550kHz, and a pulse width of 1.0μs; 10. The PSG layer formed on the sun-facing surface and sides is removed by a wet chain machine; 11. The N-poly layer on the light-facing and side surfaces and the N-poly layer in the P-area and Gap areas on the back surface are removed by alkaline washing in a wet alkaline bath. The temperature of the wet alkaline washing bath is 60℃ and the process time is 250s. At this time, the thickness of the PSG layer in the N-area becomes 20nm after passing through the alkaline bath, while the thickness of the BSG layer in the P-area becomes 10nm after passing through the alkaline bath. 12. PECVD SiO2 mask layer deposition: deposition process temperature 540℃, silane SiH4 flow rate for SiO2 preparation 931sccm, nitrous oxide N2O flow rate 12109sccm, discharge power 14kW, pulse on / off ratio 5:125ms, time 700s, mask layer thickness 60nm. 13. The mask layer formed by the wet chain machine is removed from the light-facing surface and the side surface. At this time, the mask layer and the PSG layer in the N region constitute the first composite mask, and the mask layer and the BSG layer in the P region constitute the second composite mask. 14. Texturing of the backlight side: The alkaline solution for texturing consists of H2O, NaOH, and texturing additives in a volume ratio of 470:6:11, with a solution temperature of 75℃ and a process time of 550s. The texturized silicon wafer is then acid-washed using an acid bath. The acid solution consists of H2O and HF in a volume ratio of 110:1, with a temperature of 65℃ and a process time of 50s. After texturing, the thicknesses of the first composite mask and the second composite mask on the backlight side are 20nm and 18nm, respectively. 15. A silicon oxide layer and a phosphorus-doped polycrystalline silicon layer were prepared on the textured surface of the light-facing side using LPCVD: the oxygen flow rate for preparing the silicon oxide layer was 31000 sccm, the temperature was 600℃, the process time was 1000 s, and the tube blocking time was 800 s, resulting in a silicon oxide layer with a thickness of 2.1 nm; the polycrystalline silicon layer was deposited at a temperature of 600℃, a process time of 3000 s, and silane flow rates of 190, 440, and 620 sccm for three gas inlet methods, respectively, resulting in a polycrystalline silicon layer thickness of 150 nm and a surface concentration of 5 × 10⁻⁶. 20 cm -3 The phosphorus diffusion process forms a front-side phosphorus-doped polycrystalline silicon layer. The phosphorus source flow rate is 1200 sccm, the temperature is 800℃, and the process time is 1100 s. The advance step temperature is 880℃, and the process time is 1200 s. The oxidation temperature is 870℃, the oxygen flow rate is 1500-3000 sccm, and the oxidation time is 800 s. Finally, a front-side N-poly layer + PSG layer structure is formed, where the thickness of the front-side N-poly layer is 160 nm, the thickness of the PSG layer is 50 nm, and the sheet resistance is 30. 16. The PSG layer formed on the backlight surface and sides is removed by a wet chain machine; 17. The N-poly coating deposited on the back and sides is removed by alkaline washing in a wet alkaline bath, and the BSG / PSG / mask layer on the back and the PSG layer on the light side are removed by acid washing. The alkaline bath temperature is 60℃, the process time is 300s, and the alkaline solution is composed of H2O, NaOH and polishing additives in a volume ratio of 300:18:5, with a NaOH concentration of approximately 3%. The acid bath temperature is 40℃, the process time is 120s, and the acid solution is composed of H2O and HF in a volume ratio of 3:2. 18. An aluminum oxide layer was deposited by back-to-back double-intercalation deposition using the ALD deposition method at a process temperature of 300℃ and a process time of 900s, resulting in an aluminum oxide thickness of 5nm. 19. Back film: The coating process temperature is 530℃, and it consists of 3 layers. From the silicon substrate outwards, the silicon nitride layers are deposited on the surface of the aluminum oxide layer in the following order: silicon nitride 1, silicon nitride 2, and silicon nitride 3. The silicon nitride layers are different in refractive index, and the thicknesses of each layer are 18nm, 24nm, and 28nm, respectively. The overall refractive index is 2.12. 20. A first metal grid line and a second metal grid line are formed on the back side by screen printing. After high-temperature sintering, the metal grid lines form ohmic contacts with the doped polycrystalline silicon layer to collect and conduct current, resulting in the following: Figure 3 The TBC bottom battery shown.

[0060] The fabrication process of the top-mounted solar cell is as follows: 1. Composite layer: An IZO conductive layer with a thickness of 8 nm is deposited on the upper surface of the crystalline silicon bottom cell using PVD sputtering. 2. Hole transport layer: A NiOx layer with a thickness of 24 nm was prepared on the surface of the composite layer away from the crystalline silicon base cell by PVD magnetron sputtering. 3. Perovskite Active Layer: PbI2, PbBr2, CsI, FAI, and MABr were dispersed in a mixed solvent of DMF and DMSO (DMF to DMSO volume ratio 5:1) to obtain a perovskite precursor solution. The perovskite active layer was prepared using a spin-coating method on the NiOx layer obtained in step 2: spin-coating was first performed at 2500 rpm for 10 s, and then at 3500 rpm for 25 s. 5 s before the end of the spin-coating process, 200 μL of chlorobenzene was dropped into the center of the substrate. After the spin-coating was stopped, the substrate was immediately transferred to a heating plate at 100°C and annealed for 18 min to obtain a CsI layer with a thickness of 710 nm. 0.22 FA 0.78 Pb(I 0.85 Br 0.15 3 floors; 4. Electron transport layer: A C60 layer with a thickness of 14 nm was prepared on the surface of the perovskite active layer obtained in step 3 by thermal evaporation. 5. Buffer layer: A SnO2 layer with a thickness of 20 nm is prepared on the side of the C60 layer obtained in step 4 that is away from the perovskite active layer by atomic layer deposition. 6. Transparent oxide conductive layer: An ITO conductive layer is deposited on the surface of the SnO2 layer obtained in step 5 away from the electron transport layer by sputtering. The thickness of the ITO conductive layer is 60 nm. 7. Electrode: An Ag electrode with a thickness of 90 nm was deposited on the surface of the transparent oxide conductive layer using a thermal evaporation method; 8. Antireflection layer: Using a thermal evaporation method, a 70nm thick MgF2 antireflection layer is deposited on the outermost surface of the cell, away from the transparent oxide conductive layer, thus obtaining a perovskite top cell, i.e., a three-terminal tandem solar cell, such as... Figure 4 As shown.

[0061] Comparative Example 1 The TBC bottom cell fabrication process is as follows: 1. Polishing of N-type silicon substrates is performed using an alkaline solution. The alkaline solution consists of NaOH and polishing additives in a volume ratio of 11:3, with a NaOH concentration of 2.1%, a solution temperature of 67°C, and a process time of 250 seconds. 2. A P-region tunneling silicon oxide layer and a polycrystalline silicon layer were formed on the back surface of a silicon substrate using LPCVD: The oxygen flow rate for preparing the silicon oxide layer was 32000 sccm, the temperature was 600℃, the process time was 1000 s, and the tube blocking time was 650 s, resulting in a tunneling silicon oxide layer with a thickness of 2.1 nm. The polycrystalline silicon layer was deposited at a temperature of 550℃, a process time of 11500 s, and silane flow rates of 190, 440, and 620 sccm for the three-stage gas inlet method, respectively. The polycrystalline silicon layer had a thickness of 300 nm and a surface concentration of 6 × 10⁻⁶. 19 cm -3 ; 3. Boron diffusion: The boron diffusion source flow rate is 250 sccm, the temperature is 855℃, and the process time is 1000s; the advance step temperature is 950℃, and the process time is 1100s; the oxidation temperature is 950℃, the oxygen flow rate is 8000 sccm, and the oxidation time is 1600s, ultimately forming a structure of P-poly layer (boron-doped polycrystalline silicon layer) + BSG layer. The thickness of the P-poly layer is 300nm, the thickness of the BSG layer is 50nm, and the sheet resistance is 80. 4. Laser removal of the BSG layer in the N-region and Gap region on the back side, with a laser power of 45W, an overlap rate of 55%, a frequency of 550kHz, and a pulse width of 1.0μs; 5. The BSG layer formed on the sun-facing surface and sides is removed by a wet chain machine; 6. The P-poly layer on the light-facing and side surfaces, as well as the P-poly layers in the Gap and N regions, are removed by alkaline washing using a wet alkaline washing tank. The tank temperature of the wet alkaline washing tank is 60℃, and the process time is 250s. After passing through the alkaline tank, the thickness of the BSG layer in the P region becomes 20nm. 7. An N-region tunneling silicon oxide layer and a polycrystalline silicon layer were formed on the back surface of a silicon substrate using LPCVD: The oxygen flow rate for preparing the oxide layer was 31000 sccm, the temperature was 600℃, the process time was 1100 s, and the tube blocking time was 700 s, resulting in an N-region tunneling silicon oxide layer with a thickness of 2.2 nm. The polycrystalline silicon layer was deposited at 600℃ for 4000 s, with silane flow rates of 190, 440, and 620 sccm for the three-stage gas inlet method, resulting in a polycrystalline silicon layer thickness of 200 nm and a surface concentration of 5.6 × 10⁻⁶. 20 cm -3 ; 8. Phosphorus diffusion: The phosphorus diffusion flow rate is 1200 sccm, the temperature is 800℃, and the process time is 1200s; the advance step temperature is 880℃, and the process time is 1100s; the oxidation temperature is 870℃, the oxygen flow rate is 2200 sccm, and the oxidation time is 800s; finally, an N-poly layer (phosphorus-doped polycrystalline silicon layer) + PSG layer structure is formed, where the thickness of the N-poly layer is 200nm, the thickness of the PSG layer is 50nm, and the sheet resistance is 20. 9. Laser removal of the PSG layer in the P-region and Gap region on the back side, with a laser power of 40W, an overlap rate of 55%, a frequency of 550kHz, and a pulse width of 1.0μs; 10. The PSG layer formed on the sun-facing surface and sides is removed by a wet chain machine; 11. The N-poly layer on the light-facing side and the N-poly layer on the back P area and the Gap area are removed by alkaline washing in a wet alkaline bath. The temperature of the wet alkaline washing tank is 60℃ and the process time is 250s. The BSG layer and PSG layer on the back side are removed by acid washing in an acid bath. 12. PECVD SiO2 mask layer deposition: deposition process temperature 540℃, silane SiH4 flow rate for SiO2 preparation 931sccm, nitrous oxide N2O flow rate 12109sccm, discharge power 14kW, pulse on / off ratio 5:125ms, time 700s, mask layer thickness 60nm. 13. An aluminum oxide layer was deposited by back-to-back double-insertion deposition using the ALD deposition method at a process temperature of 300℃ and a process time of 900s, resulting in an aluminum oxide thickness of 5nm. 14. Back film: The coating process temperature is 530℃, and it consists of 3 layers. From the silicon substrate outwards, the silicon nitride layers are deposited on the surface of the aluminum oxide layer in the following order: silicon nitride 1, silicon nitride 2, and silicon nitride 3. The silicon nitride layers are distinguished by their refractive indices, and the thicknesses of each layer are 18nm, 24nm, and 28nm, respectively. The overall refractive index is 2.12. 15. By screen printing, a first metal grid line and a second metal grid line are formed on the back side. After high-temperature sintering, the metal grid lines form ohmic contacts with the doped polycrystalline silicon layer to collect and conduct current. In the resulting TBC bottom cell, the light-facing surface is flat.

[0062] The fabrication process for the top cell is the same as in Example 1.

[0063] The three-terminal stacked cells obtained in Example 1 and Comparative Example 1 were subjected to performance testing. The specific testing method was as follows: using a solar simulator and IV tester, the electrical performance of the cells obtained in the above examples and comparative examples was tested through steady-state power output testing under one standard solar intensity. The test results are shown in Table 1.

[0064] Table 1

[0065] Therefore, it can be seen that the short-circuit current of silicon substrates with light-facing textured surfaces processed by the method of the present invention is significantly improved compared with the comparative example. This directly proves that the textured surface structure of the light-facing surface of the crystalline silicon bottom cell enhances the light absorption of the bottom cell, increases the short-circuit current, and improves the overall efficiency of the stacked cell.

[0066] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0067] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for preparing a three-terminal tandem solar cell, characterized in that, include: A silicon substrate is provided, the silicon substrate having a light-facing side and a light-reflecting side disposed opposite to each other; N-region structures and P-region structures are respectively fabricated on the back surface of the silicon substrate; A mask layer is formed on the surface of the N-region structure and the P-region structure, as well as on the surface of the gap region between the N-region structure and the P-region structure; A textured surface is formed on the entire light-facing surface of the silicon substrate; A silicon oxide layer and a front-side n-type doped polycrystalline silicon layer are sequentially formed on the surface of the textured surface; A composite layer and a top cell are sequentially formed on the side of the front n-type doped polycrystalline silicon layer away from the silicon substrate.

2. The method according to claim 1, characterized in that, The material of the mask layer includes silicon oxide.

3. The method according to claim 2, characterized in that, The mask layer is formed by plasma-enhanced chemical vapor deposition, and the thickness of the mask layer is 50-70 nm.

4. The method according to claim 1, characterized in that, A first phosphosilicate glass layer is provided between the N-region structure and the mask layer, and the first phosphosilicate glass layer and the mask layer on its surface constitute a first composite mask; a borosilicate glass layer is provided between the P-region structure and the mask layer, and the borosilicate glass layer and the mask layer on its surface constitute a second composite mask.

5. The method according to any one of claims 1 to 4, characterized in that, The method for forming the textured surface on the light-facing side of the silicon substrate includes: First, the light-facing surface of the silicon substrate is texturized using an alkaline texturing agent at a solution temperature of 70-80℃ and a process time of 450-650s. Then, the light-facing surface of the silicon substrate is acid-washed using an acid bath to obtain the textured surface.

6. The method according to claim 4, characterized in that, The silicon oxide layer and the front-side n-type doped polysilicon layer are sequentially formed on the textured surface using low-pressure chemical vapor deposition (LPCVD). A second phosphosilicate glass layer is then formed on the surface of the front-side n-type doped polysilicon layer. During the formation of the silicon oxide layer, the oxygen flow rate is 27000-36000 sccm, the temperature is 590-615℃, the process time is 500-1800s, the tube blocking time is 300-1000s, and the thickness of the silicon oxide layer is 1.9-2.3nm. During the formation of the front n-type doped polysilicon layer, the deposition temperature is 590-615℃, the process time is 1500-5000s, and the thickness of the front n-type doped polysilicon layer is 100-200nm.

7. The method according to claim 6, characterized in that, Also includes: The first composite mask, the second composite mask, and the second phosphosilicate glass layer are removed by the same acid washing step.

8. The method according to any one of claims 1 to 4, characterized in that, The top cell includes a perovskite cell.

9. A three-terminal tandem solar cell, characterized in that, It is prepared by the method of any one of claims 1 to 8, comprising: A silicon substrate having a light-facing surface and a back-light surface disposed opposite to each other, wherein the entire surface of the light-facing surface is textured. The N-region structure and the P-region structure are respectively disposed at intervals on the backlight surface, and the surfaces of the N-region structure and the P-region structure away from the silicon substrate are both planar. A silicon oxide layer is disposed on the surface of the textured surface; A front-side n-type doped polycrystalline silicon layer is disposed on the side of the silicon oxide layer away from the silicon substrate; A composite layer is disposed on the side of the front n-type doped polysilicon layer away from the silicon substrate; A top cell is disposed on the side of the composite layer away from the silicon substrate.

10. A photovoltaic module, characterized in that, Including the three-terminal tandem solar cell as described in claim 9.

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