A method for manufacturing a silicon photonic chip

Abstract

The application provides a preparation method of a silicon optical chip, comprising the following steps: selecting a wafer and performing a planarization treatment on the wafer; exposing a target component on the wafer and performing a developing treatment; etching a silicon waveguide, a sidewall air groove and a heat conduction via on the wafer; preparing a double gradient structure on an AWG chip output end, and preparing a heating resistor and a wavelength calibration electrode; depositing a passivation layer and etching a window on the wavelength calibration electrode; grinding a wafer surface, and performing a laser cutting on the wafer to obtain a silicon optical chip. The preparation method of the silicon optical chip provided by the application cancels a separate coupling link, simultaneously defines MRM arrays and all patterns of the AWG chip through one mask and one electron beam exposure, eliminates coupling loss caused by multiple alignment and splicing between separate devices from the source, and improves the integration of the silicon optical chip.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating a silicon photonic chip. Background Technology

[0002] Currently, silicon photonics integrated chips have become the core carrier for realizing chip-level ultra-high bandwidth and low power interconnects. To meet the requirements of multi-channel parallel transmission and bandwidth density, current silicon photonics chips generally adopt a combination architecture of micro-ring modulator (MRM) and arrayed waveguide grating (AWG) chips to realize high-speed optical signal modulation, multiplexing, demultiplexing and detection.

[0003] Most existing silicon photonic chips adopt a discrete device post-assembly mode, that is, MRM arrays and AWG chips are first fabricated on silicon photonic substrates, and then the two are spliced ​​and integrated by end-face coupling, flip bonding or fiber optic connection.

[0004] However, the discretely fabricated MRM array and AWG chip have coupling gaps, requiring additional mode-spot conversion structures or transition waveguides, which introduces additional insertion loss. At the same time, the discrete layout occupies a large chip area, hindering the miniaturization and high channel-count expansion of silicon photonics chips. This results in the current technical challenges of high optical path splicing loss and low integration density in silicon photonics chips. Summary of the Invention

[0005] The main purpose of this application is to provide a method for fabricating silicon photonic chips, which aims to solve the technical problems of high optical path splicing loss and low integration in current silicon photonic chips.

[0006] To achieve the above objectives, this application provides a method for fabricating a silicon photonic chip, comprising:

[0007] Select a wafer and perform planarization on the wafer;

[0008] The target components are exposed on the wafer and then developed; the target components include MRM array, AWG chip, bus waveguide, coupling region, AWG folded flat panel region, array waveguide, receiving waveguide, and mode converter.

[0009] Silicon waveguides, sidewall air trenches, and thermal vias are etched on the wafer;

[0010] A dual gradient structure is fabricated at the output terminal of the AWG chip, and a heating resistor and a wavelength calibration electrode are fabricated.

[0011] A passivation layer is deposited, and the wavelength calibration electrode is etched to create a window;

[0012] The wafer surface is ground, and the wafer is laser-cut to prepare a silicon photonic chip.

[0013] Optionally, selecting a wafer and planarizing the wafer includes:

[0014] Select SOI wafers;

[0015] The SOI wafer is subjected to RCA cleaning;

[0016] The cleaned SOI wafer is then polished for a first preset duration.

[0017] The SOI wafer is polished again for a second preset duration; the first preset duration is longer than the second preset duration.

[0018] The SOI wafer after polishing for a second preset time has a roughness of less than or equal to 0.25 nm and a flatness error of less than or equal to 3 nm / 20 μm.

[0019] Optionally, the step of exposing the target component on the wafer and performing a development process includes:

[0020] An adhesion promoter is coated on the bottom layer of the wafer, and a photoresist is spin-coated.

[0021] The photoresist coated on the wafer is dried using a stepped heating method;

[0022] The target component is exposed on the wafer surface using an electron beam direct writing device; wherein, the exposure dose is dynamically adjusted according to the resonant wavelength corresponding to the micro-ring modulator.

[0023] The wafer is then subjected to a development process.

[0024] Optionally, etching a silicon waveguide on the wafer includes:

[0025] Silicon waveguides were etched using inductively coupled plasma (ICP) technology.

[0026] After etching is completed, plasma is introduced to remove the photoresist;

[0027] A fluoride passivation layer is deposited to passivate the sidewalls.

[0028] Optionally, sidewall air trenches are etched on the wafer, including:

[0029] Spin-coat the photoresist again;

[0030] The sidewall air trenches were etched using inductively coupled plasma (ICP) technology.

[0031] After etching is complete, remove the photoresist;

[0032] The air grooves on the side wall are filled with air medium to form a low thermal conductivity isolation layer.

[0033] Optionally, thermally conductive vias are etched on the wafer, including:

[0034] At the etching location, the top silicon layer of the wafer is etched; the etching location is the center of the micro-ring resonator ring of the wafer biased towards the bus waveguide side;

[0035] After etching the top silicon layer of the wafer, the buried oxide layer of the wafer is etched and penetrated.

[0036] Remove the oxide layer remaining after the etching process.

[0037] Optionally, fabricating a dual-gradient structure at the output terminal of the AWG chip includes:

[0038] The physical vapor deposition (PVD) process is used to sputter the adhesion layer;

[0039] Tungsten metal was filled using chemical vapor deposition (CVD) process;

[0040] Polishing process for the tungsten metal layer;

[0041] A geometrically gradient structure and a refractive index gradient layer are fabricated at the output end of the AWG chip.

[0042] Optionally, the fabrication of the heating resistor and wavelength calibration electrode includes:

[0043] Spin-coating a double layer of photoresist and exposing the heating resistor and wavelength calibration electrode patterns;

[0044] The adhesion layer is deposited using electron beam evaporation.

[0045] The residual metal on the wafer was stripped using NMP solution, and signal electrodes, ground electrodes, and probe leads were fabricated.

[0046] Optionally, the deposition of the passivation layer and the etching of a window for the wavelength calibration electrode include:

[0047] A passivation layer is deposited using plasma-enhanced chemical vapor deposition (PECVD).

[0048] The electrode windowing area is defined using photolithography;

[0049] The window is etched using inductively coupled plasma (ICP) etching.

[0050] Plasma is introduced to remove organic matter and polymer residues from the window area.

[0051] Optionally, grinding the wafer surface and laser-cutting the wafer to prepare a silicon photonic chip includes:

[0052] The wafer surface is ground, and the ground wafer is then subjected to chemical relaxation treatment;

[0053] The wafer is laser-cut to prepare a silicon photonic chip;

[0054] The silicon photonics chip was subjected to appearance testing, electrode continuity testing, and insertion loss testing.

[0055] This application provides a method for fabricating a silicon photonic chip, comprising: selecting a wafer and planarizing it; exposing target components on the wafer and performing development; the target components include an MRM array, an AWG chip, a bus waveguide, a coupling region, an AWG folded planar region, an array waveguide, a receiving waveguide, and a mode converter; etching silicon waveguides, sidewall air trenches, and thermal vias on the wafer; fabricating a dual-gradient structure at the output end of the AWG chip and fabricating a heating resistor and a wavelength calibration electrode; depositing a passivation layer and etching a window on the wavelength calibration electrode; grinding the wafer surface and laser-cutting the wafer to obtain the silicon photonic chip. The silicon photonic chip fabrication method provided in this application eliminates the discrete coupling stage, defining the entire pattern of the MRM array and the AWG chip simultaneously through a single mask and a single electron beam exposure, thereby eliminating coupling losses caused by multiple alignments and splicing between discrete components from the source and improving the integration density of the silicon photonic chip. Attached Figure Description

[0056] To more clearly illustrate the solutions in this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 This is a flowchart of the method for fabricating a silicon photonic chip provided in the embodiments of this application. Detailed Implementation

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0059] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0060] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0061] Please see Figure 1 , Figure 1 This is a flowchart of the method for fabricating a silicon photonic chip provided in the embodiments of this application. Figure 1 As shown, the method for fabricating a silicon photonic chip provided in this application includes:

[0062] S110, Select a wafer and perform planarization on the wafer.

[0063] S120, expose the target components on the wafer and perform development processing; the target components include MRM array, AWG chip, bus waveguide, coupling region, AWG folded flat plate region, array waveguide, receiving waveguide, and mode converter.

[0064] S130, etching silicon waveguides, sidewall air trenches, and thermal vias on the wafer.

[0065] S140, a dual gradient structure is fabricated at the output end of the AWG chip, and a heating resistor and a wavelength calibration electrode are fabricated.

[0066] S150, deposit a passivation layer and etch a window onto the wavelength calibration electrode.

[0067] S160, grind the surface of the wafer, and laser cut the wafer to prepare a silicon photonic chip.

[0068] In this embodiment, a wafer is selected, optionally an SOI wafer, and the wafer is planarized to ensure that the flatness of the wafer surface meets the requirements.

[0069] The target components are then exposed on the wafer and developed. It should be understood that the target components include MRM arrays, AWG chips, bus waveguides, coupling regions, AWG folded flat panel regions, array waveguides, receiving waveguides, and mode converters.

[0070] Silicon waveguides, sidewall air trenches, and thermal vias are etched on the wafer. A dual-gradient structure is fabricated at the output of the AWG chip, and heating resistors and wavelength calibration electrodes are also fabricated.

[0071] After etching and fabricating the components, a passivation layer is deposited, and the wavelength calibration electrode is etched and windowed. Subsequently, the wafer surface is ground, and the wafer is laser-cut to obtain a silicon photonic chip.

[0072] The silicon photonics chip fabrication method provided in this application eliminates the discrete coupling stage. By defining the entire pattern of the MRM array and the AWG chip simultaneously through a single mask and a single electron beam exposure, the coupling loss caused by multiple alignments and splicings between discrete devices is eliminated from the source, and the integration of the silicon photonics chip is improved.

[0073] Optionally, selecting a wafer and planarizing the wafer includes:

[0074] Select SOI wafers;

[0075] The SOI wafer is subjected to RCA cleaning;

[0076] The cleaned SOI wafer is then polished for a first preset duration.

[0077] The SOI wafer is polished again for a second preset duration; the first preset duration is longer than the second preset duration.

[0078] The SOI wafer after polishing for a second preset time has a roughness of less than or equal to 0.25 nm and a flatness error of less than or equal to 3 nm / 20 μm.

[0079] This process uses an 8-inch high-resistivity SOI wafer with a three-layer structure. The top silicon layer has a thickness of 220nm and a buried oxide layer. Thickness: 2μm, substrate silicon resistivity High resistivity silicon substrates help reduce high-frequency electro-optic interference, providing a good electrical isolation basis for subsequent electro-optic modulation and high-frequency signal transmission.

[0080] Furthermore, the SOI wafer undergoes RCA cleaning. RCA cleaning is a standard process in semiconductor manufacturing for removing organic contaminants, metal ions, and native oxide layers from the wafer surface. This solution details it into the following cleaning steps:

[0081] (1) SC-1 Organic Cleaning:

[0082] Preparation The cleaning solution was heated in a 75°C water bath. The wafer was vertically immersed in the solution and slowly lifted and swung around for 12 minutes. The solution (ammonia-hydrogen peroxide mixture) effectively removes organic contaminants and nanoparticles from the wafer surface. Ammonia provides an alkaline environment to strip away organic matter and particles, while hydrogen peroxide acts as an oxidant to promote surface oxidation and particle removal.

[0083] (2) Stripping of dilute HF oxide layer:

[0084] Immerse in a 1.2% (v / v) diluted hydrofluoric acid (DHF) solution at room temperature for 40 seconds. DHF selectively dissolves... This removes the natural oxide layer on the surface and The impurities remaining after cleaning expose the clean silicon surface.

[0085] (3) SC-2 ion cleaning:

[0086] Preparation Clean with the cleaning solution at a constant temperature of 75℃ for 10 minutes. The solution (a mixture of hydrochloric acid and hydrogen peroxide) is mainly used to remove heavy metal ions and mobile ionic contaminants. Hydrochloric acid provides an acidic environment that converts metal ions into soluble chlorides; hydrogen peroxide promotes surface oxidation and assists in ion desorption.

[0087] (4) Rinsing and drying with high-purity water

[0088] use Rinse thoroughly with deionized water for 2 minutes to ensure the chemical cleaning solution is completely removed. Then, blow dry evenly with a nitrogen gun at a 45-degree angle, followed by baking in a 110°C vacuum baking chamber for 8 minutes to completely remove surface moisture, providing a clean and dry surface for subsequent photoresist coating and CMP polishing.

[0089] Global planarization is achieved by using chemical mechanical polishing (CMP) on the top silicon layer of the wafer.

[0090] It should be noted that chemical mechanical polishing (CMP) is a core technology for smoothing the surface of a wafer and achieving uniform thickness. In this embodiment, an alkaline silicon-specific colloidal silica polishing slurry with a particle size of 50 nm is used.

[0091] The polishing parameters are as follows: polishing pressure: 1.4 psi, polishing disk speed: 62 rpm, and wafer stage speed: 59 rpm.

[0092] Perform two-stage polishing:

[0093] Pre-polishing: Polishing is performed on the cleaned SOI wafer for a first preset time, optionally 2 minutes, to quickly remove uneven thickness on the top silicon surface.

[0094] Post-polishing: The SOI wafer is polished again for a second preset time. Optionally, the second preset time is 1 minute. Fine polishing is performed to reduce surface roughness.

[0095] The two-stage polishing process controls the total removal to approximately 5nm, removing only an extremely thin layer. The aim is to eliminate surface scratches and processing damage, rather than significantly altering the thickness of the top silicon layer. Immediately after polishing, the surface is rinsed with deionized water and dried with nitrogen.

[0096] Among them, the polished wafers must meet the following requirements: surface roughness ≤ 0.25nm and flatness error ≤ 3nm / 20μm.

[0097] This flatness is a critical prerequisite for ensuring the uniformity of subsequent waveguide etching. The transmission loss of silicon optical waveguides is extremely sensitive to waveguide geometry. Fluctuations in the thickness of the top silicon layer directly cause changes in the effective refractive index of the waveguide, which in turn affects the design values ​​of the microring resonant wavelength and the AWG channel spacing.

[0098] Optionally, the step of exposing the target component on the wafer and performing a development process includes:

[0099] An adhesion promoter is coated on the bottom layer of the wafer, and a photoresist is spin-coated.

[0100] The photoresist coated on the wafer is dried using a stepped heating method;

[0101] The target component is exposed on the wafer surface using an electron beam direct writing device; wherein, the exposure dose is dynamically adjusted according to the resonant wavelength corresponding to the micro-ring modulator.

[0102] The wafer is then subjected to a development process.

[0103] In this embodiment, an adhesion promoter is coated on the bottom layer of the wafer. Optionally, the adhesion promoter is hexamethyldisilazane (HMDS). The coating method can be a two-stage spin coating process of "low speed 300 rpm for 5 seconds + high speed 3000 rpm for 30 seconds", followed by baking at 120°C for 60 seconds. HMDS forms a hydrophobic layer on the silicon surface, enhancing the adhesion between the subsequent photoresist and the substrate and preventing the pattern from falling off during development.

[0104] In this embodiment, the photoresist is spin-coated using ZEP520A electron beam photoresist in two stages: 500 rpm for 5 seconds and 4200 rpm for 60 seconds, resulting in a photoresist thickness of 320 nm. ZEP520A electron beam photoresist is a high-resolution positive electron beam photoresist commonly used for nanoscale pattern definition.

[0105] After applying the adhesion promoter and spin-coating the photoresist, a stepped heating method was used for drying. Specifically, the stepped heating method was as follows: 100℃ for 60 seconds, followed by 150℃ for 40 seconds, and finally 180℃ for 60 seconds. Slow heating can eliminate internal stress in the resist layer and prevent pattern deformation caused by stress release. After baking, the film was cooled to room temperature, and a film thickness gauge was used for multi-point measurement to ensure that the thickness deviation was ≤ ±4nm.

[0106] In this embodiment, an electron beam direct writing device is used to expose all functional patterns in a single exposure, i.e., all target components, including: non-uniform diameter microring resonator array, bus waveguide, coupling region, AWG folded planar region, array waveguide, receiving waveguide, and adaptive mode converter. This embodiment eliminates the need for multiple alignments and exposures by exposing all functional patterns in a single exposure, avoiding alignment errors caused by multiple overlays, and achieving integrated pattern definition of the MRM and AWG on the same substrate.

[0107] The exposure parameters are as follows: accelerating voltage: 100kV; beam current: 10nA; field stitching accuracy: ≤8nm; proximity effect correction coefficient: 0.85.

[0108] This innovative approach introduces dose-compensated exposure to achieve on-wafer uniformity of the microring resonant wavelength. Specifically, the exposure dose is appropriately increased for short-wavelength microrings and decreased for long-wavelength microrings. Working principle: Direct changes in waveguide geometry affect the microring resonant wavelength, while variations in electron beam exposure dose affect the size of the photoresist pattern after development, which in turn affects the linewidth of the waveguide formed by subsequent etching, ultimately altering the effective refractive index and resonant wavelength of the microring. Therefore, local dose compensation allows for in-situ correction of wavelength deviations during manufacturing, thereby reducing the need for temperature control and power consumption in later stages.

[0109] Finally, the wafer undergoes a development process. Specifically, it is developed with n-butanol for 75 seconds and fixed with isopropanol for 35 seconds. After drying with nitrogen, the wafer is randomly selected to ensure that there are no defects such as microring breaks, waveguide adhesion, or blunt tips.

[0110] Optionally, etching a silicon waveguide on the wafer includes:

[0111] Silicon waveguides were etched using inductively coupled plasma (ICP) technology.

[0112] After etching is completed, plasma is introduced to remove the photoresist;

[0113] A fluoride passivation layer is deposited to passivate the sidewalls.

[0114] In this embodiment, inductively coupled plasma (ICP) etching is used for silicon waveguide etching. The etching parameters are as follows: Process gas: , , Chamber pressure: 8.5 mTorr; ICP source power: 1300 W; bias power: 320 W; target etching depth: 195 nm ± 3 nm.

[0115] in, and The combination is a classic gas formulation in silicon ICP etching: The fluorine radicals generated during decomposition react chemically with silicon to achieve deep etching; In plasma, fluorinated carbon polymers can form and deposit on the silicon surface, protecting the sidewalls. Ar acts as an inert gas to assist ion bombardment. Matching the ICP source power and bias power is crucial: the upper electrode power determines the plasma concentration, while the lower electrode power controls the ion bombardment energy; only when these two are coordinated can efficient and anisotropic etching be achieved.

[0116] After etching is completed, it is inserted. Plasma ashing to remove adhesive, temperature 125℃, time 6 minutes. Plasma removes organic photoresist by converting it into gaseous products through an oxidation reaction.

[0117] Access A 5 nm fluoride passivation layer was deposited in a short time to cover the waveguide sidewall surface. This fluorinated carbon polymer passivation film can protect the waveguide sidewall, reduce scattering loss and carrier absorption loss caused by surface states, and make the waveguide transmission loss ≤0.7 dB / cm.

[0118] After the above steps are completed, the wafer is sampled and inspected using a scanning electron microscope to ensure that the sidewall perpendicularity is ≥89° and the sidewall roughness is ≤1.2nm.

[0119] Optionally, sidewall air trenches are etched on the wafer, including:

[0120] Spin-coat the photoresist again;

[0121] The sidewall air trenches were etched using inductively coupled plasma (ICP) technology.

[0122] After etching is complete, remove the photoresist;

[0123] The air grooves on the side wall are filled with air medium to form a low thermal conductivity isolation layer.

[0124] In this embodiment, photoresist is recoated, and the exposure window only covers the strip trench areas on both sides of the microring. The trenches are 2.2 μm wide and cover 90% of the arc of the microring. Inductively coupled plasma (ICP) etching is used to etch the sidewall air trenches, reaching the buried oxide layer interface to a depth of approximately 220 nm. The etching selectivity is ≥15:1, where the etching rate ratio is the ratio of silicon to photoresist, ensuring that the photoresist effectively protects the non-etched areas throughout the etching process. After etching, a three-step stripping process using NMP, acetone, and isopropanol is employed to thoroughly remove photoresist and polymer residues.

[0125] After etching, the trenches are filled with an air medium. Air has extremely low thermal conductivity (approximately 0.025). Silicon has a thermal conductivity of approximately [missing information]. Buried oxygen layer Thermal conductivity approximately By introducing air trenches, a low thermal conductivity isolation layer is formed, which effectively blocks lateral thermal crosstalk between adjacent microrings and prevents heat from spreading between adjacent devices during multi-channel parallel operation, thus preventing wavelength drift from affecting each other.

[0126] Optionally, thermally conductive vias are etched on the wafer, including:

[0127] At the etching location, the top silicon layer of the wafer is etched; the etching location is the center of the micro-ring resonator ring of the wafer biased towards the bus waveguide side;

[0128] After etching the top silicon layer of the wafer, the buried oxide layer of the wafer is etched and penetrated.

[0129] Remove the oxide layer remaining after the etching process.

[0130] In this embodiment, a circular heat-conducting via with a diameter of 4.2 μm is formed on the side of the microring resonator ring that is biased towards the bus waveguide. By placing the heat dissipation channel on the side biased towards the bus waveguide rather than in the center, the influence of the heat dissipation structure on the optical mode field is reduced, and an asymmetrical heat flow distribution is achieved in the optical path direction, further reducing thermal crosstalk.

[0131] The etching steps for the thermal vias are as follows: First, etch the top silicon layer; second, etch through the buried oxide layer. The etching depth extends down to the substrate silicon; the total etching depth is approximately 2220 nm (220 nm top silicon and 2000 nm buried oxide layer).

[0132] After etching, the via is gently rinsed with diluted BOE solution for 10 seconds to remove any residual oxide layer that may have formed at the bottom of the via due to etching or exposure to the environment. This ensures that the metal filling of the heat dissipation path can make good contact with the silicon substrate, thus achieving a continuous heat conduction path.

[0133] Optionally, fabricating a dual-gradient structure at the output terminal of the AWG chip includes:

[0134] The physical vapor deposition (PVD) process is used to sputter the adhesion layer;

[0135] Tungsten metal was filled using chemical vapor deposition (CVD) process;

[0136] Polishing process for the tungsten metal layer;

[0137] A geometrically gradient structure and a refractive index gradient layer are fabricated at the output end of the AWG chip.

[0138] In this embodiment, a physical vapor deposition (PVD) process is used to sputter the adhesion layer. The adhesion layer thickness is 25 nm, the substrate temperature is 200°C, and the stress is controlled to ≤100 MPa. TiN serves as both a tungsten adhesion-promoting layer and a diffusion-blocking layer to prevent tungsten atoms from diffusing into the silicon substrate.

[0139] The process of filling tungsten metal using chemical vapor deposition (CVD) is as follows: and A reduction reaction occurs at a temperature of approximately 460℃ and a pressure of 50 Torr, generating metallic tungsten which is deposited in the through-hole, filling it completely and covering the surface by approximately 300 nm.

[0140] The core application of the aforementioned CVD process for filling tungsten is in filling contact holes or through-holes with high aspect ratios. Tungsten metal possesses excellent step coverage and gap filling capabilities, as well as good anti-electromigration properties.

[0141] The tungsten layer was polished using a tungsten-specific polishing slurry. The polishing pressure was 1.2 psi, and the tungsten pillar surface was polished until it was flush with the top silicon layer. After polishing, the surface was cleaned to ensure no polishing slurry residue remained.

[0142] This creates a vertical, low-thermal-resistance heat dissipation channel that extends from the top of the microring through the via to the substrate silicon. Heat can be quickly conducted downwards to the substrate silicon via the tungsten pillar, preventing heat accumulation in localized areas that could lead to increased microring temperature and wavelength drift.

[0143] In this embodiment, fine compensation for the length difference of the array waveguide of the folded AWG is performed, and channel crosstalk is corrected by electron beam micro-dose adjustment. It should be understood that the basic working principle of an AWG (Aspect-Oriented Waveguide) is to generate a wavelength division effect by utilizing a fixed optical path difference between arrayed waveguides. Due to process fluctuations during manufacturing, random deviations in the length difference between adjacent arrayed waveguides, core width, and core thickness can affect the crosstalk characteristics of the AWG. This solution uses micro-dose adjustment of the electron beam to finely compensate for the length difference, correcting the deviation at the source of manufacturing.

[0144] A geometrically gradient structure was fabricated at the output end of the AWG chip, in which the waveguide width linearly widened from 0.5 μm to 4.2 μm, with a length of 85 μm. The wider waveguide has a larger mode field size, resulting in a higher mode field matching degree with the optical fiber and effectively reducing coupling loss.

[0145] A refractive index gradient layer is fabricated at the output end of the AWG chip. By locally low-dose ion implantation, the equivalent refractive index of the waveguide is gradually reduced along the transmission direction to achieve optical path impedance matching and avoid light reflection loss caused by abrupt changes in refractive index.

[0146] In this embodiment, a linear tapered mode converter and a waveguide equivalent refractive index graded layer are simultaneously fabricated at the AWG output end. This achieves precise matching between the mode field size and the fiber array, while optimizing the optical path transmission impedance, further reducing insertion loss, and realizing extremely simple coupling without lenses or adapter structures. By eliminating discrete coupling loss, and simultaneously achieving optical path impedance matching through the mode spot-refractive index dual graded structure, the steady-state coupling insertion loss is ≤0.8dB, and channel crosstalk is minimized. It can stably support high-speed signal transmission.

[0147] Optionally, the fabrication of the heating resistor and wavelength calibration electrode includes:

[0148] Spin-coating a double layer of photoresist and exposing the heating resistor and wavelength calibration electrode patterns;

[0149] The adhesion layer is deposited using electron beam evaporation.

[0150] The residual metal on the wafer was stripped using NMP solution, and signal electrodes, ground electrodes, and probe leads were fabricated.

[0151] In this embodiment, a spin-coated, release-type double-layer photoresist is used to expose the pattern of a micro-heating resistor and a wavelength calibration electrode. During the release process, the photoresist pattern has an inverted trapezoidal outline, facilitating the removal of the metal as it dissolves after metal deposition, leaving only the metal within the target pattern. The release process involves immersing the metal in NMP at 80°C for 20 minutes, followed by ultrasonic-assisted removal of excess metal, while retaining the asymmetric single-point heating resistor.

[0152] An adhesion layer was deposited using electron beam evaporation, comprising a 12 nm thick Ti metal layer and a 90 nm thick Pt metal layer, with a deposition rate of [missing information]. Ti acts as an adhesion layer to improve the adhesion between Pt and silicon or oxides. Pt, as the main material of the heating resistor, has good chemical stability and high resistivity, making it suitable for the fabrication of micro heaters.

[0153] Signal electrodes, ground electrodes, and probe lead-out electrodes were fabricated simultaneously. The electrode pads were 80μm×80μm in size to meet the requirements of probe testing and wire bonding.

[0154] In this embodiment, a unique three-level thermal management structure is used, consisting of sidewall air trench isolation, bottom vertical heat-conducting through-holes, and top local micro heating resistors. At the same time, a wavelength self-calibration feedback photolithography compensation process is introduced to correct the micro-ring resonant wavelength in situ during the manufacturing stage, which greatly reduces the power consumption of the operating temperature control and solves the problem of multi-channel thermal crosstalk.

[0155] In this embodiment, through three-level thermal management—air trench isolation, eccentric thermal conductive through-holes, and asymmetric single-point micro heating—and combined with wavelength compensation technology during the manufacturing stage, the temperature control power consumption is reduced by more than 70%, and the overall energy efficiency is ≤3.5 pJ / bit.

[0156] Optionally, the deposition of the passivation layer and the etching of a window for the wavelength calibration electrode include:

[0157] A passivation layer is deposited using plasma-enhanced chemical vapor deposition (PECVD).

[0158] The electrode windowing area is defined using photolithography;

[0159] The window is etched using inductively coupled plasma (ICP) etching.

[0160] Plasma is introduced to remove organic matter and polymer residues from the window area.

[0161] In this embodiment, plasma-enhanced chemical vapor deposition (PECVD) process is used for deposition. Passivation layer, wherein the temperature is 310℃. , The deposition thickness is 420nm, and the stress is controlled to ≤150MPa to avoid excessive stress causing wafer warping or device performance drift.

[0162] The functions of the passivation layer include: protecting the metal electrodes and waveguide structure from the influence of the external environment and providing electrical insulation.

[0163] Photolithography was used to define the electrode windowing area, and inductively coupled plasma (ICP) etching was employed to create the window, with the etching rate controlled at 10 nm / s, precisely stopping at the metal electrode surface. It should be understood that dry etching offers better anisotropy than wet etching, allowing for precise opening at designated locations without damaging surrounding areas. After windowing, [further details are needed]. Plasma cleaning for 30 seconds removes organic matter and polymer residues from the window area, ensuring that the contact resistance between the metal electrode and the probe / bonding wire is ≤1Ω during subsequent testing and bonding.

[0164] Optionally, grinding the wafer surface and laser-cutting the wafer to prepare a silicon photonic chip includes:

[0165] The wafer surface is ground, and the ground wafer is then subjected to chemical relaxation treatment;

[0166] The wafer is laser-cut to prepare a silicon photonic chip;

[0167] The silicon photonics chip was subjected to appearance testing, electrode continuity testing, and insertion loss testing.

[0168] Mechanical grinding was used to thin the back side of the wafer, reducing its thickness from an initial 775 μm to 140 μm, significantly reducing the overall chip thickness. The ground wafer was then subjected to chemical relaxation treatment to reduce warpage to ≤10 μm. This thinning process improves the heat dissipation performance and packaging compatibility of the subsequent chip, while the chemical relaxation treatment eliminates surface stress and damage layers introduced by grinding, restoring the wafer's flatness.

[0169] Laser dicing of wafers involves focusing a laser beam inside the wafer to form a modified layer. Applying mechanical stress causes the layer to crack, thus separating the chips. Optionally, the dicing width is 85 μm, and the laser focusing depth is approximately one-third of the wafer thickness. This laser stealth dicing method eliminates noticeable edge chipping and microcracks, improving wafer yield.

[0170] The prepared silicon photonics chip is subjected to appearance testing, electrode continuity testing, and insertion loss testing to ensure the yield of the silicon photonics chip.

[0171] Among them, the appearance test is to visually inspect the chip surface for scratches, cracks, residues and other appearance defects using an optical microscope; the electrode continuity test is to verify the conductivity of each electrode such as heating resistor and signal electrode; and the insertion loss test is used to evaluate the coupling loss and optical transmission performance of the device.

[0172] Obviously, the embodiments described above are only some embodiments of this application, not all embodiments. The accompanying drawings show preferred embodiments of this application, but do not limit the patent scope of this application. This application can be implemented in many different forms; rather, the purpose of providing these embodiments is to provide a more thorough and comprehensive understanding of the disclosure of this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or make equivalent substitutions for some of the technical features. Any equivalent structures made using the content of this application's specification and drawings, directly or indirectly applied to other related technical fields, are similarly within the scope of patent protection of this application.

Claims

1. A method for fabricating a silicon photonic chip, characterized in that, include: Select a wafer and perform planarization on the wafer; The target components are exposed on the wafer and then developed. The target components include an MRM array, an AWG chip, a bus waveguide, a coupling region, an AWG folded flat panel region, an array waveguide, a receiving waveguide, and a mode converter. Silicon waveguides, sidewall air trenches, and thermal vias are etched on the wafer; A dual gradient structure is fabricated at the output terminal of the AWG chip, and a heating resistor and a wavelength calibration electrode are fabricated. A passivation layer is deposited, and the wavelength calibration electrode is etched to create a window; The wafer surface is ground, and the wafer is laser-cut to prepare a silicon photonic chip.

2. The method according to claim 1, characterized in that, The selection of the wafer and the planarization of the wafer include: Select SOI wafers; The SOI wafer is subjected to RCA cleaning; The cleaned SOI wafer is then polished for a first preset duration. The SOI wafer is polished again for a second preset duration; the first preset duration is longer than the second preset duration. The SOI wafer after polishing for a second preset time has a roughness of less than or equal to 0.25 nm and a flatness error of less than or equal to 3 nm / 20 μm.

3. The method according to claim 1, characterized in that, The step of exposing the target components on the wafer and performing development processing includes: An adhesion promoter is coated on the bottom layer of the wafer, and a photoresist is spin-coated. The photoresist coated on the wafer is dried using a stepped heating method; The target component is exposed on the wafer surface using an electron beam direct writing device; wherein, the exposure dose is dynamically adjusted according to the resonant wavelength corresponding to the micro-ring modulator. The wafer is then subjected to a development process.

4. The method according to claim 1, characterized in that, Etching silicon waveguides on the wafer includes: Silicon waveguides were etched using inductively coupled plasma (ICP) technology. After etching is complete, plasma is introduced to remove the photoresist; A fluoride passivation layer is deposited to passivate the sidewalls.

5. The method according to claim 1, characterized in that, Etching sidewall air trenches on the wafer includes: Spin-coat the photoresist again; The sidewall air trenches were etched using inductively coupled plasma (ICP) technology. After etching is complete, remove the photoresist; The air grooves on the side wall are filled with air medium to form a low thermal conductivity isolation layer.

6. The method according to claim 1, characterized in that, Etching thermally conductive vias on the wafer includes: At the etching location, the top silicon layer of the wafer is etched; the etching location is the center of the micro-ring resonator ring of the wafer biased towards the bus waveguide side; After etching the top silicon layer of the wafer, the buried oxide layer of the wafer is etched and penetrated. Remove the oxide layer remaining after the etching process.

7. The method according to claim 1, characterized in that, The fabrication of the dual gradient structure at the output terminal of the AWG chip includes: The physical vapor deposition (PVD) process is used to sputter the adhesion layer; Tungsten metal was filled using chemical vapor deposition (CVD) process; Polishing process for the tungsten metal layer; A geometrically gradient structure and a refractive index gradient layer are fabricated at the output end of the AWG chip.

8. The method according to claim 1, characterized in that, The preparation of the heating resistor and wavelength calibration electrode includes: Spin-coating a double layer of photoresist and exposing the heating resistor and wavelength calibration electrode patterns; The adhesion layer is deposited using electron beam evaporation. The residual metal on the wafer was stripped using NMP solution, and signal electrodes, ground electrodes, and probe leads were fabricated.

9. The method according to claim 1, characterized in that, The deposition of the passivation layer and the etching of a window for the wavelength calibration electrode include: A passivation layer is deposited using plasma-enhanced chemical vapor deposition (PECVD). The electrode windowing area is defined using photolithography; The window is etched using inductively coupled plasma (ICP) etching. Plasma is introduced to remove organic matter and polymer residues from the window area.

10. The method according to any one of claims 1-9, characterized in that, The process of grinding the wafer surface and laser-cutting the wafer to prepare a silicon photonic chip includes: The wafer surface is ground, and the ground wafer is then subjected to chemical relaxation treatment; The wafer is laser-cut to prepare a silicon photonic chip; The silicon photonics chip was subjected to appearance testing, electrode continuity testing, and insertion loss testing.

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