Preparation method of silicon optical chip

By using a single mask and a single electron beam exposure method to simultaneously define the patterns of the MRM array and the AWG chip on the wafer, the problem of high optical path splicing loss and low integration density of silicon photonics chips is solved, achieving higher integration density and smaller chip area.

CN122449686AActive Publication Date: 2026-07-24WUHAN YILUT TECH CO LTD
11 Cites 1 Cited by

Patent Information

Application Number
CN202610888927.6
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-06-18
Publication Date
2026-07-24
Estimated Expiration
2046-06-18

AI Technical Summary

Technical Problem

Existing silicon photonics chips suffer from high optical path splicing loss and low integration density, mainly due to the coupling gap between the MRM array and the AWG chip. This requires additional mode conversion structures or transition waveguides, resulting in a large chip area and making it difficult to achieve miniaturization and high channel number expansion.

Method used

The entire pattern of the MRM array and AWG chip is defined on the wafer simultaneously using a single mask and single electron beam exposure method, eliminating discrete coupling links. Silicon waveguides, sidewall air trenches, and thermal vias are etched on the wafer, and a dual gradient structure, heating resistors, and wavelength calibration electrodes are fabricated. After depositing a passivation layer, laser cutting is performed to fabricate the silicon photonic chip.

Benefits of technology

It effectively eliminates coupling losses caused by multiple alignments and splicings between discrete components, improves the integration of silicon photonics chips, reduces optical path splicing losses, and achieves higher integration and smaller chip area.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

The invention provides a preparation method of a silicon optical chip, and the method comprises the steps: selecting a wafer, and carrying out the flattening of the wafer; exposing the target component on the wafer, and carrying out developing treatment; etching a silicon waveguide, a side wall air groove and a heat conduction through hole on the wafer; preparing a double-gradient structure at the output end of the AWG chip, and preparing a heating resistor and a wavelength calibration electrode; depositing a passivation layer, and etching and windowing the wavelength calibration electrode; and grinding the surface of the wafer, and carrying out laser cutting on the wafer to prepare the silicon optical chip. According to the preparation method of the silicon optical chip provided by the invention, a discrete coupling link is canceled, all patterns of the MRM array and the AWG chip are simultaneously defined through one-time masking and one-time electron beam exposure, the coupling loss caused by multiple alignment and splicing between discrete devices is eliminated from the source, and the integration level of the silicon optical chip is improved.
Need to check novelty before this filing date? Find Prior Art