Method and system for virtual output queue allocation

Abstract

The present disclosure relates to methods and systems for virtual output queue allocation. Embodiments aggregate output content in a multi-queuing system. For example, embodiments include a plurality of input queues configured to receive data packets. In embodiments, each respective data packet received includes a plurality of data blocks, and the plurality of data blocks for a respective data packet define a complete data packet when received in its entirety. Embodiments further include an output buffer configured to maintain a list including a respective entry for each complete data packet received at each of the plurality of input queues, and control logic configured to read, based on an entry in the output buffer list, a complete data packet received at at least one of the plurality of input queues.

Description

Related applications

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 749,027, filed January 24, 2025, the entire teachings of which are incorporated herein by reference. Background Technology

[0002] In computer operating and processing systems, data is frequently transferred from one location to another, and at a given time, the system or process receiving the data may be receiving data from multiple sources. Furthermore, the sources transmitting the data may be capable of transmitting data at different data rates. This presents a problem when attempting to aggregate data received from multiple input queues into a single output queue. The embodiments disclosed herein provide improvements in aggregating output content in multi-queue systems. Summary of the Invention

[0003] The embodiments relate to a system for aggregating output content in a multi-queue system. Such a system may include multiple input queues configured to receive data packets, each received data packet comprising multiple data blocks, with a complete data packet defined for each set of data blocks when received as a whole. This embodiment may further include an output buffer configured to maintain a list containing corresponding entries for complete data packets received at each of the multiple input queues; and may further include control logic configured to read complete data packets received at at least one of the multiple input queues based on entries in the output buffer list.

[0004] According to one embodiment, each corresponding entry of a complete data packet listed in the output buffer may include at least one of the following: an indication of the position of the corresponding entry in the output buffer, an indication of the source, and the length of the corresponding complete data packet. In this embodiment, the system may also be configured to determine the length of the corresponding complete data packet by determining the total number of blocks in the corresponding data packet based on at least one of the first block and the last block of a plurality of blocks. Furthermore, in this embodiment, the indication of the position in the output buffer may be based on the time when each of a plurality of input queues receives the corresponding last block of a plurality of data blocks for the corresponding data packet.

[0005] According to one embodiment, the output buffer can also be configured to provide control logic with information related to data packets, such as, for example, queue position, packet size, and / or source.

[0006] In one embodiment, in response to the output buffer containing a corresponding entry for at least one complete data packet, the control logic may also be configured to read the complete data packet corresponding to the corresponding entry from at least one of a plurality of input queues and transmit the read complete data packet to at least one output queue. In this embodiment, in response to the read complete data packet being transmitted entirely to at least one output queue, the system may delete the corresponding entry from the output buffer.

[0007] In another embodiment, the last block of a plurality of blocks of a received given data packet may include an indication that the data packet has been received in its entirety. For example, the last data block in a data packet may include an indication that it is the end of packet (EOP).

[0008] One embodiment includes a memory configured to store complete data packets received at multiple input queues.

[0009] According to one embodiment, the plurality of input queues is a first set of input queues corresponding to a first type of data channel, the output buffer is a first output buffer corresponding to a first type of channel, and the control logic is a first control logic corresponding to a first type of channel. This embodiment further includes: a second set of plurality of input queues corresponding to a second type of channel, a second output buffer corresponding to a second type of channel, and a second control logic corresponding to a second type of channel. This embodiment may also include an output controller coupled to both the first and second control logics, the output controller being configured to orchestrate data transmission from the first and second control logics to the output queues, respectively.

[0010] Another embodiment relates to a method for aggregating output content. The method may include receiving corresponding data packets at multiple corresponding input queues, wherein each received corresponding data packet comprises multiple data blocks, and a complete data packet is defined for the multiple data blocks of the corresponding data packet when they are received as a whole. The method further includes maintaining a list at an output buffer, the list including corresponding entries for complete data packets received at each of the multiple input queues; and at a control logic, reading complete data packets received at at least one of the multiple input queues based on the entries in the output buffer list.

[0011] Another embodiment relates to an apparatus for aggregating output content in a multi-queue system. The apparatus includes: means for receiving corresponding data packets at a plurality of corresponding input queues, wherein each received corresponding data packet comprises a plurality of data blocks, and a complete data packet is defined for the plurality of data blocks of the corresponding data packet when received as a whole. The embodiment further includes: means for maintaining a list at an output buffer, the list including corresponding entries for complete data packets received at each of the plurality of input queues; and means for reading, at a control logic, a complete data packet received at at least one of the plurality of input queues based on entries in the output buffer list.

[0012] It should be noted that embodiments of the methods, systems, and apparatus can be configured to implement any of the embodiments or combinations thereof described herein. Attached Figure Description

[0013] The foregoing will become apparent from the following more detailed description of exemplary embodiments, as illustrated in the accompanying drawings, wherein the same reference numerals refer to the same parts in different views. The drawings are not necessarily drawn to scale, but rather focus on illustrating the embodiments.

[0014] Figure 1 This is a flowchart illustrating the process of aggregating output content in a multi-queue system according to an embodiment.

[0015] Figure 2 This is a flowchart of a method for aggregating output content in a multi-queue system according to an embodiment, and the associated components of the method.

[0016] Figure 3 This is a schematic diagram illustrating the aggregation of output content in a multi-queue system using an output controller according to an embodiment.

[0017] Figure 4 This is a schematic diagram of an example system for aggregating content from multiple input queues according to an embodiment. Detailed Implementation

[0018] The example embodiment is described below.

[0019] In multi-queue systems, it may be necessary to aggregate the contents of multiple input queues located on a single memory into a single output queue, such as a carrier output queue. In such a system, a first subset of the multiple input queues can be configured to receive data packets at a given data rate, and a second subset of the input queues can be configured to receive data packets at a given data rate different from that of the first subset. For example, a given channel stored in memory could be a Flex-E channel, and a separate channel stored in a separate memory could be a Low Bit Rate (LB) channel. Embodiments provide the aggregation of output contents received at multiple input queues into a single output queue at a common data rate. This data rate can be different from the data rate of any of the input queues if desired.

[0020] In a lossless system—that is, a system that retains all information from input to output—the output channel data rate should be greater than or equal to the sum of the input queue rates. If the output channel data rate is not greater than or equal to the sum of the input queue rates, then when the output queue tries to catch up, data may wait and accumulate at the input queue, which could be a losing battle.

[0021] In existing systems (which may be referred to herein as the "conventional mode"), the contents and data structure of the output queue are constructed by either copying the entire data or by copying the data pointer from the input queue to the output queue. Furthermore, the conventional mode system can generate additional output queues for aggregated channels and read data from these additional, generated output queues. This traditional approach demands higher power consumption because the entire data payload must be copied; it requires a larger memory footprint because more memory is needed to store the copied data; and it suffers a performance penalty due to the need to access memory to retrieve the data.

[0022] The embodiments disclosed herein provide improvements for queuing systems with multiple input queues (i.e., multi-queuing systems) by aggregating channel traffic without copying, moving, or altering the raw data received at multiple input queues. The embodiments enable the aggregation of data packets received at different data rates from multiple different sources into a single aggregated output queue.

[0023] The embodiment adds a connection to the memory (see Figure 1 140) Parallel output buffers (see Figure 1(130), where the output buffer contains a temporary list of complete data packets received at each input queue in the input queue. For example, the output buffer can be a first-in, first-out (FIFO) buffer, effectively an output-FIFO, i.e., OFIFFO. In embodiments, the OFIFFO buffer may also contain information about the original source queue (i.e., a given input queue), the corresponding queue position, and the length of the data packet. Embodiments may also provide dedicated read-only queue control logic (ROQ-control) (see 130). Figure 1 (150), which is based on the instructions received by OFIFFO to output queues (see 150). Figure 1 Transmit complete data packets stored in memory at a rate of 170.

[0024] In this embodiment, for each input queue, the input queue control logic (Q-control) can transfer data packets to a common payload memory associated with a given channel (i.e., there may be a first payload memory associated with flex-e, and a second payload memory associated with LB, for example). Furthermore, once the Q-control has identified that the data packet has been received in its entirety, it can transfer information related to the complete data packet to the output buffer (see [link to implementation]). Figure 1 (130). This type of information may include the data packet length and its corresponding position in the output buffer queue.

[0025] According to an embodiment, when the OFIFFO buffer is not empty and an available active time slot exists in the output queue, the RO Q-control can begin reading data packets received from the original input queue from the payload memory and transferring those data packets to the output queue. This may result in the input queue having two identifiers (IDs), one ID for writing (i.e., original) and one ID for reading (i.e., virtual). This configuration allows data to be read and written without moving the data. For example, each input queue may include two IDs. The first ID may be used for the input queue, i.e., for write operations, and the first ID is unique for the input queue. The second ID may be a virtual ID used for read operations, and this virtual ID can be shared within the input queue. Therefore, the same data structure (e.g., the input queue) may include two different IDs assigned during system configuration.

[0026] Continuing, data packets can continue to be output to the queue (see...) Figure 1The Q control reads data from the 170th position until the entire data packet has been read. Once the entire data packet has been read, the output buffer is "popped" (i.e., the top-level entry is removed from the buffer, and the next-level entry is then promoted to the top-level entry, which is the next candidate for transmission to the output queue), and the data packet associated with the next queue position can be transmitted to the output queue. In practice, the Q control operates in store-and-forward mode.

[0027] Therefore, the implementation effectively remaps the channel without altering the original data packet structure. Data packets can be received by the input queue at different data rates, but are output by the system at a common data rate.

[0028] Furthermore, since data copying is not required by copying data from the input queue or moving it to memory, the embodiments save storage space by not requiring additional memory and save time by not requiring data copying. Therefore, the embodiments provide time and memory savings, and thus improve performance.

[0029] Figure 1 This is a flowchart of a system 100 for aggregating output content in a multi-queue system according to an embodiment. This embodiment may include multiple input queues. For example, the embodiment may include input queue one (IQ-1) 101, input queue two (IQ-2) 111, and input queue three (IQ-3) 121. It should be understood that, although... Figure 1 Only three input queues 101, 111 and 121 are shown in the figure, but system 100 can utilize any number of input queues, such as input queue “n” (IQ-n) 190.

[0030] Figure 1 The components grouped into 160 will be combined below. Figure 3 It will be further referenced.

[0031] Given an input queue, such as IQ-1 101, multiple data blocks 103a to 103n can be received at a given data rate. When data blocks 103a to 103n are received as a whole by IQ-1 101, a complete data packet 104 is defined. A given input queue control (Q-control), such as Q-control 102 for IQ-1 101, can store the payload of the received data packet 104 in a payload memory / buffer 140, for example. Once Q-control 102 has received the data packet 104 as a whole, for example, when data block 103n has indicated that data block 103n is the end of packet (EOP), Q-control 102 can write an entry for the complete data packet 104 received at IQ-1 101 to the output buffer 130 (i.e., OFIFFO). Each input queue in IQ-1 101, IQ-2 111, IQ-3 121, through IQ-n 191 operates similarly. For example, IQ-2 111 can receive multiple data blocks 113a through 113n at a given data rate. Data blocks 113a through 113n, when received as a whole by IQ-2 111, define a complete data packet 114. Q-control 112 can store the payload of data packet 114 in payload memory / buffer 140. Once Q-control 112 has received data packet 114 as a whole, Q-control 112 can write the entry for the complete data packet 114 received at IQ-2 111 to output buffer 130. Continuing, IQ-3 121 can receive multiple data blocks 123a through 123n at a given data rate. When data blocks 123a to 123n are received in their entirety by IQ-3 121, a complete data packet 124 is defined. Q-control 122 can store the payload of data packet 124 in payload memory / buffer 140. Once Q-control 122 has received data packet 124 completely, Q-control 122 can write the entry for the complete data packet 124 received at IQ-3 121 to output buffer 130.

[0032] According to an embodiment, output buffer 130 maintains a list of corresponding entries for complete data packets (104, 114, 124) received at each of a plurality of input queues (101, 111, 121). Output buffer 130 includes information related to queue position 131, source 132 (e.g., indicating which input queue from), and data packet length 133. When the corresponding input queue (101, 111, 121) receives the corresponding complete data packet (104, 114, 124), the corresponding control logic (102, 112, 122) communicates to output buffer 130 that it has received the complete data packet, and also provides output buffer 130 with an indication of data packet length (e.g., size) 133. These entries are placed into output buffer 130 on a first-in, first-out basis. For example, if IQ-1 101 is in t = 1 (where t (This refers to any time unit) that has received its complete data packet 104, while IQ-2 111 has... t If a complete data packet 114 has been received when the value is greater than 1, then the indication of data packet 104 will be placed in a higher queue position 131 in the output buffer 130, regardless of its corresponding data packet length 133. It should be understood that the value provided for data packet length 133 is an arbitrary placeholder.

[0033] According to an embodiment, the read-only queue control (ROQ-control) 150 can receive from the output buffer 130 a command (e.g., an indication that the output buffer is not empty) indicating that a given data packet (i.e., a data packet with the next queue position) is scheduled to be sent to the output queue 170. The ROQ-control 150 can then identify the given packet in the payload memory 140 and transfer that packet from the payload memory 140 to the output queue 170.

[0034] In a lossless system, the depth of the output buffer 130 can have an associated depth equal to the maximum number of data packets that can be stored in the data buffer (e.g., 104). This configuration can be advantageous if each data packet is a shared data bus (SDB) packet.

[0035] According to an embodiment, the ROQ control (e.g., 150) may include a prefetch buffer. The prefetch buffer can be used to minimize or eliminate latency in the payload memory 140 by preparing it for transmission before the next available data packet is requested. For example, when the prefetch buffer has available space, it can be refilled using information associated with a complete data packet.

[0036] Figure 2This is a flowchart of a method 200 for aggregating output content in a multi-queue system. Method 200 begins at step 201, aggregating output content across multiple corresponding input queues (see...). Figure 1 Receive the corresponding data packets at positions 101, 111, and 121 (see [reference]). Figure 1 102, 112, 122); each received corresponding data packet includes multiple data blocks (see, for example, Figure 1 (103a to 103n), and for multiple data blocks of the corresponding data group, when they are received as a whole, a complete data group is defined (see, for example, Figure 1 (104). Subsequently, at step 201, method 200 passes through an output buffer (e.g., an OFIFFO buffer) (see 104). Figure 1 At step 130), a list is maintained to continue, which includes the corresponding entry for the complete data packet received at each of the multiple input queues. Then, at step 201, method 200, in its control logic (see, for example, ...), ... Figure 1 At position 150, based on entries in the output buffer list, read complete data packets received at at least one of the multiple input queues.

[0037] In some embodiments of method 200, each corresponding entry of a complete data packet listed in the output buffer may include at least one of the following: an indication of the position of the corresponding entry in the output buffer (see...). Figure 1 (131), and the length of the corresponding complete data block (see 131). Figure 1 (133). This embodiment of method 200 may further include: determining the total number of blocks in a corresponding data packet based on at least one of the first block and the last block of a plurality of blocks (e.g., see 133). Figure 1 (105a to 105n) to determine the length of the corresponding complete data packet. For example, the first block may include an indication of the data packet size, and embodiments may count the number of received blocks until that indication is reached. In some embodiments, the last data block among the plurality of blocks of a given data packet received may include an indication that the data packet is the last data block in the packet, thereby indicating that the data packet has now been received in its entirety.

[0038] In method 200, the indication of the position of the corresponding entry for a complete data packet listed in the output buffer can be based on the time when each of the multiple input queues receives the corresponding last block of multiple data blocks for the corresponding data packet. For example, entries are listed in the output buffer on a first-in, first-out (FIFO) basis. Once an input queue has received an indication that the last data block for a given data packet has been received—that is, the data packet has been received in its entirety—the corresponding entry for the corresponding data packet can be written to the output buffer. Entries in the output buffer are queued relative to when the corresponding input queue has received the data packet in its entirety; for example, entries are listed on a FIFO basis. In some embodiments, information from the output buffer can be provided to the ROQ control, such as the position of the entries in the queue, their data packet length, and the input queue number.

[0039] In some embodiments, in response to the output buffer containing at least one corresponding entry of a complete data packet, method 200 may further include: reading the complete data packet corresponding to the corresponding entry from at least one of a plurality of input queues via control logic (i.e., ROQ-control), and transferring the complete data packet to at least one output queue. In this embodiment, in response to the complete data packet being transferred as a whole to at least one output queue, method 200 may then delete the corresponding entry from the output buffer.

[0040] Some embodiments of method 200 may also include a memory (see Figure 1 (140), the memory is configured to hold complete data packets received at multiple input queues. According to an embodiment, the memory can be any data storage method.

[0041] According to an embodiment of method 200, the plurality of input queues may be a first set of input queues corresponding to a first type of data channel (e.g., flex-e), the output buffer may be a first output buffer corresponding to a first type of channel, and the control logic may be a first control logic corresponding to a first type of channel. In this embodiment, method 200 may further include: a second set of a plurality of input queues corresponding to a second type of channel (e.g., LB), a second output buffer corresponding to a second type of channel, and a second control logic corresponding to a second type of channel. In this embodiment, an output controller may be coupled to both the first control logic and the second control logic, and the output controller is configured to orchestrate the transmission of data from the first control logic and the second control logic to the output queues, respectively. For example, the output controller may provide an indication to each corresponding control logic, indicating that it is their turn to transmit data to the output queue. In this way, the output controller orchestrates the data transmitted to the output queues.

[0042] Combined with the following text Figure 3 As disclosed in schematic diagram 300, according to an embodiment, one or more of a plurality of input queues may be associated with a first type of channel, such as a flexible Ethernet (flex-e) channel (see [reference]). Figure 3 (of 160), and one or more of the multiple input queues can be connected to a second type of channel (see 160). Figure 3 This is associated with channels such as low bit rate (LB) channels (e.g., 160). The first type of channel and the second type of channel can receive and transmit data at different rates. In this embodiment, a corresponding payload memory / buffer (e.g., 140) can exist for the first type of channel, and a corresponding payload memory / buffer can exist for the second type of channel. A corresponding output buffer (i.e., OFIFFO) can also exist for the first type of channel, and a corresponding output buffer can also exist for the second type of channel. Furthermore, a corresponding ROQ-control (e.g., 150) can exist for the first type of channel, and a corresponding ROQ-control can exist for the second type of channel. In this embodiment, an output queue 170 can exist for data from the first type of channel, and an output queue 370 can exist for data from the second type of channel.

[0043] This embodiment may also include an output controller (see...) Figure 3 Output controller 310 communicates with corresponding ROQ-controls for the first and second channel types. Output controller 310 can be configured to provide an indication to a given ROQ-control (i.e., the ROQ-control associated with the first channel type, or the ROQ-control associated with the second channel type) indicating that it is the turn of that given ROQ-control to send a data packet to output queue 170. This indication can be based on a calendar ID associated with a complete data packet received by a given Q-control (e.g., a first ID) and a calendar ID associated with the output controller (e.g., a second ID). For example, when there is a match between the calendar ID associated with the Q-control and the calendar ID associated with the output controller, data is sent to the corresponding output queue. Output controller 310 can be configured to provide an indication every clock cycle, effectively alternating between output from the first channel and output from the second channel.

[0044] Figure 3 This is a schematic diagram 300 illustrating the aggregation of output content in a multi-queue system according to an embodiment. Figure 3 middle, Figure 1 The grouping of component 160 can be combined with multiple input channels (e.g., Figure 1The input channels (101, 111, 121) are associated with a first channel type, such as flex-e. Packets of component 360 are similar to those of component 160 in almost all respects, except that multiple input channels associated with packets of component 360 can be associated with a second channel type, such as LB. Output controller 310 can be configured to communicate with the corresponding ROQ-controls associated with 160 and 360. In each clock cycle, output controller 310 can send an instruction to the ROQ-control associated with 160 or 360 to transmit a given data packet to the corresponding output queue 170 associated with the first channel type 160, or the corresponding output queue 370 associated with the second channel type 360. It should be understood that while the output buffer associated with the first channel type can be written simultaneously with the output buffer associated with the second channel type, only one output buffer can drive data at a time. In this way, embodiments aggregate content from multiple input queues into a single output queue at multiple data rates.

[0045] Figure 4 This is a schematic diagram of an example system 400 for aggregating content from multiple input queues according to an embodiment. System 400 includes multiple input queues 401a to 401n associated with a first channel type (e.g., flex-e) and multiple channels 403a to 403n associated with a second channel type (e.g., LB). It should be understood that although only two channel types are shown and described, the embodiment is sufficient to be implemented using any number of input channels and any number of channel types. Each of the multiple input queues 401a to 401n and 403a to 403n also has associated RO Q-controls, 402 and 404, respectively. System 400 also includes a data buffer 405 associated with a first type of memory and a data buffer 406 associated with a second type of memory. Both data buffers 405 and 406 can include corresponding memory and corresponding memory control logic. Furthermore, system 400 may include an output buffer 408 (i.e., OFIFFO) associated with the first type of data and an output buffer 409 associated with the second type of data. System 400 also includes an output queue 407 for first type (e.g., flex-e) data and an output queue 410 for second type (e.g., LB) data to transmit data out of system 400.

[0046] The implementation supports both "normal mode" and store-and-forward mode, and can be configured to implement one mode, another mode, or both modes simultaneously. However, during store-and-forward mode, the control logic operation may differ from that in "normal mode" (traditional methods and systems). In store-and-forward mode, a given data packet must be received entirely and completely stored in the buffer before information about it can be written to the output buffer and the payload can be transmitted to the output queue (see [link to relevant documentation]). Figure 1 In embodiment 140), each corresponding input Q-control logic can count complete data packets in its queue buffer, and the counter increments as each complete data packet is counted. According to the embodiment, a first counter for counting packets and a second counter for counting blocks may exist. In store-and-forward mode, the counter associated with a packet must be greater than "0" to begin reading from the queue, while during "normal mode," a non-empty counter associated with a block may be sufficient to begin transmitting data packets.

[0047] An additional difference between this embodiment and a conventional system is that, in this embodiment, multiple Q-control units can share the same carrier channel (e.g., flex-e or LB), but only one carrier channel can drive data at a time. Therefore, to reduce the required number of channel buffers, this embodiment uses a dedicated RO Q-control to perform read operations and data prefetching. Continuing, when the output buffer is not empty, each time a calendar ID match exists between the data and the output controller, the RO Q-control begins reading data from the prefetch buffer and then transmits the data to the output queue. The RO Q-control reads data and transmits it to the output queue until the data packet is read entirely. After the data packet is read entirely, the corresponding entry in the output buffer is "popped," and the next data packet can become a candidate for transmission to the output queue.

[0048] Implementations may include loopback operations. Loopback operations also operate with a store-and-forward configuration and also utilize a dedicated carrier channel (e.g., flex-e or LB) to send traffic from shared memory. However, in loopback implementations, the outgoing loopback traffic carrier channel may differ from the incoming loopback traffic channel; that is, channel remapping may exist. For example, channel remapping may also be performed in a flex-e channel. Channel remapping can be performed when the RO Q-control is selected from the read output. The RO Q-control is read if the calendar channel ID equals the configured loopback carrier channel ID. Furthermore, the loopback carrier channel bit rate is predefined, while the incoming loopback traffic bit rate is not predefined and may reach the maximum bit rate allowed by the hardware, potentially leading to a memory overflow. In the event of a memory overflow, loopback packets may be dropped.

[0049] While exemplary embodiments have been specifically shown and described, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of the embodiments covered by the appended claims.

Claims

1. A system for aggregating output content in a multi-queue system, the system comprising: Multiple input queues are configured to receive data packets, each received corresponding data packet comprising multiple data blocks, and a complete data packet is defined for the multiple data blocks of a corresponding data packet when they are received as a whole; An output buffer is configured to maintain a list that includes corresponding entries for complete data packets received at each of the plurality of input queues; as well as Control logic configured to read the complete data packet received at at least one of the plurality of input queues based on entries in the output buffer list.

2. The system of claim 1, wherein each corresponding entry of the complete data packet listed in the output buffer includes at least one of the following: an indication of the position of the corresponding entry in the output buffer, an indication of the source, and the length of the corresponding complete data packet.

3. The system of claim 2, wherein the system is further configured to determine the length of the corresponding complete data packet by determining the total number of blocks in the corresponding data packet based on at least one of the first block and the last block of the plurality of blocks.

4. The system of claim 2, wherein the indication of the position in the output buffer is based on the time when each of the plurality of input queues receives the corresponding last block of the plurality of data blocks for the corresponding data group.

5. The system of claim 1, wherein the output buffer is further configured to provide the control logic with information related to the data packets.

6. The system according to claim 1, further comprising: In response to the output buffer containing at least one corresponding entry of a complete data packet, the control logic is configured to read the complete data packet corresponding to the corresponding entry from at least one of the plurality of input queues, and transmit the read complete data packet to at least one output queue.

7. The system of claim 6, wherein in response to the read complete data packet being transmitted as a whole to the at least one output queue, the system is further configured to delete the corresponding entry in the output buffer.

8. The system of claim 1, wherein the last block of the plurality of blocks of a received given data packet includes an indication that the data packet has been received in its entirety.

9. The system of claim 1 further includes a memory configured to store complete data packets received at the plurality of input queues.

10. The system of claim 1, wherein the plurality of input queues is a first set of input queues corresponding to a first type of data channel, the output buffer is a first output buffer corresponding to the first type of channel, and the control logic is a first control logic corresponding to the first type of channel, the system further comprising: A second set of multiple input queues corresponding to the second type of channel, a second output buffer corresponding to the second type of channel, and a second control logic corresponding to the second type of channel.

11. The system of claim 10, further comprising an output controller coupled to the first control logic and coupled to the second control logic, the output controller being configured to orchestrate data transmission from the first control logic and the second control logic to an output queue, respectively.

12. A method for aggregating output content, the method comprising: Relevant data packets are received at multiple corresponding input queues. Each received data packet includes multiple data blocks. When the multiple data blocks of a data packet are received as a whole, a complete data packet is defined. A list is maintained at the output buffer, the list including the corresponding entries for complete data packets received at each of the plurality of input queues; as well as At the control logic, based on entries in the output buffer list, the complete data packet received at at least one of the plurality of input queues is read.

13. The method of claim 12, wherein each corresponding entry of the complete data packet listed in the output buffer includes at least one of the following: an indication of the position of the corresponding entry in the output buffer, an indication of the source, and the length of the corresponding complete data packet.

14. The method of claim 13, further comprising: The length of the corresponding complete data packet is determined by determining the total number of blocks in the corresponding data packet based on the first block and the last block among the plurality of blocks.

15. The method of claim 13, wherein the indication of the position in the output buffer is based on the time when each of the plurality of input queues receives the corresponding last block of the plurality of data blocks for the corresponding data group.

16. The method of claim 12, further comprising providing information related to the data packet to the control logic via the output buffer.

17. The method of claim 12, further comprising, in response to the output buffer containing at least one corresponding entry of a complete data packet: The control logic reads the complete data packet corresponding to the corresponding entry from at least one of the plurality of input queues and transmits the complete data packet to at least one output queue.

18. The method of claim 17, further comprising: In response to the complete data packet being transmitted as a whole to the at least one output queue, the corresponding entry in the output buffer is deleted.

19. The method of claim 12, wherein the last block of the plurality of blocks of a received given data packet includes an indication that the data packet has been received in its entirety.

20. The method of claim 12, further comprising a memory configured to store complete data packets received at the plurality of input queues.

21. The method of claim 12, wherein the plurality of input queues is a first set of input queues corresponding to a first type of data channel, the output buffer is a first output buffer corresponding to the first type of channel, and the control logic is first control logic corresponding to the first type of channel, the method further comprising: Configure a second set of multiple input queues corresponding to the second type of channel, configure a second output buffer corresponding to the second type of channel, and configure a second control logic corresponding to the second type of channel.

22. The method of claim 21, further comprising: An output controller coupled to the first control logic and coupled to the second control logic orchestrates the transmission of data from the first control logic and the second control logic to the output queue, respectively.

23. An apparatus for aggregating output content in a multi-queue system, comprising: A means for receiving corresponding data packets at multiple corresponding input queues, each received corresponding data packet comprising multiple data blocks, wherein a complete data packet is defined for the multiple data blocks of the corresponding data packet when they are received as a whole; A means for maintaining a list at an output buffer, the list including corresponding entries for complete data packets received at each of the plurality of input queues; as well as A means for reading, at a control logic level, the received complete data packet from at least one of the plurality of input queues based on an entry in the output buffer list.

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