Method for implementing fixed bit-width fixed-point data rounding-off
By employing arithmetic right shift and sign bit detection to generate compensation values in FPGA, the problems of asymmetric positive and negative errors and high resource consumption during fixed-point data truncation are solved, achieving low-latency, low-resource truncation towards zero, which is suitable for digital signal processing algorithms.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING RES INST OF ELECTRONICS TECH
- Filing Date
- 2026-04-30
- Publication Date
- 2026-07-24
AI Technical Summary
Existing technologies for implementing fixed-point data truncation on FPGAs suffer from problems such as asymmetric positive and negative errors, high resource consumption, and uncertain delays. In particular, the introduction of DC components in the frequency domain causes a shift in the average signal value.
A fixed-width, fixed-point data rounding and truncation method is adopted. Through arithmetic right shift, sign bit detection, and compensation value generation, logic gates and adders are used to achieve rounding to zero and generate compensation values to correct the truncation result.
It achieves a symmetrical distribution of positive and negative errors, eliminates the DC component, consumes very few hardware resources, has a fixed delay, is suitable for high-speed pipeline design, and is fully compatible with MATLAB models.
Smart Images
Figure CN122450409A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of digital signal processing, and in particular to a method for implementing fixed-width fixed-point data rounding and truncation. Background Technology
[0002] When implementing digital signal processing algorithms (such as FFT, FIR filters, CIC compensation filters, etc.) on FPGAs, it is usually necessary to truncate the fixed-point operation results to prevent the data bit width from growing indefinitely. The most common truncation method is to directly discard the least significant bit (i.e., arithmetic right shift).
[0003] For fixed-point numbers represented in two's complement, a direct arithmetic right shift of K bits is equivalent to floor division. This method has the following drawbacks:
[0004] 1. Positive number: The result is too small (the decimal part was truncated).
[0005] 2. Negative numbers: The absolute value of the result is larger (e.g., -0.5 becomes -1 after truncation), and also tends to be smaller;
[0006] 3. One-sided error: Both positive and negative errors are negative or zero, causing a constant shift in the average value of the signal and introducing a DC component in the frequency domain.
[0007] The `fix` function in MATLAB (rounding to zero) can eliminate DC bias, but direct hardware implementation requires a comparator, sign determination, and remainder identification, resulting in high resource consumption and uncertain latency. Therefore, a low-latency, low-resource FPGA-based zero-rounding truncation solution is urgently needed. Summary of the Invention
[0008] To address the existing technical problems, this invention provides a method for implementing fixed-width, fixed-point data rounding and truncation.
[0009] The specific content of this invention is as follows: A method for implementing fixed-width, fixed-point data rounding and truncation includes the following steps:
[0010] S1, perform an arithmetic right shift on the input two's complement fixed-point number to obtain the floor value;
[0011] S2, extract the sign bit and determine whether the truncated low bits are non-zero;
[0012] S3, when the sign bit is 1 and the truncated low bits are not all zero, a compensation value of 1 is generated; otherwise, the compensation value is 0.
[0013] S4 adds the compensation value to the intermediate value of the down-rounding to obtain the final truncation result.
[0014] Furthermore, in S1, if the input data is an N-bit signed fixed-point number D represented in two's complement, the lower K bits need to be truncated, and the higher M = NK bits are retained as the final output; then D is arithmetically right-shifted by K bits to obtain the intermediate value T = floor(D / 2^K).
[0015] Furthermore, in S2, the highest bit of D is extracted as the sign bit S, where S=1 indicates a negative number and S=0 indicates a positive number; the lower K bits of D are checked to see if they are non-zero. If they are non-zero, Z=1; otherwise, Z=0.
[0016] Furthermore, in S3, generating the compensation value includes: calculating the compensation flag C = S & Z, that is, C = 1 only when S = 1 and the lower K bits are not all zero.
[0017] Furthermore, it is implemented based on an FPGA fixed-point truncation circuit for rounding down to zero, which includes:
[0018] The arithmetic right shift unit takes a fixed-point number as input and outputs the result after rounding down.
[0019] A logical OR gate that checks if all truncated low-order bits are zero.
[0020] The sign bit extraction unit extracts the sign bit.
[0021] The logic AND gate takes the sign bit and the inverted signal from the low-order all-zero detection unit as inputs and outputs a compensation flag.
[0022] The adder takes the output of the arithmetic right shift unit and the compensation flag as inputs, and outputs the final truncation value.
[0023] Furthermore, the arithmetic right shift unit is either a hardware connection or a shift register.
[0024] This invention utilizes the sign bit and whether the truncated low-order bits are all zero to generate a single-bit compensation signal, thereby correcting the direct truncation result and making it completely equivalent to MATLAB's fix function, with minimal hardware resources and fixed delay. Attached Figure Description
[0025] The invention will be further explained below with reference to the accompanying drawings.
[0026] Figure 1 The circuit diagram used for implementing the fixed-width fixed-point data rounding and truncation method of the present invention;
[0027] Figure 2 A schematic diagram comparing the errors of direct truncation (floor) and the present invention (fix) in the case of truncating 3 bits of an 8-bit signed fixed-point number. Detailed Implementation
[0028] Combination Figure 1 This invention provides a method for truncating fixed-width, fixed-point data, comprising the following steps:
[0029] S1, perform an arithmetic right shift on the input two's complement fixed-point number to obtain the floor value;
[0030] Input fixed-point number: Suppose the input data is an N-bit signed fixed-point number D in two's complement representation. The lower K bits need to be truncated, and the higher M = NK bits are retained as the final output.
[0031] Direct truncation: Arithmetic right shift D by K bits to obtain the middle value T = floor(D / 2^K) (rounded down).
[0032] S2, extract the sign bit and determine whether the truncated low bits are non-zero;
[0033] Extract the highest bit of D as the sign bit S (S=1 indicates a negative number, S=0 indicates a positive number).
[0034] Check if the lower K bits of D are non-zero. If they are non-zero, then Z=1; otherwise, Z=0.
[0035] S3, when the sign bit is 1 and the truncated low bits are not all zero, a compensation value of 1 is generated; otherwise, the compensation value is 0.
[0036] The compensation flag C = S & Z is calculated, meaning that C = 1 only when S = 1 and the lower K bits are not all zero.
[0037] S4. Add the compensation value to the middle value of the down-rounding to obtain the final truncation result to zero.
[0038] Output correction value: The final truncation result R = T + C, where R is equivalent to fix(D / 2^K) in MATLAB.
[0039] The fixed-width, fixed-point data rounding and truncation method of the present invention is based on the following circuit.
[0040] The arithmetic right shift unit takes a fixed-point number as input and outputs the result after rounding down.
[0041] A logical OR gate that checks if all truncated low-order bits are zero.
[0042] The sign bit extraction unit extracts the sign bit.
[0043] The logic AND gate takes the sign bit and the inverted signal from the low-order all-zero detection unit as inputs and outputs a compensation flag.
[0044] The adder takes the output of the arithmetic right shift unit and the compensation flag as inputs, and outputs the final truncation value.
[0045] The arithmetic right shift unit is a hardware connection or shift register and does not consume logic resources.
[0046] The technical solution of the present invention will be described in detail below with reference to a specific example (Verilog HDL implementation).
[0047] Example: 8-bit input, truncated lower 3 bits, 5-bit output
[0048] module fix_trunc
[0049] #(
[0050] parameter INPUT_W = 8,
[0051] parameter TRUNC_BITS = 3 ()(
[0053] input signed [INPUT_W -1:0] din ,
[0054] output signed [INPUT_W-TRUNC_BITS-1:0] dout );
[0056] wire sign_bit = din[INPUT_W-1];
[0057] wire trunc_nzero = |din[TRUNC_BITS-1:0];
[0058] wire fix_corr = sign_bit & trunc_nzero;
[0059] wire signed [INPUT_W -1:0] floor_val = din >> TRUNC_BITS;
[0060] wire signed [INPUT_W-TRUNC_BITS-1:0] sum = floor_val + fix_corr;
[0061] assign dout = sum;
[0062] endmodule
[0063] The truth table obtained is verified as follows:
[0064] Table 1 Truth Table Verification
[0065]
[0066] As can be seen, the output of this invention is completely consistent with MATLAB fix, while direct truncation results in a smaller error when negative numbers are not divisible.
[0067] like Figure 2 As shown, for an 8-bit signed fixed-point number -128 to 127, a 3-bit truncation operation is performed, where the error of direct truncation is ≤0. The error of this invention is symmetrically distributed.
[0068] Compared with existing technologies, this invention has the following advantages: 1. Complete elimination of DC components: Due to the use of rounding to zero, the positive and negative errors are symmetrically distributed, and the average error is zero, thus avoiding the generation of DC components in the frequency domain. 2. Minimal hardware resources: Only one multi-input OR gate, one AND gate (or equivalent logic), and one adder are required. The arithmetic right shift can be implemented through wiring, without consuming logic resources; low-order all-zero detection only requires one K-input OR gate followed by a NOT gate. The overall resource consumption is far lower than traditional schemes using comparators and multiplexers. 3. Fixed delay, no pipeline stalls: All operations are combinational logic or single-cycle addition, with a fixed delay of one shift plus one addition, facilitating timing convergence and making it suitable for high-speed pipeline design. 4. Full compatibility with MATLAB models: The truncation result is completely consistent with the fix function in the software algorithm, avoiding error accumulation between hardware simulation and the software reference model.
[0069] Many specific details have been set forth in the foregoing description to provide a thorough understanding of the present invention. However, the above description is merely a preferred embodiment of the present invention, and the present invention can be implemented in many other ways different from those described herein. Therefore, the present invention is not limited to the specific embodiments disclosed above. Furthermore, any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the present invention. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the protection scope of the present invention.
Claims
1. A method for implementing fixed-width, fixed-point data rounding and truncation, characterized in that: Includes the following steps: S1, perform an arithmetic right shift on the input two's complement fixed-point number to obtain the floor value; S2, extract the sign bit and determine whether the truncated low bits are non-zero; S3, when the sign bit is 1 and the truncated low bits are not all zero, a compensation value of 1 is generated; otherwise, the compensation value is 0. S4 adds the compensation value to the intermediate value of the down-rounding to obtain the final truncation result.
2. The method for implementing fixed-width, fixed-point data rounding and truncation according to claim 1, characterized in that: In S1, the input data is an N-bit signed fixed-point number D in two's complement representation. The lower K bits need to be truncated, and the higher M = NK bits are retained as the final output. Then, D is arithmetically right-shifted by K bits to obtain the intermediate value T = floor(D / 2^K).
3. The method for implementing fixed-width, fixed-point data rounding and truncation according to claim 2, characterized in that: In S2, the highest bit of D is extracted as the sign bit S, where S=1 indicates a negative number and S=0 indicates a positive number; the lower K bits of D are checked to see if they are non-zero. If they are non-zero, Z=1; otherwise, Z=0.
4. The method for implementing fixed-width, fixed-point data rounding and truncation according to claim 3, characterized in that: In S3, generating the compensation value includes: calculating the compensation flag C = S & Z, that is, C = 1 only when S = 1 and the lower K bits are not all zero.
5. The method for implementing fixed-width, fixed-point data rounding and truncation according to claim 1, characterized in that: This is implemented using an FPGA-based fixed-point integer truncation circuit, which includes: The arithmetic right shift unit takes a fixed-point number as input and outputs the result after rounding down. A logical OR gate that checks if all truncated low-order bits are zero. The sign bit extraction unit extracts the sign bit. The logic AND gate takes the sign bit and the inverted signal from the low-order all-zero detection unit as inputs and outputs a compensation flag. The adder takes the output of the arithmetic right shift unit and the compensation flag as inputs, and outputs the final truncation value.
6. The method for implementing fixed-width, fixed-point data rounding and truncation according to claim 5, characterized in that: The arithmetic right shift unit is either a hardware connection or a shift register.