An SRAM-based signed number analog in-memory computing circuit
By introducing sign bit control and a specific width-to-length ratio design into the SRAM standard cell, a signed number analog in-memory calculation circuit based on SRAM is realized, which can handle the dot product calculation of signed integers and expand the data range to [-15, 15].
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUNAN UNIV
- Filing Date
- 2023-02-21
- Publication Date
- 2026-07-21
AI Technical Summary
In the existing technology, analog in-memory computing circuits based on SRAM can only perform dot product calculations between externally input analog voltage signals and unsigned integers, and cannot represent negative numbers.
A 6T SRAM standard cell was designed, including a cell for storing the sign bit. By controlling the on and off states of transistors M16 and M17, and combining a specific width-to-length ratio and reference voltage relationship, the dot product calculation of signed integers is realized.
It realizes the dot product calculation of external input analog voltage signal and signed integer, and the data range is extended to [-15, 15], which solves the problem that the existing technology can only handle unsigned integers.
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Figure CN116185336B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of in-memory computing, and specifically refers to a signed number analog in-memory computing circuit based on SRAM. Background Technology
[0002] In recent years, in-memory computing circuit design has become a research hotspot in the field of integrated circuits. In-memory computing utilizes memory such as SRAM, DRAM, Flash, and ReRAM, and employs both digital and analog computing methods. In 2019, researchers proposed an analog in-memory computing method based on 8T SRAM cells (Akhilesh Jaiswal et al. published an article titled "8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing" in IEEE Transactions on Very Large Scale Integration (VLSI) Systems). Figure 3 As shown, a standard 6T SRAM cell is used as the memory, and two external transistors operate in the deep linear region to achieve analog in-memory computation. Figure 3 Taking a 6T SRAM standard cell 0 and transistors M0 and M1 as an example, the in-memory computing circuit consists of SL (Source Line), the external analog input signal, and RWL (Read Word Line), the external read control signal, which controls the reading of SRAM data. RBL (Read Bit Line), the SRAM data, is read out through RBL. 6T SRAM standard cell 0 can store 1 bit of data. The stored data is connected to the gate of transistor M1. When the data stored in the SRAM is 0, transistor M1 is off, and the drain and source of transistor M1 can be considered an open circuit, with a conductance of approximately 0. When the data stored in the SRAM is 0, transistor M1 is on. RWL is connected to the gate of transistor M0. When RWL is low, transistor M0 is off, and the drain and source of transistor M0 can be considered an open circuit, with a conductance of approximately 0. When RWL is high, transistor M0 is on. For the analog in-memory computing unit to function properly, RWL needs to be connected to a high level to turn on transistor M0. The on / off state of transistor M1 depends on the data stored in the 6T SRAM cell. When RWL is connected to a high level and the data stored in the SRAM cell is 1, both transistors M0 and M1 are turned on. By controlling the input voltage of SL within a certain range, transistors M0 and M1 can operate in the deep linear region. The on-resistance R of the transistor operating in the deep linear region...on The conductance G, expressed by formula (a1), is... on This can be expressed by formula (a2):
[0003]
[0004]
[0005] Where, μ n For electron mobility, C ox V is the gate oxide capacitance per unit area, W is the channel width, L is the channel length, and V is the capacitance per unit area. GS V is the gate-source voltage. TH Let V be the threshold voltage. in With the source of M0 clamped to 0 potential, and transistors M1 and M0 having the same dimensions (channel width W and channel length L), the current I0 through transistors M1 and M0 is expressed by formula (a3):
[0006]
[0007] I0 is the output current of SRAM computation unit 0. Similarly, I1, I2, and I3 of SRAM computation units 1, 2, and 3 can be obtained. Since μ... n C ox V GS V TH As can be seen from formulas (a2) and (a3), when the input voltage V remains unchanged... in When constant, the output current I0 and the width-to-length ratio of transistors M0 and M1 Proportional. Let the width-to-length ratio of transistors M0 and M1 be... The aspect ratio of transistors M2 and M3 is The aspect ratio of transistors M4 and M5 is The aspect ratio of transistors M6 and M7 is make The output current I3:I2:I1:I0 = 8:4:2:1. By setting the transistor width-to-length ratio in the above manner, the quantization of the 4-bit binary weights of data in different SRAM cells can be achieved. According to Kirchhoff's current law, the total output current I... out This can be expressed by formula (a4): I out =I0+I1+I2+I3(a4) In summary, this analog memory computing circuit can realize the input analog signal V in The input signal is an analog voltage, and the stored data is an unsigned integer in the range [0, 15]. The product of the input signal and the stored data is an unsigned integer in the range [0, 15]. The product of the input signal and the stored data is expressed by formula (a5):
[0008]
[0009] Where K is a constant, W i W represents the weight of the i-th bit of data stored in SRAM. i =2 i , i = 0, 1, 2, 3.
[0010] However, the above techniques have the following drawbacks: Since the dot product calculation in these techniques is based on Ohm's law and Kirchhoff's laws, ... Figure 3 The conductance of a transistor in a circuit cannot be negative, so it cannot represent the case where the data stored in SRAM is negative. Therefore, it can only perform dot multiplication between an externally input analog voltage signal and an unsigned integer. Summary of the Invention
[0011] The purpose of this invention is to address the shortcomings of the prior art by providing a signed number analog in-memory computing circuit based on SRAM. The following solution is designed to enable data stored in SRAM to represent negative numbers and to perform dot-matrix calculations between externally input analog voltage signals and signed integers.
[0012] The present invention is achieved through the following technical solution, including 6T SRAM standard cell 0, 6T SRAM standard cell 1, 6T SRAM standard cell 2 and 6T SRAM standard cell 3, which respectively store 4 bits of data Bit 0, Bit 1, Bit 2 and Bit 3;
[0013] It also includes 6T SRAM standard cell 4 storing data as sign bits, where a sign bit of 0 indicates a positive sign and a sign bit of 1 indicates a negative sign;
[0014] The data stored in the 6T SRAM standard cell 4 is connected to the gates of transistors M16 and M17, controlling the on and off states of transistors M16 and M17;
[0015] M16 is a P-type MOSFET, and M17 is an N-type MOSFET. M16 and M17 form the switching selection circuit.
[0016] To make M16 and M17 closer to the characteristics of an ideal switch and reduce their on-resistance, the width-to-length ratio of M16 and M17 is... and Yuanda and other transistors;
[0017] When the data stored in the 6T SRAM standard cell 4 is 0, transistor M17 is turned on, Vin2 is connected to the input signal, and the circuit 2 consisting of transistors M17, M15, M14, M11, M10, M7, M6, M3, and M2 between circuit nodes Vin2 and Vref is working.
[0018] When the data stored in the 6T SRAM standard cell 4 is 1, transistor M16 is turned on, Vin1 is connected to the input signal, and the circuit node Vin1 and Vref, which is composed of transistors M16, M13, M12, M9, M8, M5, M4, M1, and M0, is working.
[0019] When all 6T SRAM standard cells store data as 1, their data terminal potential is V. dd When the stored data is 0, its data terminal potential is V. ss ;
[0020] Reference voltage V ref With V dd V ss The relationship is satisfied as shown in formula (1), and the two input signals V in1 and V in2 Regarding the reference voltage V ref Symmetrical, satisfying the relationships shown in formulas (2) and (3):
[0021]
[0022] |V in1 -V ref |=|V in2 -V ref |,V in1 <V ref <V in2 (2)
[0023]
[0024] Under the conditions of satisfying formulas (1), (2), and (3), the gate-source voltage V of the transistors at corresponding positions in loop 1 and loop 2 can be made... GS same;
[0025] Let the high-level potential of RWL be V. dd The low-level potential is V ss When RWL is high and the data stored in 6T SRAM standard cell 4 is 0, the voltage V across the drain and source of transistors M0 and M1 is... DS0 V DS1 Equation (4) states that when RWL is high and the data stored in the 6T SRAM standard cell 4 is 1, the voltage V across the drain and source of transistors M2 and M3 is...DS2 V DS3 Represented by formula (5);
[0026]
[0027]
[0028] Similarly, the voltages across the drain and source terminals of transistors M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, and M15 can be obtained.
[0029] Based on the transistor's on-resistance R on and drain-source voltage V DS The output currents I0, I1, I2, and I3 are obtained. When the sign bit is 0, transistor M16 is turned on, and I0 can be represented by formula (6); when the sign bit is 1, transistor M17 is turned on, and I0 can be represented by formula (7).
[0030]
[0031]
[0032] Similarly, the expressions for I1, I2, and I3 can be obtained;
[0033] The input signal V of loop 2 of the internal computing circuit in1 and V in2 From external input signal V in This is generated through an operational circuit, where OPA1 and OPA2 are two operational amplifiers, and the resistance values of the four resistors are all R and V. ref and V ref1 There are two reference voltages; reference voltage V ref The magnitude is expressed by formula (1), and the reference voltage V ref1 and V ref The relation satisfies formula (8), V in V in1 and V in2 The expression is represented by formulas (9) and (10):
[0034]
[0035]
[0036] V in2 =-V in1 +2×V ref =-V in +2V ref (10)
[0037] Adding equations (9) and (10) together, we get equation (3), which indicates that the circuit generates the signal V. in1 and V in2 Meets design requirements;
[0038] To achieve the input analog signal V in The input signal is multiplied by the 5-bit data stored in SRAM. The input signal is an analog voltage, and the stored data is an integer in the range [-15, 15]. The result of the multiplication is the output current. The expression for the multiplication of the input signal and the stored data can be represented by formula (11):
[0039]
[0040] Where K is a constant, S represents the sign bit, and S takes the value of -1 or 1, W i W represents the weight of the i-th bit of data stored in SRAM. i =2 i , i = 0, 1, 2, 3.
[0041] Width-to-length ratio of each transistor in circuit 1 The following relationship must be satisfied:
[0042] in The aspect ratio of transistors M12 and M13. The aspect ratio of transistors M8 and M9. The aspect ratio of transistors M4 and M5. This represents the width-to-length ratio of transistors M0 and M1.
[0043] Width-to-length ratio of each transistor in circuit 2 The following relationship must be satisfied:
[0044] The aspect ratio of transistors M14 and M15. The aspect ratio of transistors M10 and M11 The aspect ratio of transistors M6 and M7. This represents the width-to-length ratio of transistors M2 and M3.
[0045] The beneficial effect of this invention is that it enables the data stored in the SRAM cell of the SRAM-based analog in-memory computing circuit to represent negative numbers, and realizes the dot product calculation of the external input analog voltage signal and the signed integer, thus solving the problem in the prior art that only the external input analog voltage signal and the unsigned integer can be multiplied. Attached Figure Description
[0046] Figure 1 This is an in-memory computing circuit for signed numbers based on SRAM.
[0047] Figure 2 This is a circuit for generating two input signals.
[0048] Figure 3 A method for simulating in-memory calculation of 4-bit weights. Detailed Implementation
[0049] To make the objectives, technical solutions, and advantages of this invention clearer, the following detailed embodiments are described in conjunction with the appendix. Figures 1 to 3 The present invention will be described in further detail below. It should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention; moreover, technical features involved in different embodiments of the invention described below can be combined with each other as long as they do not conflict with each other. The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.
[0050] A signed number analog in-memory computing circuit based on SRAM, such as Figure 1 As shown, Figure 3 The circuitry has been expanded. It includes 6T SRAM standard cells 0, 1, 2, and 3, which store 4-bit data bits 0, 1, 2, and 3 respectively; 6T SRAM standard cells 0, 1, 2, and 3 are connected to... Figure 3 Same as above.
[0051] It also includes 6T SRAM standard cell 4 storing data as sign bits, where a sign bit of 0 indicates a positive sign and a sign bit of 1 indicates a negative sign;
[0052] The data stored in the 6T SRAM standard cell 4 is connected to the gates of transistors M16 and M17, controlling the on and off states of transistors M16 and M17;
[0053] M16 is a P-type MOSFET, and M17 is an N-type MOSFET. M16 and M17 form the switching selection circuit. To make M16 and M17 closer to the characteristics of an ideal switch and reduce their on-resistance, according to formula (a1), the width-to-length ratio of M16 and M17 should be... and Yingyuanda and other transistors; when the data stored in the 6T SRAM standard cell 4 is 0, transistor M17 is turned on, Vin2 is connected to the input signal, and the circuit node Vin2 and Vref are connected to the circuit circuit 2 consisting of transistors M17, M15, M14, M11, M10, M7, M6, M3 and M2.
[0054] When the data stored in the 6T SRAM standard cell 4 is 1, transistor M16 is turned on, Vin1 is connected to the input signal, and the circuit node Vin1 and Vref, which is composed of transistors M16, M13, M12, M9, M8, M5, M4, M1, and M0, is working.
[0055] When all 6T SRAM standard cells store data as 1, their data terminal potential is V. dd When the stored data is 0, its data terminal potential is V. ss ;
[0056] Figure 1 Reference voltage V ref With V dd V ss The relationship is satisfied as shown in formula (1), and the two input signals V in1 and V in2 Regarding the reference voltage V ref Symmetrical, satisfying the relationships shown in formulas (2) and (3):
[0057]
[0058] |V in1 -V ref |=|V in2 -V ref |,V in1 <V ref <V in2 (2)
[0059]
[0060] Under the conditions of satisfying formulas (1), (2), and (3), the gate-source voltage V of the transistors (such as M0, M1, M2, and M3) at corresponding positions in loop 1 and loop 2 can be reduced. GS The same; as can be seen from formula (a1), the on-resistance of a transistor is determined by the electron mobility μ. n Gate oxide capacitance per unit area C ox Channel width W, channel length L, gate-source voltage V GS and threshold voltage V TH The determination is made regarding the μ values of transistors M0, M1, M2, and M3. n C ox W, L, VTH The same, as long as V GS If they are the same, the on-resistance R of transistors M0, M1, M2, and M3 can be made the same. on and conductivity G on same.
[0061] For the drain-source voltage V of the transistor DS Taking a 6T SRAM standard cell 0 and transistors M0, M1, M2, and M3 as an example, when the data (sign bit) stored in the 6T SRAM standard cell 4 is 0, transistor M16 is turned on. Because the on-resistance of M16 is very small, the voltage drop across it can be ignored. The potential at circuit node SL1 is approximately equal to the input signal V. in1 When the data (sign bit) stored in standard cell 4 of the 6T SRAM is 1, transistor M17 is turned on. Because the on-resistance of M17 is very small, the voltage drop across it can be ignored. The potential at circuit node SL2 is approximately equal to the input signal V. in2 .
[0062] Let the high-level potential of RWL (Read Word Line) be V. dd The low-level potential is V ss When RWL is high and the data (sign bit) stored in standard cell 4 of the 6T SRAM is 0, the voltage V across the drain and source of transistors M0 and M1 is... DS0 V DS1 Equation (4) states that when RWL is high and the data (sign bit) stored in the 6T SRAM standard cell 4 is 1, the voltage V across the drain and source of transistors M2 and M3 is... DS2 V DS3 Represented by formula (5);
[0063]
[0064]
[0065] Similarly, the voltages across the drain and source terminals of transistors M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, and M15 can be obtained.
[0066] Based on the transistor's on-resistance R on and drain-source voltage V DS The output currents I0, I1, I2, and I3 are obtained. When the sign bit is 0, transistor M16 is turned on, and I0 can be represented by formula (6); when the sign bit is 1, transistor M17 is turned on, and I0 can be represented by formula (7).
[0067]
[0068]
[0069] Similarly, the expressions for I1, I2, and I3 can be obtained; the total output current I out It can be represented by formula (a4);
[0070] The input signal V of loop 2 of the internal computing circuit in1 and V in2 From external input signal V in Generated through an operational circuit, its circuit diagram is as follows: Figure 2 As shown. OPA1 and OPA2 are two operational amplifiers, and the resistance of each of the four resistors is R, V. ref and V ref1 There are two reference voltages; reference voltage V ref The magnitude is expressed by formula (1), and the reference voltage V ref1 and V ref The relation satisfies formula (8), V in V in1 and V in2 The expression is represented by formulas (9) and (10):
[0071]
[0072]
[0073] V in2 =-V in1 +2×V ref =-V in +2V ref (10)
[0074] Adding equations (9) and (10) together, we get equation (3), which indicates that the circuit generates the signal V. in1 and V in2 Meets design requirements;
[0075] Will Figure 2 The circuit shown is Figure 1 The circuit connection shown is as follows. Figure 2 The circuit's signal output terminals Vin1 and Vin2 are connected to Figure 1 The circuit's signal input terminals Vin1 and Vin2,
[0076] Implement input analog signal V in The input signal is multiplied by the 5-bit data stored in SRAM. The input signal is an analog voltage, and the stored data is an integer in the range [-15, 15]. The result of the multiplication is the output current. The expression for the multiplication of the input signal and the stored data can be represented by formula (11):
[0077]
[0078] Where K is a constant, S represents the sign bit, and S takes the value of -1 or 1, W i W represents the weight of the i-th bit of data stored in SRAM. i =2 i , i = 0, 1, 2, 3.
[0079] The aspect ratio of each transistor in circuit 1 The following relationship must be satisfied:
[0080] in The aspect ratio of transistors M12 and M13. The aspect ratio of transistors M8 and M9. The aspect ratio of transistors M4 and M5. This represents the width-to-length ratio of transistors M0 and M1.
[0081] The aspect ratio of each transistor in circuit 2 The following relationship must be satisfied:
[0082] The aspect ratio of transistors M14 and M15. The aspect ratio of transistors M10 and M11 The aspect ratio of transistors M6 and M7. This represents the width-to-length ratio of transistors M2 and M3.
[0083] Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
Claims
1. A signed number analog in-memory computing circuit based on SRAM, comprising 6T SRAM standard cell 0, 6T SRAM standard cell 1, 6T SRAM standard cell 2, and 6T SRAM standard cell 3, respectively storing 4-bit data Bit 0, Bit 1, Bit 2, and Bit 3; characterized in that: It also includes 6T SRAM standard cell 4 storing data as sign bits, where a sign bit of 0 indicates a positive sign and a sign bit of 1 indicates a negative sign; The data stored in the 6T SRAM standard cell 4 is connected to the gates of transistors M16 and M17, controlling the on and off states of transistors M16 and M17; M16 is a P-type MOSFET, and M17 is an N-type MOSFET. M16 and M17 form the switching selection circuit. To make M16 and M17 closer to the characteristics of an ideal switch and reduce their on-resistance, the width-to-length ratio of M16 and M17 is... and Yuanda and other transistors; When the data stored in the 6T SRAM standard cell 4 is 0, transistor M17 is turned on, Vin2 is connected to the input signal, and the circuit 2 consisting of transistors M17, M15, M14, M11, M10, M7, M6, M3, and M2 between circuit nodes Vin2 and Vref is working. When the data stored in the 6T SRAM standard cell 4 is 1, transistor M16 is turned on, Vin1 is connected to the input signal, and the circuit node Vin1 and Vref, which is composed of transistors M16, M13, M12, M9, M8, M5, M4, M1, and M0, is working. When all 6T SRAM standard cells store data as 1, their data terminal potential is: When the stored data is 0, its data terminal potential is ; Reference voltage and , The relationship is satisfied as shown in formula (1), with two input signals. and Regarding the reference voltage Symmetrical, satisfying the relationships shown in formulas (2) and (3): ， ， ， Under the conditions of satisfying formulas (1), (2), and (3), the gate-source voltage of the transistors at corresponding positions in loop 1 and loop 2 can be reduced. same; Let the high-level potential of RWL be The low-level potential is ; When RWL is high and the data stored in standard cell 4 of the 6T SRAM is 0, the voltages across the drain and source of transistors M0 and M1 are... , Equation (4) states that when RWL is high and the data stored in the 6T SRAM standard cell 4 is 1, the voltages across the drain and source of transistors M2 and M3 are... , Represented by formula (5); ， ， Similarly, the voltages across the drain and source terminals of transistors M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, and M15 can be obtained. Based on the transistor's on-resistance and drain-source voltage , to obtain the output current , , , When the sign bit is 0, transistor M16 is turned on. This can be represented by formula (6); when the sign bit is 1, transistor M17 is turned on. It can be expressed by formula (7): ， ， Similarly, we can obtain , , The expression; Two input signals of the in-memory computing circuit and External input signal This is generated through an operational circuit, where OPA1 and OPA2 are two operational amplifiers, and the resistance values of the four resistors are all... , and There are two reference voltages; reference voltage The magnitude is expressed by formula (1), and the reference voltage is... and The relationship satisfies formula (8). , and The expression is given by formulas (9) and (10): ， ， ， Adding formulas (9) and (10) together, we get formula (3), which explains the generation of this circuit. and The signal meets the design requirements; To achieve input analog signal The input signal is a simulated voltage, and the stored data is an integer in the range [-15, 15]. The product of the input signal and the stored data is the output current. The expression for the product of the input signal and the stored data can be expressed by formula (11): ， Where K is a constant, and S represents the sign bit, which takes the value -1 or 1. The weight of the i-th bit of data stored in SRAM. , .
2. The signed number analog in-memory computing circuit based on SRAM according to claim 1, characterized in that, Width-to-length ratio of each transistor in circuit 1 The following relationship must be satisfied: ;in The aspect ratio of transistors M12 and M13. The aspect ratio of transistors M8 and M9. The aspect ratio of transistors M4 and M5. The aspect ratio of transistors M0 and M1 is given.
3. The signed number analog in-memory computing circuit based on SRAM according to claim 1, characterized in that, Width-to-length ratio of each transistor in circuit 2 The following relationship must be satisfied: ; The aspect ratio of transistors M14 and M15. The aspect ratio of transistors M10 and M11 The aspect ratio of transistors M6 and M7. This represents the width-to-length ratio of transistors M2 and M3.