Clock signal synchronization circuit and multi-lane phy

Abstract

A clock signal synchronization circuit and a multi-channel PHY, the circuit is applied to a multi-channel PHY, the multi-channel PHY comprises a PCS sublayer and a plurality of PMA sublayers, each PMA sublayer comprises at least one receiver, the receiver is used for receiving data transmitted by a channel corresponding to the receiver, and transmitting the received data to the PCS sublayer based on a local clock signal of the receiver; the circuit comprises: a detection module deployed in the PCS sublayer, and a calibration module deployed in the receiver, each calibration module is connected to the detection module; the detection module is used for sending a PCS local clock signal to the receiver after the receiver is powered on, so that the receiver takes the received PCS local clock signal as a reference clock signal; the calibration module is used for synchronizing the local clock signal of the receiver with the reference clock signal; and transmitting data to the PCS sublayer based on the synchronized local clock signal, so that the PCS sublayer samples the received data using the PCS local clock signal.

Description

Technical Field

[0001] This application relates to the fields of integrated circuit design and data transmission technology, and in particular to a clock signal synchronization circuit and a multi-channel PHY. Background Technology

[0002] The physical layer (PHY) of a high-speed serial interface mainly consists of the Physical Medium Dependent (PMD) sublayer, the Physical Medium Attachment (PMA) sublayer, and the Physical Coding Sublayer (PCS). In a multi-channel PHY, the clock phase of each channel is uncertain upon power-up, leading to data phase uncertainty. If the PCS directly uses registers for data reception, metastability issues can easily arise. To address this, a common solution is to insert an asynchronous FIFO at the PCS and PMA interface. At the receiver, input data is written to the FIFO using the receiver's local clock, and the PCS uses its local clock for reading, thus completing cross-clock domain data transmission. However, asynchronous FIFOs incur significant circuit overhead and high latency. Summary of the Invention

[0003] In a first aspect, embodiments of this application provide a clock signal synchronization circuit applied to a multi-channel PHY. The multi-channel PHY includes a PCS sublayer and multiple PMA sublayers. Each PMA sublayer includes at least one receiver for receiving data transmitted from the channel corresponding to the receiver, and transmitting the received data to the PCS sublayer based on the receiver's local clock signal. The circuit includes:

[0004] The detection module deployed in the PCS sublayer and the calibration module deployed in the receiver are both connected to the detection module;

[0005] The detection module is used to send PCS local clock signals to the receiver after the receiver is powered on, so that the receiver uses the received PCS local clock signals as reference clock signals.

[0006] The calibration module is used to synchronize the local clock signal of the receiver with the reference clock signal; and to transmit the data to the PCS sublayer based on the synchronized local clock signal, so that the PCS sublayer can sample the received data using the PCS local clock signal.

[0007] Secondly, embodiments of this application provide a multi-channel PHY, the multi-channel PHY comprising:

[0008] PCS sublayer, wherein a detection module is deployed in the PCS sublayer; and

[0009] Multiple PMA sublayers, each PMA sublayer including at least one receiver for receiving data transmitted through the channel corresponding to the receiver, and transmitting the received data to the PCS sublayer based on the local clock signal of the receiver; each receiver is equipped with a calibration module, and each calibration module is connected to the detection module;

[0010] The detection module is used to send PCS local clock signals to the receiver after the receiver is powered on, so that the receiver uses the received PCS local clock signals as reference clock signals.

[0011] The calibration module is used to synchronize the local clock signal of the receiver with the reference clock signal; and to transmit the data to the PCS sublayer based on the synchronized local clock signal, so that the PCS sublayer can sample the received data using the PCS local clock signal.

[0012] This application provides a clock phase adjustment circuit to replace the PCS asynchronous FIFO. On the one hand, the clock phase adjustment circuit uses a detection module and a calibration module to replace the multi-level registers in the asynchronous FIFO, thus effectively reducing circuit overhead. On the other hand, during data transmission, each receiver uses the received PCS local clock signal as a reference clock signal to synchronize its local clock signal, and transmits the data to the PCS sublayer based on the synchronized local clock signal. The PCS sublayer then samples the received data based on the PCS local clock signal. The above process does not require waiting for each channel to complete writing 1 UI of data before reading it out using the PCS local clock signal, thus reducing the latency of the data transmission process.

[0013] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments consistent with this application and, together with the description, serve to explain the technical solutions of this application.

[0015] Figure 1 This is a schematic diagram of a multi-channel PHY according to an embodiment of this application.

[0016] Figure 2 This is a schematic diagram of the clock phase adjustment circuit according to an embodiment of this application.

[0017] Figure 3This is a schematic diagram of the active alignment process of the receiver local clock signal in an embodiment of this application.

[0018] Figure 4 This is a schematic diagram of the clock phase adjustment circuit according to another embodiment of this application.

[0019] Figure 5A and Figure 5B This is a schematic diagram of the controlled alignment process of the receiver local clock signal in an embodiment of this application.

[0020] Figure 6 This is a schematic diagram of the overall architecture of the clock phase adjustment circuit according to an embodiment of this application.

[0021] Figure 7 This is a circuit diagram of the receiver and detection module of one channel in the clock phase adjustment circuit of this application embodiment.

[0022] Figure 8 This is a schematic diagram of the PCS receiving circuit according to an embodiment of this application.

[0023] Figure 9 This is a schematic diagram illustrating the operation of the clock phase adjustment circuit according to an embodiment of this application.

[0024] Figure 10 This is a simulation diagram of the active alignment of the clock phase adjustment circuit according to an embodiment of this application. Detailed Implementation

[0025] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0026] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items. Additionally, the term “at least one” herein means any combination of at least two of any one or more of a plurality.

[0027] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0028] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, and to make the above-mentioned objectives, features and advantages of the embodiments of this application more apparent and understandable, the technical solutions in the embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0029] The physical layer (PHY) of a high-speed serial interface refers to the hardware component in a high-speed serial communication system responsible for basic functions such as physical signal transmission, modulation / demodulation, encoding / decoding, and interface circuitry. See also... Figure 1 In a multi-channel PHY, there is a PCS sublayer 10 and multiple PMA sublayers 20. Each PMA sublayer 20 includes a transmitter (TX) and a receiver (RX), and each pair of transmitters (TX) and receivers (RX) corresponds to a channel for transmitting and receiving data on that channel. It should be noted that although... Figure 1 In the illustrated embodiment, each PMA sublayer 20 includes a transmitter TX and a receiver RX for transmitting and receiving data on a single channel. However, in practical applications, each PMA sublayer 20 may also include multiple transmitters TX and multiple receivers RX for transmitting and receiving data on multiple channels.

[0030] When PCS sublayer 10 communicates with PMA sublayer 20, PCS sublayer sends data to the transmitter TX of PMA sublayer 20. The transmitter TX then sends the data to the receiver RX of PMA sublayer 20 through the corresponding channel. The receiver RX then sends the received data back to PCS sublayer 10 (PCS sublayer 10 for sending data and PCS sublayer 10 for receiving data are usually located in different devices). Each time power is applied, the clock signal phase of each channel is uncertain, resulting in uncertain data phase. If PCS sublayer 10 directly uses registers for data reception, since data sampling is usually performed at the transition edge (rising or falling edge) of the clock signal, the uncertain clock signal phase may cause data to change near the transition edge (i.e., data transitions between high and low levels), leading to uncertainty in the data sampling results. This is the metastability problem.

[0031] To address the metastability issue, a common solution is to insert an asynchronous FIFO (First In First Out) at the interface between PCS sublayer 10 and PMA sublayer 20. At the receiver, data is written to the asynchronous FIFO using the receiver's local clock signal, while the PCS sublayer reads data from the asynchronous FIFO using the PCS local clock signal, thus completing data transmission across clock domains.

[0032] However, asynchronous FIFOs require multi-level registers, resulting in significant circuit overhead. Furthermore, due to the delay in data transmission between channels, PCS sublayer 10 requires each channel to complete the writing of one unit interval (UI) of data before using the PCS local clock signal for reading to achieve data alignment. This leads to substantial delays in data transmission and reception, leaving considerable room for optimization for low-latency die-to-die interconnects.

[0033] Based on this, embodiments of this application propose a clock signal synchronization circuit, combined with Figure 1 The multi-channel PHY shown, and see also Figure 2 The circuit includes:

[0034] The detection module 101 is deployed in the PCS sublayer 10, and the calibration module 201 is deployed in the receiver RX. Each calibration module 201 is connected to the detection module 101.

[0035] The detection module 101 is used to send the PCS local clock signal PCS_local_clk to the receiver RX after each receiver RX is powered on, so that the receiver RX uses the received PCS local clock signal as the reference clock signal pma_rx_base_clk;

[0036] The calibration module 201 is used to synchronize the local clock signal pma_rx_local_clk of the receiver RX with the reference clock signal pma_rx_base_clk of the receiver RX, and to transmit the data to the PCS sublayer 10 based on the synchronized local clock signal pma_rx_local_clk, so that the PCS sublayer 10 can sample the received data using the PCS local clock signal PCS_local_clk.

[0037] For ease of description, the following example illustrates the scheme of this application embodiment, assuming that the number of PMA sublayers 20 is equal to 4, and each PMA sublayer 20 includes only one transmitter TX and one receiver RX (i.e., each PMA sublayer 20 corresponds to one channel). For ease of distinction, the different PMA sublayers 20 are respectively referred to as PMA0, PMA1, PMA2, ​​and PMA3.

[0038] After multiple receivers (RX) are powered on, the detection module 101 deployed on the PCS sublayer 10 can send the PCS local clock signal PCS_local_clk to each of the multiple receivers (RX). The PCS local clock signal PCS_local_clk is the local clock signal of the PCS sublayer 10. This clock signal can be provided by any transmitter (TX) in the PMA sublayer 20, or it can be generated in other ways. The local clock signal of the transmitter (TX) and the local clock signal pma_rx_local_clk of the receivers (RX) can be from the same frequency and source; for example, they can both originate from an on-chip phase-locked loop (PLL) or an external clock source. Each time power is applied, the phase of the local clock signal pma_rx_local_clk of each receiver RX is uncertain. For ease of distinction, the local clock signals pma_rx_local_clk of the receiver RX in PMA0, PMA1, PMA2 and PMA3 are denoted as pma_rx_local_clk0, pma_rx_local_clk1, pma_rx_local_clk2 and pma_rx_local_clk3 respectively.

[0039] The PCS local clock signal PCS_local_clk can be received by each receiver RX. Due to slight differences in transmission delay between different receiving paths, the phase of the PCS local clock signal PCS_local_clk sent by the detection module may differ slightly from the phase of the PCS local clock signal received by each receiver RX. In other words, the phase of the reference clock signal pma_rx_base_clk of each receiver may be different. For ease of distinction, the reference clock signals pma_rx_base_clk of the receiver RX in PMA0, PMA1, PMA2, ​​and PMA3 will be denoted as pma_rx_base_clk0, pma_rx_base_clk1, pma_rx_base_clk2, and pma_rx_base_clk3, respectively.

[0040] The calibration module 201 deployed in the receiver RX can acquire the local clock signal pma_rx_local_clk of the receiver RX and the reference clock signal pma_rx_base_clk of the receiver RX, determine the phase difference between the local clock signal pma_rx_local_clk and the reference clock signal pma_rx_base_clk, and adjust the phase of the local clock signal pma_rx_local_clk based on this phase difference, thereby synchronizing the local clock signal pma_rx_local_clk of the receiver RX using the reference clock signal pma_rx_base_clk. The phase of the synchronized local clock signal pma_rx_local_clk' of the receiver RX is aligned with the reference clock signal pma_rx_base_clk of the receiver RX.

[0041] Taking PMA0 as an example, the calibration module 201 in the receiver RX of PMA0 can obtain the local clock signal pma_rx_local_clk0 and the reference clock signal pma_rx_base_clk0 of the receiver RX of PMA0. Based on the phase difference between pma_rx_local_clk0 and pma_rx_base_clk0, the phase of pma_rx_local_clk0 is adjusted to obtain pma_rx_local_clk0', and the phase of pma_rx_local_clk0' is aligned with the reference clock signal pma_rx_base_clk0. Similarly, the synchronized local clock signal pma_rx_local_clk1' of the receiver RX of PMA1, the synchronized local clock signal pma_rx_local_clk2' of the receiver RX of PMA2, ​​and the synchronized local clock signal pma_rx_local_clk3' of the receiver RX of PMA3 can be obtained.

[0042] In some embodiments, the phase difference between the PCS local clock signal PCS_local_clk and the local clock signal pma_rx_local_clk of the receiver RX is determined based on the edge position of the PCS local clock signal PCS_local_clk and the edge position of the local clock signal pma_rx_local_clk of the receiver RX.

[0043] Specifically, calibration module 201 can perform edge detection on the PCS local clock signal PCS_local_clk and the local clock signal pma_rx_local_clk of the receiver RX, respectively, to obtain the edges of the PCS local clock signal PCS_local_clk and the local clock signal pma_rx_local_clk of the receiver RX. Then, based on the positions of the edges of the PCS local clock signal PCS_local_clk and the local clock signal pma_rx_local_clk of the receiver RX where calibration module 201 is located, the phase difference between the PCS local clock signal PCS_local_clk and the local clock signal pma_rx_local_clk of the receiver RX where calibration module 201 is located is determined.

[0044] In some embodiments, the detection module 101 can also send a clock-ready signal pma_rx_clk_ready to each receiver RX after the PCS and RX clocks are established and stabilized. Upon receiving the clock-ready signal pma_rx_clk_ready, each calibration module 201 can perform edge detection on the PCS local clock signal PCS_local_clk and the local clock signal pma_rx_local_clk of its respective receiver RX.

[0045] In some embodiments, the local clock signal pma_rx_local_clk of the receiver RX includes multiple phases. For example, the local clock signal pma_rx_local_clk of the receiver RX can be a 4-phase clock signal or an 8-phase clock signal, correspondingly including 4 phases or 8 phases. Of course, the number of phases of the local clock signal pma_rx_local_clk of the receiver RX can also be other values, and this application does not limit this.

[0046] During phase adjustment, the calibration module 201 can determine the phase difference between the phase of the reference clock signal pma_rx_base_clk of the receiver RX and multiple phases of the receiver local clock signal pma_rx_local_clk of the receiver RX. From these multiple phases, it determines the target phase with the smallest phase difference from the reference clock signal pma_rx_base_clk of the receiver RX, and adjusts the phase of the local clock signal pma_rx_local_clk of the receiver RX to the target phase. For example, when the local clock signal pma_rx_local_clk of the receiver RX is a 4-phase clock signal, its multiple phases include 0°, 90°, 180°, and 270°. If 90° is the target phase with the smallest phase difference from the reference clock signal pma_rx_base_clk of the receiver RX, then the phase of the local clock signal pma_rx_local_clk of the receiver RX can be adjusted to 90°.

[0047] After phase adjustment of the receiver RX's local clock signal pma_rx_local_clk, the calibration module 201 can also perform clock glitch elimination on the adjusted local clock signal. Clock glitch elimination can reduce errors caused by noise and improve the accuracy and reliability of the determined phase difference.

[0048] After phase adjustment of the local clock signal pma_rx_local_clk of the receiver RX, each receiver RX can align the phase of the data received by it with the adjusted local clock signal and transmit the aligned data to PCS sublayer 10. Since there is a certain delay in the data transmission from each PMA sublayer 20 to PCS sublayer 10, there will be a certain phase difference in the data received by PCS sublayer 10 from each PMA sublayer 20. However, there is also a certain phase difference between the phases of the reference clock signals pma_rx_base_clk of each receiver RX. The phase difference between the reference clock signals pma_rx_base_clk can compensate for the phase difference of the data received by PCS sublayer 10, enabling PCS sublayer 10 to sample the data received from each receiver RX based on the PCS local clock signal PCS_local_clk.

[0049] The above-described solution of this application provides a clock phase adjustment circuit to replace the PCS asynchronous FIFO. On the one hand, the clock phase adjustment circuit does not require multi-level registers, thus effectively reducing circuit overhead. On the other hand, during data transmission, each receiver uses the received PCS local clock signal PCS_local_clk as the reference clock signal pma_rx_base_clk for clock synchronization and data transmission. The PCS sublayer 10 samples the received data based on the PCS local clock signal PCS_local_clk. The above process does not require waiting for each channel to complete the writing of 1 UI of data before using the PCS local clock signal for reading, thus reducing the latency of the data transmission process.

[0050] Figure 3 Taking PMA0 as an example, the diagram illustrates the un-phase-adjusted local clock signal pma_rx_local_clk0 of the PMA0 receiver, the original received data rx_data0 of PMA0 (assuming a data length of 32 bits in the figure), the reference clock signal pma_rx_base_clk0, and the adjusted received data rx_data0. It can be seen that before phase adjustment, the original received data rx_data0 is aligned with the rising edge of the receiver's local clock signal pma_rx_local_clk0. However, since the local clock signals pma_rx_local_clk0 of each receiver RX are different, metastability may occur. After adjustment, the receiver's local clock signal pma_rx_local_clk0 can be aligned with the reference clock signal pma_rx_base_clk0, and the adjusted received data rx_data0 is aligned to the rising or falling edge of the reference clock signal pma_rx_base_clk0. In this way, the phase of the data transmitted by each receiver is aligned with the reference clock signal pma_rx_base_clk of the corresponding receiver RX, and thus basically aligned with the local clock signal of the PCS. As a result, the PCS sublayer can directly use the local clock signal of the PCS to sample the data transmitted by each receiver.

[0051] In some embodiments, see Figure 4 Each receiver RX also includes a control module 202, which is connected to the detection module 101. Furthermore, each control module 202 is connected to the calibration module 201 within its respective receiver RX. For simplicity, only the specific structure of one receiver RX is shown in the figure; the structures of other receiver RXs can be referenced from the diagram shown and will not be described further here.

[0052] The detection module 101 is also used to perform status detection on the channels corresponding to multiple receivers RX. If a channel in a metastable state is detected, a synchronization calibration request signal pma_rx_ckph_req is sent to the control module 202 in the receiver RX corresponding to the metastable channel. Each control module 202 is used to control the calibration module 201 to adjust the phase of the receiver local clock signal pma_rx_local_clk of the receiver RX in response to receiving the synchronization calibration request signal pma_rx_ckph_req.

[0053] This application provides two adjustment modes. After each receiver RX is powered on, the clock phase adjustment circuit can enter active adjustment mode. In active adjustment mode, the calibration module 201 can synchronize the local clock signal pma_rx_local_clk of the receiver RX based on the reference clock signal pma_rx_base_clk. After phase alignment is completed in active adjustment mode, the detection module 101 can perform metastability detection on the corresponding channel of each receiver RX. If a metastable channel is detected, the clock phase adjustment circuit can switch from active adjustment mode to controlled adjustment mode. In controlled adjustment mode, the control module 202 can respond to the received synchronization calibration request signal pma_rx_ckph_req and control the calibration module 201 to adjust the phase of the local clock signal pma_rx_local_clk of its receiver RX. Active phase alignment and controlled phase alignment are independent of each other and do not affect each other.

[0054] In this embodiment, the detection module 101 in the PCS sublayer 10 can send test signals to each PMA sublayer 20, and the receivers RX of each PMA sublayer 20 can retransmit the acquired test signals back to the PCS sublayer 10. The detection module 101 can determine whether the channel corresponding to each receiver RX is in a metastable state based on the difference between the sent test signals and the signals received from each receiver RX. Assuming that the channel corresponding to PMA0 is detected to be in a metastable state, the detection module 101 can send a synchronization calibration request signal pma_rx_ckph_req to the receiver RX in PMA0. This synchronization calibration request signal pma_rx_ckph_req can be... Figure 5A The phase lead request signal pma_rx_ckph_inc_req shown can also be Figure 5BThe phase lag request signal pma_rx_ckph_dec_req is shown. Control module 202 in the receiver RX of PMA0 can respond to the phase lead request signal pma_rx_ckph_inc_req by controlling calibration module 201 to advance the phase of the local clock signal pma_rx_local_clk of the receiver RX of PMA0, and can also respond to the phase lag request signal pma_rx_ckph_dec_req by controlling calibration module 201 to advance the phase of the local clock signal pma_rx_local_clk of the receiver RX of PMA0. Since the data in the receiver RX is aligned with the receiver's aligned local clock signal, the phase lead request signal pma_rx_ckph_inc_req will advance the data transmission time, while the phase lag request signal pma_rx_ckph_dec_req will delay the data transmission time.

[0055] In some embodiments, the detection module 101 and the control module 202 can achieve the phase alignment process described above through a handshake. Specifically, see... Figure 5A and Figure 5B After receiving the synchronization calibration request signal pma_rx_ckph_req sent by the detection module 101, the control module 202 can send a response signal pma_rx_ckph_ack to the detection module 101 in response to the synchronization calibration request signal pma_rx_ckph_req. After the calibration module 201 completes the phase adjustment of the local clock signal of its receiver, the control module 202 can stop sending the response signal pma_rx_ckph_ack to the detection module 101. The detection module 101 can stop sending the synchronization calibration request signal pma_rx_ckph_req when the control module 202 stops sending the response signal pma_rx_ckph_ack.

[0056] In some embodiments, both the synchronization calibration request signal pma_rx_ckph_req and the response signal pma_rx_ckph_ack can be level signals, specifically, they can be high-level signals. That is, the detection module 101 can pull the level of the synchronization calibration request signal pma_rx_ckph_req high, and after the control module 202 detects that the synchronization calibration request signal pma_rx_ckph_req is high, it can pull the level of the response signal pma_rx_ckph_ack high. After the calibration module 201 completes the phase adjustment of the local clock signal of the receiver, the control module 202 can pull the level of the response signal pma_rx_ckph_ack low. If the detection module 101 detects that the response signal pma_rx_ckph_ack is low, it will pull the level of the synchronization calibration request signal pma_rx_ckph_req low. At this point, the handshake process between the detection module 101 and the control module 202 ends.

[0057] The detection module 101 can align the data and clock phase of each channel by handshaking with each channel PMA multiple times in the manner described above. The alignment process of each channel can be performed in parallel. Since the physical environment of the channels and each PMA is basically determined when the SerDes PHY is used, only one alignment is needed after the system is established.

[0058] In some embodiments, the control module 202 can generate a status parameter (also called a status control word) for the receiver RX, which indicates the phase adjustment mode (lead or lag) of the local clock signal pma_rx_local_clk of the receiver RX. The calibration module 201 can adjust the phase of the local clock signal pma_rx_local_clk of the receiver RX based on the status parameter. Optionally, a number (such as an integer like 0, +1, and -1) can be used as the status parameter, where a status parameter of -1 indicates that the local clock signal pma_rx_local_clk of the receiver is adjusted to lead. Taking the receiver's local clock signal pma_rx_local_clk as a 4-phase clock signal as an example, when the current phase of the receiver's local clock signal pma_rx_local_clk is 90°, by setting the status parameter to -1, the phase of the receiver's local clock signal pma_rx_local_clk can be adjusted to the previous phase, i.e., 0°. A status parameter of +1 indicates that hysteresis adjustment is performed on the receiver's local clock signal pma_rx_local_clk. When the current phase of the receiver's local clock signal pma_rx_local_clk is 90°, setting the status parameter to +1 will adjust the phase of the receiver's local clock signal pma_rx_local_clk to the next phase, i.e., 180°. A status parameter of 0 indicates that no phase adjustment is performed on the receiver's local clock signal pma_rx_local_clk.

[0059] After phase adjustment of the receiver's local clock signal pma_rx_local_clk, the detection module 101 can re-detect the state of the corresponding channel. If the channel is still in a metastable state, the phase adjustment process described above can be repeated until the channel is no longer in a metastable state.

[0060] The overall flow of the phase adjustment process of this application will be illustrated below through some specific embodiments.

[0061] Figure 6 This is a schematic diagram of the overall architecture of the clock phase adjustment circuit in an embodiment of this application. The PCS local clock signal is provided by the transmitter TX, and the TX, RX, and PCS local clock signals are of the same frequency and origin. The PCS sublayer 10 uses the PCS local clock signal to provide a reference clock signal pma_rx_base_clk at each channel, and directly samples the data transmitted by RX using the PCS local clock signal. Figure 7This is a schematic diagram of a receiver and detection module for one channel, where the clock phase adjustment circuit consists of: (1) a detection module, (2) a control module, and (3) a calibration module. For one channel PMA, the serial data passes through the analog front end (AF) and the sampler array (SLICER) to become 4 parallel data streams, which then enter the 1-bit data adjustment circuit and the 4-bit data adjustment circuit. Subsequently, a 4:16 deserializer (DEMUX) deserializes the data into 16-bit parallel data, and then a 16:32 deserializer (DEMUX) deserializes it into 32-bit parallel data. The detection module, control module, and calibration module perform phase adjustment on the receiver's local clock signal using the phase adjustment method described in the previous embodiment. Then, they align the 32-bit parallel data with the receiver's adjusted local clock signal. Since the receiver's adjusted local clock signal is aligned with the reference clock signal, the above method can ensure that the data edges sent to the PMA from each channel are aligned with the reference clock signal, allowing the PCS sublayer to directly sample the data sent by the RX using the PCS local clock signal.

[0062] The data receiving circuit of the PCS sublayer is as follows Figure 8 As shown, data is received through the registers of the PCS sublayer. The PCS sublayer retrieves the local clock signal from the buffer. This clock signal is sent to the receiver for clock signal alignment and is also used by the PCS to sample the data transmitted to the receiver. It should be noted that the clock signal used for alignment is the received signal corresponding to the PCS local clock signal at the receiver, i.e., pma_rx_base_clk, while the signal used for data sampling is the PCS local clock signal itself. Although they originate from the same source, there may be slight differences in phase due to channel transmission delay. This application eliminates cross-clock domain data read / write operations in asynchronous FIFOs. To ensure correct sampling, the RX needs to align the transmitted data to the rising or falling edge of pma_rx_base_clk to ensure maximum sampling margin. The phase relationship between rx_data and pma_rx_base_clk before and after adjustment is as follows: Figure 3 As shown.

[0063] Figure 5A and Figure 5BThis diagram illustrates the controlled alignment process of the receiver's local clock signal. After receiving data from each channel and performing metastability verification, the PCS sublayer can switch to controlled alignment if additional clock phase modification is required beyond active alignment. It sends a phase lead request signal (pma_rx_ckph_inc_req) or a phase lag request signal (pma_rx_ckph_dec_req) to each channel. Upon receiving this request, the PMA sublayer sends a response signal (pma_rx_ckph_ack) to the PCS sublayer, informing it that the request has been received. Subsequently, the PMA sublayer changes the state machine control word (i.e., the state parameters in the aforementioned embodiment) to complete the clock and data phase lead and lag operations. After adjustment confirmation, the pma_rx_ckph_ack signal is pulled low. Upon detecting this low signal, the PCS sublayer pulls the signal level of the phase lead request (pma_rx_ckph_inc_req) or the phase lag request (pma_rx_ckph_dec_req) low, completing the handshake. The PCS aligns the data and clock phase of each channel by handshaking with each channel PMA multiple times. Since the physical environment of the channels and each PMA is basically determined when the SerDes PHY is used, only one alignment is needed after the system is established.

[0064] When actively aligning, such as Figure 9 As shown, the 8-phase receiver local clock signal is used to demultiplex pma_rx_base_clk in a 1:8 ratio. The 8-bit data enters the edge detection circuit to find the edge position of pma_rx_base_clk. Based on the alignment to the rising or falling edge requirement, the 8-phase clock is selected, and the phase closest to pma_rx_base_clk is fitted. A glitch elimination circuit is used to eliminate glitches during clock switching. Finally, the lowest-speed parallel data sent by RX is retied to be emitted at the edge of the phase closest to pma_rx_base_clk. Therefore, the clock adjustment circuit has adjustment progress and a maximum error. Since 8-phase clocks are used to fit pma_rx_base_clk, the accuracy is 45 degrees. Regarding the error, this circuit operates at 1GHz with an 8-phase clock, the data retiming delay is 30ps, and the error range is [-delay, T / 8-delay], i.e., [-30p, 95p], which meets the sampling margin requirement.

[0065] Figure 10To achieve the desired time-domain alignment, CLK_ref is the input reference frequency, set to 1.05 GHz to demonstrate the alignment effect. CLK_OUT is the output mirror clock at 1 GHz, and PD_EN is the enable signal. It can be seen that when enabled, the time-domain waveform of CLK_OUT essentially overlaps with CLK_ref, with its frequency fluctuating around 1.05 GHz. When enabled is disabled, CLK_OUT is a 1 GHz signal, misaligned with CLK_ref. Compared to traditional phase-locked loop (PLL) operations, this design offers advantages such as smaller circuit size, faster locking speed, and no loop stability issues. It is suitable for power consumption and area requirements in short-distance transmission.

[0066] Regarding delay optimization, this design includes circuit and routing delays, as well as clock adjustment delay. Without adjustment, the adjustment delay is 0. After adjustment, for every 45-degree clock lag, the delay increases by 1 / 8 UI. Due to clock periodicity, the adjustment delay is always less than or equal to 7 / 8 UI. Considering that the data sent to the PCS is the lowest-speed parallel data, the circuit delays, such as those of flip-flops and routing, are far less than 1 UI and can be ignored. The maximum total delay is less than 1 UI, which is superior to the delay of commonly used alignment methods such as asynchronous FIFOs.

[0067] This application also provides a multi-channel PHY, the multi-channel PHY comprising:

[0068] PCS sublayer, wherein a detection module is deployed in the PCS sublayer; and

[0069] Multiple PMA sublayers, each PMA sublayer including at least one receiver for receiving data transmitted through the channel corresponding to the receiver, and transmitting the received data to the PCS sublayer based on the local clock signal of the receiver; each receiver is equipped with a calibration module, and each calibration module is connected to the detection module;

[0070] The detection module is used to send PCS local clock signals to the receiver after the receiver is powered on, so that the receiver uses the received PCS local clock signals as reference clock signals.

[0071] The calibration module is used to synchronize the local clock signal of the receiver with the reference clock signal; and to transmit the data to the PCS sublayer based on the synchronized local clock signal, so that the PCS sublayer can sample the received data using the PCS local clock signal.

[0072] In some embodiments, each receiver is further equipped with a control module, and each control module is connected to the detection module and the calibration module on the receiver respectively; the detection module is further configured to send a synchronization calibration request to the control module in the receiver when the channel corresponding to the receiver is in a metastable state; the control module is configured to control the calibration module to perform phase adjustment on the local clock signal of the receiver when the synchronization calibration request is received.

[0073] For details of the above-described multi-channel PHY implementation, please refer to the aforementioned implementation of the clock signal synchronization circuit, which will not be repeated here.

[0074] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate. When implementing the embodiments of this application, the functions of each module can be implemented in one or more software and / or hardware. Alternatively, some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0075] The above description is only a specific implementation of the embodiments of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the embodiments of this application, and these improvements and modifications should also be considered as the protection scope of the embodiments of this application.

Claims

1. A clock signal synchronization circuit, characterized in that, This is applied to a multi-channel PHY, which includes a PCS sublayer and multiple PMA sublayers. Each PMA sublayer includes at least one receiver for receiving data transmitted from the channel corresponding to that receiver, and transmitting the received data to the PCS sublayer based on the receiver's local clock signal. The circuit includes: The detection module deployed in the PCS sublayer and the calibration module deployed in the receiver are both connected to the detection module; The detection module is used to send PCS local clock signals to the receiver after the receiver is powered on, so that the receiver uses the received PCS local clock signals as reference clock signals. The calibration module is used to synchronize the local clock signal of the receiver with the reference clock signal; and to transmit the data to the PCS sublayer based on the synchronized local clock signal, so that the PCS sublayer can sample the received data using the PCS local clock signal.

2. The circuit according to claim 1, characterized in that, Each receiver also has a control module deployed therein, and each control module is connected to the detection module and the calibration module on the receiver respectively; The detection module is also used to send a synchronization calibration request to the control module in the receiver when the channel corresponding to the receiver is in a metastable state. The control module is used to control the calibration module to perform phase adjustment on the local clock signal of the receiver when the synchronization calibration request is received.

3. The circuit according to claim 2, characterized in that, The control module is also used for: In response to the synchronization calibration request signal, a response signal is sent to the detection module; and After the calibration module completes the phase adjustment of the local clock signal of the receiver, it stops sending response signals to the detection module. The detection module is also used to: stop sending the synchronous calibration request signal when the calibration module stops sending the response signal.

4. The circuit according to claim 2, characterized in that, After the multiple receivers are powered on, the clock phase adjustment circuit is in active adjustment mode; in active adjustment mode, each calibration module uses the reference clock signal to synchronize the local clock signal of the receiver it is in. When the detection module detects a channel in a metastable state, the clock phase adjustment circuit switches from the active adjustment mode to the controlled adjustment mode. In the controlled adjustment mode, each calibration module performs phase adjustment on the local clock signal of its respective receiver under the control of the control module in its receiver.

5. The circuit according to claim 1, characterized in that, The receiver's local clock signal includes multiple phases; the process by which the calibration module synchronizes the receiver's local clock signal using the reference clock signal includes: From the plurality of phases, determine the target phase with the smallest phase difference from the reference clock signal of the receiver. Adjust the phase of the local clock signal of the receiver to the target phase.

6. The circuit according to claim 5, characterized in that, The phase difference between the PCS local clock signal and the local clock signal of the receiver is determined based on the edge position of the PCS local clock signal and the edge position of the local clock signal of the receiver.

7. The circuit according to claim 6, characterized in that, The detection module is also used to send clock ready signals to each receiver; The calibration module is used for: Upon receiving the clock ready signal, edge detection is performed on the local clock signal of the PCS and the local clock signal of the receiver.

8. The circuit according to claim 1, characterized in that, The calibration module is also used for: Clock glitches are eliminated on the local clock signal synchronized with the receiver.

9. A multi-channel PHY, characterized in that, The multi-channel PHY includes: PCS sublayer, wherein a detection module is deployed in the PCS sublayer; and Multiple PMA sublayers, each PMA sublayer including at least one receiver for receiving data transmitted through the channel corresponding to the receiver, and transmitting the received data to the PCS sublayer based on the local clock signal of the receiver; each receiver is equipped with a calibration module, and each calibration module is connected to the detection module; The detection module is used to send PCS local clock signals to the receiver after the receiver is powered on, so that the receiver uses the received PCS local clock signals as reference clock signals. The calibration module is used to synchronize the local clock signal of the receiver with the reference clock signal; and to transmit the data to the PCS sublayer based on the synchronized local clock signal, so that the PCS sublayer can sample the received data using the PCS local clock signal.

10. The multi-channel PHY according to claim 9, characterized in that, Each receiver also has a control module deployed therein, and each control module is connected to the detection module and the calibration module on the receiver respectively; The detection module is also used to send a synchronization calibration request to the control module in the receiver when the channel corresponding to the receiver is in a metastable state. The control module is used to control the calibration module to perform phase adjustment on the local clock signal of the receiver when the synchronization calibration request is received.

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