Display device and electronic device including the same

Abstract

The present disclosure relates to a display device and an electronic device including the same. The display device can include a display panel including a pixel circuit, a gate driver, an emission driver, a data driver, and a driving controller. The pixel circuit can include a light emitting element, a first transistor, a second transistor, and a third transistor including a control electrode configured to receive a first initialization gate signal, a first electrode connected to a third node, and a second electrode receiving an initialization voltage. The driving controller can determine a light emitting element off ratio based on a maximum luminance value, and can determine a length of an active period in which the first initialization gate signal has an active level within a single frame based on the light emitting element off ratio, the light emitting element off ratio being a ratio of a period in which the light emitting element does not emit light within the single frame with respect to a length of the single frame.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and an electronic device including the display device. Background Technology

[0002] Typically, display devices can display images at a fixed drive frequency (or constant refresh rate), such as approximately 60Hz or approximately 120Hz. Recently, variable refresh rate modes have been developed that change the drive frequency depending on the characteristics of the image or the source of the image (e.g., the application that generated the image data).

[0003] In low-frequency drive mode, a single frame can include an address scan period and a self-scan period. Data voltage can be written to the pixel circuit during the address scan period, and data voltage can be left unwritten to the pixel circuit during the self-scan period.

[0004] During the self-scanning period, the voltage of the control electrode of the driving transistor, including in the pixel circuit, may be reduced due to leakage current, etc. Additionally, an initialization voltage may be applied to the source electrode of the driving transistor. The reduced voltage of the control electrode of the driving transistor reduces the difference between the voltage of the control electrode and the voltage of the source electrode. Consequently, during the self-scanning period, the pixel circuit may not emit light at the target brightness corresponding to the data voltage written to the pixel circuit during the address scan period. Flickering may occur, potentially degrading the display quality of the display device. Summary of the Invention

[0005] The present disclosure is characterized by providing a display device with improved display quality.

[0006] Another feature of this disclosure is that it provides an electronic device including the display device.

[0007] However, the features of this disclosure are not limited to those described above, and can be extended in various ways without departing from the spirit and scope of this disclosure.

[0008] According to an embodiment, the display device may include: a display panel including pixel circuitry; a gate driver configured to provide gate signals to the pixel circuitry; an emitter driver configured to provide a first emitter signal and a second emitter signal to the pixel circuitry; a data driver configured to provide a data voltage to the pixel circuitry; and a drive controller configured to control the gate driver, the emitter driver, and the data driver. The pixel circuitry may include: a light-emitting element; a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a control electrode configured to receive a write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the first node; a third transistor including a control electrode configured to receive a first initialization gate signal, a first electrode connected to the third node, and a second electrode configured to receive an initialization voltage; and a first capacitor including a first electrode connected to the first node and a second electrode connected to the third node. The drive controller can be configured to determine the light-emitting element turn-off ratio based on a maximum brightness value, and can be configured to determine the length of an active period within a single frame in which a first initialization gate signal has an active level, based on the light-emitting element turn-off ratio, wherein the maximum brightness value is a brightness value corresponding to a maximum gray level, and the light-emitting element turn-off ratio is the ratio of the period within a single frame in which the light-emitting element does not emit light to the length of the single frame.

[0009] In this embodiment, the light-emitting element turn-off ratio can be reduced as the maximum brightness value increases.

[0010] In an embodiment, a single frame may include an address scan period and a self-scan period. The drive controller may be configured to determine the length of a first activation period or a second activation period, wherein the first activation period is an activation period in the address scan period in which a first initialization gate signal has an activation level, and the second activation period is an activation period in the self-scan period in which the first initialization gate signal has an activation level.

[0011] In this embodiment, the length of the second activation period can be reduced as the turn-off ratio of the light-emitting element increases.

[0012] In an embodiment, the drive controller can be configured to maintain a constant length for the first activation period during the address scan period, regardless of the light-emitting element turn-off ratio.

[0013] In this embodiment, during the address scan period, the write gate signal may have an active level, a data voltage may be written to the pixel circuit, and the light-emitting element may be configured to emit light based on the data voltage. During the self-scan period, the write gate signal may remain at a deactivated level, and the light-emitting element may be configured to emit light based on the data voltage written to the pixel circuit during the address scan period.

[0014] In an embodiment, the pixel circuit may further include a fourth transistor, which includes a control electrode configured to receive a second initialization gate signal, a first electrode configured to receive a reference voltage, and a second electrode connected to the first node.

[0015] In an embodiment, the pixel circuit may further include a fifth transistor, which includes a control electrode configured to receive a first transmit signal, a first electrode configured to receive a first power supply voltage, and a second electrode connected to a second node.

[0016] In an embodiment, the pixel circuit may further include a sixth transistor, which includes a control electrode configured to receive a first initialization gate signal, a first electrode configured to receive an anode initialization voltage, and a second electrode connected to the anode electrode of the light-emitting element.

[0017] In an embodiment, the pixel circuit may further include a seventh transistor, which includes a control electrode configured to receive a second emission signal, a first electrode connected to a third node, and a second electrode connected to the anode electrode of the light-emitting element.

[0018] In an embodiment, the pixel circuit may further include a second capacitor, which includes a first electrode configured to receive a reference voltage and a second electrode connected to a third node.

[0019] According to an embodiment, the display device may include: a display panel including pixel circuitry; a gate driver configured to provide gate signals to the pixel circuitry; an emitter driver configured to provide a first emitter signal and a second emitter signal to the pixel circuitry; a data driver configured to provide a data voltage to the pixel circuitry; and a drive controller configured to control the gate driver, the emitter driver, and the data driver. The pixel circuitry may include: a light-emitting element; a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a control electrode configured to receive a write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the first node; a third transistor including a control electrode configured to receive a first initialization gate signal, a first electrode connected to the third node, and a second electrode configured to receive an initialization voltage; and a first capacitor including a first electrode connected to the first node and a second electrode connected to the third node. The drive controller can be configured to determine the light-emitting element turn-off ratio based on the maximum brightness value, and can be configured to determine the initialization time based on the light-emitting element turn-off ratio, wherein the maximum brightness value is the brightness value corresponding to the maximum gray level, the light-emitting element turn-off ratio is the ratio of the period in a single frame during which the light-emitting element does not emit light to the length of the single frame, and the initialization time is the time taken for the third transistor to transmit the initialization voltage to the third node.

[0020] In this embodiment, the light-emitting element turn-off ratio can be reduced as the maximum brightness value increases.

[0021] In an embodiment, a single frame may include an address scan period and a self-scan period. The drive controller may be configured to determine a first initialization time or a second initialization time, the first initialization time being the initialization time spent by the third transistor transmitting an initialization voltage to the third node during the address scan period, and the second initialization time being the initialization time spent by the third transistor transmitting an initialization voltage to the third node during the self-scan period.

[0022] In this embodiment, the second initialization time can be reduced as the turn-off ratio of the light-emitting element increases.

[0023] In an embodiment, the drive controller can be configured to set the first initialization time to a constant time during the address scan period, regardless of the light-emitting element turn-off ratio.

[0024] According to an embodiment, the electronic device may include: one or more processors configured to generate a maximum brightness value, the maximum brightness value being a brightness value corresponding to a maximum grayscale level; a display panel including pixel circuitry; a gate driver configured to provide a gate signal to the pixel circuitry; an emitter driver configured to provide a first emitter signal and a second emitter signal to the pixel circuitry; a data driver configured to provide a data voltage to the pixel circuitry; and a drive controller configured to control the gate driver, the emitter driver, and the data driver. The pixel circuitry may include: a light-emitting element; a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a control electrode configured to receive a write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the first node; a third transistor including a control electrode configured to receive a first initialization gate signal, a first electrode connected to the third node, and a second electrode configured to receive an initialization voltage; and a first capacitor including a first electrode connected to the first node and a second electrode connected to the third node. The drive controller can be configured to receive a maximum brightness value to determine the light-emitting element turn-off ratio based on the maximum brightness value, and can be configured to determine the length of an active period within a single frame in which a first initialization gate signal has an active level based on the light-emitting element turn-off ratio, the light-emitting element turn-off ratio being the ratio of the period within a single frame in which the light-emitting element does not emit light to the length of the single frame.

[0025] In an embodiment, a single frame may include an address scan period and a self-scan period. The drive controller may be configured to determine the length of a first activation period or a second activation period, wherein the first activation period is an activation period in the address scan period in which a first initialization gate signal has an activation level, and the second activation period is an activation period in the self-scan period in which the first initialization gate signal has an activation level.

[0026] In this embodiment, the length of the second activation period can be reduced as the turn-off ratio of the light-emitting element increases.

[0027] In an embodiment, the drive controller can be configured to maintain a constant length for the first activation period during the address scan period, regardless of the light-emitting element turn-off ratio.

[0028] The display device can reduce the brightness variation rate during the self-scanning period by allowing the drive controller to determine the light-emitting element turn-off ratio based on the maximum brightness value and, based on the light-emitting element turn-off ratio, determine the length of a second active period in the active period where the first initialization gate signal has an active level. The reduced brightness variation rate during the self-scanning period makes it impossible for the user of the display device to perceive the difference between the brightness during the address scan period and the brightness during the self-scanning period. Accordingly, the display quality of the display device can be improved. Attached Figure Description

[0029] The illustrative, non-limiting embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0030] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0031] Figure 2 The illustration includes Figure 1 A circuit diagram of an embodiment of the pixel circuit of the display panel in a display device.

[0032] Figure 3 It is a diagram. Figure 2 Timing diagram of an embodiment of the operation of the pixel circuit.

[0033] Figure 4 It is a graph showing the relationship between the light-emitting element turn-off ratio and the brightness change rate based on the length of the activation period of the first initialization gate signal.

[0034] Figure 5 This is a table illustrating the rate of change in brightness based on the light-emitting element turn-off ratio and the length of the activation period of the first initialization gate signal.

[0035] Figure 6 It is a graph showing the relationship between the turn-off ratio of the light-emitting element and the rate of change of brightness under various conditions.

[0036] Figure 7 This is a table illustrating the brightness change rate under different conditions based on the turn-off ratio of the light-emitting elements.

[0037] Figure 8 This is a block diagram illustrating an electronic device according to an embodiment.

[0038] Figure 9 It is a diagram. Figure 8 A schematic diagram of the electronic device. Detailed Implementation

[0039] In the following description, the display device according to the embodiment will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same parts in the drawings, and redundant descriptions of the same parts will be omitted.

[0040] Figure 1 This is a block diagram illustrating a display device 1 according to an embodiment.

[0041] refer to Figure 1 The display device 1 may include a display panel 100 and a display panel driver 700. The display panel driver 700 may include a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, a first transmit driver 600a, and a second transmit driver 600b.

[0042] For example, the drive controller 200 and the data driver 500 can be integrated into a single chip. For example, the drive controller 200, the gamma reference voltage generator 400, and the data driver 500 can be integrated into a single chip. A drive module that includes at least the drive controller 200 and the data driver 500 integrated into a single chip can be referred to as a timing controller embedded data driver (TED).

[0043] The display panel 100 may include a display area on which an image is displayed and a peripheral area adjacent to the display area. For example, the peripheral area may be referred to as a border.

[0044] The display panel 100 may include a gate line GL, a first emission line EML1, a second emission line EML2, a data line DL, and a pixel circuit PX. For example, the gate line GL may extend in a first direction D1, the first emission line EML1 may extend in a first direction D1, the second emission line EML2 may extend in a first direction D1, and the data line DL may extend in a second direction D2 that intersects the first direction D1.

[0045] The drive controller 200 can be controlled from an external device (e.g., Figure 8 The processor receives input image data IMG and input control signal CONT. For example, the input image data IMG may include red image data, green image data, and blue image data. In some embodiments, the input image data IMG may further include white image data. In another example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0046] The drive controller 200 can generate gate control signal CONT1, data control signal CONT2, gamma control signal CONT3, first transmission control signal CONT4, second transmission control signal CONT5 and data signal DATA based on the input image data IMG and the input control signal CONT.

[0047] The drive controller 200 can generate a gate control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and can output the gate control signal CONT1 to the gate driver 300. The gate control signal CONT1 may include a vertical start signal and a gate clock signal.

[0048] The drive controller 200 can generate a data control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and can output the data control signal CONT2 to the data driver 500. The data control signal CONT2 may include a horizontal start signal and a load signal.

[0049] The drive controller 200 can generate a data signal DATA based on the input image data IMG. The drive controller 200 can output the data signal DATA to the data driver 500.

[0050] The drive controller 200 can generate a gamma control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and can output the gamma control signal CONT3 to the gamma reference voltage generator 400.

[0051] The drive controller 200 can generate a first transmit control signal CONT4 for controlling the operation of the first transmit driver 600a based on the input control signal CONT, and can output the first transmit control signal CONT4 to the first transmit driver 600a.

[0052] The drive controller 200 can generate a second transmit control signal CONT5 based on the input control signal CONT for controlling the operation of the second transmit driver 600b, and can output the second transmit control signal CONT5 to the second transmit driver 600b.

[0053] Although for ease of explanation, the first transmitter driver 600a and the second transmitter driver 600b are in... Figure 1 The first transmitter driver 600a and the second transmitter driver 600b are disposed on a second side of the display panel 100, different from the first side. For example, the first transmitter driver 600a is disposed on the first side of the display panel 100, and the second transmitter driver 600b is disposed on the second side of the display panel 100. For example, the first transmitter driver 600a and the second transmitter driver 600b can be integrally formed.

[0054] The gate driver 300 can generate a gate signal that is transmitted to the pixel circuit PX via the gate line GL in response to the gate control signal CONT1 received from the drive controller 200. The gate driver 300 can output the gate signal to the gate line GL.

[0055] In one embodiment, the gate driver 300 may be integrated into the peripheral area of ​​the display panel 100. Alternatively, the gate driver 300 may be mounted on the peripheral area of ​​the display panel 100.

[0056] The gamma reference voltage generator 400 can generate a gamma reference voltage VGREF in response to the gamma control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 can output the gamma reference voltage VGREF to the data driver 500.

[0057] In an embodiment, the gamma reference voltage generator 400 may be located in the drive controller 200 or the data driver 500.

[0058] The data driver 500 can receive the data control signal CONT2 and the data signal DATA from the drive controller 200, and can receive the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 can use the gamma reference voltage VGREF to convert the digital data signal DATA into an analog data voltage VDATA. The data driver 500 can then output the data voltage VDATA to the data line DL.

[0059] In one embodiment, the data driver 500 may be integrated into the peripheral area of ​​the display panel 100. Alternatively, the data driver 500 may be mounted on the peripheral area of ​​the display panel 100.

[0060] The first transmit driver 600a can generate a first transmit signal that is transmitted to the pixel circuit PX via the first transmit line EML1 in response to a first transmit control signal CONT4 received from the drive controller 200. The first transmit driver 600a can output the first transmit signal to the first transmit line EML1.

[0061] In one embodiment, the first transmitter driver 600a may be integrated into the peripheral area of ​​the display panel 100. Alternatively, the first transmitter driver 600a may be mounted on the peripheral area of ​​the display panel 100.

[0062] The second transmit driver 600b can generate a second transmit signal that is transmitted to the pixel circuit PX via the second transmit line EML2 in response to the second transmit control signal CONT5 received from the drive controller 200. The second transmit driver 600b can output the second transmit signal to the second transmit line EML2.

[0063] In one embodiment, the second transmitter driver 600b can be integrated into the peripheral area of ​​the display panel 100. Alternatively, the second transmitter driver 600b can be mounted on the peripheral area of ​​the display panel 100.

[0064] In this embodiment, the drive controller 200 can be controlled from an external device (e.g., Figure 8 The processor receives the maximum brightness value DBV corresponding to the maximum grayscale level. For example, the input control signal CONT may include the maximum brightness value DBV. The maximum brightness value DBV may be referred to as the display brightness value.

[0065] The drive controller 200 can determine the light-emitting element off-ratio (or AMOLED off-ratio; AOR). The light-emitting element off-ratio (AOR) is the ratio of the period during which the light-emitting element EE does not emit light within a single frame to the length of the single frame.

[0066] The drive controller 200 can determine the length of an active period within a single frame in which the first initialization gate signal has an active level, based on the light-emitting element off-ratio (AOR). For example, the first active period is an active period in an address scan period in which the first initialization gate signal has an active level, and the second active period is an active period in a self-scan period in which the first initialization gate signal has an active level. The drive controller 200 can determine the length of a second active period that is shorter than the length of the first active period. The operation of the display device 1 will now be described in detail.

[0067] Figure 2 The illustration includes Figure 1 A circuit diagram of an embodiment of the pixel circuit PX of the display panel 100 in the display device 1.

[0068] refer to Figure 2 The pixel circuit PX may include a first transistor T1 to a third transistor T3, a first capacitor C1, and a light-emitting element EE. The pixel circuit PX may further include a fourth transistor T4 to a seventh transistor T7 and a second capacitor C2.

[0069] The first transistor T1 may include a control electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The first transistor T1 can generate a drive current based on the data voltage VDATA. The first transistor T1 may be referred to as a drive transistor.

[0070] The second transistor T2 may include a control electrode for receiving the write gate signal GW, a first electrode for receiving the data voltage VDATA, and a second electrode connected to the first node N1. The second transistor T2 may be referred to as the data write transistor.

[0071] The third transistor T3 may include a control electrode that receives the first initialization gate signal GI, a first electrode connected to the third node N3, and a second electrode that receives the initialization voltage VINT.

[0072] The first capacitor C1 may include a first electrode connected to a first node N1 and a second electrode connected to a third node N3. The first capacitor C1 can store the data voltage VDATA. The first capacitor C1 may be referred to as a storage capacitor.

[0073] The light-emitting element EE may include an anode electrode ANODE and a cathode electrode that receives a second power supply voltage ELVSS. The light-emitting element EE may emit light based on a drive current generated by a first transistor T1.

[0074] The fourth transistor T4 may include a control electrode that receives the second initialization gate signal GR, a first electrode that receives the reference voltage VREF, and a second electrode connected to the first node N1. The fourth transistor T4 may be referred to as the first initialization transistor.

[0075] The fifth transistor T5 may include a control electrode that receives the first transmit signal EM1, a first electrode that receives the first power supply voltage ELVDD, and a second electrode connected to the second node N2. The fifth transistor T5 may be referred to as the first emitter transistor.

[0076] The sixth transistor T6 may include a control electrode that receives the first initialization gate signal GI, a first electrode that receives the anode initialization voltage VAINT, and a second electrode that is connected to the anode electrode ANODE of the light-emitting element EE. The sixth transistor T6 may be referred to as the anode initialization transistor.

[0077] The seventh transistor T7 may include a control electrode for receiving the second emission signal EM2, a first electrode connected to the third node N3, and a second electrode connected to the anode electrode ANODE of the light-emitting element EE. The seventh transistor T7 may be referred to as the second emission transistor.

[0078] The second capacitor C2 may include a first electrode that receives the reference voltage VREF and a second electrode connected to the third node N3.

[0079] The first transistor T1 may further include a second control electrode connected to the third node N3.

[0080] The voltage at the third node N3 is applied to the second control electrode of the first transistor T1, thereby preventing stress-induced shifts in the threshold voltage of the first transistor T1. Consequently, the stability and reliability of the pixel circuit PX can be improved.

[0081] In the embodiments, the first transistor T1 to the seventh transistor T7 can be implemented as N-type transistors, but the first transistor T1 to the seventh transistor T7 are not limited to this.

[0082] Figure 3 It is a diagram. Figure 2 Timing diagram of an embodiment of the operation of the pixel circuit PX.

[0083] refer to Figure 3 The display device 1 can be operated in a variable refresh rate (VRR) mode where the driving frequency changes depending on the characteristics of the image or the source of the image (e.g., the application that generated the image data).

[0084] The number of self-scanning periods (SS) included in a single frame FP can vary depending on the drive frequency. For example, when the drive frequency is approximately 250 Hz (the maximum drive frequency), a single frame FP may include only one address scan period (AS). For example, when the drive frequency is approximately 120 Hz, a single frame FP may include one address scan period (AS) and one self-scanning period (SS). For example, when the drive frequency is approximately 80 Hz, a single frame FP may include one address scan period (AS) and two self-scanning periods (SS). Let's assume a single frame FP includes one address scan period (AS) and one self-scanning period (SS).

[0085] During the address scan period AS, the write gate signal GW can have an active level (e.g., a high level). The second transistor T2 can transfer the data voltage VDATA to the first transistor T1 in response to the active write gate signal GW. That is, the data voltage VDATA can be written to the pixel circuit PX. The first transistor T1 can generate a drive current based on the data voltage VDATA. The light-emitting element EE can emit light based on the drive current generated by the first transistor T1.

[0086] Self-scanning period (SS) can be the next period after address scan period (AS).

[0087] During the self-scan period SS, the write gate signal GW can remain at a deactivated level (e.g., low). The second transistor T2 can be turned off. That is, the data voltage VDATA can be not written to the first transistor T1. The first transistor T1 can generate a drive current based on the data voltage VDATA written to it during the address scan period AS. In other words, the drive current generated by the first transistor T1 during the self-scan period SS can be the same as the drive current generated by the first transistor T1 during the address scan period AS. The light-emitting element EE can emit light based on the drive current generated by the first transistor T1.

[0088] The drive controller 200 can determine the light-emitting element turn-off ratio (AOR) based on the maximum luminance value DBV. As the maximum luminance value DBV increases, the drive controller 200 can decrease the light-emitting element turn-off ratio (AOR).

[0089] In the address scan period AS, the period during which the light-emitting element EE does not emit light can be the first non-emission period P1, and the period during which the light-emitting element EE emits light can be the first emission period P2.

[0090] In the self-scanning period SS, the period during which the light-emitting element EE does not emit light can be the second non-emission period P3, and the period during which the light-emitting element EE emits light can be the second emission period P4.

[0091] The first activation period AP1 is the period during which the first initialization gate signal GI has an active level in the address scan period AS. Additionally, the second activation period AP2 is the period during which the first initialization gate signal GI has an active level in the self-scan period SS.

[0092] The drive controller 200 can determine the length of the first activation period AP1 and / or the length of the second activation period AP2 based on the light-emitting element off ratio (AOR).

[0093] In this embodiment, the drive controller 200 can determine the length of the first activation period AP1 to be a constant length regardless of the light-emitting element turn-off ratio (AOR). Alternatively, the drive controller 200 can determine the length of the second activation period AP2 to be shorter than the length of the first activation period AP1 based on the light-emitting element turn-off ratio (AOR).

[0094] The length of the first non-emission period P1 can be the same as the length of the second non-emission period P3. Similarly, the length of the first emission period P2 can be the same as the length of the second emission period P4. The light-emitting element off-time ratio (AOR) can be calculated using the equation "AOR=(P1 / (P1+P2))*100", where "AOR" represents the light-emitting element off-time ratio (AOR), "P1" represents the length of the first non-emission period P1, and "P2" represents the length of the first emission period P2. In other words, the light-emitting element off-time ratio (AOR) is the length of the first non-emission period P1 in which the light-emitting element EE is not emitting light, relative to the length of the address scan period AS.

[0095] During the first non-transmission period P1, the second initialization gate signal GR may have an active level (e.g., high level). The first initialization gate signal GI may have an active level (e.g., high level). The first transmit signal EM1 may have a deactivation level (e.g., low level). The second transmit signal EM2 may have a deactivation level (e.g., low level). Additionally, the write gate signal GW may have a deactivation level (e.g., low level).

[0096] The second transistor T2 can be turned off in response to a write gate signal GW with a deactivation level. The third transistor T3 can be turned on in response to a first initialization gate signal GI with an activation level. The fourth transistor T4 can be turned on in response to a second initialization gate signal GR with an activation level. The fifth transistor T5 can be turned off in response to a first emit signal EM1 with a deactivation level. The sixth transistor T6 can be turned on in response to a first initialization gate signal GI with an activation level. The seventh transistor T7 can be turned off in response to a second emit signal EM2 with a deactivation level.

[0097] The fourth transistor T4, when turned on, can transfer the reference voltage VREF to the first node N1. The first node N1 can be initialized with the reference voltage VREF.

[0098] The activated third transistor T3 can transmit the initialization voltage VINT to the third node N3.

[0099] During the first non-emission period P1, the time taken for the third transistor T3 to transmit the initialization voltage VINT to the third node N3 is the first initialization time IT1. The third transistor T3 transmits the initialization voltage VINT to the third node N3 in response to the first initialization gate signal GI with an active level, such that the first initialization time IT1 can be the same length as the first active period AP1.

[0100] The first initialization time IT1 can be sufficient time for the third transistor T3 to transmit the initialization voltage VINT to the third node N3. Accordingly, at the end of the first activation period AP1, the third node N3 can be initialized to the initialization voltage VINT.

[0101] The sixth transistor T6, when turned on, can transfer the anode initialization voltage VAINT to the anode electrode ANODE of the light-emitting element EE. The anode electrode ANODE of the light-emitting element EE can be initialized to the anode initialization voltage VAINT.

[0102] During the first non-transmit period P1, the second initialization gate signal GR can change from an active level to a deactivated level (e.g., low level). The first initialization gate signal GI can be active. The first transmit signal EM1 can be active (e.g., high level), and the second transmit signal EM2 can be deactivated. Additionally, the write gate signal GW can be deactivated.

[0103] The second transistor T2 can be turned off in response to a write gate signal GW with a deactivation level. The third transistor T3 can be turned on in response to a first initialization gate signal GI with an activation level. The fourth transistor T4 can be turned off in response to a second initialization gate signal GR with a deactivation level. The fifth transistor T5 can be turned on in response to a first emit signal EM1 with an activation level. The sixth transistor T6 can be turned on in response to a first initialization gate signal GI with an activation level. The seventh transistor T7 can be turned off in response to a second emit signal EM2 with a deactivation level.

[0104] The fifth transistor T5, once turned on, can transmit the first power supply voltage ELVDD to the second node N2.

[0105] Furthermore, the voltage difference between the first node N1 and the third node N3 can be greater than the threshold voltage of the first transistor T1. Accordingly, the first transistor T1 can be turned on. The turned-on first transistor T1 can transfer the voltage of the second node N2 to the third node N3. When the voltage difference between the first node N1 and the third node N3 is equal to the threshold voltage of the first transistor T1, the first transistor T1 can be turned off. This can compensate for the threshold voltage of the first transistor T1.

[0106] Additionally, the sixth transistor T6, when turned on, can transfer the anode initialization voltage VAINT to the anode electrode ANODE of the light-emitting element EE. The anode electrode ANODE of the light-emitting element EE can be initialized to the anode initialization voltage VAINT.

[0107] During the first non-transmit period P1, the write gate signal GW can change from a deactivated level to an active level (e.g., a high level). The first initialization gate signal GI can have an active level. The second initialization gate signal GR can have a deactivated level. The first transmit signal EM1 can have a deactivated level, and the second transmit signal EM2 can have a deactivated level.

[0108] The second transistor T2 can be turned on in response to a write gate signal GW with an activation level. The third transistor T3 can be turned on in response to a first initialization gate signal GI with an activation level. The fourth transistor T4 can be turned off in response to a second initialization gate signal GR with a deactivation level. The fifth transistor T5 can be turned off in response to a first emit signal EM1 with a deactivation level. The sixth transistor T6 can be turned on in response to a first initialization gate signal GI with an activation level. The seventh transistor T7 can be turned off in response to a second emit signal EM2 with a deactivation level.

[0109] The second transistor T2, when turned on, can transmit the data voltage VDATA to the first node N1. That is, the data voltage VDATA is written to the pixel circuit PX. The first capacitor C1 can store the difference between the voltage of the first node N1 and the voltage of the third node N3. In other words, the first capacitor C1 can store the difference between the data voltage VDATA and the initialization voltage VINT.

[0110] The sixth transistor T6, when turned on, can transfer the anode initialization voltage VAINT to the anode electrode ANODE of the light-emitting element EE. The anode electrode ANODE of the light-emitting element EE can be initialized to the anode initialization voltage VAINT.

[0111] During the first transmission period P2, the first transmission signal EM1 may have an active level. The second transmission signal EM2 may have an active level (e.g., high level). The first initialization gate signal GI may have a deactivation level (e.g., low level). The second initialization gate signal GR may have a deactivation level. Additionally, the write gate signal GW may have a deactivation level.

[0112] The second transistor T2 can be turned off in response to a write gate signal GW with a deactivation level. The third transistor T3 can be turned off in response to a first initialization gate signal GI with a deactivation level. The fourth transistor T4 can be turned off in response to a second initialization gate signal GR with a deactivation level. The fifth transistor T5 can be turned on in response to a first emit signal EM1 with an activation level. The sixth transistor T6 can be turned off in response to a first initialization gate signal GI with a deactivation level. The seventh transistor T7 can be turned on in response to a second emit signal EM2 with an activation level.

[0113] The fifth transistor T5, once turned on, can transmit the first power supply voltage ELVDD to the second node N2.

[0114] The difference between the voltage of the first node N1 and the voltage of the third node N3 can be greater than the threshold voltage of the first transistor T1. Accordingly, the first transistor T1 can be turned on. The turned-on first transistor T1 can generate a drive current corresponding to the data voltage VDATA.

[0115] The drive current can flow to the light-emitting element EE through the turned-on seventh transistor T7. Accordingly, the light-emitting element EE can emit light with a brightness corresponding to the data voltage VDATA.

[0116] During the second non-transmission period P3, the first transmit signal EM1 may have a deactivation level. The second transmit signal EM2 may have an activation level. The first initialization gate signal GI may have an activation level. The second initialization gate signal GR may have a deactivation level. The write gate signal GW may have a deactivation level.

[0117] The second transistor T2 can be turned off in response to a write gate signal GW with a deactivation level. The third transistor T3 can be turned on in response to a first initialization gate signal GI with an activation level. The fourth transistor T4 can be turned off in response to a second initialization gate signal GR with a deactivation level. The fifth transistor T5 can be turned off in response to a first emit signal EM1 with a deactivation level. The sixth transistor T6 can be turned on in response to a first initialization gate signal GI with an activation level. The seventh transistor T7 can be turned on in response to a second emit signal EM2 with an activation level.

[0118] During the second non-emission period P3, the length of the second active period AP2 can be shorter than the length of the first active period AP1.

[0119] The activated third transistor T3 can transmit the initialization voltage VINT to the third node N3.

[0120] During the second non-emission period P3, the time taken for the third transistor T3 to transmit the initialization voltage VINT to the third node N3 is the second initialization time IT2. The third transistor T3 transmits the initialization voltage VINT to the third node N3 in response to the first initialization gate signal GI with an active level, such that the second initialization time IT2 can be the same length as the second active period AP2.

[0121] The second activation period AP2 is shorter than the first activation period AP1, allowing the second initialization time IT2 to be shorter than the first initialization time IT1. Consequently, during the second initialization time IT2, the initialization voltage VINT may not be fully transmitted. Accordingly, at the end of the second activation period AP2, the third node N3 can be initialized to a voltage higher than the initialization voltage VINT.

[0122] The first capacitor C1 can store the difference between the voltage of the first node N1 and the voltage of the third node N3. For example, the first capacitor C1 can store the difference between the data voltage VDATA and the voltage of the third node N3.

[0123] The sixth transistor T6, when turned on, can transfer the anode initialization voltage VAINT to the anode electrode ANODE of the light-emitting element EE. The anode electrode ANODE of the light-emitting element EE can be initialized to the anode initialization voltage VAINT.

[0124] During the second transmission period P4, the first transmission signal EM1 can have an active level. The second transmission signal EM2 can have an active level. The first initialization gate signal GI can have a deactivation level. The second initialization gate signal GR can have a deactivation level. The write gate signal GW can have a deactivation level.

[0125] The second transistor T2 can be turned off in response to a write gate signal GW with a deactivation level. The third transistor T3 can be turned off in response to a first initialization gate signal GI with a deactivation level. The fourth transistor T4 can be turned off in response to a second initialization gate signal GR with a deactivation level. The fifth transistor T5 can be turned on in response to a first emit signal EM1 with an activation level. The sixth transistor T6 can be turned off in response to a first initialization gate signal GI with a deactivation level. The seventh transistor T7 can be turned on in response to a second emit signal EM2 with an activation level.

[0126] The fifth transistor T5, once turned on, can transmit the first power supply voltage ELVDD to the second node N2.

[0127] The difference between the voltage of the first node N1 and the voltage of the third node N3 can be greater than the threshold voltage of the first transistor T1. Accordingly, the first transistor T1 can be turned on. The turned-on first transistor T1 can generate a drive current corresponding to the data voltage VDATA.

[0128] The drive current can flow to the light-emitting element EE through the seventh transistor T7. Accordingly, the light-emitting element EE can emit light with a brightness corresponding to the data voltage VDATA.

[0129] In this embodiment, when the level of the first initialization gate signal GI changes from an active level to a deactivated level during the address scan period AS, the first node N1 can have a data voltage VDATA. The voltage of the third node N3 is the first source voltage. The difference between the voltage of the first node N1 and the voltage of the third node N3 is the first differential voltage. That is, the drive current generated by the first transistor T1 based on the first differential voltage is the first drive current.

[0130] During the self-scanning period SS, the voltage of the first node N1 may be altered due to leakage current, etc. The altered voltage of the first node N1 is the lost data voltage.

[0131] When the level of the first initialization gate signal GI changes from an active level to a deactivated level during the self-scan period SS, the first node N1 may have a lost data voltage. When the first node N1 has a lost data voltage, the voltage of the third node N3 is the second source voltage. During the self-scan period SS, the difference between the voltage of the first node N1 and the voltage of the third node N3 is the second differential voltage. The drive current generated by the first transistor T1 based on the second differential voltage is the second drive current.

[0132] When the length of the first activation period AP1 is the same as the length of the second activation period AP2, the second source voltage can have a first level and the second differential voltage can have a first amplitude.

[0133] When the length of the second activation period AP2 is shorter than the length of the first activation period AP1, the second source voltage can have a second level and the second differential voltage can have a second amplitude.

[0134] The second amplitude can be greater than the first amplitude. Correspondingly, the difference between the first differential voltage and the second differential voltage with the second amplitude can be less than the difference between the first differential voltage and the second differential voltage with the first amplitude. In other words, the second differential voltage with the second amplitude can be closer to the first differential voltage than the second differential voltage with the first amplitude.

[0135] Accordingly, the second differential voltage with a second amplitude is closer to the first differential voltage, allowing the second driving current to be closer to the first driving current. This closer proximity of the second driving current to the first driving current allows the brightness of the address scan period AS to be similar to the brightness of the self-scan period SS. In other words, the rate of change in brightness can be reduced. This reduced rate of change in brightness makes it possible for the user of the display device 1 to not perceive the difference between the brightness of the address scan period AS and the brightness of the self-scan period SS. Consequently, flickering may not occur.

[0136] Furthermore, when the length of the second activation period AP2 decreases, the second initialization time IT2 during which the initialization voltage VINT is applied to the pixel circuit PX can be reduced. This reduction in the second initialization time IT2 allows for a decrease in the power consumption of the display device 1.

[0137] Figure 4 This is a graph illustrating the relationship between the light-emitting element off-ratio (AOR) and the rate of change of brightness (LC) based on the length of the activation period TP of the first initialization gate signal GI. Figure 5This is a table illustrating the rate of change of brightness (LC) based on the light-emitting element off-ratio (AOR) and the length of the activation period TP of the first initialization gate signal GI.

[0138] refer to Figure 4 and Figure 5 The rate of change of brightness (LC) can vary depending on the length of the second activation period AP2 and the light-emitting element off-ratio (AOR). That is, the length of the second activation period AP2 with the minimum rate of change of brightness (%) can vary depending on the light-emitting element off-ratio (AOR).

[0139] The drive controller 200 can determine the length of the first activation period AP1 to be a constant length regardless of the light-emitting element turn-off ratio (AOR), or it can determine the first initialization time IT1 to be a constant time regardless of the light-emitting element turn-off ratio (AOR). That is, the length of the first activation period AP1 can vary regardless of the light-emitting element turn-off ratio (AOR). For example, when the light-emitting element turn-off ratio (AOR) is approximately 12.5%, the length of the first activation period AP1 can be approximately 46H. When the light-emitting element turn-off ratio (AOR) is approximately 40%, the length of the first activation period AP1 can be approximately 46H. Furthermore, when the light-emitting element turn-off ratio (AOR) is approximately 70%, the length of the first activation period AP1 can be approximately 46H.

[0140] The drive controller 200 can determine the length of the second activation period AP2 based on the light-emitting element off-ratio (AOR). For example, as the maximum luminance value DBV increases, the drive controller 200 can decrease the light-emitting element off-ratio (AOR). Alternatively, as the light-emitting element off-ratio (AOR) decreases, the drive controller 200 can increase the length of the second activation period AP2.

[0141] During the second non-emission period P3 of the self-scanning period SS, the gate driver 300 can output a first initialization gate signal GI having a length of the second activation period AP2 determined by the drive controller 200.

[0142] In this embodiment, it is assumed that the length of the first activation period AP1 is approximately 46H and the light-emitting element off-ratio (AOR) is approximately 12.5%.

[0143] When the length of the second activation period AP2 is approximately 46 hours, the luminance change rate (LC) can be approximately 5.7%. When the length of the second activation period AP2 is approximately 22 hours, the luminance change rate (LC) can be approximately 0.1%. When the length of the second activation period AP2 is approximately 14 hours, the luminance change rate (LC) can be approximately 1.4%. When the length of the second activation period AP2 is approximately 10 hours, the luminance change rate (LC) can be approximately 3.9%.

[0144] In other words, the rate of change of luminance (LC) can be minimized when the length of the second activation period AP2 is approximately 22H. Accordingly, when the light-emitting element off ratio (AOR) is approximately 12.5%, the drive controller 200 can determine the length of the second activation period AP2 to be approximately 22H. During the second non-emission period P3 of the self-scanning period SS, the gate driver 300 can output a first initialization gate signal GI having a length of the second activation period AP2 of approximately 22H.

[0145] In this embodiment, it is assumed that the length of the first activation period AP1 is approximately 46H and the light-emitting element off-ratio (AOR) is approximately 25.8%.

[0146] When the length of the second activation period AP2 is approximately 46 hours, the luminance change rate (LC) can be approximately 6.2%. When the length of the second activation period AP2 is approximately 22 hours, the luminance change rate (LC) can be approximately 1.4%. When the length of the second activation period AP2 is approximately 14 hours, the luminance change rate (LC) can be approximately 0.5%. When the length of the second activation period AP2 is approximately 10 hours, the luminance change rate (LC) can be approximately 2.1%.

[0147] In other words, the rate of change of luminance (LC) can be minimized when the length of the second activation period AP2 is approximately 14H. Accordingly, when the light-emitting element off ratio (AOR) is approximately 25.8%, the drive controller 200 can determine the length of the second activation period AP2 to be approximately 14H. During the second non-emission period P3 of the self-scanning period SS, the gate driver 300 can output a first initialization gate signal GI having a length of the second activation period AP2 of approximately 14H.

[0148] In this embodiment, it is assumed that the length of the first activation period AP1 is approximately 46H and the light-emitting element off-ratio (AOR) is approximately 40%.

[0149] When the length of the second activation period AP2 is approximately 46 hours, the luminance change rate (LC) can be approximately 6.4%. When the length of the second activation period AP2 is approximately 22 hours, the luminance change rate (LC) can be approximately 2.0%. When the length of the second activation period AP2 is approximately 14 hours, the luminance change rate (LC) can be approximately 1.2%. When the length of the second activation period AP2 is approximately 10 hours, the luminance change rate (LC) can be approximately 1.4%.

[0150] In other words, the rate of change of luminance (LC) can be minimized when the length of the second activation period AP2 is approximately 14H. Accordingly, when the light-emitting element off ratio (AOR) is approximately 40%, the drive controller 200 can determine the length of the second activation period AP2 to be approximately 14H. During the second non-emission period P3 of the self-scanning period SS, the gate driver 300 can output a first initialization gate signal GI having a length of the second activation period AP2 of approximately 14H.

[0151] In this embodiment, it is assumed that the length of the first activation period AP1 is approximately 46H and the light-emitting element off-ratio (AOR) is approximately 53.3%.

[0152] When the length of the second activation period AP2 is approximately 46 hours, the luminance change rate (LC) can be approximately 6.2%. When the length of the second activation period AP2 is approximately 22 hours, the luminance change rate (LC) can be approximately 2.6%. When the length of the second activation period AP2 is approximately 14 hours, the luminance change rate (LC) can be approximately 1.8%. When the length of the second activation period AP2 is approximately 10 hours, the luminance change rate (LC) can be approximately 0.8%.

[0153] In other words, the rate of change of brightness (LC) can be minimized when the length of the second activation period AP2 is approximately 10H. Accordingly, when the light-emitting element off ratio (AOR) is approximately 53.3%, the drive controller 200 can determine the length of the second activation period AP2 to be approximately 10H. During the second non-emission period P3 of the self-scanning period SS, the gate driver 300 can output a first initialization gate signal GI having a length of the second activation period AP2 of approximately 10H.

[0154] In this embodiment, it is assumed that the length of the first activation period AP1 is approximately 46H and the light-emitting element off-ratio (AOR) is approximately 70%.

[0155] When the length of the second activation period AP2 is approximately 46 hours, the luminance change rate (LC) can be approximately 4.3%. When the length of the second activation period AP2 is approximately 22 hours, the luminance change rate (LC) can be approximately 4.4%. When the length of the second activation period AP2 is approximately 14 hours, the luminance change rate (LC) can be approximately 1.9%. When the length of the second activation period AP2 is approximately 10 hours, the luminance change rate (LC) can be approximately 0.2%.

[0156] In other words, the rate of change of brightness (LC) can be minimized when the length of the second activation period AP2 is approximately 10H. Accordingly, when the light-emitting element off ratio (AOR) is approximately 70%, the drive controller 200 can determine the length of the second activation period AP2 to be approximately 10H. During the second non-emission period P3 of the self-scanning period SS, the gate driver 300 can output a first initialization gate signal GI having a length of the second activation period AP2 of approximately 10H.

[0157] As described above, the length of the second activation period AP2, which has the minimum rate of change of brightness (LC), can vary depending on the light-emitting element off-ratio (AOR). Accordingly, the drive controller 200 determines the length of the second activation period AP2 based on the light-emitting element off-ratio (AOR), thereby reducing the rate of change of brightness (LC). A reduced rate of change of brightness (LC) allows the light-emitting element EE to emit light accurately at the target brightness. Consequently, the display quality of the display device 1 can be improved.

[0158] Furthermore, as the light-emitting element off-ratio (AOR) increases, the length of the second activation period AP2 can be reduced. When the length of the second activation period AP2 decreases, the second initialization time IT2 during which the initialization voltage VINT is applied to the pixel circuit PX can be reduced. Reducing the second initialization time IT2 allows for lower power consumption of the display device 1.

[0159] Figure 6 It is a graph showing the relationship between the light-emitting element off-ratio (AOR) and the rate of change of brightness (LC) under various conditions. Figure 7 This is a table illustrating the light-emitting element off-ratio (AOR) and the rate of change of brightness (LC) for each case.

[0160] refer to Figure 6 and Figure 7 The rate of change of brightness (LC) can vary depending on the case and the light-emitting element off ratio (AOR).

[0161] In the embodiment, under the first case (Case 1), regardless of the light-emitting element off-ratio (AOR), the length of the first activation period AP1 can be approximately 46H and the length of the second activation period AP2 can be approximately 46H. That is, the length of the first activation period AP1 can be the same as the length of the second activation period AP2.

[0162] When the aperture offset ratio (AOR) is approximately 12.5%, the luminance change rate (LC) can be approximately 5.7%. When the aperture offset ratio (AOR) is approximately 25.8%, the luminance change rate (LC) can be approximately 6.2%. When the aperture offset ratio (AOR) is approximately 40%, the luminance change rate (LC) can be approximately 6.4%. When the aperture offset ratio (AOR) is approximately 53.3%, the luminance change rate (LC) can be approximately 6.2%. When the aperture offset ratio (AOR) is approximately 70%, the luminance change rate (LC) can be approximately 4.3%.

[0163] In the second case, Case 2, regardless of the light-emitting element off-ratio (AOR), the length of the first activation period AP1 can be approximately 46H and the length of the second activation period AP2 can be approximately 22H. That is, the length of the second activation period AP2 can be shorter than the length of the first activation period AP1.

[0164] When the light-emitting element off-ratio (AOR) is approximately 12.5%, the luminance change rate (LC) can be approximately 0.1%. When the light-emitting element off-ratio (AOR) is approximately 25.8%, the luminance change rate (LC) can be approximately 1.4%. When the light-emitting element off-ratio (AOR) is approximately 40%, the luminance change rate (LC) can be approximately 2.0%. When the light-emitting element off-ratio (AOR) is approximately 53.3%, the luminance change rate (LC) can be approximately 2.6%. When the light-emitting element off-ratio (AOR) is approximately 70%, the luminance change rate (LC) can be approximately 4.4%.

[0165] In the third case (Case 3), regardless of the light-emitting element turn-off ratio (AOR), the length of the first activation period AP1 can be approximately 46H. The length of the second activation period AP2 can vary depending on the light-emitting element turn-off ratio (AOR). That is, the drive controller 200 can determine the length of the second activation period AP2 based on the light-emitting element turn-off ratio (AOR). Furthermore, the length of the second activation period AP2 can be shorter than the length of the first activation period AP1.

[0166] When the light-emitting element off-ratio (AOR) is approximately 12.5%, the length of the second activation period AP2 can be approximately 22 hours and the luminance change rate (LC) can be approximately 0.1%. When the light-emitting element off-ratio (AOR) is approximately 25.8%, the length of the second activation period AP2 can be approximately 14 hours and the luminance change rate (LC) can be approximately 0.5%. When the light-emitting element off-ratio (AOR) is approximately 40%, the length of the second activation period AP2 can be approximately 14 hours and the luminance change rate (LC) can be approximately 1.2%. When the light-emitting element off-ratio (AOR) is approximately 53.3%, the length of the second activation period AP2 can be approximately 10 hours and the luminance change rate (LC) can be approximately 0.8%. When the light-emitting element off-ratio (AOR) is approximately 70%, the length of the second activation period AP2 can be approximately 10 hours and the luminance change rate (LC) can be approximately 0.2%.

[0167] In the second case, Case 2, the rate of change of luminance (LC) based on the light-emitting element off-ratio (AOR) can be less than that in the first case, Case 1.

[0168] In addition, the rate of change of brightness (LC) based on the light-emitting element off-ratio (AOR) in the third case (Case 3) can be less than the rate of change of brightness (LC) based on the light-emitting element off-ratio (AOR) in the second case (Case 2).

[0169] Accordingly, the luminance change rate (LC) based on the light-emitting element off-ratio (AOR) can be minimized in the third case, Case 3. That is, the luminance change rate (LC) can be minimized when the drive controller 200 determines the length of the second activation period AP2 based on the light-emitting element off-ratio (AOR).

[0170] As described above, when the drive controller 200 determines the length of the second activation period AP2 based on the light-emitting element off-ratio (AOR), the luminance variation rate (LC) can be minimized. A reduced luminance variation rate (LC) allows the light-emitting element EE to emit light accurately at the target luminance. Consequently, the display quality of the display device 1 can be improved.

[0171] Furthermore, as the light-emitting element off-ratio (AOR) increases, the length of the second activation period AP2 can be reduced. When the length of the second activation period AP2 decreases, the second initialization time IT2 during which the initialization voltage VINT is applied to the pixel circuit PX can be reduced. Reducing the second initialization time IT2 allows for lower power consumption of the display device 1.

[0172] Figure 8 This is a block diagram illustrating an electronic device 10 according to an embodiment. Figure 9It is a diagram. Figure 8 A schematic diagram of the electronic device 10.

[0173] refer to Figure 8 The electronic device 10 may include a display module 11, a processor 12, a memory device 13, and a power module 14.

[0174] The display device 1 can be applied to various electronic devices. In an embodiment, the electronic device 10 may include... Figure 1 The display device 1. In an embodiment, the operation of the display device 1 included in the electronic device 10 can be related to the reference. Figures 1 to 7 The operation of the described display device 1 is the same. In embodiments, in addition to the display device 1, the electronic device 10 may further include modules or devices with other additional functions.

[0175] Processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. Processor 12 may include one or more processors.

[0176] In this embodiment, the processor 12 can Figure 1 The input control signal CONT and Figure 1 The input image data provided by IMG is included in Figure 1 The display device 1 includes a drive controller 200. Additionally, the processor 12 can provide the drive controller 200 with a maximum brightness value DBV, which is the brightness value corresponding to the maximum grayscale level. For example, the input control signal CONT may include the maximum brightness value DBV.

[0177] In embodiments, the processor 12 may be provided in two or more forms in terms of function or structure. For example, the processor 12 may include a main processor in the form of a first driver chip and an auxiliary processor in the form of a second driver chip, the first driver chip including a central processing unit, and the second driver chip including a controller that receives image signals from the main processor and processes the image signals to conform to the interface specifications of the display module 11. The auxiliary processor may include components included in... Figure 1 The drive controller 200 in the display device 1. Accordingly, the main processor can... Figure 1 The input control signal CONT and Figure 1 The main processor provides the input image data (IMG) to the auxiliary processor. Additionally, the main processor can provide the auxiliary processor with a maximum brightness value (DBV), which is the brightness value corresponding to the maximum grayscale level. For example, the input control signal (CONT) may include the maximum brightness value (DBV). The auxiliary processor can process the image signal based on the maximum brightness value (DBV), the input control signal (CONT), and the input image data (IMG).

[0178] The memory device 13 may include at least one of a non-volatile memory device and a volatile memory device. Data information for the operation of the display module 11 or the processor 12 may be stored in the memory device 13. When the processor 12 executes an application stored in the memory device 13, input control signals CONT and / or input image data IMG may be transmitted to the display module 11. The display module 11 may process the input control signals CONT and / or input image data IMG provided from the processor 12, and may output image information through the display panel.

[0179] The power module 14 may include a power supply module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module and generates the power required for the operation of the electronic device 10.

[0180] At least one of the components of electronic device 10 may be included in display device 1. Additionally, some modules that are functionally included in a single module may be included in display device 1, and other modules may be provided separately from display device 1. For example, display device 1 may include display module 11, and processor 12, memory device 13, and power module 14 may be provided as other devices in electronic device 10 besides the display device.

[0181] refer to Figure 9 Various electronic devices having a display device 1 may include image display electronic devices such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e. Additionally, various electronic devices may include wearable electronic devices including display modules, such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c. Furthermore, various electronic devices may include vehicle electronic devices 10_3 including display modules, such as dashboards, central dashboards, central information displays (CID) on instrument panels, and rearview mirror displays. Electronic device 10 is not limited to image display electronic devices, wearable electronic devices, and vehicle electronic devices 10_3.

[0182] The present invention can be applied to display devices and electronic devices including display devices. For example, the present invention can be applied to televisions (TV), digital TVs, 3D TVs, mobile phones, smartphones, tablet computers, laptop computers, personal computers (PCs), home electronic devices, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0183] The foregoing is illustrative of the inventive concept and should not be construed as limiting it. Although some embodiments of the inventive concept have been described, those skilled in the art will readily understand that many modifications can be made to the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the device plus function clause is intended to cover structures described herein as performing the described functions, and not only structural equivalents but also equivalent structures. Therefore, it should be understood that the foregoing is illustrative of the inventive concept and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the claims. The inventive concept is defined by the claims, and equivalents of the claims should be included in the claims.

Claims

1. A display device, comprising: Display panel, including pixel circuitry; A gate driver is configured to provide a gate signal to the pixel circuitry; A transmitter driver is configured to provide a first transmit signal and a second transmit signal to the pixel circuit; A data driver is configured to provide a data voltage to the pixel circuitry; as well as The drive controller is configured to control the gate driver, the transmit driver, and the data driver. The pixel circuit includes: Light-emitting elements; The first transistor includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; The second transistor includes a control electrode configured to receive a write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to the first node; The third transistor includes a control electrode configured to receive a first initialization gate signal, a first electrode connected to the third node, and a second electrode configured to receive an initialization voltage; and The first capacitor includes a first electrode connected to the first node and a second electrode connected to the third node, and The drive controller is configured to determine the light-emitting element turn-off ratio based on the maximum brightness value, and is configured to determine the length of the active period in a single frame in which the first initialization gate signal has an active level based on the light-emitting element turn-off ratio, wherein the maximum brightness value is a brightness value corresponding to the maximum gray level, and the light-emitting element turn-off ratio is the ratio of the period in a single frame in which the light-emitting element does not emit light to the length of the single frame.

2. The display device according to claim 1, wherein, As the maximum brightness value increases, the off-ratio of the light-emitting element decreases.

3. The display device according to claim 1, wherein, The single frame includes an address scan period and a self-scan period, and The drive controller is configured to determine the length of a first activation period or a second activation period, wherein the first activation period is the activation period in the address scan period in which the first initialization gate signal has the activation level, and the second activation period is the activation period in the self-scan period in which the first initialization gate signal has the activation level.

4. The display device according to claim 3, wherein, As the turn-off ratio of the light-emitting element increases, the length of the second activation period decreases.

5. The display device according to claim 4, wherein, The drive controller is configured to maintain a constant length for the first activation period during the address scan period, regardless of the light-emitting element off ratio.

6. The display device according to claim 3, wherein, During the address scan period, the write gate signal has an activation level, the data voltage is written to the pixel circuit, and the light-emitting element is configured to emit light based on the data voltage. During the self-scanning period, the write gate signal remains at a deactivated level, and the light-emitting element is configured to emit light based on the data voltage written to the pixel circuit during the address scan period.

7. The display device according to claim 1, wherein, The pixel circuit further includes a fourth transistor, the fourth transistor including a control electrode configured to receive a second initialization gate signal, a first electrode configured to receive a reference voltage, and a second electrode connected to the first node.

8. The display device according to claim 7, wherein, The pixel circuit further includes a fifth transistor, the fifth transistor including a control electrode configured to receive the first transmission signal, a first electrode configured to receive a first power supply voltage, and a second electrode connected to the second node.

9. The display device according to claim 8, wherein, The pixel circuit further includes a sixth transistor, the sixth transistor including a control electrode configured to receive the first initialization gate signal, a first electrode configured to receive an anode initialization voltage, and a second electrode connected to the anode electrode of the light-emitting element.

10. The display device according to claim 9, wherein, The pixel circuit further includes a seventh transistor, which includes a control electrode configured to receive the second emission signal, a first electrode connected to the third node, and a second electrode connected to the anode electrode of the light-emitting element.

11. The display device according to claim 10, wherein, The pixel circuit further includes a second capacitor, the second capacitor including a first electrode configured to receive the reference voltage and a second electrode connected to the third node.

12. A display device, comprising: Display panel, including pixel circuitry; A gate driver is configured to provide a gate signal to the pixel circuitry; A transmitter driver is configured to provide a first transmit signal and a second transmit signal to the pixel circuit; A data driver is configured to provide a data voltage to the pixel circuitry; as well as The drive controller is configured to control the gate driver, the transmit driver, and the data driver. The pixel circuit includes: Light-emitting elements; The first transistor includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; The second transistor includes a control electrode configured to receive a write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to the first node; The third transistor includes a control electrode configured to receive a first initialization gate signal, a first electrode connected to the third node, and a second electrode configured to receive an initialization voltage; and The first capacitor includes a first electrode connected to the first node and a second electrode connected to the third node, and The drive controller is configured to determine the light-emitting element turn-off ratio based on the maximum brightness value and to determine the initialization time based on the light-emitting element turn-off ratio. The maximum brightness value is the brightness value corresponding to the maximum gray level. The light-emitting element turn-off ratio is the ratio of the period during which the light-emitting element does not emit light within a single frame to the length of the single frame. The initialization time is the time taken for the third transistor to transmit the initialization voltage to the third node.

13. The display device according to claim 12, wherein, As the maximum brightness value increases, the off-ratio of the light-emitting element decreases.

14. The display device according to claim 12, wherein, The single frame includes an address scan period and a self-scan period, and The drive controller is configured to determine a first initialization time or a second initialization time, wherein the first initialization time is the initialization time spent by the third transistor transmitting the initialization voltage to the third node during the address scan period, and the second initialization time is the initialization time spent by the third transistor transmitting the initialization voltage to the third node during the self-scan period.

15. The display device according to claim 14, wherein, As the turn-off ratio of the light-emitting element increases, the second initialization time decreases.

16. The display device according to claim 15, wherein, The drive controller is configured to determine the first initialization time as a constant time during the address scan period, regardless of the light-emitting element turn-off ratio.

17. An electronic device comprising: The display device according to any one of claims 1 to 16; as well as One or more processors are configured to generate the maximum brightness value. The drive controller is further configured to receive the maximum brightness value.

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