High-low side dual mechanism fused IGBT short circuit protection circuit

Abstract

The present application relates to a kind of high low side double mechanism fusion's IGBT short circuit protection circuit, it is related to power integrated circuit design technical field, the circuit includes high side desaturation short circuit detection circuit, low side resistance short circuit detection circuit, high side fault processing module, low side fault processing module and two-stage collaborative soft turn-off circuit;The signal output end of high side desaturation short circuit detection circuit is electrically connected to the input end of high side fault processing module and the first trigger input end of two-stage collaborative soft turn-off circuit respectively;The signal output end of low side resistance short circuit detection circuit is electrically connected to the input end of low side fault processing module and the second trigger input end of two-stage collaborative soft turn-off circuit respectively;The output end of high side fault processing module and the output end of low side fault processing module are electrically connected to the control input end of two-stage collaborative soft turn-off circuit;Two-stage collaborative soft turn-off circuit is electrically connected to high side IGBT gate and low side IGBT gate.The effect of considering turn-off speed and peak suppression is realized.

Description

Technical Field

[0001] This invention relates to the field of power integrated circuit design technology, and in particular to an IGBT short-circuit protection circuit that integrates high and low side mechanisms. Background Technology

[0002] Intelligent power drive chips are widely used in motor control, new energy vehicles, and industrial transmission. IGBTs are prone to short-circuit faults under high-power, high-frequency switching conditions. Existing protection schemes have the following shortcomings: high-side detection relies on external high-voltage diodes, which are difficult to integrate on-chip and have fixed thresholds; low-side detection relies on external sampling resistors, which introduces additional power consumption and increases the number of peripheral devices; the detection threshold lacks adaptive adjustment capability, and is prone to false triggering or missed detection over a wide temperature range and a wide bus voltage range; the protection turn-off strategy is simplistic, making it difficult to balance turn-off speed and voltage spike suppression, which can easily cause thermal damage or thermal oscillation of the device. Summary of the Invention

[0003] This invention provides an IGBT short-circuit protection circuit that integrates high and low side mechanisms to solve the problem that existing IGBT short-circuit protection circuits have a single protection strategy and cannot achieve coordinated protection between high and low sides.

[0004] This invention provides an IGBT short-circuit protection circuit that integrates high-side and low-side dual mechanisms, including a high-side desaturation short-circuit detection circuit, a low-side resistance short-circuit detection circuit, a high-side fault handling module, a low-side fault handling module, and a two-stage cooperative soft turn-off circuit. The signal output terminal of the high-side desaturation short-circuit detection circuit is electrically connected to the input terminal of the high-side fault handling module and the first trigger input terminal of the two-stage cooperative soft shutdown circuit, respectively. The signal output terminal of the low-side resistance short-circuit detection circuit is electrically connected to the input terminal of the low-side fault handling module and the second trigger input terminal of the two-stage cooperative soft shutdown circuit, respectively. The output terminals of the high-side fault handling module and the low-side fault handling module are respectively electrically connected to the control input terminals of the two-stage cooperative soft shutdown circuit. The gate drive output of the two-stage coordinated soft turn-off circuit is electrically connected to the gate of the high-side IGBT and the gate of the low-side IGBT, respectively.

[0005] A further technical solution is that the high-side desaturation short-circuit detection circuit includes a high-voltage NMOS device, an on-time shielding delay network, a noise filtering network, a temperature compensation resistor pair, and a bus voltage adaptive threshold voltage divider network. The drain terminal of the high-voltage NMOS device is electrically connected to the collector of the high-side IGBT, the source terminal is electrically connected to one end of the temperature compensation resistor, and the gate terminal is electrically connected to the output terminal of the turn-on shielded delay network. The input terminal of the shielding delay network is electrically connected to the high-side power supply, and the output terminal is electrically connected to the input terminal of the noise filtering network. The output terminal of the noise filtering network is the signal output terminal of the high-side desaturation short-circuit detection circuit. The temperature compensation resistor is grounded at the other end; The input of the adaptive threshold voltage divider network is electrically connected to the DC bus, and the output is electrically connected to the input of the comparator.

[0006] A further technical solution is that the activation shielding delay network is composed of a first resistor, a first capacitor, and a first discharge diode; One end of the first resistor is electrically connected to the high-side power supply, and the other end is electrically connected to the positive terminal of the first capacitor and the cathode of the first discharge diode. The negative terminal of the first capacitor and the anode of the first discharge diode are respectively grounded.

[0007] A further technical solution is that the noise filtering network consists of a second resistor and a second capacitor; One end of the second resistor is electrically connected to the output terminal of the shielded delay network, and the other end is electrically connected to the positive terminal of the second capacitor and the signal output terminal of the high-side desaturation short-circuit detection circuit. The negative terminal of the second capacitor is grounded.

[0008] A further technical solution is that the temperature compensation resistor pair is composed of a positive temperature coefficient resistor and a negative temperature coefficient resistor connected in series. One end of the positive temperature coefficient resistor is electrically connected to the source terminal of the high-voltage NMOS device, and the other end is electrically connected to one end of the negative temperature coefficient resistor. The other end of the negative temperature coefficient resistor is grounded.

[0009] A further technical solution is that the bus voltage adaptive threshold voltage divider network is composed of a first high voltage divider resistor and a second voltage divider resistor connected in series; One end of the first high-voltage divider resistor is electrically connected to the DC bus, and the other end is electrically connected to one end of the second voltage divider resistor and the comparator input terminal; The other end of the second voltage divider resistor is electrically connected to the internal reference voltage.

[0010] A further technical solution is that the low-side resistance short-circuit detection circuit includes an operational amplifier, a follower MOS transistor, a Cascode current mirror array, a detection switching resistor, a matching resistor pair, and a temperature feedforward correction unit; The non-inverting input of the operational amplifier is electrically connected to one end of the parasitic resistor of the emitter of the low-side IGBT, and the other end of the parasitic resistor is grounded. The inverting input of the operational amplifier is electrically connected to the source of the follower MOS transistor, and the output input is electrically connected to the gate of the follower MOS transistor. The drain terminal of the follower MOS transistor is electrically connected to the input terminal of the Cascode current mirror array. The output terminal of the Cascode-type current mirror array is electrically connected to one end of the detection conversion resistor. The other end of the detection switching resistor is grounded, and the two ends of the detection switching resistor are the signal output terminals of the low-side resistance short-circuit detection circuit. The matching resistor is connected across the source terminal of the follower MOS transistor and the reference branch of the Cascode current mirror array. The output of the temperature feedforward correction unit is electrically connected to the inverting input of the operational amplifier.

[0011] A further technical solution is that the two-stage coordinated soft shutdown circuit includes a first shutdown discharge branch and a second shutdown discharge branch. The first turn-off discharge branch is composed of a first discharge resistor and a first switching transistor connected in series, and the second turn-off discharge branch is composed of a second discharge resistor and a second switching transistor connected in series. The resistance value of the first discharge resistor is greater than the resistance value of the second discharge resistor; One end of the first turn-off discharge branch and one end of the second turn-off discharge branch are connected together to form a gate drive output terminal, and the other ends are electrically connected to the control input terminal, the first trigger input terminal, and the second trigger input terminal, respectively.

[0012] A further technical solution is that the high-side fault handling module is a cycle-by-cycle retry logic unit, and the low-side fault handling module is a full-side blocking delay unit. The input terminal of the cycle-by-cycle retry logic unit is electrically connected to the signal output terminal of the high-side desaturation short-circuit detection circuit, and the output terminal is electrically connected to the control input terminal of the two-stage cooperative soft shutdown circuit. The input terminal of the full-side blocking delay unit is electrically connected to the signal output terminal of the low-side resistance short-circuit detection circuit, and the output terminal is electrically connected to the control input terminal of the two-stage coordinated soft shutdown circuit.

[0013] A further technical solution is that the parasitic resistance is the inherent resistance formed by the traces of the emitter metal layer of the low-side IGBT.

[0014] The technical solutions provided in the embodiments of the present invention have the following advantages compared with the prior art: By integrating high- and low-side dual-mechanism detection, on-chip non-destructive protection is achieved without external devices on the high-side and without external sampling resistors on the low-side. The bus voltage adaptive threshold can adapt to a wide range of bus voltages, and the temperature compensation mechanism effectively suppresses threshold drift within a wide temperature range. The two-stage collaborative soft turn-off adopts a fast discharge with a small resistor to suppress spikes and a slow discharge with a large resistor for reliable turn-off, reducing turn-off voltage spikes. Differentiated fault handling on the high and low sides avoids thermal oscillations. The overall circuit has high integration, low power consumption, and strong anti-interference ability, significantly improving the reliability and service life of IGBTs. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0017] Figure 1 This is a structural block diagram of an IGBT short-circuit protection circuit with high and low side dual-mechanism fusion provided in an embodiment of the present invention; Figure 2 A schematic diagram of a high-side desaturation short-circuit detection circuit provided in an embodiment of the present invention; Figure 3 A schematic diagram of a low-side resistance short-circuit detection circuit provided in an embodiment of the present invention; Figure 4 A schematic diagram of IGBT distribution and equivalent parasitic resistance provided in an embodiment of the present invention; Figure 5 A structural block diagram of a short-circuit fault handling strategy provided in an embodiment of the present invention; Figure 6 A flowchart of IGBT short-circuit detection is provided for an embodiment of the present invention; Figure 7 A waveform diagram of high-side short-circuit protection operation provided in an embodiment of the present invention; Figure 8 The waveform diagram for low-side short-circuit protection provided in an embodiment of the present invention is shown. Detailed Implementation

[0018] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Similar component reference numerals in the drawings represent similar components. Obviously, the embodiments described below are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0019] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0020] It should also be understood that the terminology used in this specification of embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of the invention. As used in this specification of embodiments of the invention and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0021] Example See Figure 1 , Figure 1 This is a structural block diagram of an IGBT short-circuit protection circuit integrating high-side and low-side dual mechanisms, provided by an embodiment of the present invention. The integrated high-side and low-side dual-mechanism IGBT short-circuit protection circuit includes a high-side desaturation short-circuit detection circuit, a low-side resistance short-circuit detection circuit, a high-side fault handling module, a low-side fault handling module, and a two-stage cooperative soft-turn-off circuit. The signal output terminal of the high-side desaturation short-circuit detection circuit is electrically connected to the input terminal of the high-side fault handling module and the first trigger input terminal of the two-stage cooperative soft-turn-off circuit, respectively. The signal output terminal of the low-side resistance short-circuit detection circuit is electrically connected to the input terminal of the low-side fault handling module and the second trigger input terminal of the two-stage cooperative soft-turn-off circuit, respectively. The output terminals of the high-side and low-side fault handling modules are electrically connected to the control input terminals of the two-stage cooperative soft-turn-off circuit, respectively. The gate drive output terminals of the two-stage cooperative soft-turn-off circuit are electrically connected to the gates of the high-side and low-side IGBTs, respectively.

[0022] In this embodiment, the high-side desaturation short-circuit detection circuit is a circuit unit used to monitor the collector-emitter voltage state of the high-side IGBT and identify desaturation short circuits; the low-side resistance short-circuit detection circuit is a circuit unit used to monitor the emitter parasitic resistance voltage of the low-side IGBT and identify overcurrent short circuits; the high-side fault processing module and the low-side fault processing module are circuit units that perform logical processing on the high and low-side detection signals and output fault control signals, respectively; the two-stage cooperative soft turn-off circuit is a circuit unit that receives fault signals and outputs graded turn-off drive signals to the IGBT gate.

[0023] In one embodiment, the high-side desaturation short-circuit detection circuit includes a high-voltage NMOS device, an on-time shielding delay network, a noise filtering network, a temperature-compensated resistor pair, and a bus voltage adaptive threshold divider network. The drain of the high-voltage NMOS device is electrically connected to the collector of the high-side IGBT, the source is electrically connected to one end of the temperature-compensated resistor pair, and the gate is electrically connected to the output of the on-time shielding delay network. The input of the on-time shielding delay network is electrically connected to the high-side power supply, and the output is electrically connected to the input of the noise filtering network. The output of the noise filtering network is the signal output of the high-side desaturation short-circuit detection circuit. The other end of the temperature-compensated resistor pair is grounded. The input of the bus voltage adaptive threshold divider network is electrically connected to the DC bus, and the output is electrically connected to the comparator input.

[0024] Furthermore, the activation shielding delay network consists of a first resistor, a first capacitor, and a first discharge diode; one end of the first resistor is electrically connected to the high-side power supply, and the other end is electrically connected to the positive terminal of the first capacitor and the cathode of the first discharge diode; the negative terminal of the first capacitor and the anode of the first discharge diode are respectively grounded.

[0025] Furthermore, the noise filtering network consists of a second resistor and a second capacitor; one end of the second resistor is electrically connected to the output terminal of the shielding delay network, and the other end is electrically connected to the positive terminal of the second capacitor and the signal output terminal of the high-side desaturation short-circuit detection circuit; the negative terminal of the second capacitor is grounded.

[0026] Furthermore, the temperature compensation resistor pair is composed of a positive temperature coefficient resistor and a negative temperature coefficient resistor connected in series; one end of the positive temperature coefficient resistor is electrically connected to the source terminal of the high-voltage NMOS device, and the other end is electrically connected to one end of the negative temperature coefficient resistor; the other end of the negative temperature coefficient resistor is grounded.

[0027] Furthermore, the bus voltage adaptive threshold voltage divider network is composed of a first high-voltage voltage divider resistor and a second voltage divider resistor connected in series; one end of the first high-voltage voltage divider resistor is electrically connected to the DC bus, and the other end is electrically connected to one end of the second voltage divider resistor and the comparator input terminal; the other end of the second voltage divider resistor is electrically connected to the internal reference voltage.

[0028] In this embodiment, the high-voltage NMOS device is an on-chip integrated N-type MOS transistor capable of withstanding high voltage; the turn-on shielding delay network is a delay circuit that shields the detection signal during the initial turn-on of the IGBT to avoid false triggering; the noise filtering network is a filtering circuit that filters out high-frequency glitches in the detection signal; the temperature compensation resistor pair is a combination of resistors with positive and negative temperature coefficients that compensates for the temperature drift of the IGBT's on-resistance; and the bus voltage adaptive threshold voltage divider network is a voltage divider circuit that samples the bus voltage and dynamically adjusts the short-circuit judgment threshold.

[0029] In a specific embodiment, see Figure 2 , Figure 2 The schematic diagram of a high-side desaturation short-circuit detection circuit provided in an embodiment of the present invention is as follows: The high-side desaturation short-circuit detection circuit includes a high-voltage N-type MOS device HVMN1, an on-time shielding delay network, a noise filtering network, a biased P-type MOS device MP1, temperature-compensated resistors R3 and R4, and a first high-voltage divider resistor R that forms the bus voltage adaptive threshold voltage divider network. VDC1 Second high voltage divider resistor R VDC2 .

[0030] In this configuration, the drain of HVMN1 is connected to the high-voltage node of the high-side IGBT collector, and the source is connected to the intermediate node of the series connection between R3 and R4; one end of R1 is connected to the high-side power supply V. BS The other end is connected to the positive terminal of C1 and the cathode of D1, while the negative terminal of C1 and the anode of D1 are grounded. This node simultaneously drives the gate of HVMN1. One end of R2 is connected to the source of HVMN1, and the other end is the detection output node. C2 is connected across this node and ground. R3 is made of N-well material with a positive temperature coefficient, and R4 is made of polycrystalline silicon material with a negative temperature coefficient. The two are connected in series between the detection output node and ground. The source of MP1 is connected to V. BS The drain is connected to the source of HVMN1, and the gate is driven by the desaturation shielding control signal. The first-stage delay is composed of R1 and C1. After the IGBT gate drive rises, V... BS C1 is charged via R1. During the shielding period, HVMN1 is cut off. When the IGBT is turned off, C1 is quickly discharged and reset via D1. The second-stage delay consists of R2 and C2, used to filter out V. CE Waveform glitches and noise; the temperature compensation network consists of an N-well resistor R3 (positive temperature coefficient k3≈+7087ppm / ℃) and a polysilicon resistor R4 (negative temperature coefficient k4≈-2448ppm / ℃) connected in series. Ron When ≈k3+|k4|, the temperature characteristics of both components synergistically compensate for the VCE drift caused by the IGBT on-resistance with temperature rise, ensuring the detection threshold remains stable within the range of -40℃ to 130℃; the bus voltage adaptive threshold module samples V through a resistor divider network. DCThe comparator reference terminal is then connected to dynamically adjust the short-circuit detection threshold. The first high-voltage divider resistor R... VDC1 The upper end is directly connected to the 600V high-voltage DC bus outside the chip, and the lower end is connected to the negative input terminal of the comparator. The first high-voltage divider resistor R VDC1 The resistor has a resistance of 990 kΩ and is implemented using high-voltage polysilicon (HV Poly) technology. Its layout employs a meandering, folded trace configuration to balance high voltage isolation with chip area constraints. Its main functions are twofold: first, to introduce the high-voltage bus signal into the low-voltage control area for voltage sensing; second, to limit the leakage current flowing from the 600V high-voltage area to the 5V low-voltage area to the microampere level due to its extremely high resistance, preventing damage to the subsequent comparator due to overvoltage. The second high-voltage divider resistor R... VDC2 Connect the negative input terminal of the comparator downwards to the fixed bandgap reference voltage source Vref (typically 2.5V), and the second high-voltage divider resistor R. VDC2 The resistance value determines the magnitude of the adaptive coefficient k.

[0031] First high-voltage divider resistor R VDC1 With the second high voltage divider resistor R VDC2 Together they form the composite reference voltage at the inverting input of the comparator:

[0032]

[0033] Where VDC is the real-time sampled DC bus voltage, and Vref is the fixed internal reference of the chip. This is the adaptive coefficient. When the bus voltage increases, the short-circuit judgment threshold V... th As the voltage rises, the comparator's judgment threshold automatically increases, eliminating false triggering caused by bus fluctuations; when the bus voltage drops, the short-circuit judgment threshold V... th The sensitivity of short-circuit detection is reduced synchronously to ensure that it is accurate under low-voltage conditions, thus avoiding the problems of false triggering in high-voltage areas and missed detection in low-voltage areas when the threshold is fixed.

[0034] The bus voltage V is sampled in real time using a resistor voltage divider network. DC The short-circuit judgment benchmark is dynamically adjusted. The threshold is automatically raised when the bus voltage rises and automatically lowered when it falls. It can work stably in a wide bus voltage range of 200V-600V, eliminating false triggering caused by dV / dt noise under high voltage conditions and missed judgment under low voltage conditions when the threshold is fixed.

[0035] The workflow is divided into five stages: Static turn-off phase: The IGBT gate remains low, there is no voltage across the blanking capacitor C1, HVMN1 is off, MP1 is on, and Vout is detected. HS The output remains at a low level.

[0036] During the turn-on / shield phase: the IGBT gate flips from low to high, V BS Subsequently, the blanking capacitor C1 is continuously charged through the blanking resistor R1. During the shielding time, the gate terminal of HVMN1 has not accumulated sufficient potential and remains off, thus suspending the detection function and avoiding V during the process of the IGBT entering the saturation region from the cutoff region. CE An excessively high value can lead to misjudgment.

[0037] Normal detection phase: After the shielding time expires, the gate voltage of HVMN1 exceeds the turn-on threshold, HVMN1 turns on, and MP1 turns off. At this time, the IGBT has stably operated in the saturation region, V CE The voltage is maintained at a low saturation on-state voltage of approximately 2 to 3 volts. This voltage, after passing through the internal resistance of HVMN1 and the filter network of R2 and C2, forms the detection voltage Vout. HS Vout under normal operating conditions HS Below the short circuit judgment threshold V TH+ .

[0038] Short-circuit fault identification stage: When a short circuit occurs, the IGBT exits the saturation region, VCE rises sharply and approaches the DC bus potential, and the HVMN1 source voltage rises accordingly, causing the detection voltage to rise rapidly. During this stage, the comparator's short-circuit judgment threshold is not fixed, but rather determined by R... VDC1 With R VDC2 The high-voltage feedforward network is adaptively adjusted. Among them, R... VDC1 As a high-voltage isolation and sampling resistor directly connected to the DC bus to extract high-voltage signals; R VDC2 This signal, acting as a matching resistor, is proportionally divided and superimposed onto a fixed reference voltage Vref. This makes the threshold voltage V... TH+ It can dynamically adjust its voltage to fluctuate with the DC bus voltage, preventing false alarms caused by excessively high normal operating voltage drop due to bus overvoltage fluctuations. Once the detected voltage exceeds this adaptive threshold V... TH+ The comparator flips rapidly and outputs a high-side short-circuit fault flag.

[0039] During the IGBT turn-off reset phase: After the IGBT is turned off, the blanking capacitor C1 discharges rapidly through diode D1. The discharge time constant is much smaller than the charging time constant, so HVMN1 is quickly turned off, MP1 is turned on again, and the detection circuit is reset to its initial state. Furthermore, when a short circuit causes an abnormal rise in the source terminal potential of HVMN1, resulting in its gate-source voltage dropping below the threshold, HVMN1 also has self-protection capabilities, actively cutting off the circuit to prevent overvoltage damage to subsequent low-voltage circuits.

[0040] The temperature compensation working mechanism is as follows: the on-resistance R of the IGBT ONThe voltage coefficient (VCE) increases with increasing junction temperature, exhibiting a positive temperature coefficient. Under constant collector current conditions, VCE increases with temperature. Without compensation, the VCE in the normal conduction state at high temperatures may falsely exceed the short-circuit threshold. A series combination of resistors R3 and R4 is used. R3 is an N-well type material with a positive temperature coefficient, while R4 is a polycrystalline silicon type material with a negative temperature coefficient. Their temperature characteristics are opposite. When the parameters are appropriate, the negative temperature characteristic of R4 and the positive temperature characteristic of R3 work synergistically to compensate for the VCE caused by the positive temperature coefficient of the IGBT's on-resistance. CE The elevation effect keeps the detection threshold stable throughout the entire operating temperature range of -40°C to 130°C.

[0041] In one embodiment, the low-side resistance short-circuit detection circuit includes an operational amplifier, a follower MOSFET, a Cascode current mirror array, a detection switching resistor, a matching resistor pair, and a temperature feedforward correction unit. The non-inverting input of the operational amplifier is electrically connected to one end of the parasitic resistance of the emitter of the low-side IGBT, and the other end of the parasitic resistance is grounded. The inverting input of the operational amplifier is electrically connected to the source of the follower MOSFET, and the output is electrically connected to the gate of the follower MOSFET. The drain of the follower MOSFET is electrically connected to the input of the Cascode current mirror array. The output of the Cascode current mirror array is electrically connected to one end of the detection switching resistor. The other end of the detection switching resistor is grounded, and the two ends of the detection switching resistor are the signal output terminals of the low-side resistance short-circuit detection circuit. The matching resistor pair is connected between the source of the follower MOSFET and the reference branch of the Cascode current mirror array. The output of the temperature feedforward correction unit is electrically connected to the inverting input of the operational amplifier.

[0042] Furthermore, the parasitic resistance is the inherent resistance formed by the traces in the emitter metal layer of the low-side IGBT.

[0043] In this embodiment, the operational amplifier and the follower MOS transistor constitute a voltage follower unit to extract the differential voltage across the parasitic resistance; the Cascode current mirror array is a current mirror with high power supply rejection ratio and proportional amplification of the detection current; the detection conversion resistor is a resistor that converts the mirrored current into a voltage signal; the matching resistor pair is a combination of resistors that ensures the symmetry of the detection circuit and improves the sampling accuracy; the temperature feedforward correction unit is a correction circuit based on chip temperature to compensate for the temperature drift of the current sampling; the parasitic resistance is the inherent resistance formed by the traces of the emitter metal layer of the low-side IGBT.

[0044] In a specific embodiment, see Figure 3 , Figure 3 The schematic diagram of a low-side resistance short-circuit detection circuit provided in an embodiment of the present invention is shown below. The analysis of the low-side resistance short-circuit detection circuit is as follows: See Figure 4 , Figure 4This is a schematic diagram of an IGBT distribution and equivalent parasitic resistance provided in an embodiment of the present invention. The power IGBT adopts a racetrack-shaped cell array layout, with n identical racetrack-shaped cells arranged side by side along the axis of symmetry. Each cell contains a collector metal parasitic resistance R. m Parasitic resistance R of through-hole v and emitter metal parasitic resistance R e Three main parasitic elements. The equivalent resistance of a single-unit emitter metal trace is R. e When n units are connected in parallel, the overall equivalent parasitic resistance simplifies to R. virtual ;

[0045] Among them, the overall equivalent parasitic resistance R virtual The value is uniquely determined by the process parameters, requiring no additional area overhead.

[0046] Circuit composition: The low-side detection circuit includes an operational amplifier OPA, an N-type MOS transistor M1, a Cascode current mirror array, and a detection switching resistor R. sen Precision matching resistors R1 and R2, and voltage V output from the temperature sensor. TEMP With compensation resistor R T The temperature feedforward correction unit is constructed.

[0047] Among them, R1 and R2 have equal resistance values; in the Cascode-type current mirror array, the P-type side includes MP1 to MP10, and the N-type side includes MN1 to MN11; V TEMP The output voltage is from the chip's built-in temperature sensor and has a positive temperature coefficient; the higher the temperature, the higher the output voltage. T One end connected to V TEMP The other end is connected to the inverting input node V1 of the operational amplifier.

[0048] The working mechanism is as follows: When the chip temperature rises, the positive temperature coefficient of the IGBT's on-resistance causes the collector sampling voltage to be too high, and the non-inverting input V2 of the op-amp is consequently raised. Without compensation, the output voltage Vout will falsely trigger the short-circuit threshold; after introducing temperature feedforward, V... TEMP As the temperature rises synchronously, through R T Injecting additional current into node V1 causes the op-amp to reduce the drive to MN9 in order to maintain the virtual short (V1=V2), which reduces the current flowing through R1. The current output through the current mirror also decreases accordingly, and Vout is pulled back to the normal level, thus offsetting the sampling deviation caused by temperature drift.

[0049] Applying Kirchhoff's Current Law (KCL) to node V1, before the introduction of temperature feedforward, the node current is entirely provided by MN9:

[0050] After the temperature feedforward is introduced, V TEMP Through R T Injecting additional current into V1, the node equations become:

[0051] Therefore, V increases with temperature. TEMP Increase, injection current increases, I MN9 As the voltage decreases, the output voltage Vout drops, compensating for the sampling deviation caused by the positive temperature coefficient of the IGBT's on-resistance, thus keeping the short-circuit protection threshold stable within the range of -40℃ to 125℃, reducing high-temperature false triggering and low-temperature leakage protection.

[0052] Circuit interconnection: The non-inverting input of OPA is connected to R virtual The high-potential terminal and the inverting input terminal are connected to the source terminal of M1, and the OPA output terminal drives the gate of M1; the drain terminal of M1 is connected to the input branch of the Cascode current mirror; R1 is connected between the source terminal of M1 and ground, and R2 is connected between the source terminal of the reference branch MN11 and ground; the width-to-length ratio of MP7 and MP8 in the Cascode current mirror is set to 1:m, so that the output current satisfies I sen =m I9; Final I sen Flowing through R sen It completes the conversion from current to voltage, generating an output voltage Vout. LS Temperature sensor V TEMP The negative terminal is directly connected to GND in the low-side control circuit, and the positive terminal is connected upwards to the compensation resistor R. T At the lower end, the compensation resistor R T The upper end is directly connected to the feedback node V1 of the op-amp.

[0053] The working mechanism is as follows: The closed-loop follower structure formed by OPA and M1 makes the potentials of the two input terminals equal, thereby achieving control over R. virtual The differential voltage across the two terminals can be extracted, even if the differential signal is only on the order of millivolts. When the IGBT collector current ICE increases, R... virtual The voltage difference across the two ends increases accordingly, and the induced current flowing through R1 increases proportionally. Since the IGBT's on-state voltage drop has a positive temperature coefficient, increased temperature can lead to an artificially high extracted differential voltage, easily causing false short-circuit triggering under high-temperature conditions. Therefore, this circuit introduces a temperature sensor V at the OPA feedback node. TEMP With compensation resistor R T The feedforward injection network is constructed. When the ambient temperature rises, V... TEMP The output voltage increases linearly, and through R TCompensation current is actively injected into the feedback node. According to Kirchhoff's Current Law (KCL), this injection mechanism dynamically reduces the induced current that should be drawn by M1, thereby precisely offsetting the impact of temperature drift error on sampling accuracy at the source.

[0054] The induced current, after real-time temperature correction, is amplified by a Cascode-type current mirror at a 1:m ratio and output as I. sen Flowing through R sen The output voltage Vout is then obtained. LS Once Vout LS If the short-circuit detection threshold preset by the comparator is exceeded, a short-circuit fault is determined. The Cascode cascaded topology improves the circuit's power supply rejection ratio, effectively reducing the interference of transient noise on the low-side power supply traces on the detection results. Under the premise of stable process technology, R, determined by the layout design... virtual The error can be controlled within ±5%.

[0055] See Figure 5 , Figure 5 This is a structural block diagram of a short-circuit fault handling strategy provided in an embodiment of the present invention. The short-circuit fault handling strategy includes a high-side fault handling module that executes the high-side short-circuit protection process and a low-side fault handling module that executes the low-side short-circuit protection process. It achieves coordinated protection of the high- and low-side IGBTs through differentiated handling logic, striking a balance between response speed and system reliability.

[0056] Furthermore, the high-side fault handling module is a cycle-by-cycle retry logic unit, and the low-side fault handling module is a full-side blocking delay unit; the input terminal of the cycle-by-cycle retry logic unit is electrically connected to the signal output terminal of the high-side desaturation short-circuit detection circuit, and the output terminal is electrically connected to the control input terminal of the two-stage cooperative soft shutdown circuit; the input terminal of the full-side blocking delay unit is electrically connected to the signal output terminal of the low-side resistance short-circuit detection circuit, and the output terminal is electrically connected to the control input terminal of the two-stage cooperative soft shutdown circuit.

[0057] High-side short-circuit protection execution process: Vout generated by the high-side desaturation detection circuit HS The input voltage comparator is compared with a preset threshold V. TH+ Compare; when Vout HS consistently higher than V TH+ When the comparator outputs a valid signal, after the subsequent filtering circuit eliminates glitches and interference, a high-side fault flag (FLT) is generated. HS FLT HSThe soft-shutdown drive circuit is activated to slowly reduce the gate voltage of the high-side IGBT with a controlled slope, effectively suppressing the dI / dt overvoltage surge caused by the rapid drop in collector current, while locking the current PWM conduction cycle. The detection is retried on the rising edge of the next PWM cycle. If the fault has been cleared at this time, normal modulation is restored. If the short circuit condition continues, the above protection actions are repeated.

[0058] Low-side short-circuit protection execution process: The low-side parasitic resistance detection circuit outputs Vout. LS When the input exceeds a set threshold, the comparator toggles its output. After filtering, the output confirms the low-side fault flag (FLT). HS Effective; FLT HS The trigger soft-shutdown drive circuit performs controlled shutdown of the low-side IGBT, while simultaneously activating the signal shielding logic: The high-side and low-side IGBT drive signals are synchronously set to zero using NOR gates, as the power devices on both sides may experience large current surges during a severe short circuit on the low side; an RC delay network combined with NOR gates is used to construct a falling edge delay stage, even if the FLT... HS Even after the short circuit fault has disappeared, the delay circuit can still maintain the NOR gate's blocked output state for a period of time, keeping the high and low side drive signals off. Only after the delay period expires and the system is confirmed to be stable can the blocking be automatically released and the drive resumed.

[0059] See also Figure 5 In one embodiment, the two-stage coordinated soft shutdown circuit includes a first shutdown discharge branch and a second shutdown discharge branch; the first shutdown discharge branch is composed of a first discharge resistor and a first switch connected in series, and the second shutdown discharge branch is composed of a second discharge resistor and a second switch connected in series; the resistance value of the first discharge resistor is greater than the resistance value of the second discharge resistor; one end of the first shutdown discharge branch and one end of the second shutdown discharge branch are connected together to form a gate drive output terminal, and the other end is electrically connected to a control input terminal, a first trigger input terminal, and a second trigger input terminal, respectively.

[0060] In this embodiment, the first turn-off discharge branch refers to a slow turn-off path, which has the effects of high resistance, slow discharge, and extended turn-off time; the second turn-off discharge branch is a fast turn-off path, which has the effects of low resistance, fast discharge, and suppression of current spikes.

[0061] In a specific embodiment, the two-stage collaborative soft shutdown circuit is configured as follows: after a fault is triggered, the first-stage MOSFET discharges slowly with a low current, controlled within the range of 0.5 to 1 ampere; after a delay of 1 to 2 microseconds via an RC delay network, the second-stage MOSFET quickly shuts off the remaining current, with the second-stage discharge current controlled within the range of 2 to 4 amperes. After a fault is triggered, the first-stage slow shutdown begins, where a small-current discharge circuit with approximately 10kΩ resistor slowly pulls down the gate voltage of the power transistor, suppressing dI / dt and reducing the turn-off overvoltage spike; when the gate voltage drops to near the threshold, the circuit switches to the second-stage fast shutdown, where a large-current discharge circuit with approximately 100Ω resistor quickly pulls the gate voltage to a negative voltage, reducing the turn-off voltage overshoot by 40% to 60%, thus preventing repeated fault triggering and resulting thermal oscillations. Through this two-stage shutdown strategy, both the overvoltage caused by the rapid decrease in collector current and the reliable clearing of the fault are suppressed.

[0062] High-side cycle-by-cycle retry: After the desaturation detection output is confirmed by a comparator and filter, a high-side fault flag FLT is generated. HS The two-stage soft-shutdown circuit drives the high-side IGBT gate voltage down at a controlled rate, terminating the current PWM conduction cycle. When the next PWM rising edge arrives, detection restarts; if the fault is cleared, drive automatically resumes; otherwise, protection continues. Low-side soft-shutdown is linked to full-side blocking: the low-side detection output Vout... LS Over-limit trigger FLT LS Subsequently, a two-stage soft-shutdown gradually turns off the low-side IGBT, while simultaneously blocking the dual-path drive signals on both the high and low sides through NOR gates; the RC delay network works in conjunction with the NOR gates to achieve the desired effect at the FLT. LS After being deactivated, the locked state will remain for a typical 100μs to 1ms until the device cools down, which will automatically unlock the device to prevent IGBT thermal oscillation failure.

[0063] See Figures 5-8 The working process of this IGBT short-circuit protection circuit integrating high and low side mechanisms is as follows: Under normal modulation operation, external PWM commands drive the high-side and low-side IGBTs to conduct alternately in a fixed sequence, outputting a sinusoidal current to the motor load. The high-side desaturation detection circuit automatically enters continuous VCE monitoring state after completing the turn-on shielding during each PWM conduction period, with a shielding time of 2 to 10 microseconds. The low-side parasitic resistance detection circuit monitors the collector current I throughout the entire process. CE Both detection output voltages are below the threshold, the system maintains normal operation, and no protection action is triggered.

[0064] High-side isolated short circuit scenario: The high-side detection circuit senses V CE Desaturation, FLT HSOutput is valid; the soft shutdown circuit controls the high-side IGBT to shut down and locks the current PWM cycle; the low-side detection circuit is unaffected by this fault and maintains normal monitoring mode; when the detection restarts in the next PWM cycle, if the fault has dissipated, it will directly return to normal; otherwise, it will continue to respond to protection cycles one by one.

[0065] Low-side isolated short circuit scenario: The low-side detection circuit senses I CE The FLT exceeds the judgment threshold by 1.5 to 2.0 times the rated value. LS Output valid; soft-shutdown circuit performs controlled shutdown of low-side IGBT; simultaneously, signal shielding circuit is activated, blocking both high-side and low-side drive signals; even if the short-circuit state is briefly released, the FLT... LS Upon reset, the falling edge delay circuit remains blocked for approximately 100 microseconds to 1 millisecond; after the delay expires, the block is automatically released, and normal drive output is restored.

[0066] Simultaneous short circuit on both high and low sides: FLT HS With FLT LS Synchronization is effective; high-side triggering cycle-by-cycle protection means soft shutdown and termination of the current PWM cycle; low-side triggering soft shutdown and linkage of full-side signal blocking; signal blocking has higher priority than cycle-by-cycle retry logic to ensure that all IGBTs are turned off; after the falling edge delay ends, the system re-evaluates the fault status, and normal operation can only be restored after the fault is confirmed to be cleared.

[0067] The embodiments of the present invention can achieve the following advantages: By integrating high- and low-side dual-mechanism detection, on-chip non-destructive protection is achieved without external devices on the high-side and without external sampling resistors on the low-side. The bus voltage adaptive threshold can adapt to a wide range of bus voltages, and the temperature compensation mechanism effectively suppresses threshold drift within a wide temperature range. The two-stage collaborative soft turn-off adopts a fast discharge with a small resistor to suppress spikes and a slow discharge with a large resistor for reliable turn-off, reducing turn-off voltage spikes. Differentiated fault handling on the high and low sides avoids thermal oscillations. The overall circuit has high integration, low power consumption, and strong anti-interference ability, significantly improving the reliability and service life of IGBTs.

[0068] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0069] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0070] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0071] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0072] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0073] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0074] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Since these modifications and variations fall within the scope of the claims and their equivalents, this invention also intends to include these modifications and variations.

[0075] The above description describes specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A short-circuit protection circuit for IGBTs with integrated high- and low-side dual mechanisms, characterized in that, It includes a high-side desaturation short-circuit detection circuit, a low-side resistance short-circuit detection circuit, a high-side fault handling module, a low-side fault handling module, and a two-stage cooperative soft shutdown circuit. The signal output terminal of the high-side desaturation short-circuit detection circuit is electrically connected to the input terminal of the high-side fault handling module and the first trigger input terminal of the two-stage cooperative soft shutdown circuit, respectively. The signal output terminal of the low-side resistance short-circuit detection circuit is electrically connected to the input terminal of the low-side fault handling module and the second trigger input terminal of the two-stage cooperative soft shutdown circuit, respectively. The output terminals of the high-side fault handling module and the low-side fault handling module are respectively electrically connected to the control input terminals of the two-stage cooperative soft shutdown circuit. The gate drive output terminal of the two-stage cooperative soft turn-off circuit is electrically connected to the high-side IGBT gate and the low-side IGBT gate, respectively. The high-side desaturation short-circuit detection circuit includes a high-voltage NMOS device, an on-time shielding delay network, a noise filtering network, a temperature compensation resistor pair, and a bus voltage adaptive threshold voltage divider network. The drain terminal of the high-voltage NMOS device is electrically connected to the collector of the high-side IGBT, the source terminal is electrically connected to one end of the temperature compensation resistor, and the gate terminal is electrically connected to the output terminal of the turn-on shielded delay network. The input terminal of the shielding delay network is electrically connected to the high-side power supply, and the output terminal is electrically connected to the input terminal of the noise filtering network. The output terminal of the noise filtering network is the signal output terminal of the high-side desaturation short-circuit detection circuit. The temperature compensation resistor is grounded at the other end; The input of the adaptive threshold voltage divider network is electrically connected to the DC bus, and the output is electrically connected to the input of the comparator.

2. The IGBT short-circuit protection circuit with high and low side dual-mechanism fusion as described in claim 1, characterized in that, The activation shielding delay network consists of a first resistor, a first capacitor, and a first discharge diode; One end of the first resistor is electrically connected to the high-side power supply, and the other end is electrically connected to the positive terminal of the first capacitor and the cathode of the first discharge diode. The negative terminal of the first capacitor and the anode of the first discharge diode are respectively grounded.

3. The IGBT short-circuit protection circuit with high and low side dual-mechanism fusion as described in claim 1, characterized in that, The noise filtering network consists of a second resistor and a second capacitor; One end of the second resistor is electrically connected to the output terminal of the shielding delay network, and the other end is electrically connected to the positive terminal of the second capacitor and the signal output terminal of the high-side desaturation short-circuit detection circuit. The negative terminal of the second capacitor is grounded.

4. The IGBT short-circuit protection circuit with high and low side dual-mechanism fusion as described in claim 1, characterized in that, The temperature compensation resistor pair is composed of a positive temperature coefficient resistor and a negative temperature coefficient resistor connected in series. One end of the positive temperature coefficient resistor is electrically connected to the source terminal of the high-voltage NMOS device, and the other end is electrically connected to one end of the negative temperature coefficient resistor. The other end of the negative temperature coefficient resistor is grounded.

5. The IGBT short-circuit protection circuit with high and low side dual-mechanism fusion according to claim 1, characterized in that, The bus voltage adaptive threshold voltage divider network is composed of a first high voltage divider resistor and a second voltage divider resistor connected in series. One end of the first high-voltage divider resistor is electrically connected to the DC bus, and the other end is electrically connected to one end of the second voltage divider resistor and the comparator input terminal; The other end of the second voltage divider resistor is electrically connected to the internal reference voltage.

6. The IGBT short-circuit protection circuit with high and low side dual-mechanism fusion according to claim 1, characterized in that, The low-side resistance short-circuit detection circuit includes an operational amplifier, a follower MOSFET, a Cascode current mirror array, a detection switching resistor, a matching resistor pair, and a temperature feedforward correction unit. The non-inverting input of the operational amplifier is electrically connected to one end of the parasitic resistor of the emitter of the low-side IGBT, and the other end of the parasitic resistor is grounded. The inverting input of the operational amplifier is electrically connected to the source of the follower MOS transistor, and the output input is electrically connected to the gate of the follower MOS transistor. The drain terminal of the follower MOS transistor is electrically connected to the input terminal of the Cascode current mirror array. The output terminal of the Cascode-type current mirror array is electrically connected to one end of the detection conversion resistor. The other end of the detection switching resistor is grounded, and the two ends of the detection switching resistor are the signal output terminals of the low-side resistance short-circuit detection circuit. The matching resistor is connected across the source terminal of the follower MOS transistor and the reference branch of the Cascode current mirror array. The output of the temperature feedforward correction unit is electrically connected to the inverting input of the operational amplifier.

7. The IGBT short-circuit protection circuit with high and low side dual-mechanism fusion according to claim 1, characterized in that, The two-stage coordinated soft shutdown circuit includes a first shutdown discharge branch and a second shutdown discharge branch. The first turn-off discharge branch is composed of a first discharge resistor and a first switching transistor connected in series, and the second turn-off discharge branch is composed of a second discharge resistor and a second switching transistor connected in series. The resistance of the first discharge resistor is greater than the resistance of the second discharge resistor; One end of the first turn-off discharge branch and one end of the second turn-off discharge branch are connected together to form a gate drive output terminal, and the other ends are electrically connected to the control input terminal, the first trigger input terminal, and the second trigger input terminal, respectively.

8. The IGBT short-circuit protection circuit with high and low side dual-mechanism fusion according to claim 1, characterized in that, The high-side fault handling module is a cycle-by-cycle retry logic unit, and the low-side fault handling module is a full-side blocking delay unit. The input terminal of the cycle-by-cycle retry logic unit is electrically connected to the signal output terminal of the high-side desaturation short-circuit detection circuit, and the output terminal is electrically connected to the control input terminal of the two-stage cooperative soft shutdown circuit. The input terminal of the full-side blocking delay unit is electrically connected to the signal output terminal of the low-side resistance short-circuit detection circuit, and the output terminal is electrically connected to the control input terminal of the two-stage coordinated soft shutdown circuit.

9. The IGBT short-circuit protection circuit with high and low side dual-mechanism fusion according to claim 6, characterized in that, The parasitic resistance is the inherent resistance formed by the traces in the emitter metal layer of the low-side IGBT.

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