Los status detection circuit for sfp optical module

Abstract

The application discloses a LOS state detection circuit for an SFP optical module, which comprises an input inversion module, a signal conditioning and pulse expansion module and a threshold comparison and decision module connected in sequence. The input inversion module comprises a receiving original port link state indication signal, which is used for logical inversion of the original signal and enhancement of driving capacity. The signal conditioning module converts the data pulse stream output by a PHY chip into a smooth direct current voltage by using peak holding and RC expansion technology. The threshold comparison module intelligently judges whether the voltage represents valid signal activity through a hysteresis comparator, and finally outputs a hardware LOS signal which strictly conforms to the SFP MSA standard and is highly stable. The application realizes reliable optical signal loss detection in a full hardware mode, solves the problems of unstable output and easy misjudgment of a traditional scheme, and has the advantages of low cost, small area, fast response and high reliability, and is particularly suitable for integrated SFP optical module design.

Description

Technical Field

[0001] This invention relates to the field of optical communication technology, specifically to a demodulation circuit and method for converting a port link / activity LED flashing signal with a known period into a stable level signal. It is particularly suitable for scenarios such as switches, routers, and optical modules that require reliable detection of port physical link loss (LOS) status. Background Technology

[0002] In communication devices such as network switches, routers, and optical modules, each port is typically equipped with a dual-color or single-color link / activity indicator. This indicator is directly driven by the physical layer chip (PHY), and its drive signal (such as the TPLINK signal) has three distinct states: Always On: Indicates that the physical link connection of the port is normal, but there is currently no data transmission or reception activity.

[0003] Flashing: Indicates that the port link connection is normal and there is data transmission and reception activity. Flashing usually has a fixed period and duty cycle, such as a cycle of 20ms on and 80ms off.

[0004] Off: Indicates that the physical link to the port is disconnected.

[0005] In the aforementioned communication equipment, the system often requires a stable voltage level signal to determine whether a port link has been lost (LOS), and cannot mistakenly interpret indicator light flashing caused by data activity as a change in link status. Existing technologies primarily employ two approaches to address this issue: Microcontroller (MCU) software polling scheme: This method involves periodically sampling the indicator light pin level of the MCU and using a software timer to determine the duration of high / low levels to distinguish between blinking and constant off. This method increases the MCU's software overhead and pin resource consumption, and the response time is limited by the polling cycle, resulting in poor real-time performance.

[0006] A simple RC low-pass filter scheme uses resistors and capacitors to construct a passive low-pass filter in an attempt to filter out the flickering AC component. However, to effectively filter out flickering with a frequency of only about 10Hz (period of 100ms), a very large RC time constant is required. This will severely slow down the response speed to real link disconnection events (which may take several seconds), and the filtered DC level still has a large ripple, which can easily cause output jitter in the subsequent comparator.

[0007] Therefore, there is an urgent need for a link status indication signal demodulation scheme that is purely hardware-based, low-cost, and can both quickly respond to real link status changes and completely eliminate data activity flicker interference. Summary of the Invention

[0008] The present invention provides a LOS status detection circuit for SFP optical modules, which can at least solve one of the technical problems in the background art.

[0009] To achieve the above objectives, the present invention adopts the following technical solution: A LOS status detection circuit for an SFP optical module, the circuit comprising: an inverting input module, a signal conditioning and pulse broadening module, and a threshold comparison and decision module connected in sequence; The input inverting module receives the original port link status indication signal, performs logical flipping on the original signal, and enhances the driving capability. The input terminal of the signal conditioning and pulse broadening module is used to connect to the data output terminal of the internal PHY chip, receive pulse signals with amplitude between 0 and the power supply voltage Vcc, and output a slowly varying DC voltage. The threshold comparison and decision module compares the slowly varying DC voltage with a preset decision threshold and outputs a low-level active LOS status signal conforming to the SFPMSA specification.

[0010] Furthermore, the signal conditioning and pulse broadening module of the present invention includes: a series diode and a parallel RC network, wherein the time constant of the RC network (τ≈1.48 seconds) is much greater than the typical duration of the low level in the PHY chip output data signal (20 milliseconds).

[0011] Furthermore, the diode described in this invention is a Schottky diode, and the anode of the diode is connected to the output terminal of the PHY chip.

[0012] Furthermore, the threshold comparison and decision module of the present invention includes: a hysteresis comparator with a positive feedback network, wherein the decision threshold of the hysteresis comparator is set to be lower than the peak voltage of the high level output of the PHY chip and higher than the low level output of the PHY chip.

[0013] Furthermore, the threshold comparison and decision module of the present invention includes a comparator circuit to make the power supply voltage consistent with the digital logic interface voltage of the SFP module.

[0014] Furthermore, the threshold comparison and decision module of the present invention also includes: a pull-up resistor; One end of the pull-up resistor is connected to the output terminal of the threshold comparison and decision module, i.e., the LOS signal terminal; the other end is connected to the module's digital power supply, so that the LOS signal terminal is in a high-level state when there is no effective drive.

[0015] Furthermore, the inverting input module, signal conditioning and pulse broadening module, and threshold comparison and decision module of the present invention are integrated on the internal circuit board of the SFP module, and the LOS signal output terminal of the threshold comparison and decision module is connected to the hardware pin of the SFP module.

[0016] In summary, the technical solution proposed in this invention has the following significant advantages: Highly targeted debouncing design: For the first time, the pulse stretching principle is combined with the known fixed period characteristics of port indicator light flashing. By precisely setting the discharge time constant (significantly greater than the flashing low-level pulse width), the complete filtering of this type of specific low-frequency interference signal is achieved, solving the dilemma of general RC filtering being unable to balance response speed and debouncing effect.

[0017] Purely hardware-based, zero-latency response: requiring no MCU involvement and consuming no software resources. Upon initial power-up or link establishment, the capacitor can be instantly charged via the diode, allowing the circuit to output a stable state within milliseconds.

[0018] The structure is simple and the cost is extremely low: the entire core processing module only adds one diode, one resistor and one capacitor. The number of components is small and the material cost is extremely low. It is easy to integrate into cost and space-sensitive communication equipment such as switches and optical modules. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the LOS state detection circuit of the present invention; Figure 2 This is a schematic diagram showing the application location of the present invention in an SFP module; Figure 3 This is a timing diagram of the operating waveform of the circuit of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0021] like Figure 1 As shown, the LOS state detection circuit for SFP optical modules described in this embodiment includes an inverting input module, a signal conditioning and pulse broadening module, and a threshold comparison and decision module. The input inverting module receives the original port link status indication signal, performs logical flipping on the original signal, and enhances the driving capability.

[0022] The input of the signal conditioning and pulse broadening module is connected to the data signal output of the PHY chip inside the optical module. It is used to receive non-periodic pulse signals with an amplitude of 0 to Vcc (e.g., 2.5V), and to perform peak holding and time broadening on the non-periodic pulse signal to output a slowly varying DC voltage that is positively correlated with the pulse activity intensity. The threshold comparison and decision module is connected to the output of the signal conditioning and pulse broadening module. It has a built-in hysteresis characteristic to compare the slowly varying DC voltage with a preset decision threshold between 0 and Vcc, and output an intermediate logic level, ultimately generating a low-level active signal that conforms to the SFPMSA hardware LOS pin electrical specification.

[0023] The signal conditioning and pulse broadening module includes a peak detection unit and an RC broadening unit.

[0024] The peak detection unit consists of a high-speed Schottky diode, whose anode is connected to the output of the PHY chip.

[0025] The RC widening unit consists of an energy storage capacitor and a parallel discharge resistor. The energy storage capacitor and the discharge resistor are connected between the cathode of the high-speed Schottky diode and ground. Its time constant (τ≈1.48 seconds) is much larger than the duration of the low level in a single data pulse (20ms), thereby ensuring that its output voltage remains high during the continuous transmission of effective data.

[0026] The threshold comparison and decision module is implemented using a hysteresis comparator circuit, including a voltage comparator, a precision voltage divider network providing the decision threshold, and a positive feedback resistor network providing the hysteresis voltage. The decision threshold is set below the peak high-level output of the PHY chip but significantly higher than its low-level voltage to reliably distinguish between "pulse activity" and "no signal" states. Its power supply voltage is consistent with the digital logic voltage of the SFP optical module (typically 3.3V) to enhance drive capability and directly drive the LOS output pin.

[0027] It also includes a pull-up resistor connected between the output of the threshold comparison and decision module and the module's digital power supply (Vcc, such as 3.3V) to ensure that the LOS pin is pulled up to a high level by default (indicating signal loss state) when the module is initially powered on or when the PHY chip is not working, which complies with the safety failure principle.

[0028] The working principle and logic of the circuit of this invention are explained below: 1. Input inversion and isolation: The original TPLINK signal is fed into inverter U1 via resistor R108 (a 0Ω jumper resistor can be used for debugging). U1 can be an open-drain NAND gate (such as the MC74VHC1G03) with its two inputs shorted, effectively functioning as an inverter. After passing through this module, the signal logic is flipped: When the link is normal (On or Flash), the output of U1 is a continuous high level or a high pulse train.

[0029] When the link is disconnected (Off), the output of U1 is a constant low level.

[0030] 2. Pulse stretching and state maintenance: This is the core module for eliminating flicker interference in this solution. The output of U1 is connected to a parallel RC network consisting of capacitor C102 and resistor R109 after passing through a forward-connected diode D1 (a BAS16H type switching diode can be selected) and an isolation resistor R38 (a 0Ω resistor can be selected).

[0031] Fast charging circuit: When U1 outputs a high level, D1 is forward-biased. Due to its extremely small dynamic resistance, the charging time constant is almost 0, and C102 can be fully charged to close to the power supply voltage in a very short time.

[0032] Extremely slow discharge circuit: When U1 outputs a low level, D1 is reverse-biased and cut off, preventing current from flowing back through D1. At this time, the charge stored on C102 can only be slowly discharged through the resistor R109 connected in parallel with itself.

[0033] Targeted parameter design: In this embodiment, C102 is selected as 4.7μF and R109 is selected as 316kΩ. The calculated discharge time constant τ = R109 × C102 ≈ 1.48 seconds.

[0034] The original TPLINK signal has a single low-level width of only 20ms when it flashes.

[0035] Because the discharge time constant of 1.48 seconds is much larger than the low-level width of 20ms (more than 70 times), the voltage drop across C102 is negligible during the brief 20ms low-level period. Immediately afterwards, the next high-level pulse will immediately recharge it through D1.

[0036] Effect: Regardless of whether the original TPLINK signal is a constant low level (always on) or an intermittent pulse (flickering), the voltage across capacitor C102 is continuously maintained at a stable DC voltage close to the high level, perfectly filtering out the flickering.

[0037] Only when the port link is truly disconnected (Off), and the output of U1 remains low without any high-level pulses, will C102 discharge continuously through R109 with a time constant of approximately 1.48 seconds. This time is the debouncing delay for detecting a lost link (LOS), effectively preventing false alarms caused by momentary poor contact.

[0038] 3. Threshold decision and output: The non-inverting input (+) of comparator U2 (which can be an ADCMP370) is connected to a stable 1V DC reference voltage, and the inverting input (-) is connected to the voltage across capacitor C102.

[0039] When the link is normal: the voltage of capacitor C102 remains stable at a level much higher than 1V, the voltage at the inverting input of U2 is higher than the voltage at the non-inverting input, and the comparator output LOS_OUT is low (indicating no signal loss).

[0040] When the link is disconnected: After debouncing delay, the voltage of capacitor C102 drops below 1V, the voltage at the inverting input of U2 is lower than the voltage at the non-inverting input, the comparator output flips, and LOS_OUT outputs a high level (indicator signal is lost).

[0041] The output signal is a clean, jitter-free level signal that accurately reflects the physical link connection status of the port.

[0042] In summary, the present invention has the following advantages: Highly targeted debouncing design: For the first time, the pulse stretching principle is combined with the known fixed period characteristics of port indicator light flashing. By precisely setting the discharge time constant (significantly greater than the flashing low-level pulse width), the complete filtering of this type of specific low-frequency interference signal is achieved, solving the dilemma of general RC filtering being unable to balance response speed and debouncing effect.

[0043] Purely hardware-based, zero-latency response: requiring no MCU involvement and consuming no software resources. Upon initial power-up or link establishment, the capacitor can be instantly charged via the diode, allowing the circuit to output a stable state within milliseconds.

[0044] The structure is simple and the cost is extremely low: the entire core processing module only adds one diode, one resistor and one capacitor. The number of components is small and the material cost is extremely low. It is easy to integrate into cost and space-sensitive communication equipment such as switches and optical modules.

[0045] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0046] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0047] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A LOS status detection circuit for an SFP optical module, characterized in that, The circuit includes: an input inverting module, a signal conditioning and pulse broadening module, and a threshold comparison and decision module connected in sequence; The input inverting module includes receiving the original port link status indication signal, which is used to logically flip the original signal and enhance the driving capability. The input terminal of the signal conditioning and pulse broadening module is used to connect to the data output terminal of the internal PHY chip, receive pulse signals with amplitude between 0 and the power supply voltage Vcc, and output a slowly varying DC voltage. The threshold comparison and decision module compares the slowly varying DC voltage with a preset decision threshold and outputs an intermediate logic level.

2. The LOS status detection circuit for SFP optical modules according to claim 1, characterized in that, The signal conditioning and pulse broadening module includes a series diode and a parallel RC network. The time constant τ of the RC network is approximately 1.48 seconds, which is greater than the typical duration of the low level in the PHY chip's output data signal, which is 20 milliseconds.

3. The LOS status detection circuit for SFP optical modules according to claim 2, characterized in that, The diode is a Schottky diode, and the anode of the diode is connected to the output terminal of the PHY chip.

4. The LOS status detection circuit for SFP optical modules according to claim 1, characterized in that: The threshold comparison and decision module includes a hysteresis comparator with a positive feedback network. The decision threshold of the hysteresis comparator is set to be lower than the peak voltage of the high-level output of the PHY chip and higher than the low-level output of the PHY chip.

5. The LOS status detection circuit for an SFP optical module according to claim 1, characterized in that, The threshold comparison and decision module includes a comparator circuit to ensure that the power supply voltage matches the digital logic interface voltage of the SFP module.

6. The LOS status detection circuit for an SFP optical module according to claim 5, characterized in that, The threshold comparison and decision module also includes: pull-up resistors; One end of the pull-up resistor is connected to the output terminal of the threshold comparison and decision module, i.e., the LOS signal terminal; the other end is connected to the module's digital power supply, so that the LOS signal terminal is in a high-level state when there is no effective drive.

7. The LOS status detection circuit for an SFP optical module according to claim 5, characterized in that, The input inverting module, signal conditioning and pulse broadening module, and threshold comparison and decision module are integrated on the internal circuit board of the SFP module. The LOS signal output of the threshold comparison and decision module is connected to the hardware pin of the SFP module.

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