A power chip package structure and a manufacturing method thereof

Abstract

The application relates to the field of advanced packaging technology of integrated circuits, and particularly relates to a power chip packaging structure and a manufacturing method thereof. The power chip packaging structure is packaged with a power chip and a TVS chip, and the upper and lower ends of a conductive and heat-conductive connecting layer are connected with the TVS chip and the power chip to form a heat conduction path; the TVS chip and the power chip form a parallel circuit, and the TVS chip not only plays a role of overvoltage protection, but also serves as a temperature detection element of the power chip. The manufacturing method comprises the following steps: obtaining a chip, mounting the power chip, manufacturing the conductive and heat-conductive connecting layer, mounting the TVS chip, and manufacturing a redistribution layer. The application can realize overtemperature and overvoltage protection at the same time, reduce the cost of electronic components, reduce parasitic inductance, and adapt to a package-on-board process.

Description

Technical Field

[0001] This invention relates to the field of advanced packaging technology for integrated circuits, specifically to a power chip packaging structure and its over-temperature protection method and manufacturing method. Background Technology

[0002] In practical applications, power semiconductor devices face two core requirements: gate overvoltage protection and chip overtemperature protection. These are explained in detail below: I. Gate overvoltage protection requirements The gate of a power chip, serving as the control electrode, has an oxide film only a few hundred nanometers thick, making it structurally fragile and highly susceptible to electrostatic discharge (ESD) damage. Currently, the mainstream protection solution involves integrating a TVS (Transient Voltage Suppressor) diode into the circuit. When the gate experiences an ESD event, the TVS responds and performs overvoltage clamping. Existing methods for integrating TVS include: ① Integrating TVS chips on the power chip wafer layout can achieve protection, but TVS chips will occupy the effective area of ​​the wafer, which will significantly increase the cost of the power chip. ② Interconnection of discrete components: such as Figure 1 As shown, TVS chip 2 and power chip 1 are interconnected by planar wiring on the PCB board. The distance between their traces and package bonding wires can reach several millimeters or even centimeters. Excessive distance between traces and package bonding wires will significantly introduce parasitic inductance, such as... Figure 2 The diagram shows a TVS chip providing overvoltage protection for a power chip. When the gate experiences an electrostatic discharge event, the TVS responds and performs overvoltage clamping. ,in It is the voltage between the gate and the source. It is the clamping voltage of the TVS. It is a parasitic inductance. It is the rate of change of current. That is, the voltage drop generated by parasitic inductance, due to the ESD event. Up to 10 8 -10 12 Even inductors on the order of nH will generate an additional voltage drop of tens to hundreds of volts, resulting in A / s. The protection effect is not ideal when the voltage is too high.

[0003] II. Over-temperature protection requirements for power chips Junction temperature (the temperature of the PN junction inside a semiconductor device) is a critical parameter for measuring the operating status of power chips, assessing their lifespan, and ensuring reliable operation. It is essential to strictly prevent the junction temperature from exceeding the maximum limit during chip operation. Current technologies generally employ methods such as thermistors, infrared thermometry, or utilizing the chip's own temperature-sensitive electrical parameters (such as on-resistance and threshold voltage) for junction temperature monitoring. Thermistors are relatively large and require electrical insulation from the main chip, generally suitable for ceramic-based module packaging, resulting in poor versatility. Infrared thermometry cannot directly measure the chip's junction temperature, leading to poor measurement accuracy. Utilizing the power chip's own temperature-sensitive parameters typically requires complex measurement circuitry, and the monitoring process inevitably interferes with the chip's normal operating state.

[0004] In existing packaging solutions, overvoltage protection and overtemperature protection functions are separated, resulting in a complex system. Furthermore, both independent overvoltage and overtemperature protection solutions suffer from high costs or unsatisfactory protection effects. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a power chip packaging structure in which a TVS chip and a power chip form a direct heat conduction path and an overvoltage protection circuit. While providing overvoltage protection, the TVS chip can be reused as a temperature sensing element for the power chip, used for junction temperature detection and overtemperature protection. In another aspect, this invention provides a manufacturing method for the power chip packaging structure, which is compatible with existing board-level packaging processes.

[0006] The specific technical solution is as follows:

[0007] A power chip packaging structure, comprising: Power chips and TVS chips, the power chip having source pads and gate pads arranged on its front side and drain pads arranged on its back side, the TVS chip having cathode pads arranged on its front side and anode pads arranged on its back side. The conductive and thermally conductive connection layer is bonded to the anode pad of the TVS chip at its upper end and to the source pad of the power chip at its lower end, forming a direct heat conduction path. A dielectric layer and a first wiring layer are stacked on top of the power chip. An interconnecting via is provided through the dielectric layer to connect the power chip and the first wiring layer. The first wiring layer includes a patterned metal heat dissipation layer and a conductive and thermally conductive connection layer is connected to the metal heat dissipation layer. A dielectric layer and a second wiring layer are sequentially stacked and laminated on top of the first wiring layer and the TVS chip. The anode pad of the TVS chip is electrically connected to the source pad of the power chip through a conductive and thermally conductive connection layer, and the cathode pad of the TVS chip is electrically connected to the gate pad of the power chip through a second wiring layer, so that the TVS chip and the power chip form a parallel circuit. TVS chips not only provide overvoltage protection but also serve as temperature sensing elements for power chips.

[0008] The TVS chip and the power chip are connected vertically via a conductive and thermally conductive interconnect layer, replacing long, thin bonding wires and PCB traces. This reduces interconnect path length from millimeters or even centimeters to micrometers. Since inductance is proportional to wire length, parasitic inductance can be reduced by orders of magnitude. With extremely low parasitic inductance, when an electrostatic event occurs, transient current flows to the TVS chip almost without delay, immediately turning it on and clamping the voltage between the gate and source of the power chip to a lower level, closer to its nominal clamping voltage, providing more reliable overvoltage protection for the power chip.

[0009] The conductive and thermally conductive connection layer has multiple functions. First, it serves as a current transmission path, connecting not only the anode of the TVS chip to the source of the power chip, but also connecting to the first redistribution layer to export the anode signals of the TVS chip and the source signals of the power chip. Second, it serves as a carrier for the TVS chip, and its physical boundaries help improve the accuracy of TVS chip mounting and provide some protection for the power chip. Third, the conductive and thermally conductive connection layer also connects to the metal heat dissipation layer in the redistribution layer to export heat from the corresponding source areas.

[0010] The first wiring layer achieves electrical connection and heat dissipation with the power chip through interconnect vias, which can ensure the performance of the power chip and avoid the defects of traditional TVS chips directly bonding to the source of the power chip, occupying the source bonding area, reducing the number of wires due to the smaller wire bonding area (increased package resistance), uneven wire bonding (uneven current leading to local overheating), and excessively dense wire bonding (bonding wires are prone to crossing).

[0011] A direct heat conduction path is formed between the TVS chip and the power chip. The conductive and thermally conductive bonding layer is generally made of copper, but it can also be made of metals with excellent thermal conductivity, such as gold, silver, or nickel-gold alloys. The solder layer used to bond the TVS chip and the conductive and thermally conductive bonding layer is usually thin and also has good thermal conductivity. When the power chip is working, the junction temperature rises, and the heat is rapidly conducted to the TVS chip, causing the junction temperature of the TVS chip to change in the same direction as that of the power chip. Therefore, the TVS chip can be reused as a temperature sensor to monitor the junction temperature of the TVS chip and achieve over-temperature protection for the power chip.

[0012] Furthermore, the first wiring layer includes gate lead-out lines and source lead-out lines; One end of the gate lead-out line is electrically connected to the gate pad through a metallized hole, and the other end extends to the underside of the package through a metallized hole and is electrically connected to the external gate pad. One end of the source lead-out line is integrated with the conductive and thermally conductive connection layer, and the other end extends to the lower side of the package through a metallized hole and is electrically connected to the external source pad. The second wiring layer is electrically connected to the cathode pad and gate lead-out line of the TVS chip through metallized vias at both ends.

[0013] The first wiring layer is used to bring out the gate pad signal and source pad signal of the power chip and electrically connect them to the external gate pad and external source pad, respectively, so as to facilitate the connection with the external circuit. The second redistribution layer connects the cathode pads of the TVS chip to the gate pads of the power chip. Combined with the conductive and thermally conductive connection layer connecting the anode pads of the TVS chip to the source pads of the power chip, this forms a parallel circuit between the TVS chip and the power chip, achieving overvoltage protection. The redistribution layer manufacturing process allows for the design of the shortest and most direct interconnect traces for signal channels within the package structure. These interconnect paths can be shortened to the millimeter to micrometer level, approaching the interconnect paths within the chip itself, significantly reducing parasitic inductance and improving the overvoltage protection performance of the TVS chip. Furthermore, since there is no need to fabricate separate overvoltage protection circuits between chips in the external circuitry, the technical difficulty of using power chips is reduced.

[0014] Furthermore, a metal receiving groove is formed above the source pad. The metal receiving groove is formed simultaneously with the redistribution layer. The bottom layer of the metal receiving groove is pressed against the surface of the source pad. The TVS chip is mounted in the metal receiving groove. The bottom wall of the metal receiving groove is the conductive and thermally conductive connection layer.

[0015] A metal containment trench is formed above the source pads. This facilitates the mounting of TVS chips and improves mounting yield. On the other hand, the bottom wall of the metal containment trench is directly laminated to the surface of the source pads, and the conductive and thermally conductive bonding layer directly forms surface contact with the source pads. The contact area between the various material layers is enlarged to the bottom area of ​​the entire TVS chip, significantly reducing thermal resistance. This forms a direct heat conduction path of "source pad - conductive and thermally conductive bonding layer - solder layer - TVS chip". The junction temperature between the TVS chip and the power chip has good convergence, and the temperature detection sensitivity of the TVS is high.

[0016] Furthermore, the conductive lines of the redistribution layer have a standard thickness according to the required current carrying capacity. and standard width The thickness of the conductive and thermally conductive bonding layer and width With standard thickness and standard width The relationship simultaneously satisfies the following formula: ; ; .

[0017] To shorten the heat conduction path between the TVS chip and the power chip and improve the temperature detection sensitivity of the TVS chip, the thickness of the conductive and thermally conductive interconnect layer can be reduced through processes such as etching. Furthermore, since the conductive and thermally conductive interconnect layer also carries the source current of the power chip, its current-carrying capacity should not be less than that of the conductive lines in the redistribution layer. Since the current-carrying capacity is determined by the cross-sectional area, the cross-sectional area of ​​the thinned conductive and thermally conductive interconnect layer should not be less than that of the conductive lines in the redistribution layer. ; Furthermore, excessively thin conductive and thermally conductive interconnect layers may exhibit uneven thickness, affecting their current-carrying capacity. This invention limits their thickness to no less than half the standard thickness of the redistribution layer to meet redistribution layer process requirements and reduce the impact of thickness uniformity. ; By matching the thickness and width as described above, the current carrying capacity of the conductive and thermally conductive connection layer meets the requirements of the power chip's operation, while further shortening the thermal conduction distance and interconnection distance between the TVS chip and the power chip. This results in better overvoltage protection performance, better convergence of the junction temperature between the TVS chip and the power chip, and higher temperature detection sensitivity of the TVS chip.

[0018] Furthermore, the anode pads of the TVS chip have a copper plating layer on their surface, and the anode pads and the conductive and thermally conductive connection layer are metallurgically bonded together through a copper-copper bonding process.

[0019] This structure eliminates the solder layer, and the metallurgical bond formed between the copper layer of the anode pad of the TVS chip and the bottom of the tank has a seamless, integrated lattice structure. At this time, the thermal coupling path is further simplified to "source pad - bottom copper layer - TVS chip", which significantly reduces the thermal resistance. The junction temperature of the TVS chip is more similar to that of the power chip, and the temperature detection sensitivity of the TVS chip is higher.

[0020] Copper-copper bonding is based on the metal diffusion bonding mechanism. It promotes the interdiffusion of copper atoms across the interface through certain temperature, pressure or surface activation to form a metallurgical bonding interface. At present, there are many technologies that can achieve low-temperature (below 250℃) copper-copper bonding, such as surface activation low-temperature bonding, formic acid vapor-assisted low-temperature bonding, and hybrid bonding. In this way, the TVS chip is not damaged and a good bonding effect can be achieved.

[0021] Furthermore, the anode pads of the TVS chip are soldered to the conductive and thermally conductive connection layer using a silver sintering process, resulting in a solder void rate of less than 3%.

[0022] Conventional solders, such as tin-silver-copper solders, have an electrical conductivity of approximately 50-60 W / (m·K), much lower than that of copper, resulting in relatively high thermal resistance during heat conduction. Silver sintered solder, however, uses metallic silver as its layer. Silver-based alloy solders, whose main components are silver, copper, and zinc, have melting points between 660-725℃. They have low heating temperatures, minimal workpiece deformation, and can achieve the joining of dissimilar materials. They also possess excellent electrical conductivity, with a thermal conductivity of 200-300 W / (m·K), approaching the thermal conductivity of copper (400 W / (m·K), significantly reducing thermal resistance. Furthermore, using the silver sintering process, the anode pads of TVS chips do not require an additional copper plating layer. Therefore, silver sintering is a superior process for achieving low thermal resistance.

[0023] Furthermore, the conductive and thermally conductive connection layer is: a metallized hole array; Alternatively, the conductive and thermally conductive connection layer includes: a metallized hole array, and a hole interconnect layer connecting the metallized holes in the metallized hole array.

[0024] The via cavity is filled with solid copper. The via array simultaneously performs electrical and thermal conductivity functions. Due to the excellent thermal conductivity of copper, the heat from the source region of the power chip can be quickly conducted to the conductive and thermally conductive connection layer, realizing a low thermal resistance thermal conduction path between the TVS chip and the power chip: "source pad - via array - conductive and thermally conductive connection layer - solder layer - TVS chip".

[0025] Under different operating conditions, power chips may have uneven internal current density, resulting in inconsistent temperature rise rates in different areas of the source pad surface. This, in turn, leads to uneven thermal conductivity of the metallized vias connecting different areas, affecting the accuracy of the TVS chip's temperature response. By setting a via interconnect layer in the conductive and thermally conductive connection layer to connect the metallized vias in the array, heat can be rapidly and evenly diffused in the via interconnect layer before being transferred to the TVS chip, making the TVS chip's temperature response more accurate.

[0026] Furthermore, the conductive and thermally conductive connection layer includes a metallized hole array, which is divided into multiple sub-arrays according to the region. Each sub-array is connected to a sub-array interconnection layer, and the sub-array interconnection layers are independent of each other. The subarray interconnect layer is also connected to a subarray output line, which is used to connect to an external heat dissipation component.

[0027] When the temperature of a power chip is too high, reducing power consumption may affect its performance. By dividing the metallized hole array into multiple sub-arrays, each sub-array is connected to an external heat dissipation component through a sub-array interconnect layer and a sub-array lead-out line. By turning off or on different numbers or different areas of the external heat dissipation component, different heat dissipation effects can be achieved, which is conducive to the stable operation of the power chip.

[0028] Another aspect of the present invention provides a method for manufacturing a power chip package structure, for manufacturing any of the aforementioned power chip package structures, comprising the following steps: A. Obtaining chips: Obtaining a power chip and a TVS chip, wherein the power chip has a source pad and a gate pad arranged on its front side and a drain pad arranged on its back side, and the TVS chip has a cathode pad arranged on its front side and an anode pad arranged on its back side. B. Power chip mounting: A base island pattern layer is fabricated at one end of the separable copper foil, and the power chip is mounted on the base island pattern layer. C. Fabrication of conductive and thermally conductive connection layer: The power chip is encapsulated, and a conductive and thermally conductive connection layer and a first redistribution layer are formed through a redistribution layer manufacturing process; D. TVS chip mounting: The TVS chip is mounted on the conductive and thermally conductive connection layer, so that the upper end of the conductive and thermally conductive connection layer is bonded to the anode pad of the TVS chip, and the lower end is connected to the source pad of the power chip, forming a direct heat conduction path; the anode pad of the TVS chip is electrically connected to the source pad of the power chip through the conductive and thermally conductive connection layer. E. Manufacturing the second redistribution layer: A dielectric layer is laminated on top of the TVS chip and the first redistribution layer. The second redistribution layer is manufactured using a redistribution layer manufacturing process, so that the cathode pad of the TVS chip is electrically connected to the gate pad of the power chip through the redistribution layer; the TVS chip and the power chip form a parallel circuit.

[0029] Furthermore, the specific method for fabricating the conductive and thermally conductive connection layer is as follows: A hole is drilled in the molding compound above the power chip to the surface of the source pad and metallized to form a metallized hole array; The metallized via array is divided into multiple sub-arrays by region, and a redistribution layer process is used to fabricate the sub-array via interconnect layer and sub-array lead-out lines.

[0030] Furthermore, the conductive and thermally conductive connection layer is formed simultaneously with the redistribution layer.

[0031] The manufacturing process of the redistribution layer includes: laser drilling and slotting in the molding layer, followed by metallization to form metallized holes and metallized grooves, and then using processes such as pattern transfer and electroplating to form the redistribution layer circuit. The conductive and thermally conductive connection layer in this invention can be formed during the metallization process or during the manufacturing process of the redistribution layer circuit.

[0032] The simultaneous formation of the conductive and thermally conductive connection layer and the redistribution layer can save manufacturing process steps and reduce manufacturing costs. On the other hand, it can eliminate the interface contact resistance and potential defects between the two, improve the reliability and current carrying capacity of electrical connections, reduce parasitic parameters in the signal transmission process, and improve signal integrity and thermomechanical stability. Thirdly, by bringing out the electrical signals of the source pads through the conductive and thermally conductive connection layer and the redistribution layer, the problem of uneven distribution of solder lines caused by the fixed position and limited area of ​​the source pads can be avoided, and the pad positions can be flexibly redistributed, improving the reliability and compatibility of the package structure.

[0033] In summary, this invention discloses a power chip packaging structure and its manufacturing method. The beneficial effects of this invention using the above-described solution are as follows: 1. Form an overvoltage protection circuit and a direct heat conduction path for the TVS chip and the power chip, so that the TVS chip can play the role of overvoltage protection while also serving as a temperature detection element for the power chip. 2. The packaging structure of this invention significantly shortens the physical size of the overvoltage protection circuit and reduces the interconnection path length to the micrometer level, thereby greatly reducing parasitic inductance. When the gate of the power chip is threatened by overvoltage, the TVS chip can respond in a very short time and clamp the voltage of the power chip within a safe range, providing reliable protection for the power chip. 3. By reusing the TVS chip as an in-situ integrated temperature sensor, no additional sensor chip is needed, which significantly reduces the package size and manufacturing cost; 4. TVS chips and power chips are vertically stacked through a redistribution layer, which avoids the problem of reduced effective bonding size due to the occupation of the source pad area of ​​the power chip, and uneven wire distribution affecting the performance of the power chip. 5. The integrated packaging design reduces the number of discrete components and external interconnects, lowers the risk of failure due to solder joints and contact resistance, and enhances mechanical strength and vibration resistance. This allows the overall structure to maintain stable operation in harsh environments such as high temperature, high humidity, and high impact, significantly improving the long-term reliability of the system.

[0034] To further understand the features and technical content of this invention, please refer to the following detailed description and accompanying drawings. However, these descriptions and drawings are only for illustrating the invention and are not intended to limit the scope of protection of the invention in any way. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the discrete interconnection between a metal TVS chip and a power chip in existing technology; Figure 2 This is a circuit diagram of an existing TVS chip for overvoltage protection of a power chip; Figure 3This is a schematic diagram of a power chip packaging structure according to Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the first redistribution layer in Embodiment 1 of the present invention; Figure 5 yes Figure 3 Enlarged view of point A in the middle; Figure 6 This is a schematic diagram of the heat conduction path in Embodiment 1 of the present invention; Figure 7 This is a schematic diagram of the TVS chip's temperature-sensing parameters and temperature curve. Figure 8 This is a schematic diagram of a power chip packaging structure according to Embodiment 2 of the present invention; Figure 9 This is a schematic diagram of a power chip packaging structure according to Embodiment 3 of the present invention; Figure 10 This is a schematic diagram of the heat conduction path in Embodiment 3 of the present invention; Figure 11 This is a schematic diagram of a power chip packaging structure according to Embodiment 4 of the present invention; Figure 12 This is a schematic diagram of the planar layering of the conductive and thermally conductive connection layer in Embodiment 4 of the present invention; Figure 13 This is a schematic diagram of the carrier core plate and separable copper foil in the manufacturing method of the present invention; Figure 14 This is a schematic diagram of the base island pattern layer in the manufacturing method of the present invention; Figure 15 This is a schematic diagram of the power chip mounting process in the manufacturing method of this invention; Figure 16 This is a schematic diagram of the first molding layer in the manufacturing method of the present invention; Figure 17 This is a schematic diagram of drilling and window opening in the manufacturing method of the present invention; Figure 18 This is a schematic diagram of the first rewiring layer in the manufacturing method of the present invention; Figure 19 This is a schematic diagram of mounting a TVS chip and forming a second molding layer in the manufacturing method of the present invention; Figure 20 This is a schematic diagram of drilling in the manufacturing method of the present invention; Figure 21 This is a schematic diagram of the second wiring layer in the manufacturing method of the present invention; Figure 22 This is a schematic diagram of the second rewiring layer in the molding process of the present invention; Figure 23 This is a schematic diagram of the process of removing the insulating medium and carrier core plate in the manufacturing method of this invention; Figure 24 This is a schematic diagram of etching a separable copper foil to form an external solder pad in the manufacturing method of the present invention.

[0036] In the picture: 1-Power chip; 12-Source pad; 13-Gate pad; 14-Drain pad; 2-TVS chip; 21-Anode pad; 211-Copper plating; 22-Cathode pad; 3-Metal reservoir; 31-Conductive and thermally conductive connection layer; 311-Metalized via array; 3111-Sub-array; 3112-Sub-array via interconnect layer; 3113-Sub-array lead-out line; 312-Through-interconnect layer; 4-Base island patterning layer; 41-Die substrate island; 42-Gate bonding finger; 43-Source bonding finger; 5-First redistribution layer; 51-Gate lead-out line; 52-Source lead-out line; 53-Metal heat dissipation layer; 6-Second redistribution layer; 7-Solder layer; 81-Carrier core board; 82-Insulating medium; 83-Separable copper foil. Detailed Implementation

[0037] The following is in conjunction with the appendix Figures 3 to 23 The present invention provides a further description of a power chip packaging structure and its manufacturing method.

[0038] Example 1 Figures 3 to 4 The diagram shows a power chip package structure according to a first embodiment of the present invention, which includes: Power chip 1 and TVS chip 2, wherein the power chip 1 has a source pad 12 and a gate pad 13 arranged on its front side and a drain pad 14 arranged on its back side, and the TVS chip 2 has a cathode pad 22 arranged on its front side and an anode pad 21 arranged on its back side. A metal receiving groove 3 is formed above the source pad 12. The metal receiving groove 3 is formed simultaneously with the first redistribution layer 5. The bottom layer of the metal receiving groove 3 is pressed against the surface of the source pad 12. The TVS chip 2 is mounted in the metal receiving groove 3. The bottom wall of the metal receiving groove 3 is a conductive and thermally conductive connection layer 31. The upper end of the conductive and thermally conductive connection layer 31 is bonded to the anode pad 21 of the TVS chip 2, and the lower end is connected to the source pad 12 of the power chip 1, forming a direct heat conduction path. A dielectric layer and a first redistribution layer 5 are stacked and laminated on top of the power chip 1. Interconnection vias and heat-conducting vias are disposed through the dielectric layer to connect the power chip 1 and the first redistribution layer 5. The first redistribution layer 5 includes a patterned metal heat dissipation layer 53. The conductive and thermally conductive connection layer 31 is connected to the metal heat dissipation layer 53. A dielectric layer and a second wiring layer 6 are sequentially stacked and laminated on top of the first wiring layer 5 and the TVS chip 2. The anode pad 21 of the TVS chip 2 is electrically connected to the source pad 12 of the power chip 1 through the conductive and thermally conductive connection layer 31, and the cathode pad 22 of the TVS chip 2 is electrically connected to the gate pad 13 of the power chip 1 through the second redistribution layer 6, so that the TVS chip 2 and the power chip 1 form a parallel circuit. The first redistribution layer 5 includes a gate lead-out line 51 and a source lead-out line 52; One end of the gate lead-out line 51 is electrically connected to the gate pad 13 through a metallized hole, and the other end extends to the lower side of the package through a metallized hole and is electrically connected to the external gate pad. One end of the source electrode output line 52 is integrally connected to the conductive and thermally conductive connection layer 31, and the other end extends to the lower side of the package through a metallized hole and is electrically connected to the external source electrode pad. The two ends of the second redistribution layer 6 are electrically connected to the cathode pad 22 and the gate lead-out line 51 of the TVS chip 2 through metallized holes, respectively.

[0039] The TVS chip 2 not only serves as overvoltage protection, but also as a temperature detection element for the power chip 1.

[0040] like Figure 3 , Figure 5 As shown, in some embodiments, the surface of the anode pad 21 of the TVS chip 2 has a copper plating layer 211, and the anode pad 21 and the conductive and thermally conductive connection layer 31 are metallurgically bonded by a copper-copper bonding process.

[0041] like Figure 6 As shown, the conductive lines of the redistribution layer have a standard thickness according to the required current carrying capacity. and standard width The thickness of the conductive and thermally conductive connection layer 31 and width With the standard thickness and standard width The relationship simultaneously satisfies the following formula: ; ; .

[0042] Figure 5The diagram shows the direct heat conduction path between the TVS chip 2 and the power chip 1 formed by a power chip packaging structure according to the first embodiment of the present invention: "Source pad 12 - conductive and thermally conductive connection layer 31 - anode pad 21". Since the parameters of the source pad 12, the copper layer at the bottom of the trench (conductive and thermally conductive connection layer 31), and the substrate of the TVS chip 2 are fixed and all have good thermal conductivity, the junction temperature of the TVS chip 2 is correlated with the junction temperature of the power chip 1. The junction temperature of the power chip 1 can be indirectly obtained by monitoring the junction temperature of the TVS chip 2. Based on this, over-temperature protection of the power chip 1 can be achieved by setting a junction temperature threshold and other means.

[0043] In some embodiments, the over-temperature protection method based on the above power chip package structure includes the following steps: S10 Measurement of the temperature-sensitive parameters of TVS chip 2 - junction temperature model curve; S20 is based on the design and measurement of the direct heat conduction path and the temperature-junction temperature model of the TVS chip 2. The curve calibrates the maximum junction temperature difference between TVS chip 2 and power chip 1. ; When S30 power chip 1 is working, the junction temperature of TVS chip 2 is measured. Calculate the simulated junction temperature of power chip 1. ; S40 is based on the maximum junction temperature threshold specified in the power chip 1 design. Set a junction temperature critical region [ , ),in As a preset safety margin, when the simulated junction temperature value Entering the junction temperature critical region [ , ( ), or, reaching or exceeding the maximum junction temperature threshold. In this case, the power consumption level of the power chip 1 is reduced or heat dissipation is enhanced to reduce the junction temperature, thereby achieving over-temperature protection.

[0044] TVS chips have the following temperature-sensitive parameters: The reverse breakdown voltage VBR, forward voltage drop VF, and reverse leakage current IR of a TVS chip are typical temperature-sensitive parameters. The forward voltage drop VF is linearly negatively correlated with the junction temperature. The reverse breakdown voltage VBR exhibits different temperature characteristics depending on the voltage range. When the TVS chip is reverse biased and has not reached the breakdown voltage VBR, the reverse leakage current IR is in the reverse cutoff region, at which time only a small reverse leakage current flows. This leakage current IR increases significantly with increasing temperature.

[0045] Based on the aforementioned temperature-sensitive parameter characteristics, the junction temperature of the TVS chip can be obtained by monitoring one of its temperature-sensitive parameters.

[0046] The specific method for establishing the temperature-sensing parameter-temperature curve (K1 curve) of TVS chip 2 is as follows: The entire package structure is placed in a temperature-controlled test chamber. Several test temperature points are set, such as -25℃, 0℃, 25℃, 50℃, 75℃, 100℃, 125℃, 150℃, and 175℃. At each temperature point, a preset holding time (5-30 minutes) is established until the chip in the package structure reaches thermal equilibrium with the ambient temperature. The temperature-sensing parameters of TVS chip 2 are then tested. After obtaining the temperature-sensing parameters at all temperature points, a linear relationship between the temperature-sensing parameters and temperature is fitted to obtain the temperature-sensing parameter-temperature curve. Curve. At this point, the temperature-sensitive parameter of the TVS can be selected from one of the following: forward voltage drop VF, reverse breakdown voltage VBR, and reverse leakage current IR. Figure 7 This shows a reverse leakage current-junction temperature. Schematic diagram of the curve.

[0047] When power chip 1 is working, it measures the temperature-sensitive parameters of TVS chip 2 and substitutes the measured temperature-sensitive parameter values ​​into the corresponding... The curve shows the junction temperature of TVS chip 2. Calculate the simulated junction temperature of power chip 1 using the following formula. : .

[0048] According to the maximum junction temperature threshold specified in the power chip 1 design. Set a junction temperature critical region [ , ),in As a preset safety margin, when the simulated junction temperature value Entering the junction temperature critical region [ , ( ), or, reaching or exceeding the maximum junction temperature threshold. In this case, the power consumption level of the power chip 1 is reduced or heat dissipation is enhanced to reduce the junction temperature, thereby achieving over-temperature protection.

[0049] Example 2 like Figure 8 The diagram shows the power chip packaging structure of the second embodiment of the present invention. The difference from the first embodiment is that the conductive and thermally conductive connection layer 31 in this embodiment is a metallized hole array 311; the TVS chip 2 is soldered and mounted on the upper end of the metallized hole array 311; the lower end of the metallized hole in the metallized hole array 311 is connected to the source pad 12, and the upper end is connected to the anode pad 21 of the TVS chip 2.

[0050] One end of the source lead-out line 52 is electrically connected to the source pad 12 through a metallized hole, and the other end extends to the lower side of the package through a metallized hole and is electrically connected to the external source pad. The rest of the structure is the same as in Example 1.

[0051] The metallized via array provides an efficient vertical heat conduction path between the source pad 12 of the power chip 1 and the anode pad 21 of the TVS chip 2. Since the source pad surface exhibits uneven heat generation and inconsistent temperature rise rates in different areas, the number, diameter, and arrangement of the vias can be optimized based on the heat distribution on the source pad surface; for example, denser vias can be placed in high-heat areas.

[0052] Example 3 like Figure 9 The diagram shows a power chip packaging structure according to a third embodiment of the present invention. The difference from embodiment 1 is that the conductive and thermally conductive connection layer 31 in this embodiment includes a metallized hole array 311 and a hole interconnect layer 312 that connects all the metallized holes in the metallized hole array 311. The TVS chip 2 is mounted on the upper end of the hole interconnect layer 312. The lower end of the metallized holes in the metallized hole array 311 is connected to the source pad 12, and the upper end is connected to the lower end of the hole interconnect layer 312. The anode pad 21 of the TVS chip 2 is soldered to the interconnect layer 312 using a silver sintering process to form a solder layer 7 with a solder void rate of less than 3%.

[0053] Figure 10 The diagram shows the direct heat conduction path between a TVS chip 2 and a power chip 1 formed by a power chip packaging structure according to a second embodiment of the present invention: "Source pad 12 - Metallized via array 311 - Via interconnect layer 312 - Solder layer 7 - TVS chip 2". Since the parameters of the source pad 12, metallized via array 311, via interconnect layer 312, solder layer 7, and TVS chip 2 substrate are fixed and all have good thermal conductivity, the junction temperature of the TVS chip 2 is correlated with the junction temperature of the power chip 1. The junction temperature of the power chip 1 can be indirectly obtained by monitoring the junction temperature of the TVS chip 2. Based on this, over-temperature protection of the power chip 1 can be achieved by setting a junction temperature threshold or other means.

[0054] The interconnect layer 312 can uniformize the uneven heat generation in the source pad area, making the junction temperature change of TVS chip 2 more stable and facilitating better monitoring of the junction temperature of power chip 1.

[0055] Example 4 like Figure 11 The power chip packaging structure shown is the fourth embodiment of the present invention. The difference from embodiment 3 is that the conductive and thermally conductive connection layer 31 includes: a metallized hole array 311. The metallized hole array 311 is divided into multiple sub-arrays 3111 according to the region. Each sub-array 3111 is connected to a sub-array hole interconnect layer 3112. The sub-array hole interconnect layers 3112 are independent of each other and together constitute the hole interconnect layer 312. The subarray via interconnect layer 3112 is also connected to a subarray output line 3113, which is used to connect to an external heat dissipation component.

[0056] One end of the source lead-out line 52 is electrically connected to the source pad 12 through a metallized hole, and the other end extends to the lower side of the package through a metallized hole and is electrically connected to the external source pad; the rest of the structure is the same as in Embodiment 3.

[0057] Figure 12 The diagram shown is a planar layered schematic of the conductive and thermally conductive connection layer 31 in the fourth embodiment.

[0058] Example 5 A method for manufacturing a power chip package structure, such as Figures 13 to 24 As shown, it includes the following steps: A. Obtaining chips: Obtain power chip 1 and TVS chip 2. The power chip 1 has a source pad 12 and a gate pad 13 arranged on its front side and a drain pad 14 arranged on its back side. The TVS chip 2 has a cathode pad 22 arranged on its front side and an anode pad 21 arranged on its back side. B. Power chip mounting: A base island pattern layer 4 is fabricated at one end of the separable copper foil 83, and the power chip 1 is mounted on the base island pattern layer 4. In some alternative embodiments, an insulating medium 82 and a separable copper foil 83 are laminated onto a carrier core board 81, wherein the insulating medium 82 may be a prepreg or a molding compound; a base island pattern layer 4 is formed at one end of the separable copper foil 83 by copper electroplating and etching processes, the base island pattern layer 4 including a substrate island 41, gate bonding fingers 42 and source bonding fingers 43; the power chip 1 is mounted on the substrate island 41, with the drain pad 14 of the power chip 1 facing the substrate island 41; The pads of power chip 1 are usually made of aluminum, which is easily oxidized in the air to form a dense, non-conductive aluminum oxide film on the surface. This affects the wettability of the solder and the electrical performance after soldering. It is not easy to maintain stability during high-temperature reflow soldering and is also prone to stress caused by the mismatch between the coefficient of thermal expansion and the redistribution layer. Before mounting, the front pads of power chip 1 are metallized. Specifically, a metal layer with a thickness of 0.1-3μm is first deposited on the aluminum pad by vapor deposition or sputtering. The metal can be selected from titanium, nickel, silver, or copper. Then, a thicker copper layer is electroplated. The thickness of the thickened copper layer can be 5-30μm. The mounting method can use reflow soldering, and the soldering residue should be removed after soldering is completed; C. Fabrication of conductive and thermally conductive connection layer: The plastic-encapsulated power chip 1 forms a conductive and thermally conductive connection layer 31 through a redistribution layer manufacturing process; Specifically, the plastic-encapsulated power chip 1 and the base island pattern layer 4 form a first plastic-encapsulated layer; drilling, slotting, and metallizing are performed to fabricate the conductive and thermally conductive connection layer 31 and the first redistribution layer 5; In some alternative implementations, the manufacturing process includes: Drilling and windowing: Drill holes from the first molding layer to the gate bonding finger 42, the source bonding finger 43, and the gate pad 13 to form vias; create grooves from the first molding layer to expose part of the surface of the source pad 12, with the outline size of the groove slightly larger than the external size of the TVS chip 2. Metallization and patterning process: The above holes and trenches are metallized to form metallized vias and metal receiving trenches 3 by subtractive or modified semi-additive processes, and gate lead-out lines 51 and source lead-out lines 52 are formed on the surface of the first molding layer. The size parameters of the metallized vias, metal receiving trenches 3 and lines can be determined according to the current requirements of the power chip 1 and the processing capabilities. The bottom of the metal receiving tank 3 is the conductive and thermally conductive connecting layer 31. In some alternative implementations, the manufacturing process includes: A metallized via array 311 is formed by drilling holes from the first molding layer to a portion of the surface of the source pad 12. In some alternative implementations, the manufacturing process includes: A hole interconnect layer 312 is formed by a patterning process, which connects all the metallized holes in the array of all metallized holes 311. In some alternative implementations, the manufacturing process includes: The metallized via array 311 is divided into multiple sub-arrays 3111 according to the region, and the sub-array via interconnect layer 3112 and sub-array lead-out line 3113 are fabricated using the redistribution layer fabrication process. D. TVS chip mounting: TVS chip 2 is mounted on the conductive and thermally conductive connection layer 31, so that the upper end of the conductive and thermally conductive connection layer 31 is bonded to the anode pad 21 of TVS chip 2, and the lower end is connected to the source pad 12 of power chip 1, forming a direct heat conduction path; the anode pad 21 of TVS chip 2 is electrically connected to the source pad 12 of power chip 1 through the conductive and thermally conductive connection layer 31. Specifically, the anode pad 21 faces the conductive and thermally conductive connection layer 31; the mounting process of the TVS chip 2 can be selected from one of the following: high thermal conductivity soldering, silver sintering, or copper-copper bonding. To ensure the welding quality, X-ray, ultrasonic testing, and other methods can be used to check the integrity of the solder joints to ensure that the defects of cold solder joints and voids are within an acceptable range, such as a void rate of <3%; E. Manufacturing the redistribution layer: The TVS chip 2 is plastic-encapsulated, and the cathode pad 22 of the TVS chip 2 is electrically connected to the gate pad 13 of the power chip 1 through the redistribution layer manufacturing process; the TVS chip 2 and the power chip 1 form a parallel circuit. Specifically, the TVS chip 2 is mounted in the metal receiving groove 3, and the TVS chip 2, the metal receiving groove 3 and the first redistribution layer 5 are molded to form a second molding layer; Drilling: Drill holes from the surface of the second molding layer to the gate lead-out line 51 and the cathode pad 22 of the TVS chip 2 respectively; Metallization and patterning process: The above-mentioned openings are metallized to form metallized vias using subtractive or modified semi-additive processes. The metallized via cavity connecting the gate lead-out line 51 is filled with solid copper using an electroplating filling process. A line connecting the gate lead-out line 51 and the TVS chip cathode pad 22 is formed on the surface of the second molding layer. The second rewiring layer 6 is encapsulated, and the insulating medium 82 and carrier core board 81 on the lower surface of the separable copper foil 83 are removed; F. The separable copper foil 83 is etched to form external solder pads, and then cut to obtain a single finished product.

Claims

1. A power chip packaging structure, characterized in that the packaging... have: The power chip (1) and the TVS chip (2) have a source pad (12) and a gate pad (13) arranged on its front side and a drain pad (14) arranged on its back side, and the TVS chip (2) has a cathode pad (22) arranged on its front side and an anode pad (21) arranged on its back side. A conductive and thermally conductive connection layer (31) is formed by bonding the upper end of the conductive and thermally conductive connection layer (31) to the anode pad (21) of the TVS chip (2) and the lower end to the source pad (12) of the power chip (1). A dielectric layer and a first redistribution layer (5) are stacked and laminated on top of the power chip (1). An interconnecting via is provided through the dielectric layer to connect the power chip (1) and the first redistribution layer (5). The first redistribution layer (5) includes a patterned metal heat dissipation layer (53). The conductive and thermally conductive connection layer (31) is connected to the metal heat dissipation layer (53). A dielectric layer and a second wiring layer (6) are stacked and laminated on top of the first wiring layer (5) and the TVS chip (2). The anode pad (21) of the TVS chip (2) is electrically connected to the source pad (12) of the power chip (1) through the conductive and thermally conductive connection layer (31), and the cathode pad (22) of the TVS chip (2) is electrically connected to the gate pad (13) of the power chip (1) through the second redistribution layer (6), so that the TVS chip (2) and the power chip (1) form a parallel circuit; The TVS chip (2) is the temperature detection element of the power chip (1).

2. The power chip packaging structure as described in claim 1, characterized in that, The first redistribution layer (5) includes a gate lead-out line (51) and a source lead-out line (52). One end of the gate lead-out line (51) is electrically connected to the gate pad (13) through a metallized hole, and the other end extends to the lower side of the package through a metallized hole and is electrically connected to the gate external pad. One end of the source lead-out line (52) is integrally connected to the conductive and thermally conductive connection layer (31), and the other end extends to the lower side of the package through the metallized hole and is electrically connected to the external source pad. The second redistribution layer (6) is electrically connected to the cathode pad (22) and gate lead-out line (51) of the TVS chip (2) through metallized holes at both ends.

3. The power chip packaging structure as described in claim 1, characterized in that, A metal receiving groove (3) is formed above the source pad (12). The metal receiving groove (3) is formed synchronously with the redistribution layer. The bottom layer of the metal receiving groove (3) is pressed against the surface of the source pad (12). The TVS chip (2) is mounted in the metal receiving groove (3). The bottom wall of the metal receiving groove (3) is the conductive and thermally conductive connection layer (31).

4. The power chip packaging structure as described in claim 3, characterized in that, The conductive lines of the rewiring layer have a standard thickness according to the required current carrying capacity. and standard width The thickness of the conductive and thermally conductive connection layer (31) and width With the standard thickness and standard width The relationship simultaneously satisfies the following formula: ; ; .

5. The power chip packaging structure as described in claim 1, characterized in that, The surface of the anode pad (21) of the TVS chip (2) has a copper plating layer (211), and the anode pad (21) and the conductive and thermally conductive connection layer (31) are metallurgically bonded by a copper-copper bonding process.

6. The power chip packaging structure as described in claim 1, characterized in that, The anode pad (21) of the TVS chip (2) is welded to the conductive and thermally conductive connection layer (31) using a silver sintering process, with a welding void rate of less than 3%.

7. The power chip packaging structure as described in claim 2, characterized in that, The conductive and thermally conductive connection layer (31) is: a metallized hole array (311). Alternatively, the conductive and thermally conductive connection layer (31) may include: a metallized hole array (311) and a hole interconnect layer (312) that connects the metallized holes in the metallized hole array (311).

8. The power chip packaging structure as described in claim 2, characterized in that, The conductive and thermally conductive connection layer (31) includes: a metallized hole array (311), which is divided into multiple sub-arrays (3111) according to the region. Each sub-array (3111) is connected to a sub-array hole interconnection layer (3112). The sub-array hole interconnection layers (3112) are independent of each other and together constitute the hole interconnection layer (312). The subarray interconnect layer (3112) is also connected to a subarray output line (3113), which is used to connect to an external heat dissipation component.

9. A method for manufacturing a power chip package structure, characterized in that, For manufacturing the power chip package structure as described in any one of claims 1-8, the following steps are included: A. Obtaining chips: Obtaining a power chip (1) and a TVS chip (2), wherein the power chip (1) has a source pad (12) and a gate pad (13) arranged on its front side and a drain pad (14) arranged on its back side, and the TVS chip (2) has a cathode pad (22) arranged on its front side and an anode pad (21) arranged on its back side. B. Power chip mounting: A base island pattern layer (4) is made at one end of the separable copper foil (83), and the power chip (1) is mounted on the base island pattern layer (4). C. Fabrication of conductive and thermally conductive connection layer: The power chip (1) is encapsulated, and a conductive and thermally conductive connection layer (31) and a first redistribution layer (5) are formed through a redistribution layer manufacturing process. D. TVS chip mounting: The TVS chip (2) is mounted on the conductive and thermally conductive connection layer (31), so that the upper end of the conductive and thermally conductive connection layer (31) is bonded to the anode pad (21) of the TVS chip (2), and the lower end of the conductive and thermally conductive connection layer (31) is connected to the source pad (12) of the power chip (1), forming a direct heat conduction path; and the anode pad (21) of the TVS chip (2) is electrically connected to the source pad (12) of the power chip (1) through the conductive and thermally conductive connection layer (31); E. Manufacturing the second redistribution layer: A dielectric layer is laminated on the TVS chip (2) and the first redistribution layer (5), and the second redistribution layer (6) is manufactured by the redistribution layer manufacturing process, so that the cathode pad (22) of the TVS chip (2) is electrically connected to the gate pad (13) of the power chip (1) through the redistribution layer; the TVS chip (2) and the power chip (1) form a parallel circuit.

10. The manufacturing method as described in claim 9, characterized in that, The method for fabricating the conductive and thermally conductive connection layer (31) is as follows: A hole is drilled in the molding layer above the power chip (1) to the surface of the source pad (12) and metallized to form a metallized hole array (311). The metallized via array (311) is divided into multiple sub-arrays (3111) according to the region. The sub-array via interconnect layer (3112) and sub-array outgoing lines (3113) are fabricated using the redistribution layer process.

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