System-in-package substrate and processing method thereof

Abstract

The application discloses a kind of system-in-package substrate and its processing method, comprising: the intermediate plate formed with ultra-thick copper micro pitch circuit pattern is prepared, the relative length difference between multiple SET plate board edge area B of the intermediate plate and the reentrant lead connected with circuit pattern is not more than 15% respectively made out;Thermally reformed characteristic photosensitive insulating resin film and first ink dry film are stacked on the intermediate plate to fill the micro gap between circuit pattern;Part of the composite insulating film is removed to expose circuit pattern and reentrant lead;Make out solder mask layer and electroplated gold layer, control height difference between electroplated gold layer and solder mask layer ≤5 μm.The processing method is simple, easy to implement, and the system-in-package substrate obtained meets the technical requirements of high-density integrated packaging, ultra-high heat dissipation, resin-filled circuit pattern, ink thickness on copper surface ultra-thin, height difference between soldering surface and solder mask layer ≤5 μm, etc.;Promote the development of system-in-package technology.

Description

Technical Field

[0001] This invention relates to the field of packaging substrate technology, and in particular to a system-in-package substrate and its processing method. Background Technology

[0002] With the development of society and science and technology, the development of system-in-package (SiP) substrates is no longer merely about providing electrical connections, but has evolved into a core technology that determines the performance, cost, and reliability of the entire system. The current and future development trend of SiP substrates is to simultaneously meet the requirements of high-density integrated packaging and ultra-high heat dissipation. Specifically, SiP substrates must meet the following technical parameters: copper thickness ≥ 60 μm, micro-pitch ≤ 30 μm, ink thickness ≤ 12 μm, and height difference between the ink surface and the solder surface ≤ 8 μm.

[0003] However, existing system-in-package (SIPP) substrate fabrication processes have the following shortcomings when implemented: ① To address the need for both fine-pitch and thick copper, the current common practice is to perform a secondary plating process after etching the circuit pattern, involving pulling leads. However, the thick copper etching process can lead to a significant increase in lateral etching, making it difficult to precisely control the line width within 30μm. Furthermore, the lateral etching can further reduce the effective spacing between dense lines, increasing the risk of short circuits. At the same time, the secondary plating process can amplify the surface roughness of the circuit, affecting the impedance consistency of high-frequency signal transmission.

[0004] ② When the copper thickness is ≥50μm, in order to cover the height difference of the copper surface and achieve an insulation thickness of ≥18μm, traditional processes are forced to use 2-3 layers of solder resist printing. However, multiple solder resist printings not only produce cumulative deviations, but also easily cause defects such as oil flow, bubbles, and pinholes at the edges of thick copper lines. More seriously, multiple layers of curing lead to a sharp increase in residual stress inside the ink, and the excessively thick ink layer expands / contracts far more than the substrate when subjected to high and low temperature thermal cycling, which easily causes micro-cracks or even "burst holes" at the corners of the lines, weakening the long-term reliability of the product.

[0005] ③ In right-angle corners and densely packed areas of thick copper circuits, due to the thixotropic and fluid properties of the ink, conventional screen printing or spraying is difficult to achieve conformal coverage, often resulting in reddish edges (exposed copper) or missed gold plating. These localized weak protection areas can lead to high-voltage breakdown or electrochemical migration. In subsequent PCBA assembly, the highly active flux from wave soldering can easily penetrate along these microcracks or gaps, weakening the long-term reliability of the product.

[0006] ④ To meet the insulation requirements of thick copper plates, existing processes often result in an excessively thick solder mask layer, causing a height difference of more than 8μm between the ink surface and the solder surface. During flip-chip packaging, this height difference directly disrupts the coplanarity of the solder balls, leading to incomplete soldering or uneven stress on some joints. To compensate for the reliability risks caused by this physical difference, production lines have to introduce complex compensation processes such as BOL (Buffer Oxide Layer) or optimized underfill adhesive solutions. This not only significantly increases the difficulty of packaging but also raises manufacturing costs.

[0007] In view of this, the present invention is hereby proposed. Summary of the Invention

[0008] To overcome the above-mentioned defects, the present invention provides a system-in-package substrate and its processing method. The processing method is simple, reasonable, flexible and easy to implement. The resulting system-in-package substrate can well meet the technical requirements of high-density integrated packaging, ultra-high heat dissipation, resin filling with precision circuits with ultra-thick copper micro-pitch characteristics, ultra-thin ink thickness above the copper surface, and a height difference between the solder surface and the solder resist layer of ≤5μm. It greatly promotes the development of system-in-package technology.

[0009] The technical solution adopted by this invention to solve its technical problem is: a method for processing a system-in-package substrate, comprising: An intermediate board with a circuit pattern is fabricated using the MSAP process. The copper thickness of the circuit pattern is ≥65μm and the line spacing is ≤25μm. Simultaneously, based on the MSAP process, multiple clamping points for power supply plating fixtures are fabricated on the edge region A of the intermediate board. Furthermore, loop-shaped leads electrically connected to the circuit pattern are fabricated on the edge regions B of multiple SET boards within the intermediate board. Each loop-shaped lead is electrically connected to one of the clamping points, and the relative length difference between the loop-shaped leads is no greater than 15%. After the intermediate plate is roughened, a composite insulating film is applied to the plate surface on which the circuit pattern is provided to fill the gaps between the circuit patterns; wherein, the composite insulating film includes a photosensitive insulating resin film and a first ink dry film stacked together, and the photosensitive insulating resin film has thermorheological properties to achieve uniform filling of the gaps between the circuit patterns. Remove part of the composite insulating film to expose the circuit pattern and the loop lead, and then bake the plate to completely cure the remaining composite insulating film; Solder resist and electroplating operations are performed to obtain solder resist layer and electroplating layer respectively; wherein, during the electroplating operation, the circuit pattern is connected to an external power source through the loop lead and the clamp, so that the height difference between the electroplating layer and the solder resist layer formed on the surface of the circuit pattern is ≤5μm.

[0010] As a further improvement of the present invention, based on the above-mentioned MSAP process, multiple dummy pads are also made on the edge region A of the intermediate board, and multiple guide holes with through-hole structures are made on the edge region B of each SET board; the multiple dummy pads are electrically connected to the multiple clamps one-to-one to play a diversion role, and the multiple guide holes are used to accelerate the flow and exchange of electroplating chemicals.

[0011] As a further improvement of the present invention, the processing conditions for the above-mentioned electroplating operation are: the guide hole is not blocked, and the electroplating current density is 1±0.5A / dm. 2 .

[0012] As a further improvement of the present invention, the photosensitive insulating resin film has the following characteristics: it exhibits a semi-cured state with a viscosity of 200–250 dPa·s at room temperature; it exhibits a molten state with a viscosity of 100–120 dPa·s at 80–100°C; and after complete thermal curing, its CTE value is 25–35 ppm / °C, and its volume resistivity is 10⁻⁶. 14 ~10 15 Ω·cm, breakdown strength is 50~80KV / mm.

[0013] As a further improvement of the present invention, the photosensitive insulating resin film and the first ink dry film are sequentially laminated onto the intermediate board and the board surface with the circuit pattern is provided by the vacuum lamination process. Furthermore, the processing parameters used for vacuum lamination of the photosensitive insulating resin film are: lamination temperature of 30–50°C, vacuum time of 20–40 s, and vacuum pressure of 5–7 kgf / cm². 2 The leveling temperature is 90±2℃, and the leveling pressure is 5±1 kgf / cm². 2 The leveling time is 45±2s; The processing parameters used for vacuum lamination of the first ink dry film are: lamination temperature 30–50°C, vacuum time 20–40 s, and vacuum pressure 5–7 kgf / cm². 2 The leveling temperature is 80±2℃, and the leveling pressure is 5±1 kgf / cm². 2 The leveling time is 45±2s.

[0014] As a further improvement of the present invention, the thickness of the photosensitive insulating resin film filling the gaps between the circuit patterns is 80% to 90% of the copper thickness of the circuit patterns; the thickness of the first ink dry film is 15 to 25 μm.

[0015] As a further improvement of the present invention, the first ink dry film is first exposed and developed to remove the first ink dry film that is directly above the circuit pattern and the loop lead; then a first baking process is performed at a baking temperature of 120±5℃ for 18±2 minutes to preliminarily cure the retained composite insulating film; then the photosensitive insulating resin film covered on the surface of the circuit pattern and the loop lead is removed by a grinding plate, while controlling the retained composite insulating film to be flush with the circuit pattern and the loop lead; then a second baking process is performed at a baking temperature of 155±5℃ for 60±5 minutes to completely cure the retained composite insulating film.

[0016] As a further improvement of the present invention, the intermediate plate is roughened by a browning process, and the surface wetting angle of the intermediate plate is greater than 90°.

[0017] As a further improvement of the present invention, the board obtained after the baking process is defined as intermediate board A; firstly, a second ink dry film is applied to the surface of intermediate board A using a vacuum lamination process, and then exposure, development, and baking processes are performed sequentially to obtain the solder resist layer; wherein, the processing parameters of the above vacuum lamination process are: lamination temperature of 30-50°C, vacuum time of 20-40s, and vacuum pressure of 5-7 kgf / cm². 2 The leveling temperature is 80±2℃, and the leveling pressure is 5±1 kgf / cm². 2 The leveling time is 20±2s.

[0018] The present invention also provides a system-in-package substrate, which is manufactured using the system-in-package substrate processing method described in the present invention.

[0019] The beneficial effects of this invention are as follows: Compared with the prior art, this invention has the following advantages: ① This invention utilizes the MSAP process to fabricate precision circuits with copper thickness ≥65μm and line spacing ≤25μm, while also fabricating electroplating auxiliary patterns and the aforementioned guiding holes; through the aforementioned precision circuits, the technical requirements of high-density integrated packaging process and ultra-high heat dissipation can be met simultaneously, and there is no need to pull leads for secondary circuit plating, which not only avoids the technical defects caused by secondary plating, but also saves 30% to 40% of design space due to the elimination of lead pulling, providing a technical basis for smaller design size; through the aforementioned electroplating auxiliary patterns and guiding holes, it provides very good technical support for reducing current density, improving the uniformity of current density distribution, and balancing the electroplating solution exchange rate during electroplating operations, thereby helping to improve the thickness consistency of the obtained electroplated gold layer and helping to ensure that the height difference between the obtained electroplated gold layer (soldering surface) and the solder resist layer meets the control requirements. Specifically, the thickness consistency of the obtained electroplated gold layer can be improved by more than 20%, and the height difference between the obtained electroplated gold layer and the solder resist layer reaches ≤5μm. ② This invention first vacuum-lamps a photosensitive insulating resin film with thermorheological properties and good fluidity onto the intermediate plate, allowing the photosensitive insulating resin film to fully and uniformly fill the micro-gaps between the circuit patterns during the leveling stage; then, vacuum-lamps a first ink dry film with relatively moderate fluidity and thinner thickness onto the intermediate plate, achieving air removal and ink leveling on the surface of the photosensitive insulating resin film; thus, the overall flatness of the composite insulating film formed by the combination and curing of the first ink dry film and the photosensitive insulating resin film is ≤5μm, which effectively ensures subsequent high-density interconnection and high-reliability assembly. ③ Due to the ultra-thin ink thickness above the copper surface (ink thickness is 10±2μm), reliable and micro-crack-free subsequent encapsulation is well guaranteed. In summary, the processing method provided by this invention is simple, reasonable, flexible, and easy to implement. The system-in-package substrate produced by this processing method can well meet the technical requirements of high-density integrated packaging, ultra-high heat dissipation, resin filling with ultra-thick copper micro-pitch characteristics for precision circuits, ultra-thin ink thickness above the copper surface, and a height difference of ≤5μm between the solder surface and the solder resist layer. It has greatly promoted the development of system-in-package technology. Attached Figure Description

[0020] Figure 1 This is a flowchart of the system-in-package substrate processing method described in this invention; Figure 2 This is a schematic cross-sectional view of the composite material A obtained in Embodiment 1 of the present invention; Figure 3 This is a schematic cross-sectional view of the composite material B obtained in Embodiment 1 of the present invention; Figure 4 This is a schematic cross-sectional view of the intermediate plate obtained in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the electroplating auxiliary pattern formed on the intermediate plate in Embodiment 1 of the present invention; Figure 6 This is a cross-sectional structural diagram of a photosensitive insulating resin film being applied to an intermediate plate using a vacuum lamination process in Embodiment 1 of the present invention. Figure 7 This is a schematic cross-sectional view of the first ink dry film being coated onto the photosensitive insulating resin film using a vacuum lamination process in Embodiment 1 of the present invention. Figure 8 This is a schematic cross-sectional view of the intermediate plate A obtained in Embodiment 1 of the present invention; Figure 9 This is a schematic cross-sectional view of the intermediate plate A after a solder resist layer has been applied in Embodiment 1 of the present invention. Figure 10 This is a schematic cross-sectional view of the system-in-package substrate obtained in Embodiment 1 of the present invention.

[0021] Referring to the accompanying drawings, the following explanations are provided: 1. Circuit pattern; 20. Grip point; 21. Loop lead; 22. Dummy pad; 23. Through hole; 3. Composite insulating film; 31. Photosensitive insulating resin film; 32. First ink dry film; 4. Solder resist layer; 5. Electroplating layer; 60. Carrier copper layer; 61. Ultra-thin copper layer; 7. Prepreg; 8. Interlayer conductive layer; B1. Intermediate board. Detailed Implementation

[0022] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] Example 1:

[0024] Please see the appendix Figure 1 To be continued Figure 10 As shown, this embodiment 1 provides a method for processing a system-in-package substrate, including the following processing steps: S1: Create an intermediate board B1 with circuit pattern 1 and electroplating auxiliary pattern.

[0025] Regarding the intermediate board B1, its implementation structure is determined according to product design requirements, and this application does not impose any limitations. However, in order to clearly and thoroughly explain the processing method of the system-in-package substrate provided in this application, this application uses the MSAP process to fabricate the intermediate board B1, specifically as follows: S11: Provide two composite copper foils and a prepreg 7; the composite copper foil consists of a carrier copper layer 60 and an ultrathin copper layer 61 disposed on the carrier copper layer 60 in a detachable manner, and the thickness of the carrier copper layer 60 is preferably 17±2μm, and the thickness of the ultrathin copper layer 61 is preferably 3±0.2μm; the thickness and quantity of the prepreg 7 are not limited and are determined according to the product design requirements.

[0026] Additional explanation: Regarding the composite copper foil, the ultrathin copper layer 61 is deposited on the carrier copper layer 60 via an electrodeposition process. Prior to electrodeposition, the carrier copper layer 60 undergoes a chemical treatment to ensure a predetermined peel force between the carrier copper layer 60 and the ultrathin copper layer 61, enabling effective mechanical separation. This is a conventional technique in the field of circuit board technology and will not be described in detail here.

[0027] S12: The two composite copper foils and the prepreg 7 are stacked together, with the prepreg 7 positioned between the ultrathin copper layers 61 of the two composite copper foils. Then, they are hot-pressed together to firmly bond the two composite copper foils and the prepreg 7 together, resulting in composite board A. See Appendix for details. Figure 2 As shown.

[0028] Furthermore, the processing parameters for hot pressing are optimized as follows: heating rate ≥ 8℃ / min, maximum pressing temperature ≥ 230℃, and maximum pressing pressure ≥ 450Psi; to ensure that the interlayer bonding of the resulting composite board A is very strong.

[0029] S13: First, use a QR code printing machine to mark a unique PNL QR code on the edge area C of the obtained composite board A. Then, use mechanical drilling to drill the required holes on the obtained composite board A, including: tool holes (such as alignment holes) formed on the edge area C of the obtained composite board A and the prototype of guide holes (through hole structure) formed on the edge area D of multiple SET boards A in the obtained composite board A.

[0030] Supplementary Explanation: In this application, ① Composite board A can be understood as a single PNL board (or production board), which can be divided into multiple SET boards A (or spliced ​​boards). ② The aforementioned "board edge region D" refers to the board edge region of SET board A, and the aforementioned "board edge region C" refers to the board edge region of composite board A. It can be understood that board edge region C surrounds the outer side of multiple SET boards A.

[0031] S14: Mechanically remove the carrier copper layer 60 from the two composite copper foils to obtain composite board B. See attached document for details. Figure 3 As shown.

[0032] S15: The obtained composite board B is subjected to laser windowing and drilling, whole-board copper plating, film coating, exposure, development, hole filling electroplating, film removal and flash etching to produce circuit pattern 1 and electroplating auxiliary pattern, that is, to obtain the intermediate board B1. For details, please refer to the appendix. Figure 4 As shown.

[0033] Furthermore, the aforementioned laser windowing and drilling refers to the process of creating X-shaped through holes in the effective graphic areas of multiple SET boards B in the obtained composite board B by combining etching windowing and laser drilling processes, which serve as the basis for interlayer conduction.

[0034] Note: For SET board B, please refer to SET board A above. The aforementioned whole-board copper plating refers to the whole-board copper plating operation performed after removing adhesive residue from the inner wall of the holes (including the hole walls of alignment holes, guide hole prototypes, and X-shaped through holes), and the copper thickness of the copper plating layer can be optimally controlled within 0.8±0.2μm.

[0035] Note: After copper plating was performed on the prototype of the guide hole, the guide hole 23 was obtained.

[0036] The aforementioned coating, exposure, and development process refers to the process of applying the photosensitive dry film to the two ultra-thin copper layers 61 using a vacuum laminator, exposing a portion of the photosensitive dry film to the coating according to the work instructions and using an LDI exposure machine, and then removing the unexposed areas of the photosensitive dry film using a vertical development machine.

[0037] Note: According to product design requirements, the thickness of the photosensitive dry film should not be less than the thickness of the subsequent electroplated copper layer, such as 75μm; the ADTEC IP4 exposure machine is preferred for LDI exposure; the TKC vertical development machine can be used for development, and the development points are controlled to 50% to 55% during development.

[0038] The aforementioned via-filling electroplating refers to electroplating copper on the area of ​​the ultra-thin copper layer 61 exposed outside the photosensitive dry film, to obtain: ① a precision circuit pattern prototype with a line width of 15-60 μm, a line spacing of 15-25 μm, and a copper plating thickness of 75±7 μm; it is understood that each of the SET boards B has the precision circuit pattern prototype formed thereon; ② an interlayer conductive layer 8 formed in the X-hole and used to connect the two precision circuit pattern prototypes on each of the SET boards B; and ③ an electroplating auxiliary pattern prototype.

[0039] The electroplating auxiliary pattern prototype includes multiple clamping point prototypes and multiple dummy pad prototypes formed on the edge region E of the composite board B, and loop-shaped lead prototypes formed on the edge region F of each SET board B. The multiple clamping point prototypes are respectively connected to the multiple dummy pad prototypes, and each loop-shaped lead prototype is respectively connected to the precision circuit pattern prototype on its corresponding SET board B. The multiple loop-shaped lead prototypes are also respectively connected to the multiple dummy pad prototypes.

[0040] The aforementioned film removal and flash etching refer to the process of removing the photosensitive dry film using a stripping solution, followed by flash etching of the entire board using a vacuum two-fluid flash etching line to remove the ultrathin copper layer 61 that is exposed (i.e., removing the ultrathin copper layer 61 that was previously covered by the photosensitive dry film), thereby forming the final circuit pattern 1 and electroplating auxiliary pattern, and producing the intermediate board B1.

[0041] Understandably, ① the intermediate board B1 can be divided into multiple SET boards, and the circuit pattern 1 is formed on both sides of each SET board. The structural parameters of the circuit pattern 1 are optimally controlled as follows: line width 15–60 μm, line spacing 15–25 μm, and copper thickness 75 ± 7 μm. That is, the circuit pattern 1 is a precision circuit with ultra-thick copper and micro-pitch (micro-line spacing) characteristics. Please also refer to the appendix. Figure 4 As shown, the two circuit patterns 1 located on the same SET board are also connected through the interlayer conductive layer 8.

[0042] ②Please refer to the appendix Figure 5 As shown, the electroplating auxiliary pattern includes multiple clamping points 20 and multiple dummy pads 22 formed on the edge region A of the intermediate board, and loop leads 21 formed on the edge region B of multiple SET boards in the intermediate board. Figure 5 In the diagram, the "red line" represents the edge of the intermediate board, and the "magenta line" represents the edge of the effective circuit pattern area of ​​the SET board. The multiple clamping points 20 are used for clamping the electroplating fixture, that is: when performing electroplating operations in the subsequent application, a contact clamping method can be adopted, which can not only provide a stable clamping force, but also achieve very uniform electrical contact, reduce overplating, and also greatly reduce physical obstruction and liquid residue dead corners, thereby improving electroplating quality.

[0043] The dummy pads are electrically connected to the clamps 20 respectively to serve as current shunting points. The length of the dummy pads 22 can be designed to be 3 times the length of the clamps 20, and the width of the dummy pads 22 can be designed to be 0.25 to 0.35 times the width of the clamps 20.

[0044] Each of the loop leads 21 is connected to the circuit pattern 1 on its corresponding SET board. Simultaneously, multiple loop leads 21 are also electrically connected to multiple dummy pads 22 (pinch points 20). Furthermore, the relative length difference between the multiple loop leads 21 is controlled to be no greater than 15%. By employing the loop leads 21 and specifically controlling their length as described above, the distance from the pinch point 20 to the effective electroplating pattern can be lengthened, significantly reducing the current density during electroplating. On the other hand, the near-uniform length of the loop leads 21 effectively overcomes the problem of uneven current density distribution during electroplating, thereby significantly improving the thickness consistency of the subsequent electroplating layer 5 (verified to improve the thickness consistency of the electroplating layer 5 by 20% or more), and thus significantly improving the electroplating quality.

[0045] ③ On the edge region B of each SET plate, a plurality of through holes 23 are formed. These through holes 23 are used to accelerate the flow and exchange of electroplating chemicals to balance the electroplating chemical exchange rate in each SET plate region. Furthermore, the diameter of the through holes 23 can be optimally controlled to be 1.8±0.05mm.

[0046] In summary, this embodiment utilizes the MSAP process to fabricate precision circuitry with a copper thickness ≥65μm and line spacing ≤25μm, while also fabricating electroplating auxiliary patterns and guide holes 23. These precision circuitry simultaneously meet the technical requirements of high-density integrated packaging and ultra-high heat dissipation, eliminating the need for secondary plating with lead wires. This not only avoids the technical defects associated with secondary plating but also saves 30%–40% of design space due to the elimination of lead wires, providing a technical basis for smaller design dimensions. Furthermore, the electroplating auxiliary patterns and guide holes 23 provide excellent technical support for reducing current density, improving the uniformity of current density distribution, and balancing the electroplating solution exchange rate during subsequent electroplating operations. This is beneficial for improving the thickness consistency of the resulting electroplated layer 5 and ensuring that the height difference between the resulting electroplated layer 5 (soldering surface) and the solder resist layer 4 meets control requirements.

[0047] In addition, after the intermediate board B1 is manufactured, this embodiment also performs 100% visual inspection and confirmation on the circuit pattern 1, the electroplating auxiliary pattern and the guide hole 23 to ensure the quality of pattern processing.

[0048] S2: First, the intermediate board B1 is roughened using a browning process, ensuring that the surface wetting angle of the intermediate board is greater than 90°. Understandably, the browning process creates a micro-rough structure on the copper surface of the intermediate board B1 and forms an organic metal bridging film. During subsequent vacuum lamination, this allows for both physical anchoring and chemical cross-linking between the copper surface of the intermediate board B1 and the photosensitive insulating resin film 31, resulting in excellent adhesion. Furthermore, by precisely controlling the surface wetting angle of the intermediate board to be greater than 90°, the flow of the molten photosensitive insulating resin film 31 into the micro-spacing between the circuit patterns 1 can be accelerated during vacuum lamination (especially during leveling). In other words, the browning process provides excellent technical support for high-quality subsequent vacuum lamination.

[0049] Then, the photosensitive insulating resin film 31 (see appendix) is applied using a vacuum lamination process. Figure 6 The black filler portion in the middle) and the first ink dry film 32 (see appendix) Figure 7 The green filling portion is sequentially layered on the middle plate B1 and the plate surface with the circuit pattern 1 to fill the micro gaps between the circuit patterns 1.

[0050] Furthermore, since the circuit pattern 1 has ultra-thick copper and micro-spacing characteristics, in order to achieve uniform and good filling of the micro-gaps between the circuit patterns 1, this embodiment also specifically optimizes the selection of materials and vacuum lamination processing parameters of the photosensitive insulating resin film 31, specifically as follows: ① Preferably, a resin film with the following characteristics is used: the photosensitive insulating resin film 31 exhibits a semi-cured state with a viscosity of 200–250 dPa·s at room temperature; it exhibits a molten state with a viscosity of 100–120 dPa·s at 80–100℃; after complete thermal curing, its CTE value (coefficient of thermal expansion) is 25–35 ppm / ℃, and its volume resistivity is 10 Ω·cm. 14 ~10 15 The breakdown strength is 50–80 kV / mm, with an Ω·cm. It is understood that the photosensitive insulating resin film 31 preferably used in this embodiment has thermorheological properties, good fluidity, cures upon heating, low CTE value, and high insulation properties.

[0051] More specifically, the photosensitive insulating resin film 31 can preferably be made of modified filler ink UCP-50A-4 produced by Sanei Chemical Co., Ltd. The raw material components of this modified filler ink include photosensitive epoxy resin, modified resin (special resins such as benzocyclobutene), photoinitiator (such as TPO-L, benzophenone, etc.), silica, and nano-sized fumed silica. Among them, the photosensitive epoxy resin, as the matrix resin and modified by the modified resin, can provide excellent electrical insulation, high temperature resistance and low dielectric constant. The photoinitiator can generate free radicals under ultraviolet light irradiation, triggering cross-linking polymerization reaction. Silica can adjust the coefficient of thermal expansion of the filler ink and enhance wear resistance and scratch resistance. Nano-sized fumed silica can increase the storage modulus and tensile strength of the filler ink, and also act as a rheology control agent.

[0052] ② Based on the above-mentioned characteristics of the photosensitive insulating resin film 31, the preferred processing parameters for vacuum lamination of the photosensitive insulating resin film 31 in this embodiment are: lamination temperature of 30-50°C, vacuum time of 20-40s, and vacuum pressure of 5-7 kgf / cm². 2 The leveling temperature is 90±2℃, and the leveling pressure is 5±1 kgf / cm². 2 The leveling time is 45±2s. Meanwhile, based on the above processing parameters, the thickness of the photosensitive insulating resin film 31, which is ultimately filled in the micro-gaps between the circuit patterns 1, is controlled to be 80% to 90% of the copper thickness of the circuit pattern 1.

[0053] Furthermore, based on the aforementioned characteristics of the photosensitive insulating resin film 31, this embodiment also optimizes the processing parameters for vacuum lamination of the first ink dry film 32, specifically: lamination temperature of 30–50°C, vacuum time of 20–40 s, and vacuum pressure of 5–7 kgf / cm². 2 The leveling temperature is 80±2℃, and the leveling pressure is 5±1 kgf / cm². 2 The leveling time is 45±2s. Meanwhile, based on the above processing parameters, the thickness of the first ink dry film 32 finally formed on the surface of the photosensitive insulating resin film 31 is controlled to be 15~25μm.

[0054] Regarding the material of the first ink dry film 32, this embodiment does not impose any restrictions. For example, solder resist ink commonly used in the circuit board processing field can be used.

[0055] As described above, in this embodiment, by first vacuum-laden the photosensitive insulating resin film 31 with thermorheological properties and good fluidity onto the intermediate plate B1, the photosensitive insulating resin film 31 can be fully and uniformly filled into the micro gaps between the circuit patterns 1 with ultra-thick copper micro-pitch characteristics during the leveling stage. Then, by vacuum-laden the first ink dry film 32 with relatively general fluidity and thinner film thickness onto the intermediate plate B1, air can be removed and ink can be leveled on the surface of the photosensitive insulating resin film 31. Thus, the overall flatness of the composite insulating film 3 formed by the combination and curing of the first ink dry film 32 and the photosensitive insulating resin film 31 can be ≤5μm.

[0056] Supplementary Explanation: ① For ease of description of subsequent processes, this embodiment refers to the photosensitive insulating resin film 31 and the first ink dry film 32 together as the composite insulating film 3. ② Since the photosensitive insulating resin film 31 is a semi-solid adhesive film and the first ink dry film 32 is a dry film, a PI protective film is generally applied to the surface of the film materials to prevent contamination during production and transportation. Understandably, during vacuum lamination, the PI protective film needs to be peeled off before vacuum lamination. This maximizes the cleanliness of the surfaces of the photosensitive insulating resin film 31 and the first ink dry film 32, ensuring the strong bond between the two films and the intermediate plate B1.

[0057] S3: First, the first ink dry film 32 is exposed and developed to remove the first ink dry film 32 that is directly overlaid on the circuit pattern 1 and the loop lead 21; then, a first baking operation is performed at a baking temperature of 120±5℃ for 18±2 minutes to preliminarily cure the retained composite insulating film 3; then, the photosensitive insulating resin film 31 overlaid on the surface of the circuit pattern 1 and the loop lead 21 is removed by a grinding plate (such as a mechanical grinding plate using a ceramic brush wheel and a non-woven brush wheel), while simultaneously controlling the retained composite insulating film 3 to be flush with the circuit pattern 1 and the loop lead 21. It can be understood that at this time, part of the composite insulating film 3 is removed to expose the circuit pattern 1 and the loop lead 21; then, a second baking operation is performed at a baking temperature of 155±5℃ for 60±5 minutes to completely cure the retained composite insulating film 3.

[0058] In addition, for ease of subsequent process description, this embodiment will define the board obtained after completing the above S3 operation as intermediate board A, as detailed in the appendix. Figure 8 As shown.

[0059] S4: First, the second ink dry film is laminated onto the surface of the intermediate board A using a vacuum lamination process. Then, exposure, development, and baking operations are performed sequentially to obtain a solder resist layer 4 with an ink flatness ≤2μm and an ink thickness of 10±2μm. See the appendix for details. Figure 9 The blue-filled portion in the diagram; then, an electroplating process is performed to form an electroplating layer 5 at the predetermined position of the circuit pattern 1, as detailed in the appendix. Figure 10 As shown.

[0060] For further details, please refer to the appendix. Figure 9 As shown, the solder resist layer 4 is formed above the first ink dry film 32, and the material of the solder resist layer 4 (i.e., the second ink dry film) is the same as the material of the first ink dry film 32, so that the two are bonded very firmly. In addition, based on the arrangement of the solder resist layer 4, it can be concluded that the ink thickness above the copper surface is extremely thin, which can well ensure reliability and no micro-cracks during subsequent packaging.

[0061] Furthermore, based on the aforementioned relationship between the second ink dry film and the first ink dry film 32, the processing parameters used in this embodiment for vacuum laminating the second ink dry film are: lamination temperature of 30–50°C, vacuum time of 20–40 s, and vacuum pressure of 5–7 kgf / cm². 2 The leveling temperature is 80±2℃, and the leveling pressure is 5±1 kgf / cm². 2 The leveling time is 20±2s.

[0062] In addition, the "exposure, development and baking operations" mentioned above are all commonly used solder mask processing techniques in the circuit board industry, so they will not be described in detail here.

[0063] Furthermore, in this embodiment, during the electroplating operation, the circuit pattern 1 is connected to an external power source via the loop lead 21, the dummy pad 22, and the clamp point 20. Based on the aforementioned characteristics of the loop lead 21 and the unblocked flow guide hole 23 (see S15 above), the thickness uniformity of the electroplating layer 5 formed on the surface of the circuit pattern 1 can be improved by more than 20%, and the height difference between the electroplating layer 5 and the solder resist layer 4 can reach ≤5μm.

[0064] Furthermore, based on the aforementioned characteristics of the loop lead 21, the electroplating current density during electroplating operations in this embodiment is 1 ± 0.5 A / dm². 2 Compared to the commonly used electroplating current density in the industry (2±1A / dm), 2 It decreased by 50%.

[0065] Furthermore, according to product design requirements, the electroplated gold layer 5 includes a nickel layer with a thickness of 10±5μm and a gold layer with a thickness of ≥0.2μm.

[0066] S5: Following the product design requirements, the semi-finished packaging substrate obtained after processing in S4 is subjected to routine molding, finished product testing and inspection, laser cutting, PCS assembly, shipment inspection, packaging, and shipping operations to obtain the system-level packaging substrate; see appendix for details. Figure 10 As shown.

[0067] As can be seen from the above, compared with the prior art, ① this embodiment utilizes the MSAP process to fabricate precision circuits with copper thickness ≥65μm and line spacing ≤25μm, while also fabricating electroplating auxiliary patterns and the aforementioned guide holes 23; through the aforementioned precision circuits, the technical requirements of high-density integrated packaging technology and ultra-high heat dissipation can be met simultaneously, and there is no need to pull leads for secondary circuit plating. This not only avoids the technical defects caused by secondary plating, but also saves 30% to 40% of design space due to the elimination of lead pulling, providing a technical basis for smaller design sizes. The above-mentioned electroplating auxiliary patterns and guide holes 23 provide excellent technical support for reducing current density, improving the uniformity of current density distribution, and balancing the electroplating solution exchange rate during electroplating operations. This is beneficial for improving the thickness consistency of the obtained electroplated gold layer 5 and ensuring that the height difference between the obtained electroplated gold layer 5 (welding surface) and the solder resist layer 4 meets the control requirements. Specifically, the thickness consistency of the obtained electroplated gold layer 5 can be improved by more than 20%, and the height difference between the obtained electroplated gold layer 5 and the solder resist layer 4 can reach ≤5μm.

[0068] ② In this embodiment, by first vacuum-laminating the photosensitive insulating resin film 31, which has thermorheological properties and good fluidity, onto the intermediate plate, the photosensitive insulating resin film 31 can be fully and uniformly filled into the micro gaps between the circuit patterns 1 during the leveling stage. Then, by vacuum-laminating the first ink dry film 32, which has relatively general fluidity and a thinner film thickness, onto the intermediate plate, air can be removed and ink can be leveled on the surface of the photosensitive insulating resin film 31. As a result, the overall flatness of the composite insulating film 3 formed by the combination and curing of the first ink dry film 32 and the photosensitive insulating resin film 31 can be ≤5μm, which well ensures the subsequent high-density interconnection and high-reliability assembly.

[0069] ③ Because the ink thickness above the copper surface is ultra-thin (10±2μm), it can effectively ensure reliable packaging without micro-cracks.

[0070] Example 2:

[0071] This embodiment 2 provides a system-in-package substrate, which is manufactured using the processing method of the system-in-package substrate provided in embodiment 1 above.

[0072] Specifically, the system-in-package substrate structure provided in this embodiment 2 is as follows: Please refer to the appendix. Figure 10 As shown, the device includes a prepreg 7 and circuit patterns 1 disposed on opposite sides of the prepreg 7. The two circuit patterns 1 are connected by an interlayer conductive layer 8, and both circuit patterns 1 have a copper thickness ≥65μm and a line spacing ≤25μm. In addition, a composite insulating film 3 is filled in the micro gap between each circuit pattern 1, and a solder resist layer 4 is coated on the composite insulating film 3. An electroplated gold layer 5 is disposed at a predetermined position on each circuit pattern 1, and the height difference between the electroplated gold layer 5 and the solder resist layer 4 is ≤5μm.

[0073] As can be seen from the above, the system-in-package substrate provided in this embodiment 2 can well meet the technical requirements of: high-density integrated packaging, ultra-high heat dissipation, resin filling with ultra-thick copper micro-pitch characteristics for precision circuits, ultra-thin ink thickness above the copper surface, and height difference between the solder surface and the solder resist layer reaching ≤5μm; thus greatly promoting the development of system-in-package technology.

[0074] Finally, it should be noted that the prefixes such as "first" and "second" in the component names in this application specification (e.g., first ink dry film, second ink dry film, etc.) and the suffixes such as "A" and "B" in the component names (e.g., composite board A, composite board B, etc.) are only for the purpose of clarity of description and are not intended to limit the scope of implementation of this invention patent.

[0075] Many specific details have been set forth in the foregoing description to provide a thorough understanding of the present invention. However, the above description is merely a preferred embodiment of the present invention, and the present invention can be implemented in many other ways different from those described herein. Therefore, the present invention is not limited to the specific embodiments disclosed above. Furthermore, any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the present invention. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A method for fabricating a system-in-package substrate, characterized in that: include: An intermediate board with a circuit pattern (1) is formed using the MSAP process. The copper thickness of the circuit pattern (1) is ≥65μm and the line spacing is ≤25μm. At the same time, based on the above MSAP process, multiple clamping points (20) for power supply plating fixtures are made on the board edge area A of the intermediate board, and loop leads (21) electrically connected to the circuit pattern (1) are made on the board edge areas B of multiple SET boards in the intermediate board. The multiple loop leads (21) are electrically connected to the multiple clamping points (20) respectively, and the relative length difference between the multiple loop leads (21) is not greater than 15%. After the intermediate plate is roughened, a composite insulating film (3) is applied to the plate surface on which the circuit pattern (1) is provided to fill the gap between the circuit patterns (1); wherein, the composite insulating film (3) includes a photosensitive insulating resin film (31) and a first ink dry film (32) stacked together, and the photosensitive insulating resin film (31) has thermorheological properties to achieve uniform filling of the gap between the circuit patterns (1); Remove part of the composite insulating film (3) to expose the circuit pattern (1) and the loop lead (21), and then bake the plate to completely cure the remaining composite insulating film (3). Solder resist and electroplating operations are performed to obtain a solder resist layer (4) and an electroplating layer (5) respectively; wherein, during the electroplating operation, the circuit pattern (1) is connected to an external power source through the loop lead (21) and the clamp (20) so that the height difference between the electroplating layer (5) and the solder resist layer (4) formed on the surface of the circuit pattern (1) is ≤5μm.

2. The method for processing a system-in-package substrate according to claim 1, characterized in that: Based on the above MSAP process, multiple dummy pads (22) are also made on the edge area A of the intermediate board, and multiple guide holes (23) with through-hole structure are made on the edge area B of each SET board. The multiple dummy pads (22) are electrically connected to the multiple clamps (20) one by one to play a diversion role, and the multiple guide holes (23) are used to accelerate the flow and exchange of electroplating solution.

3. The method for processing a system-in-package substrate according to claim 2, characterized in that: The processing conditions for the above electroplating operation are: the guide hole (23) is not blocked, and the electroplating current density is 1±0.5A / dm. 2 .

4. The method for processing a system-in-package substrate according to claim 1, characterized in that: The photosensitive insulating resin film (31) has the following characteristics: at room temperature, it exhibits a semi-cured state with a viscosity of 200–250 dPa·s; at 80–100°C, it exhibits a molten state with a viscosity of 100–120 dPa·s; after complete thermal curing, its CTE value is 25–35 ppm / °C, and its volume resistivity is 10 Ω·cm. 14 ~10 15 Ω·cm, breakdown strength is 50~80KV / mm.

5. The method for processing a system-in-package substrate according to claim 1, characterized in that: The photosensitive insulating resin film (31) and the first ink dry film (32) are sequentially laminated onto the intermediate board and the board surface with the circuit pattern (1) by a vacuum lamination process. Furthermore, the processing parameters used when vacuum bonding the photosensitive insulating resin film (31) are: bonding temperature of 30-50℃, vacuum time of 20-40s, and vacuum pressure of 5-7kgf / cm. 2 The leveling temperature is 90±2℃, and the leveling pressure is 5±1 kgf / cm². 2 The leveling time is 45±2s; The processing parameters used for vacuum lamination of the first ink dry film (32) are: lamination temperature of 30-50℃, vacuum time of 20-40s, and vacuum pressure of 5-7kgf / cm². 2 The leveling temperature is 80±2℃, and the leveling pressure is 5±1 kgf / cm². 2 The leveling time is 45±2s.

6. The method for processing a system-in-package substrate according to claim 5, characterized in that: The thickness of the photosensitive insulating resin film (31) filling the gaps between the circuit patterns (1) is 80% to 90% of the copper thickness of the circuit patterns (1); the thickness of the first ink dry film (32) is 15 to 25 μm.

7. The method for processing a system-in-package substrate according to claim 1, characterized in that: First, the first ink dry film (32) is exposed and developed to remove the first ink dry film (32) that is directly overlaid on the circuit pattern (1) and the loop lead (21); then, a first baking operation is performed at a baking temperature of 120±5℃ for 18±2 minutes to preliminarily cure the retained composite insulating film (3); then, the photosensitive insulating resin film (31) overlaid on the surface of the circuit pattern (1) and the loop lead (21) is removed by a grinding plate, while controlling the retained composite insulating film (3) to be flush with the circuit pattern (1) and the loop lead (21); then, a second baking operation is performed at a baking temperature of 155±5℃ for 60±5 minutes to completely cure the retained composite insulating film (3).

8. The method for processing a system-in-package substrate according to claim 1, characterized in that: The intermediate board is roughened using a browning process, resulting in a surface wetting angle greater than 90°.

9. The method for processing a system-in-package substrate according to claim 1, characterized in that: The board obtained after completing the baking process is defined as intermediate board A; First, the second ink dry film is laminated onto the surface of the intermediate board A using a vacuum lamination process. Then, exposure, development, and baking operations are performed sequentially to obtain the solder resist layer (4). The processing parameters of the vacuum lamination process are: lamination temperature of 30-50℃, vacuum time of 20-40s, and vacuum pressure of 5-7kgf / cm². 2 The leveling temperature is 80±2℃, and the leveling pressure is 5±1 kgf / cm². 2 The leveling time is 20±2s.

10. A system-in-package substrate, characterized in that: It is manufactured using the processing method of any one of claims 1-9 for a system-in-package substrate.

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