A package structure of a chip and a packaging method thereof

Abstract

The application provides a chip packaging structure and a packaging method thereof, comprising the following steps: forming a plurality of first chips on a substrate; forming a stress relief layer and a heat dissipation column between adjacent first chips, the stress relief layer is connected to the substrate, and a through hole is formed on the stress relief layer, one end of the heat dissipation column penetrates through the through hole and is connected to the substrate; forming a plastic encapsulation layer covering the first chips, the stress relief layer and the heat dissipation column, and forming a groove on the plastic encapsulation layer, the top end of the heat dissipation column is flush with the bottom surface of the groove, and one end of the first chip is located directly below the groove; slotting the plastic encapsulation layer at the bottom of the groove to form a vertical hole, and setting a metal layer in the vertical hole, the bottom end of the metal layer is electrically connected to the first chip; and placing a second chip in the groove and bonding the second chip and the metal layer to be electrically connected. The application reduces the stacking thickness and reduces the risk of cracking of the first chip and the plastic encapsulation layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure and packaging method. Background Technology

[0002] As integrated circuits develop towards higher performance and higher integration, multi-chip integrated packaging has become one of the mainstream technologies. In system-in-package (SiP) and fan-out packaging, it is often necessary to integrate multiple first and second chips (such as processors and memory, MEMS sensors and ASICs) together. In existing technologies, chips are placed in a stacked or side-by-side manner, but this has problems such as large thickness, poor heat dissipation, and thermal stress leading to delamination. Summary of the Invention

[0003] This invention provides a chip packaging method and structure, aiming to solve the problems of poor heat dissipation, stress concentration and complex interconnection when multiple chips are integrated in the prior art.

[0004] A chip packaging method includes the following steps: Several first chips are formed on the substrate; A stress relief layer and a heat dissipation pillar are formed between adjacent first chips. The stress relief layer is connected to the substrate and has through holes. One end of the heat dissipation pillar passes through the through holes and is connected to the substrate. A molding compound is formed covering the first chip, the stress relief layer and the heat sink, and a groove is formed on the molding compound, with the top of the heat sink flush with the bottom of the groove, and one end of the first chip located directly below the groove; A groove is made in the plastic encapsulation layer at the bottom of the groove to form a vertical hole, and a metal layer is placed in the vertical hole. The bottom end of the metal layer is electrically connected to the first chip. The second chip is placed in the groove and bonded to make the second chip electrically connected to the metal layer.

[0005] Optionally, an adhesive layer is formed on the substrate, and the first chip is fixed to the substrate by the adhesive layer.

[0006] Optionally, the method further includes the following steps: forming a thermally conductive interface layer within the groove; a vertical hole penetrating the thermally conductive interface layer, with the top section of the heat dissipation column connected to the thermally conductive interface layer.

[0007] Optionally, the substrate can be removed after the protective cover is formed.

[0008] Optionally, the method further includes the step of forming a protective cover over the second chip.

[0009] Optionally, the top surface of the second chip is higher than or flush with the molding layer.

[0010] Optionally, the method further includes the following steps: before forming the thermally conductive interface layer, the encapsulation layer on the bottom surface of the groove is activated by oxygen plasma and coated with an epoxy silane coupling agent, and the thermally conductive interface layer is an epoxy thermally conductive adhesive cured layer.

[0011] Optionally, the method also includes the step of depositing an aluminum oxide layer on the side of the heat sink column.

[0012] A chip packaging structure, comprising: Multiple first chips and a second chip disposed between adjacent first chips; Both the first chip and the second chip are disposed in the molding compound, with the first chip disposed below the second chip, and one surface of the first chip exposed outside the molding compound; The first chip and the second chip are electrically connected through a metal layer; It also includes a stress relief layer and a heat sink in the molding compound. One end of the heat sink is connected to the second chip, and the other end is exposed outside the molding compound. The stress relief layer is disposed between the first chip and the heat sink, and the surface of the stress relief layer away from the second chip is exposed outside the molding compound.

[0013] Optionally, a protective cover over the second chip may also be included. Beneficial effects

[0014] By integrating the first chip and the second chip on the encapsulation layer, the metal layer inside the vertical hole achieves short-path interconnection between the first chip and the second chip, reducing the stacking thickness; and the stress relief layer reduces the stress damage to the first chip during the encapsulation process, reducing the risk of cracking of the first chip and the encapsulation layer; and the heat is dissipated outside the package body through direct contact between the heat dissipation pillar and the second chip or through the thermal interface layer, resulting in high heat dissipation efficiency.

[0015] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings.

[0016] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 A schematic diagram of the structure after forming a plurality of first chips on a substrate in the packaging method provided in the embodiments of the present invention; Figure 2A schematic diagram of the structure after forming a stress relief layer and a heat dissipation pillar between adjacent first chips in the packaging method provided in the embodiments of the present invention; Figure 3 A schematic diagram of the structure after forming a molding compound covering the first chip, the stress relief layer, and the heat dissipation pillars in the packaging method provided in the embodiments of the present invention; Figure 4 A schematic diagram of the structure after forming a groove on the molding layer in the encapsulation method provided in the embodiments of the present invention; Figure 5 A schematic diagram of the structure after a thermally conductive interface layer is formed in the groove in the encapsulation method provided in this embodiment of the invention; Figure 6 A schematic diagram of the structure after slotting the plastic encapsulation layer at the bottom of the groove to form a vertical hole and setting a metal layer in the vertical hole in the encapsulation method provided in the embodiment of the present invention. Figure 7 This is a schematic diagram of the structure after placing the second chip in the groove and bonding it to electrically connect the second chip to the metal layer in the packaging method provided in the embodiment of the present invention. Figure 8 The packaging method provided in the embodiments of the present invention also includes a structural diagram of the structure after the protective cover covers the second chip; Figure 9 This is a schematic diagram of the structure after removing the substrate in the packaging method provided in an embodiment of the present invention. Detailed Implementation

[0018] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0019] This embodiment provides a chip packaging method, such as... Figures 1 to 9 As shown, it includes the following steps: Step 1: Provide a substrate and fix the first chip like Figure 1 As shown, a substrate 1 is provided. This substrate can be a silicon wafer, glass plate, metal plate, or organic substrate, and an adhesive layer 11 is formed on its surface. The adhesive layer 11 can be a heat-release tape, a UV anti-adhesion film, or a photothermal conversion temporary bonding material. A plurality of first chips 2 are fixed to the substrate 1 using a high-precision pick-and-place machine via the adhesive layer 11. The first chips 2 can be logic chips, memory chips, MEMS chips, or sensor chips, with their active surfaces facing upwards and away from the substrate for subsequent interconnection.

[0020] Step 2: Forming a stress-relieving layer and heat dissipation columns like Figure 2 As shown, a stress relief layer 31 and a heat dissipation pillar 32 are formed between adjacent first chips 2. The specific steps are as follows: 2a. Coating stress-relieving material: A low-modulus polymer material is coated on the spacer area between the substrate 1 and the first chip 2 using spin coating, spray coating, or slot coating methods. The material of the stress-relieving layer 31 is selected from UV-curable silicone rubber, polyurethane elastomer, microcapsule-containing epoxy resin, or photosensitive polyimide.

[0021] 2b. Forming through holes: For photosensitive stress-relieving materials, through holes are formed directly through exposure and development; for non-photosensitive materials, through holes are formed by ultraviolet laser drilling.

[0022] 2c Electroplated Heatsink Pillars: First, a metal seed layer such as Ti / Cu with a thickness of 100~200nm is sputtered or deposited on the surface of substrate 1. Then, thick photoresist is used to define the precise position and height of the heatsink pillars. Through-holes are filled by pulse electroplating or DC electroplating, and growth continues upward to form metal pillars. The material of heatsink pillar 32 is copper, nickel, silver, or a copper / silver composite structure.

[0023] Optionally, an aluminum oxide layer is deposited on the side of the heat sink 32: an Al2O3 layer is deposited on the exposed surface of the heat sink using atomic layer deposition (ALD) technology. This aluminum oxide layer enhances the adhesion between the heat sink and the subsequent molding compound 4, preventing interface delamination.

[0024] Step 3: Form the molding layer and create the grooves like Figure 3 As shown, an epoxy molding compound is used to form a molding compound 4 covering the first chip 2, the stress relief layer 31, and the heat dissipation pillar 32 through compression molding or transfer molding processes.

[0025] like Figure 4 As shown, a groove 41 is formed on the molding layer 4 in the area between adjacent first chips 2 by mechanical milling or laser ablation. The bottom surface of the groove is flush with the top of the heat sink 32, exposing the top of the heat sink to the bottom surface of the groove. One end of the first chip 2, i.e., its side edge, is located directly below the groove 41, so that the side electrode or top electrode of the first chip can be exposed when a vertical hole is subsequently formed.

[0026] Step 4: Forming a thermally conductive interface layer like Figure 5 As shown, a thermally conductive interface layer 33 is formed within the groove 41. Preferably, before forming the thermally conductive interface layer, the plastic sealing layer 4 on the bottom surface of the groove 41 is surface-treated: activated by oxygen plasma, for example, with a power of 200-500W, an oxygen flow rate of 200 sccm, a pressure of 0.3 Torr, and a time of 60 seconds, followed by coating with an epoxy silane coupling agent KH-560 in a 0.5% ethanol solution, and drying at 100°C for 2 minutes. The thermally conductive interface layer 33 is made of epoxy thermally conductive adhesive, applied to the bottom surface of the groove by stencil printing or dispensing.

[0027] Step 5: Form vertical holes and metal interconnects like Figure 6 As shown, a vertical hole is formed in the molding layer 4 at the bottom of the groove 41 using a 355nm ultraviolet laser or a femtosecond laser. The depth extends from the bottom of the groove to the electrode surface of the first chip 2. The electrode of the first chip 2 exposed at the bottom of the vertical hole can be an aluminum pad or a copper bump. Then, a titanium / copper seed layer is sputtered, and the vertical hole is filled with electroplated copper to form a metal layer 5.

[0028] Step 6: Place and bond the second chip like Figure 7 As shown, the second chip 6 is placed in the recess 41. The second chip 6 can be a MEMS sensor, RF chip, or memory, and its back side can be pre-metallized, such as by sputtering Ti / Ni / Au. The pads of the second chip 6 are aligned with the top of the metal layer 5. Electrical connection is formed between the second chip 6 and the metal layer 5 through thermocompression bonding at a temperature of 150~300℃ and a pressure of 10~50N / chip or through reflow soldering. If a thermally conductive interface layer 33 is already present in the recess, the back side of the second chip 6 forms thermal contact with the heat sink 32 through the thermally conductive interface layer. The top surface of the second chip 6 can be higher than the top surface of the molding compound 4, such as... Figure 7 As shown, it can also be flush with the molding layer 4, depending on the actual needs.

[0029] Step 7: Form the protective cap like Figure 8 As shown, a protective cover 7 is formed to cover the second chip 6. The protective cover 7 can be a metal cover plate such as copper, aluminum, or stainless steel, or an epoxy molding compound for the second molding layer. If a metal cover plate is used, a thermally conductive interface material such as thermally conductive silicone grease or a phase change material needs to be applied between the second chip 6 and the cover plate, and the edge of the cover plate is fixed to the surface of the molding layer 4 with thermally conductive adhesive or solder, which also serves as electromagnetic shielding and heat dissipation. If a second molding layer is used, the second chip 6 is encapsulated by a molding process, and then the top of the metal layer 5 is ground to expose the external pins.

[0030] Step 8: Remove the substrate like Figure 9 As shown, the temporary substrate 1 is removed. If the adhesive layer 11 is a heat-release tape, it is heated to 150~200℃ to lose its adhesiveness, and then the substrate is mechanically peeled off; if it is a UV-resistant adhesive film, it is peeled off after UV irradiation. After removing the substrate, the back side of the first chip 2, the lower surface of the stress relief layer 31, and the lower end of the heat sink 32 are all exposed to the outside of the molding compound 4. Due to its low modulus, the stress relief layer 31 can absorb the stress generated by thermal cycling, protecting the first chip 2 from damage. The lower end of the heat sink 32 can be connected to an external heat sink as needed to further improve heat dissipation capacity.

[0031] Thus, we have obtained the following: Figure 9The chip packaging structure shown includes: multiple first chips 2, second chips 6 located between adjacent first chips, a molding compound 4, a stress relief layer 31, a heat sink 32, a metal layer 5, and an optional protective cover 7. The first chips 2 are disposed below the second chips 6, with their back surfaces exposed outside the molding compound 4; the first chips and second chips are electrically connected via the metal layer 5; the stress relief layer 31 is disposed between the first chips 2 and the heat sink 32, with its lower surface exposed; one end of the heat sink 32 is thermally coupled to the second chip 6 via a thermally conductive interface layer 33, and the other end is exposed outside the molding compound, forming an efficient heat dissipation path.

[0032] This structure has advantages such as thin thickness, good heat dissipation with heat dissipation pillars directly dissipating heat, high interconnection density vertical hole metal layer, and high reliability stress relief layer absorbing thermomechanical stress.

[0033] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A chip packaging method, characterized in that, Includes the following steps: Several first chips (2) are formed on the substrate (1); A stress relief layer (31) and a heat dissipation pillar (32) are formed between adjacent first chips (2). The stress relief layer (31) is connected to the substrate (1) and has a through hole. One end of the heat dissipation pillar (32) passes through the through hole and connects to the substrate (1). A molding layer (4) is formed covering the first chip (2), the stress relief layer (31) and the heat sink (32), and a groove (41) is formed on the molding layer (4). The top of the heat sink (32) is flush with the ground of the groove (41), and one end of the first chip (2) is located directly below the groove (41). A vertical hole is formed by slotting the plastic encapsulation layer (4) at the bottom of the groove (41), and a metal layer (5) is placed in the vertical hole. The bottom end of the metal layer (5) is electrically connected to the first chip (2). The second chip (6) is placed in the groove (41) and bonded to make the second chip (6) electrically connected to the metal layer (5).

2. The chip packaging method according to claim 1, characterized in that, An adhesive layer (11) is formed on the substrate (1), and the first chip (2) is fixed to the substrate (1) through the adhesive layer (11).

3. The chip packaging method according to claim 1, characterized in that, It also includes the following steps: A thermal interface layer (33) is formed in the groove (41); a vertical hole penetrates the thermal interface layer (33), and the top section of the heat dissipation column (32) is connected to the thermal interface layer (33).

4. The chip packaging method according to claim 1, characterized in that, After forming the protective cover (7), remove the substrate (1).

5. The chip packaging method according to claim 1, characterized in that, It also includes the following steps: A protective cover (7) is formed to cover the second chip (6).

6. The chip packaging method according to claim 1, characterized in that, The top surface of the second chip (6) is higher than or flush with the molding layer (4).

7. The chip packaging method according to claim 1, characterized in that, It also includes the following steps: Before forming the thermally conductive interface layer (33), the plastic seal layer (4) on the bottom surface of the groove (41) is activated by oxygen plasma and coated with epoxy silane coupling agent. The thermally conductive interface layer (33) is an epoxy thermally conductive adhesive curing layer.

8. The chip packaging method according to claim 1, characterized in that, It also includes the following steps: An aluminum oxide layer is deposited on the side of the heat sink column.

9. A chip packaging structure, characterized in that, The device includes multiple first chips (2) and second chips (6) disposed between adjacent first chips (2). Both first chips (2) and second chips (6) are disposed in a molding compound (4). The first chips (2) are disposed below the second chips (6), and one surface of the first chips (2) is exposed outside the molding compound (4). The first chips (2) and the second chips (6) are electrically connected through a metal layer (5). The device also includes a stress relief layer (31) and a heat sink (32) disposed in the molding compound (4). One end of the heat sink (32) is connected to the second chip (6), and the other end is exposed outside the molding compound (4). The stress relief layer (31) is disposed between the first chips (2) and the heat sink (32), and the surface of the stress relief layer (31) away from the second chip (6) is exposed outside the molding compound (4).

10. The chip packaging structure according to claim 9, characterized in that, It also includes a protective cover (7) covering the second chip (6).

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