Multilayer ceramic capacitor

Abstract

The first end face (T) on the first main surface (101) side of each of the plurality of first via conductors (140) and the plurality of second via conductors (150) is exposed on the first main surface (101). The second end face (B) on the second main surface (102) side of each of the plurality of first via conductors (140) and the plurality of second via conductors (150) is covered by the second outer layer (112). The second end face (B) of at least one of the plurality of first via conductors (140) and the plurality of second via conductors (150) is bent into a convex shape toward the second main surface (102) side in the aforementioned stacking direction. In the second main surface (102), if the area that overlaps with the inner layer (E) when viewed from the above-mentioned stacking direction is defined as the first region (A1), the area that does not overlap with the inner layer (E) is defined as the second region (A2), and the area that overlaps with at least one of the plurality of first via conductors (140) and the plurality of second via conductors (150) is defined as the third region (A3), then in the second region (A2), a recess (C) that is recessed in the above-mentioned stacking direction is formed, and in the third region (A3), a protrusion (P) that is located in the recess (C) and protrudes in the above-mentioned stacking direction is formed.

Description

Technical Field

[0001] This invention relates to multilayer ceramic capacitors. Background Technology

[0002] As a prior art document disclosing the structure of a multilayer capacitor, there is Japanese Patent Application Publication No. 2021-48261 (Patent Document 1). The multilayer capacitor described in Patent Document 1 includes a multilayer body, a plurality of first external electrodes and a plurality of second external electrodes, a plurality of first through-hole conductors, and a plurality of second through-hole conductors. In the multilayer body, a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are stacked. The plurality of first external electrodes and the plurality of second external electrodes are formed on the outer surface of the multilayer body. The plurality of first through-hole conductors electrically connect the first external electrodes and the plurality of first internal electrodes. The plurality of second through-hole conductors electrically connect the second external electrodes and the plurality of second internal electrodes. A through-hole is formed in the second internal electrode, and the first through-hole conductors penetrate this through-hole in a state of insulation from the second internal electrode. Similarly, a through-hole is formed in the first internal electrode, and the second through-hole conductors penetrate this through-hole in a state of insulation from the first internal electrode. Neither the first nor the second external electrode is formed on one main surface, but only on the other.

[0003] Prior art literature

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-48261 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] Around the first and second via conductors, through-holes are formed in the first or second inner electrode layer. Therefore, compared to the inner layer portion, which is stacked and opposite to the first and second inner electrode layers to have electrostatic capacitance, the thickness of the laminate is thinner. Consequently, in the main surface where the first and second via conductors are not exposed, a depression sometimes forms in the thinner portion of the laminate. In this case, when holding this main surface with a suction nozzle, it is impossible to make close contact between the suction nozzle and the main surface, which has reduced flatness due to the depression, making it difficult to stably hold the laminated ceramic capacitor.

[0008] The present invention was made in view of the above-mentioned problems, and its object is to provide a multilayer ceramic capacitor with improved flatness of the main surface of the conductor without exposed vias.

[0009] Technical solutions for solving the problem

[0010] The multilayer ceramic capacitor according to the present invention includes a multilayer body, a plurality of first via conductors, and a plurality of second via conductors. The multilayer body includes a plurality of first internal electrode layers and a plurality of second internal electrode layers alternately stacked in a stacking direction, sandwiching dielectric layers, and has a first main surface and a second main surface located on the side opposite to the first main surface in the stacking direction. The plurality of first via conductors are disposed inside the multilayer body and electrically connected to the plurality of first internal electrode layers. The plurality of second via conductors are disposed inside the multilayer body and electrically connected to the plurality of second internal electrode layers. The multilayer body includes an inner layer portion, a first outer layer portion, and a second outer layer portion. In the inner layer portion, opposing portions of the first and second internal electrode layers are stacked in the stacking direction. The first outer layer portion is adjacent to the inner layer portion in the stacking direction and forms a first main surface. The second outer layer portion is adjacent to the inner layer portion in the stacking direction and forms a second main surface. The first end face of each of the plurality of first via conductors and the plurality of second via conductors is exposed on the first main surface. The second end face of each of the plurality of first via conductors and the plurality of second via conductors is covered by the second outer layer. The second end face of at least one of the plurality of first via conductors and the plurality of second via conductors is bent into a convex shape on the second main surface side in the aforementioned stacking direction. In the second main surface, if the area overlapping with the inner layer in the aforementioned stacking direction is designated as the first region, the area not overlapping with the inner layer is designated as the second region, and the area overlapping with at least one of the plurality of first via conductors and the plurality of second via conductors is designated as the third region, then in the second region, a recessed portion is formed in the aforementioned stacking direction, and in the third region, a convex portion is formed located within the aforementioned recessed portion and protruding in the aforementioned stacking direction.

[0011] Invention Effects

[0012] According to the present invention, the flatness of the main surface of the conductor without exposed vias can be improved. Attached Figure Description

[0013] Figure 1 This is a top view of a multilayer ceramic capacitor according to an embodiment of the present invention, viewed from the first main side.

[0014] Figure 2 Observe from the direction of the arrow on line II-II Figure 1 A cross-sectional view of a multilayer ceramic capacitor.

[0015] Figure 3 This is a bottom view of a multilayer ceramic capacitor according to an embodiment of the present invention, viewed from the second main side.

[0016] Figure 4 It is Figure 2 An enlarged cross-sectional view showing the area around the second via conductor.

[0017] Figure 5 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to an embodiment of the present invention.

[0018] Figure 6 This is an image taken by magnifying the second main surface of the multilayer ceramic capacitor involved in the embodiment.

[0019] Figure 7 It will be along Figure 6 The image shown is a magnified longitudinal section of the stacked ceramic capacitor shown by line L.

[0020] Figure 8 It shows from Figure 6 A graph showing the shift in height of the line L from its starting point S to its ending point F, with the lowest position in the concave part of the second main surface as the reference.

[0021] Figure 9 It is a diagram used to illustrate the method of measuring the dimensional relationship between concave and convex parts.

[0022] Figure 10 This is a top view of a modified embodiment of the present invention, referring to a multilayer ceramic capacitor, viewed from the first main plane side. Detailed Implementation

[0023] Hereinafter, a multilayer ceramic capacitor according to an embodiment of the present invention will be described with reference to the figures. In the following description of the embodiment, the same or equivalent parts in the figures will be labeled with the same reference numerals, and their descriptions will not be repeated.

[0024] Figure 1 This is a top view of a multilayer ceramic capacitor according to an embodiment of the present invention, viewed from the first main side. Figure 2 Observe from the direction of the arrow on line II-II Figure 1 A cross-sectional view of a multilayer ceramic capacitor. Figure 3 This is a bottom view of a multilayer ceramic capacitor according to an embodiment of the present invention, viewed from the second main side. Figure 4 It is Figure 2 An enlarged cross-sectional view showing the area around the second via conductor.

[0025] like Figures 1-4 As shown, a multilayer ceramic capacitor 100 according to one embodiment of the present invention includes a multilayer body 10, a plurality of first via conductors 140 and a plurality of second via conductors 150.

[0026] like Figure 2 as well as Figure 4As shown, the laminate 10 includes a plurality of first internal electrode layers 120 and a plurality of second internal electrode layers 130 alternately stacked in the stacking direction with dielectric layers 110 sandwiched between them, and has a first main surface 101 and a second main surface 102 located on the side opposite to the first main surface 101 in the stacking direction.

[0027] The dielectric layer 110 can be made of any material, such as a ceramic material with BaTiO3, CaTiO3, SrTiO3, SrZrO3, or CaZrO3 as the main components. Alternatively, secondary components selected from the group containing Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds, in smaller quantities than the main components, can be added to these main components.

[0028] The shape of the laminate 10 is arbitrary. In this embodiment, the laminate 10 has a cuboid shape overall. A cuboid shape overall means, for example, a shape with rounded corners and edges, which is not a perfect cuboid but has six surfaces and can be understood as a cuboid overall. Therefore, the laminate 10 has a first main surface 101, a second main surface 102, a first side surface 103, a second side surface 104, a third side surface 105, and a fourth side surface 106.

[0029] The first side surface 103 to the fourth side surface 106 of the laminate 10 constitute four side surfaces of the laminate 10, other than the first main surface 101 and the second main surface 102. That is, the laminate 10 also has four side surfaces, namely the first side surface 103 to the fourth side surface 106, that connect the first main surface 101 and the second main surface 102. The first side surface 103 faces the second side surface 104, and the third side surface 105 faces the fourth side surface 106. In this embodiment, the first side surface 103 to the fourth side surface 106 of the laminate 10 are orthogonal to the first main surface 101 and the second main surface 102, but they may not be orthogonal.

[0030] The dimensions of the laminate 10 are arbitrary, but for example, when viewed from the first main surface 101, the longitudinal dimension of the rectangle can be set to 0.3 mm or more and 3.0 mm or less, the transverse dimension can be set to 0.3 mm or more and 3.0 mm or less, and the dimensions in the lamination direction of the dielectric layer 110, the first internal electrode layer 120, and the second internal electrode layer 130 can be set to 50 μm or more and 200 μm or less. The dimensions of the laminate 10 in the aforementioned lamination direction refer to the maximum thickness of the laminate 10.

[0031] Each of the plurality of first internal electrode layers 120 and the plurality of second internal electrode layers 130 has a rectangular shape. For example... Figure 2 as well as Figure 4As shown, each of the plurality of first internal electrode layers 120 has a plurality of first through holes 120h formed to allow the plurality of second through-hole conductors 150 to be inserted. Each of the plurality of second internal electrode layers 130 has a plurality of second through holes 130h formed to allow the plurality of first through-hole conductors 140 to be inserted.

[0032] The materials of the first internal electrode layer 120 and the second internal electrode layer 130 are arbitrary, for example, containing metals such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or alloys containing these metals as the main components. The first internal electrode layer 120 and the second internal electrode layer 130 may also contain the same ceramic material as the dielectric ceramic contained in the dielectric layer 110, as a common material. In this case, the proportion of the common material contained in the first internal electrode layer 120 and the second internal electrode layer 130 is, for example, 20 vol% or less.

[0033] The thickness of each of the first internal electrode layer 120 and the second internal electrode layer 130 is arbitrary, but can be set to a thickness of 0.3 μm or more and 1.0 μm or less. The number of the first internal electrode layer 120 and the second internal electrode layer 130 is arbitrary, but can be set to a thickness of 10 or more and 150 or less when combined.

[0034] like Figure 2 as well as Figure 4 As shown, the laminate 10 includes an inner layer portion E, a first outer layer portion 111, and a second outer layer portion 112. In the inner layer portion E, opposing portions of the first internal electrode layer 120 and the second internal electrode layer 130 are stacked in the aforementioned stacking direction. The first outer layer portion 111 is adjacent to the inner layer portion E in the aforementioned stacking direction and forms a first main surface 101. The second outer layer portion 112 is adjacent to the inner layer portion E in the aforementioned stacking direction and forms a second main surface 102. Both the first outer layer portion 111 and the second outer layer portion 112 are formed by a dielectric layer 110.

[0035] Multiple first via conductors 140 are disposed inside the laminate 10 and electrically connected to multiple first internal electrode layers 120. Multiple first via conductors 140 are inserted through second through-holes 130h formed in each of the multiple second internal electrode layers 130 and are insulated from the multiple second internal electrode layers 130. For example... Figure 1 As shown, in this embodiment, viewed from the aforementioned stacking direction, the plurality of first via conductors 140 are arranged in a serrated shape along the edge of the first main surface 101. The first internal electrode layer 120 is electrically connected to the four first via conductors 140.

[0036] A plurality of second via conductors 150 are disposed inside the laminate 10 and electrically connected to a plurality of second internal electrode layers 130. The plurality of second via conductors 150 are inserted through first through-holes 120h formed in each of the plurality of first internal electrode layers 120 and are insulated from the plurality of first internal electrode layers 120. In this embodiment, viewed from the aforementioned lamination direction, the plurality of second via conductors 150 are arranged in a serrated shape along the edge of the first main surface 101. The first via conductors 140 and the second via conductors 150 are arranged in a matrix configuration. The second internal electrode layer 130 is electrically connected to five of the second via conductors 150.

[0037] A plurality of first via conductors 140 and a plurality of second via conductors 150 are each disposed inside the laminate 10 in the aforementioned lamination direction, extending from the first main surface 101 toward the second main surface 102. That is, the plurality of first via conductors 140 and the plurality of second via conductors 150 are each exposed on the first main surface 101 of the laminate 10, but not on the second main surface 102. Specifically, the first end face T of each of the plurality of first via conductors 140 and the plurality of second via conductors 150 on the first main surface 101 side is exposed on the first main surface 101. The second end face B of each of the plurality of first via conductors 140 and the plurality of second via conductors 150 on the second main surface 102 side is covered by the second outer layer portion 112. This suppresses short circuits between the electronic components and the laminated ceramic capacitor 100 disposed on the second main surface 102 side.

[0038] By alternately arranging a plurality of first via conductors 140 and a plurality of second via conductors 150 in a sawtooth shape as described above, the magnetic fields induced by the currents flowing through the first via conductors 140 and the second via conductors 150 respectively cancel each other out, thereby reducing the equivalent series inductance (ESL) of the multilayer ceramic capacitor 100.

[0039] The shapes of the first via conductor 140 and the second via conductor 150 are arbitrary; for example, they can be cylindrical. In this case, the diameter of each of the first via conductor 140 and the second via conductor 150 is, for example, 15 μm or more and 40 μm or less. Furthermore, the distance between adjacent first via conductors 140 and second via conductors 150, more specifically, the distance between the center of the first via conductor 140 and the center of the second via conductor 150, is, for example, 50 μm or more and 500 μm or less.

[0040] The materials of the first via conductor 140 and the second via conductor 150 are arbitrary, such as metals like Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn or Au, or alloys containing these metals.

[0041] like Figure 2 as well as Figure 4 As shown, at least one of the plurality of first via conductors 140 and the plurality of second via conductors 150 has its second end face B bent into a convex shape toward the second main surface 102 in the aforementioned stacking direction. Preferably, all the second end faces B of the plurality of first via conductors 140 and the plurality of second via conductors 150 are bent into a convex shape toward the second main surface 102 in the aforementioned stacking direction. The second end face B of the aforementioned at least one is located closer to the second main surface 102 than the internal electrode layer among the plurality of first internal electrode layers 120 and the plurality of second internal electrode layers 130 that is closest to the third region A3 in the aforementioned stacking direction.

[0042] like Figures 2-4 As shown, in the second main surface 102, if the area overlapping with the inner layer E when viewed from the aforementioned stacking direction is designated as the first region A1, the area not overlapping with the inner layer E is designated as the second region A2, and the area overlapping with at least one of the plurality of first via conductors 140 and the plurality of second via conductors 150 is designated as the third region A3, then a recess C that is recessed in the aforementioned stacking direction is formed in the second region A2, and a protrusion P located within the recess C and protruding in the aforementioned stacking direction is formed in the third region A3. Furthermore, the third region A3 is included in the second region A2. Since the protrusion P is located within the recess C, the tip of the protrusion P is not located further outward than the opening end of the recess C in the aforementioned stacking direction.

[0043] like Figure 2 as well as Figure 4 As shown, the convex portion P is bent into a convex shape, mimicking the second end face B. That is, the convex portion P is bent into a convex shape towards the second main face 102 in the aforementioned stacking direction.

[0044] like Figure 4 As shown, the maximum depth D of the recess C in the aforementioned stacking direction is, for example, 1 μm or more and 2.5 μm or less. The minimum distance H between the tip of the protrusion P and the opening end of the recess C in the aforementioned stacking direction is, for example, 1.25 μm or less. The ratio of the minimum distance H between the tip of the protrusion P and the opening end of the recess C in the aforementioned stacking direction to the maximum depth D of the recess C in the aforementioned stacking direction is, for example, 0.5 or less. Furthermore, in any longitudinal section, at least one recess C and protrusion P need to satisfy the above-described dimensions and dimensional relationships.

[0045] On the first main surface 101, multiple external electrodes may also be formed, each connected to the first via conductor 140 and the second via conductor 150. The material of the external electrodes is arbitrary. For example, the external electrodes may be plated electrodes formed by a plating process based on spin plating. Examples of materials constituting the plated electrodes include Cu, Ni, and Sn. The plated electrodes may be composed of a single layer or multiple layers. Alternatively, the external electrodes may be formed by firing a metal paste applied to the first main surface 101. A glassy inorganic material may also be included in the metal paste as a common material.

[0046] Here, a method for manufacturing a multilayer ceramic capacitor 100 according to an embodiment of the present invention will be described.

[0047] Figure 5 This is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 5 As shown, firstly, an intermediate laminate (S1) is prepared, in which ceramic green sheets that form the inner layer E and the first outer layer 111 are stacked. Conductive paste that forms the first internal electrode layer 120 and the second internal electrode layer 130 is applied to the ceramic green sheet that forms the inner layer E, but conductive paste is not applied to the ceramic green sheet that forms the first outer layer 111.

[0048] Next, the intermediate laminate is pressed from both sides in the lamination direction (S2). At this time, an elastomer disposed on the rigid body abuts on the first main surface 101 side, and an elastomer disposed on the rigid body abuts on the second main surface 102 side. The rigid body is made of metal, and the elastomer is made of resin. The elastomer is, for example, a PET (polyethylene terephthalate) film. Compared with the inner layer E, the portion around the first through-hole conductor 140 and the second through-hole conductor 150 has less conductive paste that forms the first internal electrode layer 120 and the second internal electrode layer 130. Therefore, during pressing, this portion around the first through-hole conductor 140 and the second through-hole conductor 150 is pressed into the inner side of the intermediate laminate by the elastomer.

[0049] Next, through-holes for via conductors are formed at predetermined formation positions of the first via conductor 140 and the second via conductor 150 in the intermediate laminate (S3). The through-holes for via conductors are formed, for example, by laser irradiation.

[0050] Next, conductive paste is used to fill the through-holes for via conductors, forming the first via conductor 140 and the second via conductor 150 (S4). At this time, the filling rate of the conductive paste relative to the through-holes for via conductors is increased to a range of 105% or more and 115% or less of the usual filling rate. The so-called usual filling rate is a filling rate set so that the through-holes for via conductors will not be over- or under-filled by the first via conductor 140 and the second via conductor 150 after firing, as described later.

[0051] Next, the ceramic green sheet, which will become the second outer layer 112, is adhered to the intermediate laminate to form an unfired laminate (S5). As a result, one end of the through-hole conductor on the second main surface 102 side is blocked. At this time, the conductive paste that becomes the first through-hole conductor 140 and the second through-hole conductor 150, and the ceramic green sheet that becomes the second outer layer 112, can be either in contact with each other or separated from each other.

[0052] Next, the unfired laminate is pressed from both sides in the lamination direction (S6). At this time, an elastomer disposed on the rigid body abuts on the first main surface 101 side and an elastomer disposed on the rigid body abuts on the second main surface 102 side. The rigid body is made of metal, and the elastomer is made of resin. The elastomer is, for example, a PET film. Compared with the inner layer E, the conductive paste layer that forms the first internal electrode layer 120 and the second internal electrode layer 130 around the first through-hole conductor 140 and the second through-hole conductor 150 is less. Therefore, during pressing, the ceramic green sheet that covers this part around the first through-hole conductor 140 and the second through-hole conductor 150, forming the second outer layer 112, is pressed into the inside of the unfired laminate by the elastomer. As a result, a recess C is formed in the second region A2 of the second main surface 102.

[0053] The first end face T of the first through conductor 140 and the second through conductor 150, which abut against the elastomer, becomes a generally flat surface. However, corresponding to the increase in the filling rate of the conductive paste relative to the through-hole of the through conductor, the second end face B of the first through conductor 140 and the second through conductor 150 bulges towards the second outer layer 112. As a result, the second end face B of the first through conductor 140 and the second through conductor 150 bends into a convex shape towards the second main surface 102 in the aforementioned lamination direction.

[0054] Furthermore, the second outer layer 112 covering the first via conductor 140 and the second via conductor 150 is bent into a convex shape in imitation of the second end face B. As a result, a convex portion P is formed in the third region A3 of the second main surface 102, located within the recess C and protruding in the aforementioned stacking direction.

[0055] Next, the unfired laminate is fired (S7). Through firing, the dielectric contained in the ceramic green sheet and the conductive material contained in the conductive paste are sintered.

[0056] The multilayer ceramic capacitor 100 is manufactured using the manufacturing method described above. Alternatively, when forming external electrodes, a conductive paste that serves as the external electrode can be applied before firing, or a plating process can be performed after firing to form the external electrode.

[0057] In the multilayer ceramic capacitor 100 according to this embodiment, the first end face T of each of the plurality of first via conductors 140 and the plurality of second via conductors 150 on the first main surface 101 side is exposed on the first main surface 101. The second end face B of each of the plurality of first via conductors 140 and the plurality of second via conductors 150 on the second main surface 102 side is covered by the second outer layer portion 112. The second end face B of at least one of the plurality of first via conductors 140 and the plurality of second via conductors 150 is bent into a convex shape toward the second main surface 102 side in the aforementioned stacking direction. In the second main surface 102, if the area that overlaps with the inner layer E when viewed from the above-mentioned stacking direction is defined as the first region A1, the area that does not overlap with the inner layer E is defined as the second region A2, and the area that overlaps with at least one of the plurality of first via conductors 140 and the plurality of second via conductors 150 is defined as the third region A3, then in the second region A2, a recessed portion C is formed that is recessed in the above-mentioned stacking direction, and in the third region A3, a protrusion P that is located in the recessed portion C and protrudes in the above-mentioned stacking direction is formed.

[0058] This improves the flatness of the second main surface 102 of the multilayer ceramic capacitor 100, where the first via conductor 140 and the second via conductor 150 are not exposed.

[0059] The following describes the multilayer ceramic capacitor involved in the embodiments. Figure 6 This is an image taken by magnifying the second main surface of the multilayer ceramic capacitor involved in the embodiment. Figure 7 It will be along Figure 6 The image shown is a magnified longitudinal section of the stacked ceramic capacitor shown by line L. Figure 8 It shows from Figure 6 A graph showing the height shift within the interval from the starting point S to the ending point F of line L, with the lowest point in the concave region of the second principal surface as the reference. Figure 8 In the diagram, the vertical axis shows the height (μm), and the horizontal axis shows the position (μm) along line L from the starting point S.

[0060] Figure 6 as well as Figure 7 The magnified image shown was taken using a metallurgical microscope. Figure 8The surface shape of the second principal surface shown was measured using a digital microscope (VHX-8000) manufactured by Keyence. Figure 6 As shown, viewed from the above stacking direction, the stacked ceramic capacitor involved in the embodiment has a square shape with one side length of 680μm. Figure 7 The diameter of the second via conductor 150 shown is 23.4 μm, which is in the range of 15 μm or more and 40 μm or less.

[0061] like Figure 7 As shown, the second end face B of the second via conductor 150 is bent into a convex shape towards the second main surface 102 in the aforementioned stacking direction. In the second main surface 102, a recess C is formed in the second region A2, which is recessed in the aforementioned stacking direction; and a convex portion P is formed in the third region A3, located within the recess C and protruding in the aforementioned stacking direction. The convex portion P is bent into a convex shape similar to the second end face B. Figure 8 As shown, in from Figure 6 In the interval from the starting point S to the ending point F of the line L shown, a convex part P is formed inside each of the three concave parts C.

[0062] Figure 9 This is a diagram illustrating the method for measuring the dimensional relationships between concave and convex parts. Figure 9 In the middle, Figure 8 The deepest recess C, located in the center, is shown magnified among the three recesses C shown. (See attached image.) Figure 9 As shown, in the longitudinal section, sometimes the heights of the opening ends K1 and K2 of the recess C are inconsistent, and the heights of the bottom N1 and bottom N2 of the recess C are inconsistent.

[0063] In this case, the maximum depth D of the recess C in the aforementioned stacking direction is set as the dimension of the shortest distance between the intersection point X1 and the intersection point X2 in the aforementioned stacking direction. The intersection point X1 is the intersection of the line segment L1 connecting the opening end K1 and the opening end K2 with the straight line L3 extending in the aforementioned stacking direction and passing through the top end XP of the protrusion P. The intersection point X2 is the intersection of the line segment L2 connecting the bottom N1 and the bottom N2 with the straight line L3.

[0064] The dimension of the shortest distance H between the top of the convex portion P and the opening end of the concave portion C in the aforementioned stacking direction is set as the dimension of the shortest distance between the intersection point X1 and the top of the convex portion P XP in the aforementioned stacking direction.

[0065] like Figure 8 as well as Figure 9 As shown in the embodiment, regarding height, the opening end K1 is 2.31 μm, the opening end K2 is 2.02 μm, the bottom N1 is 0.16 μm, the bottom N2 is 0 μm, and the top of the protrusion P, XP, is 1.31 μm. The height of intersection X1 is 2.17 μm, and the height of intersection X2 is 0.08 μm.

[0066] The maximum depth D of the recess C in the aforementioned stacking direction is 2.09 μm, which is within the range of more than 1 μm and less than 2.5 μm.

[0067] The shortest distance H between the top of the convex portion P and the opening end of the concave portion C in the aforementioned stacking direction is 0.86 μm, which is within the range of 1.25 μm or less.

[0068] The ratio of the shortest distance H between the top of the protrusion P and the opening end of the concave C in the aforementioned stacking direction to the maximum depth D of the concave C in the aforementioned stacking direction is 0.41, which is within the range of 0.5 or less.

[0069] The multilayer ceramic capacitor described in this embodiment effectively improves the flatness of the second main surface 102, where the first through-hole conductor 140 and the second through-hole conductor 150 are not exposed, by satisfying the numerical range of the dimensions and dimensional relationships described above. This allows the suction nozzle to be in close contact with the second main surface 102, thereby stably holding the multilayer ceramic capacitor. Preferably, in any longitudinal section, all the recesses C and convex portions P satisfy the dimensions and dimensional relationships described above.

[0070] Furthermore, the configuration of the first via conductor 140 and the second via conductor 150 is not limited to the configuration shown in the above-described embodiments and examples. Figure 10 This is a top view of a modified embodiment of the present invention, referring to a multilayer ceramic capacitor, viewed from the first main surface side. (See attached image.) Figure 10 As shown, in a modified embodiment of the multilayer ceramic capacitor 100a according to the present invention, viewed from the stacking direction, a plurality of first via conductors 140 are arranged in a sawtooth shape along the diagonal of the outline of the first main surface 101. Viewed from the stacking direction, a plurality of second via conductors 150 are arranged in a sawtooth shape along the diagonal of the outline of the first main surface 101. The first via conductors 140 and the second via conductors 150 are arranged in a matrix. By alternately arranging the plurality of first via conductors 140 and the plurality of second via conductors 150 in a sawtooth shape as described above, the magnetic fields induced by the currents flowing through the first via conductors 140 and the second via conductors 150 respectively cancel each other out, thereby reducing the equivalent series inductance (ESL) of the multilayer ceramic capacitor 100a.

[0071] (Postscript)

[0072] Those skilled in the art will understand that the above exemplary embodiments are specific examples of the following approaches.

[0073] <1>

[0074] A multilayer ceramic capacitor, comprising:

[0075] A laminate comprising a plurality of first internal electrode layers and a plurality of second internal electrode layers alternately stacked in a stacking direction with dielectric layers sandwiched between them, having a first main surface and a second main surface located on the side opposite to the first main surface in the stacking direction.

[0076] A plurality of first via conductors are disposed inside the laminate and electrically connected to the plurality of first internal electrode layers; and

[0077] Multiple second via conductors are disposed inside the laminate and electrically connected to the multiple second internal electrode layers.

[0078] The laminate includes an inner layer portion in which opposing portions of the first inner electrode layer and the second inner electrode layer are stacked in the stacking direction, a first outer layer portion adjacent to the inner layer portion in the stacking direction and forming the first main surface, and a second outer layer portion adjacent to the inner layer portion in the stacking direction and forming the second main surface.

[0079] The first end face of each of the plurality of first via conductors and the plurality of second via conductors is exposed on the first main surface.

[0080] The second end face of the second main surface of each of the plurality of first via conductors and the plurality of second via conductors is covered by the second outer layer.

[0081] The second end of at least one of the plurality of first via conductors and the plurality of second via conductors is bent into a convex shape towards the second main surface side in the stacking direction.

[0082] In the second main surface, if the region overlapping with the inner layer in the stacking direction is designated as the first region, the region not overlapping with the inner layer is designated as the second region, and the region overlapping with at least one of the plurality of first via conductors and the plurality of second via conductors is designated as the third region, then

[0083] In the second region, a recessed portion is formed in the stacking direction.

[0084] Within the third region, a protrusion is formed that is located within the recess and protrudes in the stacking direction.

[0085] <2>

[0086] according to <1> The described multilayer ceramic capacitors, among which,

[0087] The protrusion is bent into a convex shape in imitation of the second end face.

[0088] <3>

[0089] according to <1> or <2> The described multilayer ceramic capacitors, among which,

[0090] The maximum depth of the recess in the stacking direction is greater than 1 μm and less than 2.5 μm.

[0091] <4>

[0092] according to <3> The described multilayer ceramic capacitors, among which,

[0093] The shortest distance in the stacking direction between the top of the protrusion and the opening end of the recess is less than 1.25 μm.

[0094] <5>

[0095] according to <1> or <2> The described multilayer ceramic capacitors, among which,

[0096] The ratio of the shortest distance in the stacking direction between the top of the protrusion and the opening end of the concave portion to the maximum depth of the concave portion in the stacking direction is 0.5 or less.

[0097] <6>

[0098] according to <1> to <5> Among the multilayer ceramic capacitors described in any one of the following,

[0099] The diameter of each of the plurality of first via conductors and the plurality of second via conductors is 15 μm or more and 40 μm or less.

[0100] In the above description of the embodiments and examples, the combinable structures can also be combined with each other.

[0101] It should be understood that the embodiments and examples disclosed herein are illustrative and not restrictive in all respects. The scope of the invention is set forth not by the foregoing description but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0102] Explanation of reference numerals in the attached figures

[0103] 10: Laminated body; 100: Laminated ceramic capacitor; 101: First main surface; 102: Second main surface; 103: First side surface; 104: Second side surface; 105: Third side surface; 106: Fourth side surface; 110: Dielectric layer; 111: First outer layer; 112: Second outer layer; 120: First internal electrode layer; 120h: First through hole; 130: Second internal electrode layer; 130h: Second through hole; 140: First via conductor; 150: Second via conductor; A1: First region; A2: Second region; A3: Third region; B: Second end face; C: Recess; E: Inner layer; F: End point; H: Shortest distance; K1, K2: Opening end; N1, N2: Bottom; P: Protrusion; S: Starting point; T: First end face; X1, X2: Intersection point; XP: Top point.

Claims

1. A multilayer ceramic capacitor, comprising: A laminate comprising a plurality of first internal electrode layers and a plurality of second internal electrode layers alternately stacked in a stacking direction with dielectric layers sandwiched between them, having a first main surface and a second main surface located on the side opposite to the first main surface in the stacking direction. A plurality of first via conductors are disposed inside the laminate and electrically connected to the plurality of first internal electrode layers; and Multiple second via conductors are disposed inside the laminate and electrically connected to the multiple second internal electrode layers. The laminate includes an inner layer portion in which opposing portions of the first inner electrode layer and the second inner electrode layer are stacked in the stacking direction, a first outer layer portion adjacent to the inner layer portion in the stacking direction and forming the first main surface, and a second outer layer portion adjacent to the inner layer portion in the stacking direction and forming the second main surface. The first end face of each of the plurality of first via conductors and the plurality of second via conductors is exposed on the first main surface. The second end face of the second main surface of each of the plurality of first via conductors and the plurality of second via conductors is covered by the second outer layer. The second end of at least one of the plurality of first via conductors and the plurality of second via conductors is bent into a convex shape towards the second main surface side in the stacking direction. In the second main surface, if the region overlapping with the inner layer in the stacking direction is designated as the first region, the region not overlapping with the inner layer is designated as the second region, and the region overlapping with at least one of the plurality of first via conductors and the plurality of second via conductors is designated as the third region, then In the second region, a recessed portion is formed in the stacking direction. Within the third region, a protrusion is formed that is located within the recess and protrudes in the stacking direction.

2. The multilayer ceramic capacitor according to claim 1, wherein, The protrusion is bent into a convex shape in imitation of the second end face.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein, The maximum depth of the recess in the stacking direction is greater than 1 μm and less than 2.5 μm.

4. The multilayer ceramic capacitor according to claim 3, wherein, The shortest distance in the stacking direction between the top of the protrusion and the opening end of the recess is less than 1.25 μm.

5. The multilayer ceramic capacitor according to claim 1 or 2, wherein, The ratio of the shortest distance in the stacking direction between the top of the protrusion and the opening end of the concave portion to the maximum depth of the concave portion in the stacking direction is 0.5 or less.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein, The diameter of each of the plurality of first via conductors and the plurality of second via conductors is 15 μm or more and 40 μm or less.

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