A method and system for FT test program front-end verification based on UVM and virtual instrument linkage
By using the FT test procedure forward verification method that links UVM with virtual instruments, the problem of fragmented chip mass production test procedures has been solved. This enables the early detection and repair of logic errors and timing mismatch issues in the design phase, shortens the development cycle, reduces costs, and improves resource utilization efficiency and mass production stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HANGZHOU XINGUANG SEMICONDUCTOR CO LTD
- Filing Date
- 2026-04-22
- Publication Date
- 2026-07-28
AI Technical Summary
The traditional chip mass production testing program development and verification work is disconnected, which makes it impossible to fully verify key parameters in the design stage. Problems are found after tape-out and need to be reworked, resulting in long cycles and high costs.
The FT test procedure forward verification method based on UVM and virtual instrument linkage is adopted. By analyzing chip requirements, a forward verification environment is constructed, functional simulation is performed and verification data packets are generated, which are converted into virtual instrument simulation layer signals, hardware-in-the-loop simulation is performed, and physical calibration is fed back to form a closed-loop iterative optimization.
By identifying and fixing logic errors and timing mismatch issues before tape-out, we can shorten the development cycle, reduce reliance on physical machines, improve resource utilization efficiency, ensure mass production stability, reduce the cost of repetitive development, and achieve full-chain traceability of defects.
Smart Images
Figure CN122470286A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor chip testing technology, specifically to a method and system for forward verification of FT test procedures based on the linkage of UVM and virtual instruments. Background Technology
[0002] In the traditional chip mass production test program development process, the development and verification of test programs usually only begin after the chip tape-out is completed. The design and testing phases are disconnected, which means that key parameters such as timing configurations, level thresholds, and decision logic contained in the test program cannot be fully verified during the design phase. Once a logic error or timing mismatch problem is found in the test program during the mass production implementation phase after tape-out, it is necessary to go back to the design phase for modification and regenerate the test vector. This process involves cross-phase collaboration among multiple teams in design, verification, and testing, which significantly extends the problem-solving cycle and greatly increases development costs. Summary of the Invention
[0003] The purpose of this invention is to provide a method and system for forward verification of FT test procedures based on the linkage of UVM and virtual instruments, so as to solve the problems mentioned in the background art.
[0004] To achieve the above objectives, the present invention provides the following technical solution: a method for forward verification of FT test procedures based on the linkage of UVM and virtual instruments, comprising the following steps: S1. Analyze the chip FT test requirements, extract test vectors, timing parameters and judgment conditions, and transform the analyzed information into standardized UVM verification components to build a forward verification environment framework. S2. Load the standardized UVM verification components in the UVM verification environment, perform functional simulation, collect simulation coverage data, and generate a UVM simulation verification data package containing excitation waveforms, coverage reports, and intermediate state information. S3. The UVM simulation verification data package is converted into drive signals and timing configurations that can be recognized by the virtual instrument simulation layer through the cross-stage adaptation layer. S4. The virtual instrument simulation layer loads a virtual instrument model that is consistent with the behavior of the mass production test machine. It performs hardware-in-the-loop simulation based on the converted drive signals and timing configuration, compares the virtual output with the expected results, calculates the timing error, and generates a virtual verification report. S5. Deploy the test program that has passed virtual verification to the physical mass production test machine, perform physical calibration test, and collect physical test data; S6. Through the cross-stage adaptation layer, the physical machine test data is fed back to the UVM verification environment and the virtual instrument simulation layer. Based on the feedback data, the simulation model and interface adaptation parameters are calibrated to form a closed-loop iterative optimization.
[0005] As a preferred embodiment of the present invention, the standardized UVM verification components in step S1 include an excitation generator, a driver, a monitor, and a scoreboard. The stimulus generator generates a stimulus sequence based on the test case specifications. The driver drives the stimulus sequence to the interface of the design under test. The monitor collects the output response of the design under test. The scoreboard compares the actual output with the expected response and records the comparison results.
[0006] As a preferred embodiment of the present invention, the data conversion performed by the cross-stage adaptation layer in step S3 includes at least one of the following conversion methods: Convert the test vector format output by the UVM verification layer into the driving signal format corresponding to the virtual instrument simulation layer; Map UVM timing window parameters to timing configuration parameters that can be executed by the virtual instrument; Convert the signal level standard in the UVM verification layer to a level threshold configuration compatible with the virtual instrument simulation layer; Convert assertion expressions in the UVM verification environment into decision condition rules for the virtual instrument simulation layer.
[0007] As a preferred embodiment of the present invention, the process of performing hardware-in-the-loop simulation in step S4 further includes: S41. The virtual instrument simulation layer applies excitation to the virtual instrument model cycle by cycle according to the converted drive signal and the timing configuration. S42, Virtual instrument model simulates the hardware behavior of mass production test equipment, including pin driving, timing generation, level comparison and parameter measurement; S43. Collect the output response of the virtual instrument model, compare it with the expected response cycle by cycle, and record the comparison status of each test cycle. S44. Count the number of comparison failures for all test cycles, calculate the timing error distribution, and generate a virtual verification report containing error waveforms and error statistics tables.
[0008] As a preferred embodiment of the present invention, the closed-loop iterative optimization in step S6 includes at least one of the following calibration operations: The timing compensation parameters obtained during the physical machine calibration process are reverse-updated to the timing constraints in the UVM verification component library. Synchronize the actual level threshold measured by the physical instrument to the level comparator model in the virtual instrument simulation layer; The judgment deviation rules found in the physical machine test are used to correct the scoreboard judgment logic in the UVM verification environment. The channel deviation values in the physical machine test data are fed back to the signal mapping table of the cross-stage adaptation layer to correct the signal alignment accuracy in the subsequent conversion process.
[0009] A forward verification system for FT testing procedures based on the linkage of UVM and virtual instruments includes: The requirement parsing layer is used to receive and parse the chip FT test requirements, extract test vectors, timing parameters and decision conditions, and transform the parsed information into standardized UVM verification components to build a forward verification environment framework. The UVM verification layer connects to the requirements parsing layer. It is used to load standardized UVM verification components and perform functional simulation, collect simulation coverage data, and generate a UVM simulation verification data package containing excitation waveforms, coverage reports, and intermediate state information. The cross-stage adaptation layer connects to the UVM verification layer and is used to receive UVM simulation verification data packets and convert the UVM simulation verification data packets into drive signals and timing configurations that can be recognized by the virtual instrument simulation layer. The virtual instrument simulation layer connects to the cross-stage adaptation layer. It is used to load virtual instrument models that are consistent with the behavior of mass production test equipment, perform hardware-in-the-loop simulation based on the converted drive signals and timing configuration, compare the virtual output with the expected results, calculate the timing error, and generate a virtual verification report. The physical machine calibration interface connects to the cross-stage adaptation layer and is used to deploy the test program that has passed virtual verification to the physical mass production test machine to perform physical calibration tests and collect physical machine test data. The closed-loop feedback module, integrated within the cross-stage adaptation layer, is used to feed back physical machine test data to the UVM verification layer and the virtual instrument simulation layer. Based on the feedback data, the simulation model and interface adaptation parameters are calibrated to form a closed-loop iterative optimization.
[0010] As a preferred embodiment of the present invention, the UVM verification layer has a built-in reusable UVM test component library, which includes an excitation generator, a driver, a monitor, and a scoring board. The stimulus generator generates a stimulus sequence based on the test case specifications, the driver drives the stimulus sequence to the interface of the design under test, the monitor collects the output response of the design under test, and the scoreboard compares the actual output with the expected response and records the comparison results.
[0011] As a preferred technical solution of the present invention, the cross-stage adaptation layer includes at least one of a data format conversion unit, a timing mapping unit, a level conversion unit, and a judgment rule mapping unit. The data format conversion unit is used to convert the test vector format output by the UVM verification layer into the drive signal format corresponding to the virtual instrument simulation layer; The timing mapping unit is used to map UVM timing window parameters to timing configuration parameters that can be executed by the virtual instrument; The level conversion unit is used to convert the signal level standard in the UVM verification layer to a level threshold configuration compatible with the virtual instrument simulation layer; The decision rule mapping unit is used to convert assertion expressions in the UVM verification environment into decision condition rules for the virtual instrument simulation layer.
[0012] As a preferred embodiment of the present invention, the virtual instrument simulation layer includes an excitation application unit, a hardware behavior simulation unit, a response acquisition unit, and an error statistics unit; The excitation application unit is used to apply excitation cycle by cycle according to the timing configuration of the converted drive signal; The hardware behavior simulation unit is used to simulate the pin driving, timing generation, level comparison and parameter measurement behavior of mass production test equipment; The response acquisition unit is used to acquire the output response of the virtual instrument model and compare it with the expected response cycle by cycle. The error statistics unit is used to count the number of alignment failures, calculate the timing error distribution, and generate a virtual verification report that includes error waveforms and error statistics tables.
[0013] As a preferred technical solution of the present invention, the closed-loop feedback module includes a parameter extraction unit and a model update unit. The model update unit further includes at least one of a timing compensation subunit, a level calibration subunit, a decision logic correction subunit, and a signal mapping correction subunit. The parameter extraction unit is used to extract timing compensation parameters, level threshold deviations, judgment deviation rules, and channel deviation values from physical machine test data; The timing compensation subunit is used to update the timing compensation parameters in reverse to the timing constraints in the UVM verification component library; The level calibration subunit is used to synchronize the actual level threshold measured by the physical instrument to the level comparator model in the virtual instrument simulation layer; The decision logic correction subunit is used to reverse the decision deviation rules and correct the scoreboard decision logic in the UVM verification environment. The signal mapping correction subunit is used to feed back the channel deviation value to the signal mapping table of the cross-stage adaptation layer.
[0014] Compared with the prior art, the beneficial effects of the present invention are: 1. This invention moves the development and verification of FT test programs to the chip design stage, and constructs a three-level closed-loop process of simulation verification, virtual verification and physical calibration. This can detect and fix logic errors and timing mismatch problems in the test program in advance before tape-out, and significantly shorten the test program development cycle.
[0015] 2. This invention loads a virtual instrument model that behaves identically to a mass production test machine through a virtual instrument simulation layer, and performs hardware-in-the-loop simulation. This replaces a large amount of debugging work that relies on physical machines, effectively reducing the time spent on physical machines, alleviating machine resource bottlenecks, and improving resource utilization efficiency.
[0016] 3. This invention achieves data format conversion and verification standard mapping between the UVM verification layer, the virtual instrument simulation layer and the physical machine through a cross-stage adaptation layer. Combined with a closed-loop feedback mechanism, the actual test data of the physical machine is used to calibrate the simulation model in reverse, ensuring the timing consistency and functional completeness between the virtual verification environment and the mass production environment, and ensuring the stability and reliability of the test program when it is migrated to the mass production stage.
[0017] 4. This invention transforms FT test requirements into standardized UVM verification components through a requirement parsing layer, establishing a reusable UVM test component library that supports rapid adaptation to multiple chip models, significantly reducing repetitive development costs and promoting the standardization of FT test processes within enterprises.
[0018] 5. This invention establishes a defect traceability management mechanism through a cross-stage adaptation layer, recording the entire process of defect discovery from UVM simulation, virtual verification and reproduction to physical calibration and repair, realizing full-link traceability and reproducibility of defects, and effectively improving the efficiency of problem location and quality control capabilities. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of the overall process of the FT test procedure forward verification method based on the linkage of UVM and virtual instruments according to the present invention. Figure 2 This is a structural framework diagram of an FT test procedure forward verification system based on the linkage of UVM and virtual instruments according to the present invention. Detailed Implementation
[0020] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0021] Example 1 A method for forward verification of FT test procedures based on the linkage of UVM and virtual instruments includes the following steps: S1. Analyze the chip FT test requirements, extract test vectors, timing parameters and judgment conditions, and transform the analyzed information into standardized UVM verification components to build a forward verification environment framework. S2. Load the standardized UVM verification components in the UVM verification environment, perform functional simulation, collect simulation coverage data, and generate a UVM simulation verification data package containing excitation waveforms, coverage reports, and intermediate state information. S3. The UVM simulation verification data package is converted into drive signals and timing configurations that can be recognized by the virtual instrument simulation layer through the cross-stage adaptation layer. S4. The virtual instrument simulation layer loads a virtual instrument model that is consistent with the behavior of the mass production test machine. It performs hardware-in-the-loop simulation based on the converted drive signals and timing configuration, compares the virtual output with the expected results, calculates the timing error, and generates a virtual verification report. S5. Deploy the test program that has passed virtual verification to the physical mass production test machine, perform physical calibration test, and collect physical test data; S6. Through the cross-stage adaptation layer, the physical machine test data is fed back to the UVM verification environment and the virtual instrument simulation layer. Based on the feedback data, the simulation model and interface adaptation parameters are calibrated to form a closed-loop iterative optimization.
[0022] Furthermore, the standardized UVM verification components in step S1 include an excitation generator, a driver, a monitor, and a scoreboard. The stimulus generator generates a stimulus sequence based on the test case specifications. The driver drives the stimulus sequence to the interface of the design under test. The monitor collects the output response of the design under test. The scoreboard compares the actual output with the expected response and records the comparison results.
[0023] Furthermore, the data transformation performed across the stage adaptation layer in step S3 includes at least one of the following transformation methods: Convert the test vector format output by the UVM verification layer into the driving signal format corresponding to the virtual instrument simulation layer; Map UVM timing window parameters to timing configuration parameters that can be executed by the virtual instrument; Convert the signal level standard in the UVM verification layer to a level threshold configuration compatible with the virtual instrument simulation layer; Convert assertion expressions in the UVM verification environment into decision condition rules for the virtual instrument simulation layer.
[0024] Furthermore, the process of performing hardware-in-the-loop simulation in step S4 further includes: S41. The virtual instrument simulation layer applies excitation to the virtual instrument model cycle by cycle according to the converted drive signal and the timing configuration. S42, Virtual instrument model simulates the hardware behavior of mass production test equipment, including pin driving, timing generation, level comparison and parameter measurement; S43. Collect the output response of the virtual instrument model, compare it with the expected response cycle by cycle, and record the comparison status of each test cycle. S44. Count the number of comparison failures for all test cycles, calculate the timing error distribution, and generate a virtual verification report containing error waveforms and error statistics tables.
[0025] Furthermore, the closed-loop iterative optimization in step S6 includes at least one of the following calibration operations: The timing compensation parameters obtained during the physical machine calibration process are reverse-updated to the timing constraints in the UVM verification component library. Synchronize the actual level threshold measured by the physical instrument to the level comparator model in the virtual instrument simulation layer; The judgment deviation rules found in the physical machine test are used to correct the scoreboard judgment logic in the UVM verification environment. The channel deviation values in the physical machine test data are fed back to the signal mapping table of the cross-stage adaptation layer to correct the signal alignment accuracy in the subsequent conversion process.
[0026] A forward verification system for FT testing procedures based on the linkage of UVM and virtual instruments includes: The requirement parsing layer is used to receive and parse the chip FT test requirements, extract test vectors, timing parameters and decision conditions, and transform the parsed information into standardized UVM verification components to build a forward verification environment framework. The UVM verification layer connects to the requirements parsing layer. It is used to load standardized UVM verification components and perform functional simulation, collect simulation coverage data, and generate a UVM simulation verification data package containing excitation waveforms, coverage reports, and intermediate state information. The cross-stage adaptation layer connects to the UVM verification layer and is used to receive UVM simulation verification data packets and convert the UVM simulation verification data packets into drive signals and timing configurations that can be recognized by the virtual instrument simulation layer. The virtual instrument simulation layer connects to the cross-stage adaptation layer. It is used to load virtual instrument models that are consistent with the behavior of mass production test equipment, perform hardware-in-the-loop simulation based on the converted drive signals and timing configuration, compare the virtual output with the expected results, calculate the timing error, and generate a virtual verification report. The physical machine calibration interface connects to the cross-stage adaptation layer and is used to deploy the test program that has passed virtual verification to the physical mass production test machine to perform physical calibration tests and collect physical machine test data. The closed-loop feedback module, integrated within the cross-stage adaptation layer, is used to feed back physical machine test data to the UVM verification layer and the virtual instrument simulation layer. Based on the feedback data, the simulation model and interface adaptation parameters are calibrated to form a closed-loop iterative optimization.
[0027] Furthermore, the UVM validation layer includes a built-in reusable UVM test component library, which includes stimulus generators, drivers, monitors, and scoreboards. The stimulus generator generates a stimulus sequence based on the test case specifications, the driver drives the stimulus sequence to the interface of the design under test, the monitor collects the output response of the design under test, and the scoreboard compares the actual output with the expected response and records the comparison results.
[0028] Furthermore, the cross-stage adaptation layer includes at least one of the following units: a data format conversion unit, a timing mapping unit, a level conversion unit, and a decision rule mapping unit. The data format conversion unit is used to convert the test vector format output by the UVM verification layer into the drive signal format corresponding to the virtual instrument simulation layer; The timing mapping unit is used to map UVM timing window parameters to timing configuration parameters that can be executed by the virtual instrument; The level conversion unit is used to convert the signal level standard in the UVM verification layer to a level threshold configuration compatible with the virtual instrument simulation layer; The decision rule mapping unit is used to convert assertion expressions in the UVM verification environment into decision condition rules for the virtual instrument simulation layer.
[0029] Furthermore, the virtual instrument simulation layer includes an excitation application unit, a hardware behavior simulation unit, a response acquisition unit, and an error statistics unit; The excitation application unit is used to apply excitation cycle by cycle according to the timing configuration of the converted drive signal; The hardware behavior simulation unit is used to simulate the pin driving, timing generation, level comparison and parameter measurement behavior of mass production test equipment; The response acquisition unit is used to acquire the output response of the virtual instrument model and compare it with the expected response cycle by cycle. The error statistics unit is used to count the number of alignment failures, calculate the timing error distribution, and generate a virtual verification report that includes error waveforms and error statistics tables.
[0030] Furthermore, the closed-loop feedback module includes a parameter extraction unit and a model update unit. The model update unit further includes at least one of the following sub-units: a timing compensation sub-unit, a level calibration sub-unit, a decision logic correction sub-unit, and a signal mapping correction sub-unit. The parameter extraction unit is used to extract timing compensation parameters, level threshold deviations, judgment deviation rules, and channel deviation values from physical machine test data; The timing compensation subunit is used to update the timing compensation parameters in reverse to the timing constraints in the UVM verification component library; The level calibration subunit is used to synchronize the actual level threshold measured by the physical instrument to the level comparator model in the virtual instrument simulation layer; The decision logic correction subunit is used to reverse the decision deviation rules and correct the scoreboard decision logic in the UVM verification environment. The signal mapping correction subunit is used to feed back the channel deviation value to the signal mapping table of the cross-stage adaptation layer.
[0031] Example 2 This embodiment takes a multi-channel power management chip for the automotive electronics field as an example to further illustrate the specific application and logical derivation process of the proposed FT test procedure forward verification method and system based on UVM and virtual instrument linkage in complex analog mixed signal chip test scenarios.
[0032] This power management chip includes 8 independent output DC-DC converters, 3 LDO regulators, 2 voltage monitors, and 1 SPI communication interface, totaling 64 FT test cases, covering output voltage accuracy testing, load regulation testing, line regulation testing, overcurrent protection threshold testing, overheat protection response testing, and SPI communication protocol consistency testing.
[0033] During the requirements analysis phase, the requirements analysis layer receives the FT test specification of the chip and extracts the test vectors, timing parameters, and judgment conditions corresponding to each test case. Taking the output voltage accuracy test as an example, the extracted test vectors include the output voltage setting command code, the enable signal sequence, and the feedback voltage reading command; the timing parameters include the command code setup time, the hold time, and the reading window width; the judgment condition is that the deviation between the actual output voltage and the nominal value does not exceed ±1.5%. The requirements analysis layer transforms the above 64 test cases into 64 standardized UVM verification components one by one. Each component encapsulates the corresponding stimulus sequence, expected response, and judgment criteria, thereby constructing a forward verification environment framework for the power management chip.
[0034] During the UVM simulation verification phase, the UVM verification layer loads the aforementioned 64 standardized UVM verification components and performs functional simulation. The excitation generator generates an excitation sequence containing setting instruction codes and enable signals according to the specifications of the output voltage accuracy test case. The driver drives this sequence to the SPI interface and enable pin of the design under test. The monitor collects the feedback voltage value and status flag bit output by the design under test. The scoring board compares the actual output voltage value with the expected nominal value one by one. During the simulation, the scoring board recorded three comparison failures: two of the failures were due to incorrect setting of the judgment threshold offset in the load regulation test case, and the other failure was due to the protection response timing window configuration in the overcurrent protection test case not matching the datasheet. After the developers corrected the above errors according to the comparison failure records output by the scoring board, the simulation was re-executed. Finally, the test coverage of the UVM verification layer reached 98.7%, and the coverage report showed that all functional points were covered.
[0035] During the cross-stage adaptation and conversion phase, the cross-stage adaptation layer receives the UVM simulation verification data packet and performs multi-dimensional data conversion. The data format conversion unit converts the binary test vector sequence output by the UVM verification layer into a waveform description format recognizable by the virtual instrument simulation layer. The timing mapping unit maps the setup time, hold time, and read window width parameters defined in the UVM environment in clock cycles to timing configuration parameters based on nanosecond-level time resolution in the virtual instrument simulation layer. The level conversion unit converts the 1.8V and 3.3V digital signal level standards in the UVM verification layer into threshold voltage configurations compatible with the virtual instrument simulation layer. The decision rule mapping unit converts the SystemVerilog assertion expressions in the UVM verification environment into executable condition decision rule statements in the virtual instrument simulation layer. After completing the above conversions, the cross-stage adaptation layer generates a complete drive signal and timing configuration file.
[0036] During the hardware-in-the-loop simulation phase of the virtual instrument, the virtual instrument simulation layer loads a virtual instrument model that behaves identically to the Teradyne UltraFLEX mass production test bench. This model fully simulates the driving capability of the pin electronics modules of the Teradyne UltraFLEX bench, the resolution accuracy of the timing generator, the threshold setting range of the voltage comparator, and the measurement accuracy of the parameter measurement unit. The excitation application unit applies excitation to the virtual instrument model cycle by cycle according to the converted drive signal file and the timing configuration file. Taking the SPI communication protocol conformance test as an example, the excitation application unit generates a 10MHz SPI clock signal, serial data output signal, and chip select signal on the digital channel of the virtual instrument model. The timing configuration strictly follows the requirements of a setup time of not less than 5ns and a hold time of not less than 5ns specified in the chip datasheet. The hardware behavior simulation unit simulates the bench pins. The electronic module drives the applied excitation with a level, while the analog parameter measurement unit performs analog-to-digital conversion measurement on the feedback voltage. The response acquisition unit acquires the response signal output by the virtual instrument model and compares it with the expected response cycle by cycle, recording the pass or fail status of the comparison in each test cycle. The error statistics unit performs statistical analysis on the comparison results of all test cycles and calculates the maximum timing error to be 2.8 ns, corresponding to a timing error percentage of 2.1%. This value is lower than the preset error tolerance threshold of 5% in this embodiment. The error statistics unit also generates a virtual verification report containing an error waveform diagram and an error statistics table. The report clearly marks the specific time location and magnitude of the error.
[0037] During the physical calibration phase, the test program that passed virtual verification was deployed to the physical Teradyne UltraFLEX mass production test machine to perform actual calibration on the first batch of engineering samples. The physical calibration interface loads the test program into the machine controller and executes the complete FT test sequence. Taking the actual operation of a chip packaging and testing factory in East China as an example, the physical machine performed full-parameter testing on 50 engineering samples. The test results were highly consistent with the expected results in the virtual verification report. The physical calibration interface collects the test data of the physical machine, including the measured output voltage of each chip, the protection threshold trigger point, the response time measurement, and the SPI communication bit error rate statistics.
[0038] During the closed-loop feedback optimization phase, the parameter extraction unit of the closed-loop feedback module extracts the following parameters from the physical test data: In the output voltage accuracy test, there is a constant deviation of 0.8% between the measured average value and the nominal value; in the overcurrent protection threshold test, the measured protection trigger point is 2.5% lower than the design value; in the SPI communication test, there is a measured inter-channel deviation of 1.2ns between the clock line and the data line. The timing compensation subunit converts the 0.8% deviation in the output voltage accuracy test into timing compensation parameters and updates the corresponding timing constraints in the UVM verification component library in reverse, so that the expected results in the subsequent simulation are aligned with the actual measurement results. The level calibration subunit synchronizes the 2.5% deviation in the overcurrent protection threshold test to the level comparator model of the virtual instrument simulation layer and corrects the reference voltage setting value of the threshold comparator in the virtual model. The signal mapping correction subunit feeds back the 1.2ns inter-channel deviation value measured in the SPI communication test to the signal mapping table of the cross-stage adaptation layer, and automatically performs timing alignment compensation for the channel pair during the subsequent test program conversion process.
[0039] After the above closed-loop iterative optimization, the virtual instrument hardware-in-the-loop simulation and physical machine calibration test were performed again. The timing error was reduced from the initial 2.8ns to less than 0.5ns. The pass rate of all test cases reached 100%. The development cycle of the FT test program of this power management chip was shortened by about 45% compared with the traditional mode. Moreover, the optimized UVM verification component library has been successfully reused in the other two power management chips developed in this series. The component reuse rate reached 83%.
[0040] This embodiment demonstrates through technical logic derivation that the cross-stage adaptation layer proposed in this invention achieves seamless conversion of heterogeneous data between the UVM simulation environment and the virtual instrument simulation layer; the closed-loop feedback module reverse-drives the simulation model calibration with the actual measured data from the physical instrument, forming an iterative convergence mechanism of simulation-virtual verification-physical calibration. The above technical logic does not depend on specific chip types or test instrument models and has wide applicability and reproducibility.
[0041] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention.
Claims
1. A method for forward verification of FT test procedures based on the linkage of UVM and virtual instruments, characterized in that, Includes the following steps: S1. Analyze the chip FT test requirements, extract test vectors, timing parameters and judgment conditions, and transform the analyzed information into standardized UVM verification components to build a forward verification environment framework. S2. Load the standardized UVM verification components in the UVM verification environment, perform functional simulation, collect simulation coverage data, and generate a UVM simulation verification data package containing excitation waveforms, coverage reports, and intermediate state information. S3. The UVM simulation verification data package is converted into drive signals and timing configurations that can be recognized by the virtual instrument simulation layer through the cross-stage adaptation layer. S4. The virtual instrument simulation layer loads a virtual instrument model that is consistent with the behavior of the mass production test machine. It performs hardware-in-the-loop simulation based on the converted drive signals and timing configuration, compares the virtual output with the expected results, calculates the timing error, and generates a virtual verification report. S5. Deploy the test program that has passed virtual verification to the physical mass production test machine, perform physical calibration test, and collect physical test data; S6. Through the cross-stage adaptation layer, the physical machine test data is fed back to the UVM verification environment and the virtual instrument simulation layer. Based on the feedback data, the simulation model and interface adaptation parameters are calibrated to form a closed-loop iterative optimization.
2. The method according to claim 1, characterized in that, The standardized UVM verification components in step S1 include an excitation generator, a driver, a monitor, and a scoreboard. The stimulus generator generates a stimulus sequence based on the test case specifications. The driver drives the stimulus sequence to the interface of the design under test. The monitor collects the output response of the design under test. The scoreboard compares the actual output with the expected response and records the comparison results.
3. The method according to claim 1, characterized in that, The data transformation performed in step S3 across the stage adaptation layer includes at least one of the following transformation methods: Convert the test vector format output by the UVM verification layer into the driving signal format corresponding to the virtual instrument simulation layer; Map UVM timing window parameters to timing configuration parameters that can be executed by the virtual instrument; Convert the signal level standard in the UVM verification layer to a level threshold configuration compatible with the virtual instrument simulation layer; Convert assertion expressions in the UVM verification environment into decision condition rules for the virtual instrument simulation layer.
4. The method according to claim 1, characterized in that, The hardware-in-the-loop simulation process in step S4 further includes: S41. The virtual instrument simulation layer applies excitation to the virtual instrument model cycle by cycle according to the converted drive signal and the timing configuration. S42, Virtual instrument model simulates the hardware behavior of mass production test equipment, including pin driving, timing generation, level comparison and parameter measurement; S43. Collect the output response of the virtual instrument model, compare it with the expected response cycle by cycle, and record the comparison status of each test cycle. S44. Count the number of comparison failures for all test cycles, calculate the timing error distribution, and generate a virtual verification report containing error waveforms and error statistics tables.
5. The method according to claim 1, characterized in that, The closed-loop iterative optimization in step S6 includes at least one of the following calibration operations: The timing compensation parameters obtained during the physical machine calibration process are reverse-updated to the timing constraints in the UVM verification component library. Synchronize the actual level threshold measured by the physical instrument to the level comparator model in the virtual instrument simulation layer; The judgment deviation rules found in the physical machine test are used to correct the scoreboard judgment logic in the UVM verification environment. The channel deviation values in the physical machine test data are fed back to the signal mapping table of the cross-stage adaptation layer to correct the signal alignment accuracy in the subsequent conversion process.
6. A forward verification system for FT testing procedures based on the linkage of UVM and virtual instruments, characterized in that, include: The requirement parsing layer is used to receive and parse the chip FT test requirements, extract test vectors, timing parameters and decision conditions, and transform the parsed information into standardized UVM verification components to build a forward verification environment framework. The UVM verification layer connects to the requirements parsing layer. It is used to load standardized UVM verification components and perform functional simulation, collect simulation coverage data, and generate a UVM simulation verification data package containing excitation waveforms, coverage reports, and intermediate state information. The cross-stage adaptation layer connects to the UVM verification layer and is used to receive UVM simulation verification data packets and convert the UVM simulation verification data packets into drive signals and timing configurations that can be recognized by the virtual instrument simulation layer. The virtual instrument simulation layer connects to the cross-stage adaptation layer. It is used to load virtual instrument models that are consistent with the behavior of mass production test equipment, perform hardware-in-the-loop simulation based on the converted drive signals and timing configuration, compare the virtual output with the expected results, calculate the timing error, and generate a virtual verification report. The physical machine calibration interface connects to the cross-stage adaptation layer and is used to deploy the test program that has passed virtual verification to the physical mass production test machine to perform physical calibration tests and collect physical machine test data. The closed-loop feedback module, integrated within the cross-stage adaptation layer, is used to feed back physical machine test data to the UVM verification layer and the virtual instrument simulation layer. Based on the feedback data, the simulation model and interface adaptation parameters are calibrated to form a closed-loop iterative optimization.
7. The system according to claim 6, characterized in that, The UVM verification layer has a built-in reusable UVM test component library, which includes an excitation generator, driver, monitor, and scoreboard. The stimulus generator generates a stimulus sequence based on the test case specifications, the driver drives the stimulus sequence to the interface of the design under test, the monitor collects the output response of the design under test, and the scoreboard compares the actual output with the expected response and records the comparison results.
8. The system according to claim 6, characterized in that, The cross-stage adaptation layer includes at least one of the following units: a data format conversion unit, a timing mapping unit, a level conversion unit, and a decision rule mapping unit. The data format conversion unit is used to convert the test vector format output by the UVM verification layer into the drive signal format corresponding to the virtual instrument simulation layer; The timing mapping unit is used to map UVM timing window parameters to timing configuration parameters that can be executed by the virtual instrument; The level conversion unit is used to convert the signal level standard in the UVM verification layer to a level threshold configuration compatible with the virtual instrument simulation layer; The decision rule mapping unit is used to convert assertion expressions in the UVM verification environment into decision condition rules for the virtual instrument simulation layer.
9. The system according to claim 6, characterized in that, The virtual instrument simulation layer includes an excitation application unit, a hardware behavior simulation unit, a response acquisition unit, and an error statistics unit. The excitation application unit is used to apply excitation cycle by cycle according to the timing configuration of the converted drive signal; The hardware behavior simulation unit is used to simulate the pin driving, timing generation, level comparison and parameter measurement behavior of mass production test equipment; The response acquisition unit is used to acquire the output response of the virtual instrument model and compare it with the expected response cycle by cycle. The error statistics unit is used to count the number of alignment failures, calculate the timing error distribution, and generate a virtual verification report that includes error waveforms and error statistics tables.
10. The system according to claim 6, characterized in that, The closed-loop feedback module includes a parameter extraction unit and a model update unit. The model update unit further includes at least one of the following sub-units: a timing compensation sub-unit, a level calibration sub-unit, a decision logic correction sub-unit, and a signal mapping correction sub-unit. The parameter extraction unit is used to extract timing compensation parameters, level threshold deviations, judgment deviation rules, and channel deviation values from physical machine test data; The timing compensation subunit is used to update the timing compensation parameters in reverse to the timing constraints in the UVM verification component library; The level calibration subunit is used to synchronize the actual level threshold measured by the physical instrument to the level comparator model in the virtual instrument simulation layer; The decision logic correction subunit is used to reverse the decision deviation rules and correct the scoreboard decision logic in the UVM verification environment. The signal mapping correction subunit is used to feed back the channel deviation value to the signal mapping table of the cross-stage adaptation layer.