A method, system and electronic device for testing an accelerator card

Abstract

The application discloses a test method, system and electronic equipment of an acceleration card, and relates to the technical field of computers. The method comprises the following steps: in the case that a target acceleration card executes a target test vector according to a first attribute parameter, detecting target difference information of the target acceleration card according to target running information, the target difference information being used for indicating a first difference degree between a load intensity of a running load of the target acceleration card and an expected load intensity; adjusting the first attribute parameter according to the target difference information to obtain a second attribute parameter, wherein a second difference degree between the load intensity of the running load and the expected load intensity when the target acceleration card executes the target test vector according to the execution intensity indicated by the second attribute parameter is smaller than the first difference degree; and controlling the target acceleration card to execute the target test vector according to the second attribute parameter. Through the application, the technical problem of poor test flexibility of the acceleration card in the related art is solved, and the technical effect of improving the test flexibility of the acceleration card is achieved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a testing method, system and electronic device for an accelerator card. Background Technology

[0002] As the application scenarios for high-computing power in servers continue to expand, accelerator cards, as a core computing power carrier, are attracting increasing attention. In related technologies, accelerator cards are tested by executing fixed scripts; however, this testing method can only test the performance of accelerator cards under constant load conditions, lacking flexibility. Summary of the Invention

[0003] This application provides a testing method, system, and electronic device for accelerator cards, to at least solve the problem of poor testing flexibility for accelerator cards in related technologies.

[0004] This application provides a testing method for an accelerator card, comprising: when a target accelerator card executes a target test vector according to a first attribute parameter, detecting target difference information of the target accelerator card according to the target operation information of the target accelerator card, wherein the first attribute parameter is used to indicate the execution intensity of the target accelerator card executing the target test vector, the target operation information is used to indicate the operating load of the target accelerator card, and the target difference information is used to indicate a first difference between the load intensity of the operating load of the target accelerator card and the expected load intensity; adjusting the first attribute parameter according to the target difference information to obtain a second attribute parameter, wherein the second difference between the load intensity of the operating load of the target accelerator card when executing the target test vector according to the execution intensity indicated by the second attribute parameter and the expected load intensity is less than the first difference; and controlling the target accelerator card to execute the target test vector according to the second attribute parameter.

[0005] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the testing method of any of the above-described accelerator cards.

[0006] This application addresses the issue that, when a target accelerator card executes a target test vector according to a first attribute parameter, it detects target difference information based on target operation information indicating the target accelerator card's operating load. The first attribute parameter is adjusted according to the target difference information to obtain a second attribute parameter. When the target accelerator card executes the target test vector with the execution intensity indicated by the second attribute parameter, the second difference between the load intensity of the operating load and the expected load intensity is less than the first difference. Then, the target accelerator card is controlled to execute the target test vector according to the second attribute parameter. In other words, during the testing process of the target accelerator card, by adjusting the execution intensity of the target accelerator card executing the target test vector according to the target difference information, the load intensity of the target accelerator card's operating load is adjusted towards the expected load intensity. This allows the performance of the target accelerator card to be tested under varying load intensity conditions, improving the flexibility of accelerator card testing. Therefore, this addresses the technical problem of poor testing flexibility in related technologies, achieving the technical effect of improving the testing flexibility of accelerator cards. Attached Figure Description

[0007] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a hardware structure block diagram of the testing method for the accelerator card according to an embodiment of this application;

[0009] Figure 2 This is a flowchart of a testing method for an accelerator card according to an embodiment of this application;

[0010] Figure 3 This is a schematic diagram of a testing method for an accelerator card according to an embodiment of this application. Figure 1 ;

[0011] Figure 4 This is a schematic diagram of a fault reporting process according to an embodiment of this application;

[0012] Figure 5 This is a flowchart illustrating the dynamic testing phase according to an embodiment of this application;

[0013] Figure 6 This is a schematic diagram of a test system for an accelerator card according to an embodiment of this application. Figure 1 ;

[0014] Figure 7This is a schematic diagram of a test system for an accelerator card according to an embodiment of this application. Figure 2 ;

[0015] Figure 8 This is a schematic diagram of a test system for an accelerator card according to an embodiment of this application. Figure 3 ;

[0016] Figure 9 This is a schematic diagram of a test system for an accelerator card according to an embodiment of this application. Figure 4 ;

[0017] Figure 10 This is a schematic diagram of a test system for an accelerator card according to an embodiment of this application. Figure 5 ;

[0018] Figure 11 This is a structural block diagram of a test apparatus for an accelerator card according to an embodiment of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0020] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0021] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] The specific application environment architecture or specific hardware architecture on which the testing methods for the accelerator card depend is described here.

[0023] The methods and embodiments provided in this application can be executed on a server device or a similar computing device. Taking running on a server device as an example, Figure 1 This is a hardware structure block diagram of the testing method for the accelerator card according to an embodiment of this application. For example... Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown in the image. A processor 102 (which may include, but is not limited to, a central processing unit (CPU), microprocessor (MCU), or programmable logic device (FPGA), etc.) and a memory 104 for storing data are also shown. The server device may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the server equipment described above. For example, the server equipment may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0024] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the accelerator card testing method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the above-described method. The memory 104 may include high-speed random access memory and non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to server devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0025] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the server device. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0026] The embodiments of this application provide a testing method for an accelerator card. The method is described in detail below in conjunction with the execution flow of the testing method for the accelerator card.

[0027] This embodiment provides a testing method for accelerator cards. Figure 2 This is a flowchart of a testing method for an accelerator card according to an embodiment of this application, such as... Figure 2 As shown, the method includes the following steps:

[0028] Step S202: When the target accelerator card executes the target test vector according to the first attribute parameter, the target difference information of the target accelerator card is detected according to the target operation information of the target accelerator card. The first attribute parameter is used to indicate the execution intensity of the target accelerator card in executing the target test vector, the target operation information is used to indicate the operation load of the target accelerator card, and the target difference information is used to indicate the first difference between the load intensity of the operation load of the target accelerator card and the expected load intensity.

[0029] Step S204: Adjust the first attribute parameter according to the target difference information to obtain the second attribute parameter, wherein the second difference between the load intensity of the target accelerator card when executing the target test vector according to the execution intensity indicated by the second attribute parameter and the expected load intensity is less than the first difference.

[0030] Step S206: Control the target acceleration card to execute the target test vector according to the second attribute parameter.

[0031] Based on the above, when the target accelerator card executes the target test vector according to the first attribute parameter, the target difference information is detected based on the target operation information used to indicate the target accelerator card's operating load. The first attribute parameter is adjusted according to the target difference information to obtain the second attribute parameter. When the target accelerator card executes the target test vector according to the execution intensity indicated by the second attribute parameter, the second difference between the load intensity of the operating load and the expected load intensity is less than the first difference. Then, the target accelerator card is controlled to execute the target test vector according to the second attribute parameter. That is, during the testing process of the target accelerator card, by adjusting the execution intensity of the target accelerator card executing the target test vector according to the target difference information, the load intensity of the target accelerator card's operating load is adjusted towards the expected load intensity. This allows the performance of the target accelerator card to be tested under varying load intensity conditions, improving the flexibility of accelerator card testing. Therefore, this solves the technical problem of poor testing flexibility of accelerator cards in related technologies, achieving the technical effect of improving the testing flexibility of accelerator cards.

[0032] In the embodiment provided in step S202, the accelerator card may refer to, but is not limited to, a dedicated hardware acceleration device with independent data processing and computing capabilities. The accelerator card may be used, but is not limited to, for high-computing scenarios such as graphics rendering, artificial intelligence training, deep learning inference, and large-scale scientific computing. Optionally, the accelerator card may include, but is not limited to, GPUs (Graphics Processing Units), FPGAs (Field-Programmable Gate Arrays), etc.

[0033] Optionally, in this embodiment, the test vector may refer to, but is not limited to, a set of input data sequences or instruction streams, used to send specific computation commands, graphics rendering commands, or memory access operations to the accelerator card to verify whether the accelerator card's functions are correct, whether its performance meets the standards, or whether there are any hardware defects. Optionally, the test vector may include, but is not limited to, CUDA (Compute Unified Device Architecture) instructions, video memory read / write instructions, scientific computing instructions, etc.

[0034] Optionally, in this embodiment, the first attribute parameter may, but is not limited to, indicating the execution intensity of the target accelerator card in executing the target test vector. The first attribute parameter may, but is not limited to, include the instruction frequency of the target test vector, and / or, the data throughput of the target test vector, etc. The instruction frequency may, but is not limited to, determine the number of computation instructions (such as CUDA instructions, memory read / write instructions, scientific computing instructions, etc.) executed by the accelerator card per unit time; a higher frequency may, but is not limited to, mean that more computation instructions are completed in each clock cycle. The data throughput may, but is not limited to, determine the total number of bytes of data read or written by the accelerator card through the accelerator card interface per unit time; a higher throughput may, but is not limited to, mean that the accelerator card needs to initiate TLP (Transaction Layer Packet) requests more frequently and handle more memory read / write transactions.

[0035] Optionally, in this embodiment, the target operating information may be used, but is not limited to, to indicate the operating load of the target accelerator card. The target operating information may be, but is not limited to, monitoring data generated in real time by the target accelerator card during operation that reflects its underlying hardware status and load characteristics. For example, it may be the power supply voltage of the accelerator card, the bandwidth usage of the accelerator card, and the PCIe (Peripheral Component Interconnect Express) link latency of the accelerator card, etc. These data may be, but are not limited to, directly characterizing the actual physical operating status of the accelerator card under the current vector execution intensity.

[0036] Optionally, in this embodiment, the target difference information may be used, but is not limited to, to indicate the first difference between the load intensity of the target accelerator card's operating load and the expected load intensity. The target difference information may be used, but is not limited to, to quantitatively assess whether the current operating state of the accelerator card deviates from the preset expected operating state.

[0037] Optionally, in this embodiment, the desired load intensity can be, but is not limited to, set to different values ​​at different test time points. Combined with the test method for the accelerator card provided in this application, it is possible to test the operating performance of the accelerator card under various load intensities during a single test of the accelerator card.

[0038] In the embodiment provided in step S204, the first attribute parameter can be adjusted according to the target difference information to obtain the second attribute parameter. When the target accelerator card executes the target test vector according to the execution intensity indicated by the adjusted second attribute parameter, the second difference between the load intensity of the running load and the expected load intensity is less than the aforementioned first difference.

[0039] Optionally, in this embodiment, a correspondence between different difference information and different attribute parameters can be set, and the second attribute parameter corresponding to the target difference information can be determined based on such a correspondence.

[0040] In the embodiment provided in step S206, after obtaining the second attribute parameter, the target accelerator card can be controlled to execute the target test vector according to the second attribute parameter, so that the load intensity of the target accelerator card's operating load is adjusted to the desired load intensity.

[0041] As an optional implementation, the target difference information of the target accelerator card can be detected based on the target operating information of the target accelerator card in the following ways, but not limited to: detecting the reference load parameters of the target accelerator card based on the target operating information of the target accelerator card, wherein the reference load parameters are used to indicate the load intensity of the operating load of the target accelerator card; comparing the reference load parameters and the target load parameters to obtain the target difference information, wherein the target load parameters are used to indicate the expected load intensity.

[0042] Optionally, in this embodiment, the specific operating load of the target accelerator card reflected in the target operating information can be converted into the operating load intensity level of the target accelerator card, that is, the reference load parameters of the target accelerator card can be detected based on the target operating information.

[0043] Optionally, in this embodiment, the difference between the current operating load intensity level of the target accelerator card and the expected operating load intensity level can be determined by comparing the reference load parameters and the target load parameters.

[0044] Optionally, in this embodiment, comparing the current operating load intensity level of the target accelerator card with the expected operating load intensity level can more clearly show the gap between the current operating state and the expected operating state of the target accelerator card compared to directly comparing the specific load situation of the accelerator card with the expected load situation.

[0045] As an optional implementation, the reference load parameters of the target accelerator card can be detected based on the target operating information of the target accelerator card in the following manner, but not limited to: obtaining a first parameter, a second parameter, and a third parameter, wherein the first parameter indicates the power supply voltage of the target accelerator card, the second parameter indicates the busy level of data transmission between the target accelerator card and the memory of the target accelerator card, and the third parameter indicates the communication latency between the target accelerator card and the processor to which the target accelerator card is connected; the target operating information includes the first parameter, the second parameter, and the third parameter; and calculating a weighted sum of the first parameter, the second parameter, and the third parameter based on the first weight value of the first parameter, the second weight value of the second parameter, and the third weight value of the third parameter to obtain the reference load parameters.

[0046] Optionally, in this embodiment, the aforementioned target operating information may include, but is not limited to, the first parameter, the second parameter, and the third parameter. Multiple operating parameters may be combined to determine the reference load parameter, thereby improving the accuracy of the reference load parameter.

[0047] Optionally, in this embodiment, the first parameter may be, but is not limited to, used to indicate the power supply voltage of the target accelerator card. Optionally, the first parameter may be, but is not limited to, the power supply voltage fluctuation value of the core of the target accelerator card.

[0048] Optionally, in this embodiment, the second parameter may be, but is not limited to, indicating the level of activity in data transfer between the target accelerator card and its memory. Optionally, the second parameter may be, but is not limited to, the video memory (i.e., the aforementioned memory of the target accelerator card) bandwidth utilization.

[0049] Optionally, in this embodiment, the third parameter may be, but is not limited to, used to indicate the communication latency between the target accelerator card and the processor to which the target accelerator card is connected. Optionally, the third parameter may be, but is not limited to, the PCIe link latency of the accelerator card.

[0050] Optionally, in this embodiment, three high-precision analog-to-digital converter chips with independent acquisition designs using a single chip and single parameter (to avoid signal interference between parameters) can be set up to acquire three types of low-level hardware parameters: GPU (i.e., the aforementioned target accelerator card) core voltage fluctuation value ΔV, memory bandwidth utilization B, and PCIe link latency D. The output of the high-precision analog-to-digital converter chip can be connected to the FPGA via an SPI (Serial Peripheral Interface) bus, and the acquired raw data can be directly transmitted to the FPGA for preprocessing.

[0051] Optionally, in this embodiment, during the process of acquiring the GPU core voltage fluctuation value, the core voltage analog signal enters the analog front end of the high-precision analog-to-digital converter chip, filters out power frequency interference through the chip's built-in low-pass filter, and then obtains a digital signal through analog-to-digital conversion; the digital signal is transmitted to the FPGA in real time through the SPI bus to ensure real-time capture of voltage fluctuations.

[0052] Optionally, in this embodiment, during the process of obtaining the video memory bandwidth utilization rate, the FPGA can, but is not limited to, monitor the amount of video memory read and write data through the PCIe bus and calculate the actual bandwidth utilization ratio in real time. The sampling frequency can, but is not limited to, 1ms / time. The FPGA can, but is not limited to, have a built-in hardware counter to accumulate the total number of bytes of the selected video memory read and write TLP packets in a statistical window of 1ms. Since the maximum effective payload of the PCIe TLP packet is 1024 bytes, the length field of the packet header is directly extracted through hardware logic, and the total amount of video memory read and write data (unit: bytes) in each statistical window is accumulated. The video memory bandwidth utilization rate is further calculated by the formula: Video memory bandwidth utilization rate = (total amount of video memory read and write data in the statistical window × 8) / (statistical window duration × theoretical bandwidth of GPU video memory) × 100%; where the theoretical bandwidth of GPU video memory is a pre-stored characteristic parameter of the GPU, the statistical window duration can, but is not limited to, be fixed at 1ms, and the sampling frequency is synchronized with the statistical window at 1ms / time.

[0053] Optionally, in this embodiment, during the acquisition of PCIe link latency, test data packets can be sent from the FPGA to the GPU, and the time difference between data packet transmission and reception response can be recorded. The FPGA can send test data packets to the GPU at a frequency of 1ms / time, triggering a built-in hardware timer to start timing the instant of transmission. After receiving the test data packet, the GPU returns a response data packet (carrying the unique identifier ID of the original test data packet) directly through hardware logic without software intervention. After receiving the response data packet, the FPGA extracts the identifier ID and matches it with the sent test data packet. If the match is successful, the hardware timer is stopped immediately, and the timing duration is recorded. Further, the PCIe link latency can be calculated using the formula: PCIe link latency = response data packet reception timing value - test data packet transmission timing value. Since the hardware timer accuracy is 1ns (nanosecond), combined with the hardware response latency of the FPGA and GPU being ≤1ns, a measurement accuracy of ±1ns can be achieved. Optionally, to further reduce random errors, three test data packets can be sent consecutively each time the latency is measured, and the arithmetic mean of the three measurement results is taken as the final PCIe link latency value to ensure data stability.

[0054] Optionally, in this embodiment, after acquiring the first, second, and third parameters, and before calculating the reference load parameters using the acquired parameters, the acquired parameter data can be preprocessed, but is not limited to this. The data preprocessing function can be performed by the FPGA, performing sliding window variance calculation on the acquired raw data (averaging 10 consecutive 1ms data points) to quantify the dispersion and oscillation of the data.

[0055] Optionally, the FPGA may, but is not limited to, maintain a sliding data queue of length N in memory (e.g., N=10, representing 10 consecutive cycles of sampled data). For a dataset X={x1,x2,…,xN} in the queue, its local mean may, but is not limited to, be calculated first: Then, the amplitude of parameter oscillation within this time window is calculated using the discrete variance formula:

[0056] ;

[0057] It is possible, but not limited to, to use the variance and mean to perform a moving average filter on the data in the queue after determining the mean and variance y, and then calculate the mean of the data in the queue after filtering to obtain the filtered stable parameters ΔV0 (i.e., the first parameter) (unit: V (volts)), B0 (i.e., the second parameter), and D0 (i.e., the third parameter) (unit: ns) after removing occasional anomalies (i.e., eliminating random interference signals in the circuit).

[0058] Optionally, in this embodiment, after filtering the collected data by combining the mean and variance, the filtered data can be standardized by hardware logic circuitry to convert parameters of different units and orders of magnitude into dimensionless standardized parameters between 0 and 1, thereby eliminating the influence of dimensional differences on coefficient calculation.

[0059] Optionally, but not limited to, different parameters may be normalized in the following manner: for core voltage fluctuations, the normalized parameter is ΔV'=ΔV0 / 0.005V (where 0.005V is the GPU core voltage fluctuation threshold); for memory bandwidth, the normalized parameter is B'=B0 / 100 (that is, converting the bandwidth utilization in percentage form to a coefficient of 0-1); for PCIe link latency, the normalized parameter is D'=D0 / 50ns (50ns is the link latency threshold of the PCIe 4.0 bus).

[0060] Optionally, in this embodiment, the reference load parameters can be determined using the first parameter, the second parameter, and the third parameter in a weighted summation manner, but not limited to this method.

[0061] As an optional implementation, the first weight value of the first parameter, the second weight value of the second parameter, and the third weight value of the third parameter can be determined, but are not limited to, in the following manner: before calculating the weighted sum of the first, second, and third parameters based on the first, second, and third weight values ​​of the first, second, and third parameters, a first fitting curve is generated based on multiple sets of first parameters, a second fitting curve is generated based on multiple sets of second parameters, and a third fitting curve is generated based on multiple sets of third parameters. Each set of first parameters includes first parameters and load parameters collected from the target accelerator card at the same time, and each set of second parameters includes parameters collected from the target accelerator card at the same time. The system obtains the second parameter and load parameter. A set of third parameters includes the third parameter and load parameter collected from the target accelerator card at the same time. The load parameter is used to indicate the computing power utilization on the target accelerator card. The first fitting curve is used to indicate how the load parameter changes with the first parameter. The second fitting curve is used to indicate how the load parameter changes with the second parameter. The third fitting curve is used to indicate how the load parameter changes with the third parameter. The system detects the target proportional relationship between the fitting determination coefficients of the first, second, and third fitting curves. The system generates a first weight value, a second weight value, and a third weight value that conform to the target proportional relationship.

[0062] Optionally, in this embodiment, the load parameter may be used, but is not limited to, to indicate the computing power utilization on the target accelerator card. Optionally, the load parameter may be, but is not limited to, the utilization rate of the core of the target accelerator card.

[0063] Optionally, in this embodiment, the sum of the first weight value, the second weight value, and the third weight value is equal to 1.

[0064] Optionally, in this embodiment, a first fitting curve can be obtained by fitting a functional relationship between the first parameter and the load parameter based on multiple sets of first parameters and load parameters collected from the target accelerator card at the same time. Similarly, a second fitting curve can be obtained by fitting a functional relationship between the second parameter and the load parameter based on multiple sets of second parameters and load parameters collected from the target accelerator card at the same time, and a third fitting curve can be obtained by fitting a functional relationship between the third parameter and the load parameter based on multiple sets of third parameters and load parameters collected from the target accelerator card at the same time.

[0065] Optionally, in this embodiment, the coefficient of determination can be used, but is not limited to, to measure the goodness of fit of the regression model to the observed data.

[0066] Optionally, in this embodiment, a first weight value, a second weight value, and a third weight value are generated to determine the target proportional relationship between the fitting determination coefficients of the first fitting curve, the second fitting curve, and the third fitting curve. Through regression analysis, the weight generation is based on the high correlation between measured data and the computing power utilization of the accelerator card. This objectively quantifies the impact of parameters such as power supply voltage, memory bandwidth usage, and communication latency on the actual load intensity of the accelerator card, ensuring that the weight allocation truly reflects the physical characteristics of the hardware. Consequently, the reference load parameters calculated according to the weight values ​​determined in this way can more accurately and scientifically characterize the actual operating state of the accelerator card.

[0067] Optionally, in this embodiment, the overall load coefficient S can be calculated by using hardware multipliers and adders to set weights based on the degree of influence of each parameter on the GPU load; or, not limited to, by performing least squares linear regression on the measured GPU memory bandwidth utilization data to obtain a fitting slope of 0.87 for the relationship between memory bandwidth utilization and load fluctuation, meaning that for every 10% change in bandwidth utilization, the load fluctuates by 8.7%, and the fitting determination coefficient R is obtained. 2 =0.92. By performing least-squares linear regression on the measured core voltage fluctuation data of the GPU, it was determined that for every 0.001V change in core voltage, the GPU load fluctuation is approximately 2.1%, and the fitting determination coefficient R0 was obtained. 2 =0.65. By performing least-squares linear regression on the measured GPU data, it was found that for every 10ns change in PCIe link latency, the GPU load fluctuation is approximately 2.0%, with a correlation coefficient R0. 2 =0.63; The results can be obtained, but are not limited to, using the individual fitting determination coefficients R0. 2 Calculate the weights: the coefficient of determination R for fitting memory bandwidth usage and GPU load. 2 =0.92, core voltage fluctuation R 2 =0.65, PCIe link latency R 2 =0.63; After normalizing the three and rounding the result, the weights are 0.4, 0.3, and 0.3; The formula for calculating the reference load parameter S is: S = 0.3 × ΔV' + 0.4 × B' + 0.3 × D'.

[0068] As an optional implementation, the comparison of reference load parameters and target load parameters to obtain target difference information can be achieved by, but is not limited to, the following methods: obtaining multiple load parameter ranges, wherein the multiple load parameter ranges are divided according to the target load parameters, and the load intensity of the target accelerator card's operating load indicated by load parameters falling into different load parameter ranges differs from the expected load intensity; detecting the target parameter range into which the reference load parameters fall within the multiple load parameter ranges, wherein the target difference information includes the target parameter range.

[0069] Optionally, in this embodiment, multiple load parameter ranges may be divided according to the target load parameter, for example, the three load parameter ranges [0,0.3), [0.3,0.7] and (0.7,1] may be divided according to the target load parameter 0.5.

[0070] Optionally, in this embodiment, the difference between the load intensity of the target accelerator card's operating load and the expected load intensity indicated by load parameters falling within different load parameter ranges may, but is not limited to, be different. For example, the difference between the load intensity of the target accelerator card's operating load and the expected load intensity indicated by load parameters falling within [0, 0.3) may, but is not limited to, be different from the difference between the load intensity of the target accelerator card's operating load and the expected load intensity indicated by load parameters falling within [0.3, 0.7]. The difference between the load intensity of the target accelerator card's operating load and the expected load intensity indicated by load parameters falling within [0, 0.3) may, but is not limited to, be different from the difference between the load intensity of the target accelerator card's operating load and the expected load intensity indicated by load parameters falling within (0.7, 1).

[0071] Optionally, in this embodiment, the difference level (whether it is too much or too little, and how much it differs) between the load intensity of the target accelerator card's operating load indicated by the reference load parameter and the expected load intensity can be determined by detecting the target parameter range into which the reference load parameter falls. This prepares for adjusting the first attribute parameter based on the difference level.

[0072] As an optional implementation, the second attribute parameter can be obtained by adjusting the first attribute parameter based on the target difference information in the following manner, but not limited to: finding the target adjustment parameter corresponding to the target parameter range into which the reference load parameter falls from the corresponding load parameter range and adjustment parameter, wherein the reference load parameter is used to indicate the load intensity of the target accelerator card's operating load, the load parameter range is divided according to the target load parameter of the target accelerator card, the target load parameter is used to indicate the expected load intensity, the load parameters falling into different load parameter ranges indicate different degrees of difference between the load intensity of the target accelerator card's operating load and the expected load intensity, the target difference information includes the target parameter range, and the target adjustment parameter is used to indicate the adjustment direction and adjustment magnitude of the execution intensity indicated by the first attribute parameter; adjusting the first attribute parameter according to the target adjustment parameter to obtain the second attribute parameter.

[0073] Optionally, in this embodiment, a correspondence between different degrees of difference and different adjustment parameters may be set, but is not limited to, including the correspondence between load parameter range and adjustment parameters.

[0074] Optionally, in this embodiment, but not limited to, by establishing a correspondence between load parameter ranges and adjustment parameters, rapid decision-making for load adjustment can be achieved, avoiding complex real-time calculations or iterative convergence processes. It is only necessary to determine the parameter range in which the reference load parameters fall to directly look up the corresponding adjustment parameters in the table, thereby completing closed-loop control with extremely low algorithm latency and improving the real-time performance of the test.

[0075] Optionally, in this embodiment, the target adjustment parameter may be, but is not limited to, the adjustment direction and adjustment range used to indicate the execution intensity indicated by the first attribute parameter. The adjustment direction may include, but is not limited to, the magnification direction and the reduction direction, and the adjustment range may refer to the magnitude of magnification / reduction of the first attribute parameter.

[0076] Optionally, in this embodiment, Figure 3 This is a schematic diagram of a testing method for an accelerator card according to an embodiment of this application. Figure 1 .like Figure 3As shown, various parameters (including the first, second, and third parameters) can be acquired by a miniature load inductive chip, and the aforementioned moving average filtering can be performed by an FPGA, but is not limited to. After filtering, the parameters are standardized by the MCU, and the comprehensive load S (i.e., the aforementioned reference load parameter) is calculated using the standardized parameters. After calculating S, the range of S can be determined, and the corresponding load adjustment coefficient K (i.e., the aforementioned target adjustment parameter) is output according to the range that S falls into. If, but not limited to, S < 0.3, the GPU is determined to be operating under low load and low fluctuation, and K = 1.5 is output. This increases the test vector instruction frequency from the baseline 100MHz (Megahertz) to 150MHz and the test vector data throughput from the baseline 1GB / s (Gigabytes per second) to 1.5GB / s, thereby increasing the GPU load. If, but not limited to, 0.3 ≤ S ≤ 0.7, the GPU is determined to be operating under stable load, and K = 1.0 is output. This maintains the test vector parameters at the baseline parameters (instruction frequency 100MHz, data throughput 1GB / s) (i.e., the aforementioned first attribute parameters). If, but not limited to, S > 0.7, the GPU is determined to be operating under high load and high fluctuation, and K = 0.5 is output. This reduces the test vector instruction frequency to 50MHz and the test vector data throughput to 0.5GB / s, thereby reducing the GPU load and preventing hardware damage. After determining K, the MCU can, but is not limited to, transmit K to the FPGA. After receiving the K value, the FPGA completes the reconfiguration of the test vector execution strength and sends the test vector to the GPU under test through the PCIe 4.0 interface according to the reconfigured execution strength. At the same time, the FPGA can, but is not limited to, feed back the test vector execution status to the MCU every 10ms to achieve closed-loop control.

[0077] As an optional implementation, the detection of target difference information of the target accelerator card based on the target operation information of the target accelerator card can also be achieved in the following ways, but not limited to: detecting the fluctuation range of the operating load of the target accelerator card based on the target operation information; when the fluctuation range is greater than the fluctuation range threshold, adjusting the first attribute parameter according to the safety adjustment parameter to obtain the third attribute parameter, wherein the safety adjustment parameter is used to reduce the execution intensity indicated by the first attribute parameter; controlling the target accelerator card to execute the target test vector according to the third attribute parameter; and detecting target difference information based on the target operation information when the fluctuation range is less than or equal to the fluctuation range threshold.

[0078] Optionally, in this embodiment, in addition to adjusting the first attribute parameter in conjunction with the desired load intensity, the first attribute parameter can also be adjusted according to the fluctuation range of the target accelerator card's operating load, in order to avoid the execution of excessive test vectors from completely breaking down the physical hardware.

[0079] Optionally, in this embodiment, the fluctuation range of the target accelerator card's operating load can be detected by detecting the variance of multiple target operating information obtained in multiple consecutive time periods.

[0080] Optionally, in this embodiment, when the MCU detects that the variance is greater than the jitter tolerance threshold (i.e., the aforementioned fluctuation amplitude threshold), it can, but is not limited to, prove that the GPU's underlying signal is experiencing severe high-frequency oscillation. At this time, the MCU can, but is not limited to, immediately force the output of a derating factor K=0.5 (i.e., the aforementioned safety adjustment parameter) through closed-loop logic to prevent excessive test vectors from completely damaging the physical hardware.

[0081] As an optional implementation, the detection of target difference information of the target accelerator card based on the target operating information of the target accelerator card can be achieved, but is not limited to, by the following methods: detecting the reference load parameter of the target accelerator card based on the target operating information of the target accelerator card, wherein the reference load parameter is used to indicate the load intensity of the operating load of the target accelerator card; calculating the absolute value of the difference between the reference load parameter and the target load parameter to obtain the target absolute value; and comparing the magnitude relationship between the reference load parameter and the target load parameter to obtain the target magnitude relationship, wherein the target load parameter is used to indicate the expected load intensity, and the target difference information includes the target absolute value and the target magnitude relationship.

[0082] Optionally, in this embodiment, the reference load parameter A may be, but is not limited to, 0.5, and the target load parameter B may be, but is not limited to, 0.8. Then, the absolute value of the difference between A and B, 0.3, can be calculated to obtain the target absolute value of 0.3, and the target size relationship between A and B can be determined to be A less than B.

[0083] As an optional implementation, the second attribute parameter can be obtained by adjusting the first attribute parameter based on the target difference information in the following ways, but not limited to: determining an adjustment sub-parameter based on the target absolute value, wherein there is a positive correlation between the adjustment sub-parameter and the absolute value of the difference; when the target size relationship is that the reference load parameter is greater than or equal to the target load parameter, calculating the difference between the initial adjustment parameter and the adjustment sub-parameter to obtain the first adjustment parameter, wherein the initial adjustment parameter is 1, and the first adjustment parameter is used to indicate the reduction in the execution intensity indicated by the first attribute parameter; when the target size relationship is that the reference load parameter is less than the target load parameter, calculating the sum of the initial adjustment parameter and the adjustment sub-parameter to obtain the second adjustment parameter, wherein the initial adjustment parameter is 1, and the second adjustment parameter is used to indicate the amplification of the execution intensity indicated by the first attribute parameter; adjusting the first attribute parameter according to the first adjustment parameter, or the second adjustment parameter, to obtain the second attribute parameter.

[0084] Optionally, in this embodiment, the adjustment sub-parameter and the absolute value of the difference may, but are not limited to, have a positive correlation, that is, the larger the absolute value of the difference, the larger the adjustment sub-parameter.

[0085] Optionally, in this embodiment, for the reference load parameter A and the target load parameter B, the adjustment sub-parameter can be determined to be 0.4 based on the target absolute value of 0.3, but is not limited to. Since A is less than B, the sum of the initial adjustment parameter 1 and the adjustment sub-parameter 0.4 is calculated to obtain the second adjustment parameter 1.4. The second attribute parameter can be obtained by multiplying the second adjustment parameter and the first attribute parameter, but is not limited to.

[0086] Optionally, in this embodiment, if the reference load parameter C equals 0.9 and the target load parameter D equals 0.5, then the target absolute value is 0.4. The adjustment sub-parameter can be determined to be 0.45 based on the target absolute value of 0.4. Since C is greater than D, the difference between the initial adjustment parameter 1 and the adjustment sub-parameter 0.45 is calculated to obtain the second adjustment parameter of 0.55. The second attribute parameter can be obtained by multiplying the second adjustment parameter and the first attribute parameter.

[0087] Optionally, in this embodiment, the first adjustment parameter, the second adjustment parameter, and the aforementioned target adjustment parameter and safety adjustment parameter may, but are not limited to, all be greater than 0. It may, but is not limited to, determine that an error has occurred in the accelerator card test when it is determined that the first adjustment parameter, the second adjustment parameter, or the aforementioned target adjustment parameter or safety adjustment parameter is less than or equal to 0, suspend the test, and report the test error.

[0088] By constructing a refined closed-loop control strategy that decouples deviation and direction, adaptive and precise adjustment and dynamic balance of the accelerator card load intensity are achieved.

[0089] As an optional implementation, when the target accelerator card executes the target test vector, fault characteristics can be saved in the following ways, but are not limited to: detecting fault information of the target accelerator card, wherein the fault information is used to indicate whether a fault has occurred in the operation of the target accelerator card; when the fault information is detected to indicate that a fault has occurred in the operation of the target accelerator card, controlling the target accelerator card to stop running, and collecting the current operating information and current attribute parameters of the target accelerator card; reporting the current operating information and current attribute parameters; controlling the target accelerator card to execute the target test vector according to the safety attribute parameters, wherein the safety attribute parameters are used to indicate the execution strength of the target accelerator card executing the target test vector to ensure the safe operation of the target accelerator card.

[0090] Optionally, in this embodiment, during the testing of the target accelerator card, the target accelerator card may experience hardware failures such as ECC (Error Correcting Code) errors or memory timeouts. It is possible, but not limited to, collecting all parameters at the moment of the detected accelerator card failure, to provide accurate fault data for subsequent maintenance personnel to locate the fault, thus aiding in precise and rapid fault location.

[0091] Optionally, in this embodiment, when a malfunction is detected in the target accelerator card, the target accelerator card is also controlled to stop operating, reducing the time the target accelerator card operates in a faulty state and reducing the equipment damage caused by the malfunction. Furthermore, after reporting the parameters at the time of the fault, the target accelerator card is controlled to execute the target test vector according to the security attribute parameters, ensuring that the accelerator card test can continue.

[0092] Optionally, in this embodiment, Figure 4 This is a schematic diagram of a fault reporting process according to an embodiment of this application. For example... Figure 4 As shown, when the GPU triggers hardware failures such as ECC errors or memory timeouts, the GPU sends a fault signal to the FPGA via the PCIe 4.0 bus at 0ms. The FPGA forwards the fault signal to the MCU. The MCU can receive the fault signal at, but is not limited to, 4ms. After receiving the fault signal, the MCU freezes all current hardware operating parameters (filtered ΔV0, B0, D0) and test vector attribute parameters (current instruction frequency, data throughput) within 1ms, prohibiting parameter refresh to ensure that the data at the moment of the fault is not overwritten by subsequent normal data. At 5ms, the MCU assembles fault feature entries according to a fixed format of timestamp, core voltage fluctuation value, memory bandwidth utilization, PCIe link latency, test vector frequency, and test vector throughput. All parameters retain their original measurement units to ensure that maintenance personnel can directly understand the fault. At 6ms, the MCU performs CRC32 hardware verification on the assembled fault feature entry, calculates a 32-bit checksum and appends it to the end of the fault entry to ensure data integrity. At 7ms, the MCU stores the fault entry locally and simultaneously uploads it to the test management platform in real time via the Ethernet chip. At 10ms, the MCU sends a "resume test" command to the FPGA. At 15ms, the FPGA loads the benchmark test vector, and the entire test system returns to the dynamic test phase. The test management platform provides a "successful upload" signal within 10ms. If the upload fails, the MCU marks the fault entry as "to be retransmitted" and initiates a retry upload every 30 seconds until the upload is successful.

[0093] As an optional implementation, the testing method for the accelerator card provided in this application can be further described using a GPU as the test object, but is not limited to this one.

[0094] Optionally, in this embodiment, the testing device may be, but is not limited to, based on a 120mm × 80mm PCB (Printed Circuit Board) design. The selection of components for each module strictly follows the principles of industrial grade, low latency, and anti-interference, and the installation process meets the mass production standards for server hardware testing. All chips are soldered using surface mount technology to avoid communication delays or signal interference caused by poor soldering or solder bridging. Circuit connectivity testing is performed after soldering. The PCB traces of the PCIe bus and SPI bus are made of equal length to reduce signal attenuation and ensure the stability of data transmission. The entire device is treated with anti-static treatment, and four grounding pins are reserved on the edge of the PCB board for reliable grounding to the server chassis to resist electromagnetic interference inside the server chassis. The PCIe gold fingers are gold-plated to improve the contact reliability with the GPU slot and adapt to the requirements of multiple insertion and removal tests on the mass production line.

[0095] Optionally, the testing device in this embodiment can divide the GPU testing process into three stages, including but not limited to the initialization stage, the dynamic testing stage, and the fault handling stage. The working steps of each stage are automatically implemented by hardware circuits without manual intervention, and the dynamic test can run continuously. The specific process is as follows:

[0096] Initialization Phase: The initialization phase is the parameter configuration and self-calibration process after the test device is powered on, ensuring that each module works normally and that parameter acquisition is accurate, laying the foundation for subsequent testing. The specific steps of the initialization phase include: After the test device obtains input voltage through the server GPU slot, the power supply module prioritizes providing 1.2V core power to the FPGA, and the FPGA completes low-level logic initialization (including PCIe 4.0 protocol adaptation logic, test vector core loading, and filtering logic); after the FPGA initialization is complete, the power supply module provides power to the MCU, sensor chip, Flash memory, and Ethernet chip, and each chip enters standby mode; the MCU reads the pre-stored GPU model configuration in the Flash chip via the SPI bus and sends interface configuration commands to the FPGA via the I2C (Inter-Integrated Circuit) bus, and the FPGA automatically matches PCIe 4.0. The x16 communication protocol is used to complete the interface adaptation with the GPU. The sensor chip performs three-point self-calibration, outputting standard voltages of 0.8V, 1.0V, and 1.2V to the GPU core voltage pins in sequence, and collecting sampled values ​​V1, V2, and V3 respectively. The calibration coefficients Kv1=0.8V / V1, Kv2=1.0 / VV2, and Kv3=1.2V / V3 are calculated and stored in the MCU's built-in random access memory. Subsequent voltage acquisition values ​​are multiplied by the corresponding calibration coefficient to eliminate acquisition errors. The FPGA loads the GPU's benchmark test vector from its local logic unit and sends a "initialization complete" low-level signal back to the MCU. The test device enters standby mode, waiting for the test start command, which takes 10ms.

[0097] Dynamic testing phase: After the test management platform sends the start command, the test device enters the dynamic testing phase, realizing adaptive adjustment of GPU load and real-time acquisition of parameters. Figure 5 This is a flowchart illustrating the dynamic testing phase according to an embodiment of this application, as shown below. Figure 5As shown, the specific steps include (executed in a loop, each loop taking 5ms): The sensor chip collects raw data at a frequency of 1ms / time, that is, it collects the GPU VCC (positive power supply voltage) pin voltage, and obtains ΔV after correction by a calibration coefficient; it monitors TLP data packets through the PCIe bus to count the amount of data read and written to the video memory, and calculates B; it sends test data packets to the GPU and records the transmission and reception time difference, and obtains D; the FPGA performs moving average filtering and variance calculation on 10 consecutive 1ms-collected ΔV, B, and D, and obtains the filtered data ΔV0, B0, and D0, and transmits the filtered data to the MCU every 10ms via the SPI bus; the MCU then uses hardware logic... The circuit sequentially calculates the standardized parameters ΔV', B', and D', and then calculates the weighted comprehensive load factor S, outputting the corresponding load adjustment factor K. The following is a calculation example from a real test: ΔV0 = 0.002V, B0 = 60%, D0 = 30ns; ΔV' = 0.002V / 0.005V = 0.4, B' = 60 / 100 = 0.6, D' = 30ns / 50ns = 0.6; S = 0.3 × 0.4 + 0.4 × 0.6 + 0.3 × 0.6 = 0.54. Since 0.3 ≤ S ≤ 0.7, the output K = 1.0, therefore the benchmark test vector parameters (i.e., the aforementioned first attribute parameter) must be maintained. The MCU sends the adjustment factor K (i.e., the aforementioned target adjustment parameter) to the FPGA via the I2C bus. The FPGA completes the test vector parameter adjustment and sends the test vector to the GPU via the PCIe 4.0 x16 interface according to the adjusted test vector parameters. In addition, the FPGA will also send a test vector execution status feedback to the MCU every 10ms (such as "instruction sent successfully" or "GPU response is normal"). If the FPGA reports "execution abnormality", the MCU will immediately adjust the K value to 0.5 to reduce the GPU load and record the abnormal status to ensure GPU hardware safety.

[0098] Fault Handling Phase: During testing, when an ECC error occurs in the GPU memory, the testing device triggers a fault handling procedure to ensure complete recording of fault data. Specific steps may include, but are not limited to:

[0099] 0ms: The GPU memory triggers an ECC error, sending a high-level exception signal to the FPGA via the PCIe 4.0 bus; 3ms: The FPGA captures the exception signal and forwards it to the MCU via the I2C bus, with a forwarding delay of 3ms; 4ms: Upon receiving the exception signal, the MCU immediately freezes the current hardware parameters and test vector parameters: ΔV0=0.003V, B0=85%, D0=45ns, test vector frequency 150MHz, throughput 1.5GB / s; 5ms: The MCU assembles the fault characteristic entry according to the format: XXXXX (serial number)-XXXXXXXX (time)-0.003V-85%-45ns-150MHz-1.5GB / s; 6ms: The MCU performs CRC32 (32-bit cyclic redundancy check) on the fault entry. Hardware verification (verification code) calculates the verification code XXXXXX, appends it to the end of the entry, and obtains the final fault data: XXXXX (serial number) - XXXXXXXX (time) - 0.003V - 85% - 45ns - 150MHz - 1.5GB / s - XXXXXX (verification code); 7-10ms: The MCU simultaneously performs local storage and remote upload: writes the fault data to the Flash chip partition block; and uploads the fault data to the test management platform via the Ethernet chip; 10ms: The test management platform sends a "upload successful" low-level signal. After receiving the feedback, the MCU sends a "resume test" command to the FPGA; 15ms: The FPGA loads the benchmark test vector, and the test device returns to the dynamic test phase to continue executing the GPU adaptive test.

[0100] Through the above testing methods, hardware-level dynamic load adjustment simulates the load fluctuation scenarios of GPUs in real-world applications such as AI (Artificial Intelligence) training and scientific computing. This reduces the false negative rate of stability issues under high load fluctuations, ensuring the operational stability of the GPU. A four-dimensional correlation fault feature entry system is established, linking load, hardware parameters, test vectors, and faults. Fault troubleshooting eliminates the need for manual backtracking of the testing process; testers can directly locate the root cause of the problem through the fault entry. High-precision hardware-level acquisition of underlying hardware parameters such as GPU core voltage and PCIe link latency ensures that the test results are consistent with... The system improves the matching degree of GPU's actual application operation status; it abandons operating system scheduling and uses an FPGA+MCU hardware control architecture to adjust the load across the entire link latency, accurately capturing rapid changes in GPU load; parameters such as compatible GPU model, PCIe interface version, and voltage fluctuation threshold can be modified through MCU software configuration without replacing hardware, making it compatible with multiple mainstream server GPUs and reducing the adaptation and update costs of the test equipment; it adopts a dual storage design of Flash local cache + Ethernet remote upload, combined with hardware checksum, to ensure that fault data is not lost or tampered with, and automatically retryes when upload fails, reducing the fault data loss rate.

[0101] This embodiment also provides a testing system for accelerator cards. Figure 6 This is a schematic diagram of a test system for an accelerator card according to an embodiment of this application. Figure 1 ,like Figure 6 As shown, the test system includes a control unit and a sensor; the control unit is connected to the sensor, and both the sensor and the control unit are used to connect to the target accelerator card.

[0102] Optionally, in this embodiment, the sensor is used to: collect target operation information of the target accelerator card when the target accelerator card executes the target test vector according to the first attribute parameter, wherein the first attribute parameter is used to indicate the execution intensity of the target accelerator card executing the target test vector, and the target operation information is used to indicate the operation load of the target accelerator card; the control unit is used to: detect target difference information of the target accelerator card according to the target operation information, wherein the target difference information is used to indicate the first difference between the load intensity of the target accelerator card's operation load and the expected load intensity; adjust the first attribute parameter according to the target difference information to obtain a second attribute parameter, wherein the second difference between the load intensity of the target accelerator card's operation load and the expected load intensity when the target accelerator card executes the target test vector according to the execution intensity indicated by the second attribute parameter is less than the first difference; and control the target accelerator card to execute the target test vector according to the second attribute parameter.

[0103] Through the above testing system, when the target accelerator card executes the target test vector according to the first attribute parameter, the system detects the target difference information based on the target operation information used to indicate the target accelerator card's operating load. The first attribute parameter is adjusted according to the target difference information to obtain the second attribute parameter. When the target accelerator card executes the target test vector according to the execution intensity indicated by the second attribute parameter, the second difference between the operating load intensity and the expected load intensity is less than the first difference. Then, the system controls the target accelerator card to execute the target test vector according to the second attribute parameter. In other words, during the testing process of the target accelerator card, by adjusting the execution intensity of the target accelerator card executing the target test vector according to the target difference information, the load intensity of the target accelerator card's operating load is adjusted towards the expected load intensity. This allows the performance of the target accelerator card to be tested under varying load intensity conditions, improving the flexibility of accelerator card testing. Therefore, this system can solve the technical problem of poor testing flexibility in related technologies, achieving the technical effect of improving the testing flexibility of accelerator cards.

[0104] Optionally, in this embodiment, the control unit may be, but is not limited to, a single data processing device, or a combination of multiple data processing devices. For example, the control unit may be, but is not limited to, a CPU / MCU, or a combination of the aforementioned MCU and FPGA.

[0105] In an exemplary embodiment, the control component may, but is not limited to, being used to: detect a reference load parameter of the target accelerator card based on the target operating information of the target accelerator card, wherein the reference load parameter is used to indicate the load intensity of the operating load of the target accelerator card; and compare the reference load parameter and the target load parameter to obtain target difference information, wherein the target load parameter is used to indicate the expected load intensity.

[0106] In one exemplary embodiment, Figure 7 This is a schematic diagram of a test system for an accelerator card according to an embodiment of this application. Figure 2 ,like Figure 7 As shown, the control unit may include, but is not limited to, a first controller and a second controller, and the sensors include a first sensor, a second sensor, and a third sensor; the first controller is connected to the second controller, and the first controller is also connected to the first sensor, the second sensor, and the third sensor; the first controller is used to connect to the target accelerator card, and the first sensor, the second sensor, and the third sensor are all used to connect to the target accelerator card.

[0107] Optionally, in this embodiment, the first sensor may be used, but is not limited to: acquiring a first parameter, wherein the first parameter is used to indicate the power supply voltage of the target accelerator card; the second sensor may be used, but is not limited to: acquiring a second parameter, wherein the second parameter is used to indicate the busy level of data transmission between the target accelerator card and the memory of the target accelerator card; the third sensor may be used, but is not limited to: acquiring a third parameter, wherein the third parameter is used to indicate the communication delay between the target accelerator card and the processor connected to the target accelerator card; the target operating information includes the first parameter, the second parameter, and the third parameter; the first controller may be used, but is not limited to: acquiring the first parameter, the second parameter, and the third parameter; sending the first parameter, the second parameter, and the third parameter to the second controller; and, upon receiving the target adjustment parameter, adjusting the first attribute parameter according to the target adjustment parameter to obtain the second attribute parameter, wherein the target adjustment parameter is used to indicate the adjustment direction and adjustment magnitude of the execution intensity indicated by the first attribute parameter; controlling the target accelerator card... The accelerator card executes the target test vector according to the second attribute parameter; the second controller may, but is not limited to, being used to: calculate a weighted sum of the first parameter, the second parameter, and the third parameter based on the first weight value of the first parameter, the second weight value of the second parameter, and the third weight value of the third parameter to obtain a reference load parameter, wherein the reference load parameter is used to indicate the load intensity of the operating load of the target accelerator card; detect the target parameter range into which the reference load parameter falls in multiple load parameter ranges, wherein the target difference information includes the target parameter range; search for the target adjustment parameter corresponding to the target parameter range from the load parameter ranges and adjustment parameters with corresponding relationships, wherein the load parameter range is divided according to the target load parameter of the target accelerator card, the target load parameter is used to indicate the expected load intensity, and the load parameters falling into different load parameter ranges indicate different differences between the load intensity of the operating load of the target accelerator card and the expected load intensity, the target difference information includes the target parameter range; and send the target adjustment parameter to the first controller.

[0108] Optionally, in this embodiment, the first controller may be, but is not limited to, the aforementioned FPGA, and the second controller may be, but is not limited to, the aforementioned MCU.

[0109] Optionally, in this embodiment, Figure 8 This is a schematic diagram of a test system for an accelerator card according to an embodiment of this application. Figure 3 .like Figure 8As shown, FPGA, MCU, and sensor modules (i.e., the aforementioned sensors) can be integrated onto a single PCB board at the hardware level, enabling low-latency hardware-level communication via buses such as SPI, I2C, and PCIe 4.0. The core processor, which may include, but is not limited to, FPGA and MCU, is the core carrier for algorithm execution and instruction control. The GPU interface, which may be, but is not limited to, the physical interface connecting the core processor and the GPU, can be implemented via gold fingers directly inserted into the server GPU slot, enabling high-speed PCIe 4.0 communication, test vector transmission, and fault signal interaction. Figure 8 The GPU shown actually represents the external GPU under test, and the hardware sensing link between this device and the GPU (not a component of the device itself, used to illustrate the connection relationship). The sensor module can be used, but is not limited to, to collect three types of core hardware parameters: GPU core voltage, memory bandwidth, and PCIe link latency (i.e., the aforementioned first, second, and third parameters). The power management unit can be, but is not limited to, responsible for converting the server input voltage to 1.2V, 3.3V, and 5V to provide independent low-ripple power to the FPGA, MCU, and sensor module. Figure 8 The interface area next to the sensor module shown in the diagram corresponds to the integration of the SPI bus interface (connecting the FPGA and the sensor module) and the I2C bus interface (connecting the FPGA and the MCU). Figure 9 This is a schematic diagram of a test system for an accelerator card according to an embodiment of this application. Figure 4 . Figure 9 This may include, but is not limited to, PCB layout diagrams of modular devices, including surface mount layouts of the core processor, sensor modules, and power management units. The core processor, sensor modules, and power management units may be placed at locations 1, 2, and 3, but is not limited to.

[0110] Optionally, in this embodiment, before the second controller calculates the weighted sum of the first, second, and third parameters based on the first weight value of the first parameter, the second weight value of the second parameter, and the third weight value of the third parameter, the second controller or other computing-capable devices in the test system (e.g., a third controller in the test system other than the first and second controllers) or other computing-capable devices outside the test system may perform the following steps to determine the first, second, and third weight values: generating a first fitting curve based on multiple sets of first parameters, generating a second fitting curve based on multiple sets of second parameters, and generating a third fitting curve based on multiple sets of third parameters, wherein a set of first parameters includes the first set of parameters collected from the target accelerator card at the same time. The system includes a first parameter and a load parameter. A second parameter set includes second parameters and load parameters collected from the target accelerator card at the same time. A third parameter set includes third parameters and load parameters collected from the target accelerator card at the same time. The load parameter is used to indicate the computing power utilization on the target accelerator card. A first fitting curve is used to indicate how the load parameter changes with the first parameter. A second fitting curve is used to indicate how the load parameter changes with the second parameter. A third fitting curve is used to indicate how the load parameter changes with the third parameter. The system detects the target proportional relationship between the fitting determination coefficients of the first, second, and third fitting curves. The system generates a first weight value, a second weight value, and a third weight value that conform to the target proportional relationship.

[0111] Optionally, in this embodiment, after the first weight value, the second weight value, and the third weight value are determined by the second controller or other computing devices in the test system or other computing devices outside the test system, the determined first weight value, the second weight value, and the third weight value may be transmitted to the second controller.

[0112] In an exemplary embodiment, the control component may include, but is not limited to, a first controller and a second controller; the first controller is connected to the second controller and to a sensor, and is used to connect to the target accelerator card; wherein, the first controller may be used, but is not limited to, to: detect the fluctuation amplitude of the operating load of the target accelerator card according to the target operating information; send the fluctuation amplitude to the second controller; and, upon receiving a safety adjustment parameter, adjust a first attribute parameter according to the safety adjustment parameter to obtain a third attribute parameter, wherein the safety adjustment parameter is used to reduce the execution intensity indicated by the first attribute parameter; control the target accelerator card to execute the target test vector according to the third attribute parameter; the second controller may be used, but is not limited to, to: detect target difference information according to the target operating information when the fluctuation amplitude is less than or equal to a fluctuation amplitude threshold; and send the safety adjustment parameter to the first controller when the fluctuation amplitude is greater than the fluctuation amplitude threshold.

[0113] In an exemplary embodiment, the control component may include, but is not limited to, a first controller and a second controller, the first controller being connected to the second controller and a sensor, the first controller being used to connect to the target accelerator card; wherein, the first controller may be used, but is not limited to, for: detecting a reference load parameter of the target accelerator card based on the target operation information of the target accelerator card, wherein the reference load parameter is used to indicate the load intensity of the operating load of the target accelerator card; sending the reference load parameter to the second controller; and, upon receiving a first adjustment parameter or a second adjustment parameter, adjusting a first attribute parameter based on the first adjustment parameter or the second adjustment parameter to obtain a second attribute parameter, wherein the first adjustment parameter is used to indicate a reduction in the reduction magnitude of the execution intensity indicated by the first attribute parameter, and the second adjustment parameter is used to indicate an amplification magnitude of the execution intensity indicated by the first attribute parameter; the second controller may be, but is not limited to, [the following]. It is used for: calculating the absolute value of the difference between the reference load parameter and the target load parameter to obtain the target absolute value, and comparing the magnitude relationship between the reference load parameter and the target load parameter to obtain the target magnitude relationship, wherein the target load parameter is used to indicate the expected load intensity, and the target difference information includes the target absolute value and the target magnitude relationship; determining adjustment sub-parameters based on the target absolute value, wherein there is a positive correlation between the adjustment sub-parameters and the absolute value of the difference; when the target magnitude relationship is that the reference load parameter is greater than or equal to the target load parameter, calculating the difference between the initial adjustment parameter and the adjustment sub-parameter to obtain the first adjustment parameter, wherein the initial adjustment parameter is 1; when the target magnitude relationship is that the reference load parameter is less than the target load parameter, calculating the sum of the initial adjustment parameter and the adjustment sub-parameter to obtain the second adjustment parameter, wherein the initial adjustment parameter is 1; and sending the first adjustment parameter or the second adjustment parameter to the first controller.

[0114] In one exemplary embodiment, Figure 10 This is a schematic diagram of a test system for an accelerator card according to an embodiment of this application. Figure 5 ,like Figure 10 As shown, the test system also includes: a transmission component; a control component connected to the transmission component, and the transmission component being used to connect to the test management platform.

[0115] In an exemplary embodiment, the control unit may, but is not limited to, further be configured to: detect fault information of the target accelerator card when the target accelerator card executes the target test vector, wherein the fault information is used to indicate whether the operation of the target accelerator card has failed; if the fault information is detected indicating that the operation of the target accelerator card has failed, control the target accelerator card to stop running, and collect the current running information and current attribute parameters of the target accelerator card; send the current running information and current attribute parameters to the transmission unit; control the target accelerator card to execute the target test vector according to the security attribute parameters, wherein the security attribute parameters are used to indicate the execution strength of the target accelerator card executing the target test vector to ensure the safe operation of the target accelerator card; the transmission unit is configured to: transmit the current running information and current attribute parameters to the test management platform upon receiving them.

[0116] Optionally, in this embodiment, the transmission component may be, but is not limited to, a transmission device with data transmission function. For example, the transmission component may be, but is not limited to, an Ethernet chip.

[0117] For a description of the features in the embodiment corresponding to the test system of the accelerator card, please refer to the relevant description of the embodiment corresponding to the test method of the accelerator card, which will not be repeated here.

[0118] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0119] Embodiments of this application also provide a testing apparatus for an accelerator card. Figure 11 This is a structural block diagram of a testing apparatus for an accelerator card according to an embodiment of this application, as shown below. Figure 11 As shown, the device includes:

[0120] The first detection module 1102 is used to detect the target difference information of the target accelerator card based on the target operation information of the target accelerator card when the target accelerator card executes the target test vector according to the first attribute parameter. The first attribute parameter is used to indicate the execution intensity of the target accelerator card in executing the target test vector, the target operation information is used to indicate the operation load of the target accelerator card, and the target difference information is used to indicate the first difference between the load intensity of the operation load of the target accelerator card and the expected load intensity.

[0121] The adjustment module 1104 adjusts the first attribute parameter according to the target difference information to obtain the second attribute parameter, wherein the second difference between the load intensity of the target accelerator card when executing the target test vector according to the execution intensity indicated by the second attribute parameter and the expected load intensity is less than the first difference.

[0122] The first control module 1106 controls the target acceleration card to execute the target test vector according to the second attribute parameter.

[0123] Through the above device, when the target accelerator card executes the target test vector according to the first attribute parameter, the target difference information is detected based on the target operation information used to indicate the operating load of the target accelerator card. This information indicates the first difference between the load intensity of the target accelerator card's operating load and the expected load intensity. The first attribute parameter is adjusted according to the target difference information to obtain the second attribute parameter. When the target accelerator card executes the target test vector according to the execution intensity indicated by the second attribute parameter, the second difference between the load intensity of the operating load and the expected load intensity is less than the first difference. Then, the target accelerator card is controlled to execute the target test vector according to the second attribute parameter. That is, during the testing process of the target accelerator card, by adjusting the execution intensity of the target accelerator card executing the target test vector according to the target difference information, the load intensity of the target accelerator card's operating load is adjusted towards the expected load intensity. This allows the performance of the target accelerator card to be tested under varying load intensity conditions, improving the flexibility of accelerator card testing. Therefore, this solves the technical problem of poor testing flexibility of accelerator cards in related technologies, achieving the technical effect of improving the testing flexibility of accelerator cards.

[0124] In some embodiments, the first detection module includes: a first detection unit, configured to detect a reference load parameter of the target accelerator card based on the target operating information of the target accelerator card, wherein the reference load parameter is used to indicate the load intensity of the operating load of the target accelerator card; and a comparison unit, configured to compare the reference load parameter and the target load parameter to obtain target difference information, wherein the target load parameter is used to indicate the expected load intensity.

[0125] In some embodiments, the first detection unit is further configured to: acquire a first parameter, a second parameter, and a third parameter, wherein the first parameter indicates the power supply voltage of the target accelerator card, the second parameter indicates the busy level of data transmission between the target accelerator card and its memory, and the third parameter indicates the communication latency between the target accelerator card and the processor to which it is connected; the target operating information includes the first parameter, the second parameter, and the third parameter; and calculate a weighted sum of the first parameter, the second parameter, and the third parameter based on the first weight value of the first parameter, the second weight value of the second parameter, and the third weight value of the third parameter to obtain a reference load parameter.

[0126] In some embodiments, the first detection module further includes: a first generation unit, configured to generate a first fitting curve based on multiple sets of first parameters, a second fitting curve based on multiple sets of second parameters, and a third fitting curve based on multiple sets of third parameters before calculating the weighted sum of the first parameter, the second parameter, and the third parameter based on the first weight value of the first parameter, the second weight value of the second parameter, and the third weight value of the third parameter. The first set of first parameters includes a first parameter and a load parameter collected from the target accelerator card at the same time; the second set of second parameters includes a second parameter and a load parameter collected from the target accelerator card at the same time; and the third set of third parameters includes a first parameter and a load parameter collected from the target accelerator card at the same time. The system continuously collects third parameters and load parameters from the target accelerator card. The load parameter indicates the computing power utilization of the target accelerator card. The first fitting curve indicates how the load parameter changes with the first parameter, the second fitting curve indicates how the load parameter changes with the second parameter, and the third fitting curve indicates how the load parameter changes with the third parameter. The system also includes a second detection unit, which detects the target proportional relationship between the fitting determination coefficients of the first, second, and third fitting curves. Finally, a second generation unit generates first, second, and third weight values ​​that conform to the target proportional relationship.

[0127] In some embodiments, the comparison unit is further configured to: acquire a plurality of load parameter ranges, wherein the plurality of load parameter ranges are divided according to a target load parameter, and the load intensity of the target accelerator card indicated by load parameters falling into different load parameter ranges differs from the expected load intensity; detect the target parameter range into which the reference load parameter falls in the plurality of load parameter ranges, wherein the target difference information includes the target parameter range.

[0128] In some embodiments, the first detection module includes: a third detection unit, configured to detect the fluctuation range of the operating load of the target accelerator card according to the target operating information; a first adjustment unit, configured to adjust the first attribute parameter according to the safety adjustment parameter to obtain the third attribute parameter when the fluctuation range is greater than the fluctuation range threshold, wherein the safety adjustment parameter is used to reduce the execution intensity indicated by the first attribute parameter; and control the target accelerator card to execute the target test vector according to the third attribute parameter; and a fourth detection unit, configured to detect target difference information according to the target operating information when the fluctuation range is less than or equal to the fluctuation range threshold.

[0129] In some embodiments, the adjustment module includes: a lookup unit, configured to look up a target adjustment parameter corresponding to the target parameter range into which the reference load parameter falls from a load parameter range and adjustment parameters having a corresponding relationship, wherein the reference load parameter is used to indicate the load intensity of the operating load of the target accelerator card, the load parameter range is divided according to the target load parameter of the target accelerator card, the target load parameter is used to indicate the expected load intensity, the load parameters falling into different load parameter ranges indicate different differences between the load intensity of the operating load of the target accelerator card and the expected load intensity, the target difference information includes the target parameter range, and the target adjustment parameter is used to indicate the adjustment direction and adjustment magnitude of adjusting the execution intensity indicated by the first attribute parameter; and a second adjustment unit, configured to adjust the first attribute parameter according to the target adjustment parameter to obtain the second attribute parameter.

[0130] In some embodiments, the first detection module includes: a fifth detection unit, configured to detect a reference load parameter of the target accelerator card based on the target operating information of the target accelerator card, wherein the reference load parameter is used to indicate the load intensity of the operating load of the target accelerator card; and a first calculation unit, configured to calculate the absolute value of the difference between the reference load parameter and the target load parameter to obtain the target absolute value, and to compare the magnitude relationship between the reference load parameter and the target load parameter to obtain the target magnitude relationship, wherein the target load parameter is used to indicate the expected load intensity, and the target difference information includes the target absolute value and the target magnitude relationship.

[0131] In some embodiments, the adjustment module includes: a determining unit, configured to determine an adjustment sub-parameter based on a target absolute value, wherein the adjustment sub-parameter and the absolute value have a positive correlation; a second calculation unit, configured to calculate the difference between an initial adjustment parameter and an adjustment sub-parameter to obtain a first adjustment parameter when the target size relationship is that the reference load parameter is greater than or equal to the target load parameter, wherein the initial adjustment parameter is 1, and the first adjustment parameter is used to indicate the reduction in the execution intensity indicated by the first attribute parameter; and to calculate the sum of the initial adjustment parameter and the adjustment sub-parameter to obtain a second adjustment parameter when the target size relationship is that the reference load parameter is less than the target load parameter, wherein the initial adjustment parameter is 1, and the second adjustment parameter is used to indicate the amplification of the execution intensity indicated by the first attribute parameter; and a third adjustment unit, configured to adjust the first attribute parameter according to the first adjustment parameter or the second adjustment parameter to obtain a second attribute parameter.

[0132] In some embodiments, the testing apparatus further includes: a second detection module, configured to detect fault information of the target accelerator card when the target accelerator card executes the target test vector, wherein the fault information is used to indicate whether the operation of the target accelerator card has failed; a second control module, configured to control the target accelerator card to stop running when the fault information is detected to indicate that the operation of the target accelerator card has failed, and to collect the current operating information and current attribute parameters of the target accelerator card; a reporting module, configured to report the current operating information and current attribute parameters; and a third control module, configured to control the target accelerator card to execute the target test vector according to the security attribute parameters, wherein the security attribute parameters are used to indicate the execution strength of the target accelerator card executing the target test vector to ensure the safe operation of the target accelerator card.

[0133] For a description of the features in the embodiment corresponding to the testing device for the accelerator card, please refer to the relevant description in the embodiment corresponding to the testing method for the accelerator card, which will not be repeated here.

[0134] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described test method embodiments for accelerator cards.

[0135] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described test method embodiments for accelerator cards when run.

[0136] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0137] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described accelerator card testing method embodiments.

[0138] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described test method embodiments for accelerator cards.

[0139] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be performed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or one or more combinations thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0140] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0141] The foregoing has provided a detailed description of the testing method, system, and electronic device for an accelerator card provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A testing method for an accelerator card, characterized in that, include: When the target accelerator card executes the target test vector according to the first attribute parameter, the target difference information of the target accelerator card is detected according to the target operation information of the target accelerator card. The first attribute parameter is used to indicate the execution intensity of the target accelerator card in executing the target test vector, the target operation information is used to indicate the operation load of the target accelerator card, and the target difference information is used to indicate the first difference between the load intensity of the operation load of the target accelerator card and the expected load intensity. The first attribute parameter is adjusted according to the target difference information to obtain the second attribute parameter, wherein the second difference between the load intensity of the running load when the target accelerator card executes the target test vector according to the execution intensity indicated by the second attribute parameter and the expected load intensity is less than the first difference. The target accelerator card is controlled to execute the target test vector according to the second attribute parameter; Wherein, adjusting the first attribute parameter according to the target difference information to obtain the second attribute parameter includes: The first attribute parameter is adjusted based on the target parameter range into which the reference load parameter falls within multiple load parameter ranges, as well as the corresponding load parameter ranges and adjustment parameters, to obtain the second attribute parameter. The reference load parameter is used to indicate the load intensity of the target accelerator card's operating load. The target difference information includes the target parameter range. The adjustment parameter is used to indicate the adjustment direction and adjustment magnitude of the execution intensity indicated by the adjustment attribute parameter. Alternatively, the first attribute parameter can be adjusted based on the target absolute value and the target size relationship to obtain the second attribute parameter. Here, the target absolute value is the absolute value of the difference between the reference load parameter and the target load parameter; the target load parameter indicates the desired load intensity; the target absolute value determines the adjustment range of the first attribute parameter; the target size relationship is the size relationship between the reference load parameter and the target load parameter; the target size relationship determines the adjustment direction of the first attribute parameter; and the target difference information includes the target absolute value and the target size relationship.

2. The testing method for the accelerator card according to claim 1, characterized in that, The step of detecting the target difference information of the target accelerator card based on the target operation information of the target accelerator card includes: The reference load parameters are detected based on the target operation information of the target accelerator card. The target difference information is obtained by comparing the reference load parameters and the target load parameters.

3. The testing method for the accelerator card according to claim 2, characterized in that, The step of detecting the reference load parameter based on the target operating information of the target accelerator card includes: Acquire a first parameter, a second parameter, and a third parameter, wherein the first parameter is used to indicate the power supply voltage of the target accelerator card, the second parameter is used to indicate the busy level of data transmission between the target accelerator card and the memory of the target accelerator card, and the third parameter is used to indicate the communication latency between the target accelerator card and the processor connected to the target accelerator card. The target running information includes the first parameter, the second parameter, and the third parameter. The reference load parameter is obtained by calculating the weighted sum of the first parameter, the second parameter, and the third parameter based on the first weight value of the first parameter, the second weight value of the second parameter, and the third weight value of the third parameter.

4. The testing method for the accelerator card according to claim 3, characterized in that, Before calculating the weighted sum of the first parameter, the second parameter, and the third parameter based on the first weight value of the first parameter, the second weight value of the second parameter, and the third weight value of the third parameter, the method further includes: A first fitting curve is generated based on multiple sets of first parameters, a second fitting curve is generated based on multiple sets of second parameters, and a third fitting curve is generated based on multiple sets of third parameters. Each set of first parameters includes first parameters and load parameters collected simultaneously from the target accelerator card. Each set of second parameters includes second parameters and load parameters collected simultaneously from the target accelerator card. Each set of third parameters includes third parameters and load parameters collected simultaneously from the target accelerator card. The load parameters indicate the computing power utilization on the target accelerator card. The first fitting curve indicates how the load parameters change with the first parameters. The second fitting curve indicates how the load parameters change with the second parameters. The third fitting curve indicates how the load parameters change with the third parameters. The target proportional relationship between the fitting determination coefficients of the first fitted curve, the second fitted curve, and the third fitted curve is detected. Generate the first weight value, the second weight value, and the third weight value that conform to the target ratio relationship.

5. The testing method for the accelerator card according to claim 2, characterized in that, The step of comparing the reference load parameters and the target load parameters to obtain the target difference information includes: The multiple load parameter ranges are obtained, wherein the multiple load parameter ranges are divided according to the target load parameter, and the load parameters falling into different load parameter ranges indicate different differences between the load intensity of the target accelerator card's operating load and the expected load intensity; Detect the range of the target parameters.

6. The testing method for the accelerator card according to claim 1, characterized in that, The step of detecting the target difference information of the target accelerator card based on the target operation information of the target accelerator card includes: The fluctuation range of the target accelerator card's operating load is detected based on the target operating information; If the fluctuation amplitude is greater than the fluctuation amplitude threshold, the first attribute parameter is adjusted according to the safety adjustment parameter to obtain the third attribute parameter, wherein the safety adjustment parameter is used to reduce the execution intensity indicated by the first attribute parameter; and the target acceleration card is controlled to execute the target test vector according to the third attribute parameter. If the fluctuation amplitude is less than or equal to the fluctuation amplitude threshold, the target difference information is detected based on the target operation information.

7. The testing method for the accelerator card according to claim 1, characterized in that, The step of adjusting the first attribute parameter according to the target difference information to obtain the second attribute parameter includes: The target adjustment parameter corresponding to the target parameter range is found from the corresponding load parameter range and adjustment parameters. The load parameter range is divided according to the target load parameter of the target accelerator card. The load parameters falling into different load parameter ranges indicate different differences between the load intensity of the target accelerator card's operating load and the expected load intensity. The target adjustment parameter is used to indicate the adjustment direction and adjustment range of the execution intensity indicated by the first attribute parameter. The first attribute parameter is adjusted according to the target adjustment parameter to obtain the second attribute parameter.

8. The testing method for the accelerator card according to claim 1, characterized in that, The step of detecting the target difference information of the target accelerator card based on the target operation information of the target accelerator card includes: The reference load parameters are detected based on the target operation information of the target accelerator card. The absolute value of the difference between the reference load parameter and the target load parameter is calculated to obtain the target absolute value, and the size relationship between the reference load parameter and the target load parameter is compared to obtain the target size relationship.

9. The testing method for the accelerator card according to claim 8, characterized in that, The step of adjusting the first attribute parameter according to the target difference information to obtain the second attribute parameter includes: Adjustment sub-parameters are determined based on the target absolute value, wherein there is a positive correlation between the adjustment sub-parameters and the absolute value of the difference; When the target size relationship is such that the reference load parameter is greater than or equal to the target load parameter, the difference between the initial adjustment parameter and the adjustment sub-parameter is calculated to obtain a first adjustment parameter, wherein the initial adjustment parameter is 1, and the first adjustment parameter is used to indicate the reduction of the execution intensity indicated by the first attribute parameter; when the target size relationship is such that the reference load parameter is less than the target load parameter, the sum of the initial adjustment parameter and the adjustment sub-parameter is calculated to obtain a second adjustment parameter, wherein the initial adjustment parameter is 1, and the second adjustment parameter is used to indicate the amplification of the execution intensity indicated by the first attribute parameter; The first attribute parameter is adjusted according to the first adjustment parameter or the second adjustment parameter to obtain the second attribute parameter.

10. The testing method for the accelerator card according to claim 1, characterized in that, When the target accelerator card executes the target test vector, the method further includes: Detect the fault information of the target accelerator card, wherein the fault information is used to indicate whether the operation of the target accelerator card has failed; If the fault information is detected indicating that the target accelerator card has malfunctioned, the target accelerator card is controlled to stop running, and the current running information and current attribute parameters of the target accelerator card are collected. Report the current running information and the current attribute parameters; The target accelerator card is controlled to execute the target test vector according to security attribute parameters, wherein the security attribute parameters are used to indicate the execution strength of the target accelerator card in executing the target test vector to enable the target accelerator card to operate safely.

11. A testing system for an accelerator card, characterized in that, include: A control unit and a sensor; the control unit is connected to the sensor, and both the sensor and the control unit are used to connect to the target accelerator card; The sensor is configured to: collect target operation information of the target accelerator card when the target accelerator card executes the target test vector according to the first attribute parameter, wherein the first attribute parameter is used to indicate the execution intensity of the target accelerator card in executing the target test vector, and the target operation information is used to indicate the operating load of the target accelerator card; The control unit is configured to: detect target difference information of the target accelerator card based on the target operating information, wherein the target difference information is used to indicate a first difference between the load intensity of the target accelerator card's operating load and the expected load intensity; adjust the first attribute parameter based on the target difference information to obtain a second attribute parameter, wherein the second difference between the load intensity of the target accelerator card's operating load and the expected load intensity when the target accelerator card executes the target test vector according to the execution intensity indicated by the second attribute parameter is less than the first difference; and control the target accelerator card to execute the target test vector according to the second attribute parameter. The control component is used for: The first attribute parameter is adjusted based on the target parameter range into which the reference load parameter falls within multiple load parameter ranges, as well as the corresponding load parameter ranges and adjustment parameters, to obtain the second attribute parameter. The reference load parameter is used to indicate the load intensity of the target accelerator card's operating load. The target difference information includes the target parameter range. The adjustment parameter is used to indicate the adjustment direction and adjustment magnitude of the execution intensity indicated by the adjustment attribute parameter. Alternatively, the first attribute parameter can be adjusted based on the target absolute value and the target size relationship to obtain the second attribute parameter. Here, the target absolute value is the absolute value of the difference between the reference load parameter and the target load parameter; the target load parameter indicates the desired load intensity; the target absolute value determines the adjustment range of the first attribute parameter; the target size relationship is the size relationship between the reference load parameter and the target load parameter; the target size relationship determines the adjustment direction of the first attribute parameter; and the target difference information includes the target absolute value and the target size relationship.

12. The testing system for the accelerator card according to claim 11, characterized in that, The control component includes: a first controller and a second controller; the sensor includes: a first sensor, a second sensor, and a third sensor; the first controller is connected to the second controller, and the first controller is also connected to the first sensor, the second sensor, and the third sensor; the first controller is used to connect to the target accelerator card, and the first sensor, the second sensor, and the third sensor are all used to connect to the target accelerator card. The first sensor is used to: collect a first parameter, wherein the first parameter is used to indicate the power supply voltage of the target accelerator card; The second sensor is used to: acquire a second parameter, wherein the second parameter is used to indicate the level of data transmission activity between the target accelerator card and the memory of the target accelerator card; The third sensor is used to: collect a third parameter, wherein the third parameter is used to indicate the communication delay between the target accelerator card and the processor connected to the target accelerator card; the target operating information includes the first parameter, the second parameter and the third parameter; The first controller is configured to: acquire the first parameter, the second parameter, and the third parameter; send the first parameter, the second parameter, and the third parameter to the second controller; and, upon receiving a target adjustment parameter, adjust the first attribute parameter according to the target adjustment parameter to obtain the second attribute parameter, wherein the target adjustment parameter is used to indicate the adjustment direction and adjustment magnitude of the execution intensity indicated by the first attribute parameter; and control the target accelerator card to execute the target test vector according to the second attribute parameter. The second controller is configured to: calculate a weighted sum of the first parameter, the second parameter, and the third parameter based on the first weight value of the first parameter, the second weight value of the second parameter, and the third weight value of the third parameter to obtain the reference load parameter; detect the target parameter range; search for the target adjustment parameter corresponding to the target parameter range from the load parameter ranges and adjustment parameters that have a corresponding relationship, wherein the load parameter range is divided according to the target load parameter of the target accelerator card, and the load parameters falling into different load parameter ranges indicate different differences between the load intensity of the target accelerator card's operating load and the expected load intensity; and send the target adjustment parameter to the first controller.

13. The testing system for the accelerator card according to claim 11, characterized in that, The control unit includes: a first controller and a second controller; the first controller is connected to the second controller and is also connected to the sensor; the first controller is used to connect to the target acceleration card. The first controller is configured to: detect the fluctuation range of the operating load of the target accelerator card according to the target operating information; send the fluctuation range to the second controller; and, upon receiving a safety adjustment parameter, adjust the first attribute parameter according to the safety adjustment parameter to obtain a third attribute parameter, wherein the safety adjustment parameter is used to reduce the execution intensity indicated by the first attribute parameter; and control the target accelerator card to execute the target test vector according to the third attribute parameter. The second controller is configured to: detect the target difference information based on the target operation information when the fluctuation amplitude is less than or equal to the fluctuation amplitude threshold; and send the safety adjustment parameters to the first controller when the fluctuation amplitude is greater than the fluctuation amplitude threshold.

14. The testing system for the accelerator card according to claim 11, characterized in that, The testing system further includes: a transmission component; the control component is connected to the transmission component, and the transmission component is used to connect to the test management platform; The control component is further configured to: detect fault information of the target accelerator card when the target accelerator card executes the target test vector, wherein the fault information is used to indicate whether the operation of the target accelerator card has failed; if the fault information is detected indicating that the operation of the target accelerator card has failed, control the target accelerator card to stop running, and collect the current operating information and current attribute parameters of the target accelerator card; send the current operating information and the current attribute parameters to the transmission component; control the target accelerator card to execute the target test vector according to the security attribute parameters, wherein the security attribute parameters are used to indicate the execution strength of the target accelerator card executing the target test vector to ensure the safe operation of the target accelerator card; The transmission component is configured to: upon receiving the current operating information and the current attribute parameters, transmit the current operating information and the current attribute parameters to the test management platform.

15. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the test method for the accelerator card as described in any one of claims 1 to 10.

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