An arbitrary frequency high-precision low-noise non-polar phase modulation device and method
By combining a receiver, a digital phase-locked loop, and an analog phase-locked loop, high-precision, low-noise stepless phase modulation of the frequency reference source is achieved, solving the problem that the output clock in the prior art cannot simultaneously meet the requirements of high precision and low noise, and realizing flexible frequency adjustment and high-precision phase synchronization.
Patent Information
- Application Number
- CN202610921859.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-25
- Publication Date
- 2026-08-25
- Estimated Expiration
- 2046-06-25
AI Technical Summary
Existing technologies cannot simultaneously achieve high precision, low noise, and phase fine-tuning of a frequency reference source, especially since the output clock cannot meet the low noise requirements.
The system employs a combination of a receiver, a 10MHz thermostatic crystal oscillator, a digital phase-locked loop (PLL), an analog PLL, an FPGA module, an MCU module, a TDC time difference measurement module, and a thermostatic crystal oscillator Y1. It achieves high-precision, low-noise, stepless phase modulation through phase measurement and phase adjustment. The TDC time difference measurement module and the MCU module are used for phase difference feedback, and the digital PLL and the analog PLL are used for frequency synchronization.
It achieves high-precision, low-noise clock output, with clock phase adjustment accuracy up to 30ps, and the temperature-controlled crystal oscillator can be replaced according to different output frequency requirements, allowing for flexible adjustment of the output frequency.
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Figure CN122475696B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of time and frequency technology, specifically to a high-precision, low-noise stepless phase modulation device and method for arbitrary frequencies. Background Technology
[0002] Currently, the use of frequency reference sources in the time and frequency industry is becoming increasingly widespread. The requirements for frequency references in system clocks are becoming more and more stringent, including high precision, low noise, and phase fine-tuning. However, there are currently two methods for frequency reference output in the industry: one is to output directly through a docile cryogenic crystal. Although this method can achieve high precision and low noise, phase fine-tuning can only be achieved at the nanosecond level through DAC control. The other method is to provide a reference clock to a DPLL digital phase-locked loop after docile the cryogenic crystal, and then generate an output clock through the DPLL. Although this method can achieve phase fine-tuning down to 30ps, the output clock cannot meet the low noise requirements. Summary of the Invention
[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a high-precision, low-noise stepless phase modulation device and method for arbitrary frequencies.
[0004] The objective of this invention is achieved through the following technical solution: In a first aspect, this application discloses a high-precision, low-noise, stepless phase modulation device with arbitrary frequency, comprising: a receiver, a 10MHz thermostatic crystal oscillator, a digital phase-locked loop, an analog phase-locked loop, an FPGA module, an MCU module, a TDC time difference measurement module, and a thermostatic crystal oscillator Y1. The output of the receiver is connected to the FPGA module. The receiver receives satellite signals and demodulates the external 1PPS pulse signal and TOD time signal. Then, the external 1PPS pulse signal and TOD time signal are output to the FPGA module. The FPGA module is connected to the receiver, the 10MHz constant temperature crystal oscillator, the TDC time difference measurement module and the MCU module respectively. The FPGA module generates a local 1PPS pulse signal by dividing the 10MHz reference clock output by the 10MHz constant temperature crystal oscillator, and sends the external 1PPS pulse signal and the local 1PPS pulse signal to the stop1 channel and stop2 channel of the TDC time difference measurement module respectively for phase measurement. The TDC time difference measurement module is connected to the MCU module via the SPI bus, and the TDC time difference measurement module feeds back the phase difference between the external 1PPS pulse signal and the local 1PPS pulse signal to the MCU module. The MCU module adjusts the 10MHz thermostatic crystal oscillator via a digital-to-analog converter (DAC) based on the phase difference fed back by the TDC time difference measurement module, thereby completing the star clock synchronization and discipline of the 10MHz reference clock. The digital phase-locked loop uses a trained 10MHz thermostatic crystal oscillator as a reference clock to generate an adjustable frequency CLK_CH0. Based on the required output clock frequency CLK_OUT, the adjustable frequency CLK_CH0 is configured as the corresponding clock frequency. The analog phase-locked loop receives the adjustable frequency CLK_CH0 of the digital phase-locked loop and the output frequency CLK_CH1 of the oven-controlled crystal oscillator Y1, respectively. It performs phase detection on the adjustable frequency CLK_CH0 and the output frequency CLK_CH1, and outputs a DAC voltage-controlled signal to the oven-controlled crystal oscillator Y1. The output phase of the oven-controlled crystal oscillator Y1 is adjusted by the DAC voltage-controlled signal so that the output frequency CLK_CH1 is synchronized with the adjustable frequency CLK_CH0. The MCU module is also connected to an analog phase-locked loop via an SPI bus to adjust the phase of the adjustable frequency CLK_CH0 of the digital phase-locked loop. At the same time, the temperature-controlled crystal oscillator Y1 changes the phase of the output frequency CLK_CH1 synchronously with the digital phase-locked loop. The output terminal of the thermostatic crystal oscillator Y1 is also connected to a signal amplification circuit and a filter circuit in sequence, and outputs the required output clock frequency CLK_OUT.
[0005] Based on the first aspect, the TDC time difference measurement module adopts an MS1050NA four-channel time-to-digital converter.
[0006] Based on the first aspect, the thermostatic crystal oscillator Y1 is a replaceable structure. The thermostatic crystal oscillator Y1 with the corresponding frequency can be replaced according to the required output clock frequency CLK_OUT. At the same time, the adjustable frequency CLK_CH0 of the digital phase-locked loop is configured to be consistent with the output frequency CLK_CH1 of the thermostatic crystal oscillator Y1.
[0007] Based on the first aspect, the signal amplification circuit is an LNA low-noise amplifier. After the output frequency CLK_CH1 of the temperature-controlled crystal oscillator Y1 is amplified by the LNA low-noise amplifier and filtered by the filtering circuit, the phase noise of the LNA low-noise amplifier and the entire output path deteriorates by less than 5dBc relative to the temperature-controlled crystal oscillator Y1.
[0008] Based on the first aspect, the FPGA module and the MCU module are interconnected via GPIO pins.
[0009] Based on the first aspect, the digital phase-locked loop adopts the NCS23345 digital phase-locked loop chip.
[0010] Based on the first aspect, the simulated phase-locked loop uses the ADF4002 simulated phase-locked loop chip.
[0011] Secondly, this application discloses a high-precision, low-noise, stepless phase modulation method for arbitrary frequencies, utilizing the aforementioned high-precision, low-noise, stepless phase modulation device for arbitrary frequencies, comprising the following steps: S1. The receiver receives satellite signals, demodulates the external 1PPS pulse signal and TOD time signal, and then outputs the external 1PPS pulse signal and TOD time signal to the FPGA module. S2, the FPGA module uses the 10M reference clock output from the 10M constant temperature crystal oscillator to divide the frequency and generate a local 1PPS pulse signal; S3, the FPGA module sends the external 1PPS pulse signal and the local 1PPS pulse signal to different measurement channels of the TDC time difference measurement module to measure the phase difference between the two signals and upload them to the MCU module; S4. The MCU module drives the digital-to-analog converter (DAC) to adjust the 10MHz thermostatic crystal oscillator according to the phase difference, so that the 10MHz thermostatic crystal oscillator synchronizes with the star clock signal and outputs a disciplined 10MHz reference clock. S5. Input the tamed 10M reference clock into the digital phase-locked loop, configure the output frequency of the digital phase-locked loop according to the preset output frequency, and make it consistent with the output frequency of the 10M temperature-controlled crystal oscillator. S6. The analog phase-locked loop performs phase detection on the adjustable frequency CLK_CH0 of the digital phase-locked loop and the output frequency CLK_CH1 of the thermostatic crystal oscillator Y1, and outputs a voltage control signal to adjust the thermostatic crystal oscillator Y1 so that the adjustable frequency CLK_CH0 and the output frequency CLK_CH1 of the thermostatic crystal oscillator Y1 are consistent. S7. The MCU module sends a phase adjustment command to the digital phase-locked loop to adjust the phase of the adjustable frequency CLK_CH0 of the digital phase-locked loop. At the same time, the output frequency CLK_CH1 of the thermostatic crystal oscillator Y1 is synchronously changed in phase to achieve stepless phase adjustment. The output frequency CLK_CH1 clock signal of S8 and the constant temperature crystal oscillator Y1 is amplified and filtered with low noise before being output to the external clock at the required output frequency CLK_OUT.
[0012] Based on the second aspect, when it is necessary to change the required output clock frequency CLK_OUT, replace the temperature-controlled crystal oscillator Y1 corresponding to the required frequency, and reconfigure the adjustable frequency CLK_CH0 of the digital phase-locked loop.
[0013] The beneficial effects of this invention are: 1) This application can provide a high-precision, low-noise clock output; the clock phase adjustment accuracy can reach 30ps.
[0014] 2) This application allows the replacement of the thermostatic crystal oscillator according to different output frequency requirements. It is only necessary to configure the adjustable frequency of the digital phase-locked loop output to the clock corresponding to the replaced thermostatic crystal oscillator. Attached Figure Description
[0015] Figure 1This is a schematic diagram of the structure of an arbitrary frequency, high-precision, low-noise stepless phase modulation device according to an embodiment of the present invention. Detailed Implementation
[0016] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0017] For example, this application discloses a high-precision, low-noise stepless phase modulation device for arbitrary frequencies, the structural schematic of which is shown below. Figure 1 As shown, it includes: a receiver, a 10MHz thermostatic crystal oscillator, a digital phase-locked loop, an analog phase-locked loop, an FPGA module, an MCU module, a TDC time difference measurement module, and a thermostatic crystal oscillator Y1; The output of the receiver is connected to the FPGA module. The receiver receives satellite signals and demodulates the external 1PPS pulse signal and TOD time signal. Then, the external 1PPS pulse signal and TOD time signal are output to the FPGA module. The FPGA module is connected to the receiver, the 10MHz constant temperature crystal oscillator, the TDC time difference measurement module and the MCU module respectively. The FPGA module generates a local 1PPS pulse signal by dividing the 10MHz reference clock output by the 10MHz constant temperature crystal oscillator, and sends the external 1PPS pulse signal and the local 1PPS pulse signal to the stop1 channel and stop2 channel of the TDC time difference measurement module respectively for phase measurement. The TDC time difference measurement module is connected to the MCU module via the SPI bus, and the TDC time difference measurement module feeds back the phase difference between the external 1PPS pulse signal and the local 1PPS pulse signal to the MCU module. The MCU module adjusts the 10MHz thermostatic crystal oscillator via a digital-to-analog converter (DAC) based on the phase difference fed back by the TDC time difference measurement module, thereby completing the star clock synchronization and discipline of the 10MHz reference clock. The digital phase-locked loop uses a trained 10MHz thermostatic crystal oscillator as a reference clock to generate an adjustable frequency CLK_CH0. Based on the required output clock frequency CLK_OUT, the adjustable frequency CLK_CH0 is configured as the corresponding clock frequency. The analog phase-locked loop receives the adjustable frequency CLK_CH0 of the digital phase-locked loop and the output frequency CLK_CH1 of the oven-controlled crystal oscillator Y1, respectively. It performs phase detection on the adjustable frequency CLK_CH0 and the output frequency CLK_CH1, and outputs a DAC voltage-controlled signal to the oven-controlled crystal oscillator Y1. The output phase of the oven-controlled crystal oscillator Y1 is adjusted by the DAC voltage-controlled signal so that the output frequency CLK_CH1 is synchronized with the adjustable frequency CLK_CH0. The MCU module is also connected to an analog phase-locked loop via an SPI bus to adjust the phase of the adjustable frequency CLK_CH0 of the digital phase-locked loop. At the same time, the temperature-controlled crystal oscillator Y1 synchronously changes the phase of the output frequency CLK_CH1 following the digital phase-locked loop; the accuracy can reach 30ps. The output terminal of the thermostatic crystal oscillator Y1 is also connected to a signal amplification circuit and a filter circuit in sequence, and outputs the required output clock frequency CLK_OUT.
[0018] For example, the TDC time difference measurement module uses an MS1050NA four-channel time-to-digital converter. The MS1050NA is a high-performance time-to-digital converter with four built-in measurement channels, CMOS input, and serial SPI output. It features high measurement performance and high data transfer rate; flexible configuration and unlimited measurement range, making it suitable for many applications; it does not use any PLL technology, but calculates all internal STOP signal measurements and compares them with a configured reference clock. Each STOP channel can achieve a maximum measurement accuracy of 10 ps, a minimum pulse interval of 10 ns, and a total data transfer rate via SPI of approximately 1.5 MSPS. Key features include 4 STOP channels with 20ns pulse intervals; 2 combined channels with 10ns pulse intervals; a maximum SPI data transmission rate of 1.5MSPS; independent channel single-pulse measurement accuracy of 20psrms, and measurement accuracy of 10psrms in high-resolution mode, with a measurement range of 0s to 16s; each channel is equipped with 16-level FIFOs, which can automatically calibrate the reference clock (without PLL or DLL); differential reference clock input of 2MHz to 12.5MHz; CMOS level input and SPI readout output; and low power consumption (60mW).
[0019] For example, the thermostatic crystal oscillator Y1 is a replaceable structure. The thermostatic crystal oscillator Y1 with the corresponding frequency can be replaced according to the required output clock frequency CLK_OUT. At the same time, the adjustable frequency CLK_CH0 of the digital phase-locked loop is configured to be consistent with the output frequency CLK_CH1 of the thermostatic crystal oscillator Y1.
[0020] For example, the signal amplification circuit is an LNA low-noise amplifier. After the output frequency CLK_CH1 of the temperature-controlled crystal oscillator Y1 is amplified by the LNA low-noise amplifier and filtered by the filtering circuit, the phase noise of the LNA low-noise amplifier and the entire output path deteriorates by less than 5dBc relative to the temperature-controlled crystal oscillator Y1.
[0021] For example, the FPGA module and the MCU module are interconnected via GPIO pins.
[0022] For example, the digital phase-locked loop uses the NCS23345 digital phase-locked loop chip. The NCS23345 digital phase-locked loop chip has the following characteristics: Phase Adjustment: 10 output channels, each of which can be phase adjusted with an adjustment accuracy of less than 30ps; Skew Adjustment / Clock Offset Calibration: All 10 output channels can be aligned with one clock channel as a reference. Zero-delay: This mode is suitable for applications that require a defined and consistent minimum delay between the selected input and output clocks. This mode is supported for all 10 output channels.
[0023] For example, the simulated phase-locked loop uses the ADF4002 simulated phase-locked loop chip.
[0024] For example, this application discloses a high-precision, low-noise stepless phase modulation method for arbitrary frequencies, which utilizes the aforementioned high-precision, low-noise stepless phase modulation device for arbitrary frequencies, and includes the following steps: S1. The receiver receives satellite signals, demodulates the external 1PPS pulse signal and TOD time signal, and then outputs the external 1PPS pulse signal and TOD time signal to the FPGA module. S2, the FPGA module uses the 10M reference clock output from the 10M constant temperature crystal oscillator to divide the frequency and generate a local 1PPS pulse signal; S3, the FPGA module sends the external 1PPS pulse signal and the local 1PPS pulse signal to different measurement channels of the TDC time difference measurement module to measure the phase difference between the two signals and upload them to the MCU module; S4. The MCU module drives the digital-to-analog converter (DAC) to adjust the 10MHz thermostatic crystal oscillator according to the phase difference, so that the 10MHz thermostatic crystal oscillator synchronizes with the star clock signal and outputs a disciplined 10MHz reference clock. S5. Input the tamed 10M reference clock into the digital phase-locked loop, configure the output frequency of the digital phase-locked loop according to the preset output frequency, and make it consistent with the output frequency of the 10M temperature-controlled crystal oscillator. S6. The analog phase-locked loop performs phase detection on the adjustable frequency CLK_CH0 of the digital phase-locked loop and the output frequency CLK_CH1 of the thermostatic crystal oscillator Y1, and outputs a voltage control signal to adjust the thermostatic crystal oscillator Y1 so that the adjustable frequency CLK_CH0 and the output frequency CLK_CH1 of the thermostatic crystal oscillator Y1 are consistent. S7. The MCU module sends a phase adjustment command to the digital phase-locked loop to adjust the phase of the adjustable frequency CLK_CH0 of the digital phase-locked loop. At the same time, the output frequency CLK_CH1 of the thermostatic crystal oscillator Y1 is synchronously changed in phase to achieve stepless phase adjustment. The output frequency CLK_CH1 clock signal of S8 and the constant temperature crystal oscillator Y1 is amplified and filtered with low noise before being output to the external clock at the required output frequency CLK_OUT.
[0025] For example, when it is necessary to change the required output clock frequency CLK_OUT, replace the temperature-controlled crystal oscillator Y1 corresponding to the required frequency, and reconfigure the adjustable frequency CLK_CH0 of the digital phase-locked loop.
[0026] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.
Claims
1. A high-precision, low-noise stepless phase modulation device for arbitrary frequencies, characterized in that, include: Receiver, 10MHz thermostatic crystal oscillator, digital phase-locked loop, analog phase-locked loop, FPGA module, MCU module, TDC time difference measurement module and thermostatic crystal oscillator Y1; The output of the receiver is connected to the FPGA module. The receiver receives satellite signals and demodulates the external 1PPS pulse signal and TOD time signal. Then, the external 1PPS pulse signal and TOD time signal are output to the FPGA module. The FPGA module is connected to the receiver, the 10MHz constant temperature crystal oscillator, the TDC time difference measurement module and the MCU module respectively. The FPGA module generates a local 1PPS pulse signal by dividing the 10MHz reference clock output by the 10MHz constant temperature crystal oscillator, and sends the external 1PPS pulse signal and the local 1PPS pulse signal to the stop1 channel and stop2 channel of the TDC time difference measurement module respectively for phase measurement. The TDC time difference measurement module is connected to the MCU module via the SPI bus, and the TDC time difference measurement module feeds back the phase difference between the external 1PPS pulse signal and the local 1PPS pulse signal to the MCU module. The MCU module adjusts the 10MHz thermostatic crystal oscillator via a digital-to-analog converter (DAC) based on the phase difference fed back by the TDC time difference measurement module, thereby completing the star clock synchronization and discipline of the 10MHz reference clock. The digital phase-locked loop uses a trained 10MHz thermostatic crystal oscillator as a reference clock to generate an adjustable frequency CLK_CH0. Based on the required output clock frequency CLK_OUT, the adjustable frequency CLK_CH0 is configured as the corresponding clock frequency. The analog phase-locked loop receives the adjustable frequency CLK_CH0 of the digital phase-locked loop and the output frequency CLK_CH1 of the oven-controlled crystal oscillator Y1, respectively. It performs phase detection on the adjustable frequency CLK_CH0 and the output frequency CLK_CH1, and outputs a DAC voltage-controlled signal to the oven-controlled crystal oscillator Y1. The output phase of the oven-controlled crystal oscillator Y1 is adjusted by the DAC voltage-controlled signal so that the output frequency CLK_CH1 is synchronized with the adjustable frequency CLK_CH0. The MCU module is also connected to an analog phase-locked loop via an SPI bus to adjust the phase of the adjustable frequency CLK_CH0 of the digital phase-locked loop. At the same time, the temperature-controlled crystal oscillator Y1 changes the phase of the output frequency CLK_CH1 synchronously with the digital phase-locked loop. The output terminal of the thermostatic crystal oscillator Y1 is also connected to a signal amplification circuit and a filter circuit in sequence, and outputs the required output clock frequency CLK_OUT.
2. The arbitrary frequency, high-precision, low-noise, stepless phase modulation device according to claim 1, characterized in that: The TDC time difference measurement module uses an MS1050NA four-channel time-to-digital converter.
3. The arbitrary frequency, high-precision, low-noise, stepless phase-tuning device according to claim 1, characterized in that: The thermostatic crystal oscillator Y1 is a replaceable structure. The thermostatic crystal oscillator Y1 with the corresponding frequency can be replaced according to the required output clock frequency CLK_OUT. At the same time, the adjustable frequency CLK_CH0 of the digital phase-locked loop is configured to be consistent with the output frequency CLK_CH1 of the thermostatic crystal oscillator Y1.
4. The arbitrary frequency, high-precision, low-noise, stepless phase-tuning device according to claim 1, characterized in that: The signal amplification circuit is an LNA low-noise amplifier. After the output frequency CLK_CH1 of the temperature-controlled crystal oscillator Y1 is amplified by the LNA low-noise amplifier and filtered by the filter circuit, the phase noise of the LNA low-noise amplifier and the entire output path deteriorates by less than 5dBc relative to the temperature-controlled crystal oscillator Y1.
5. The arbitrary frequency, high-precision, low-noise, stepless phase-tuning device according to claim 1, characterized in that: The FPGA module and the MCU module are interconnected via GPIO pins.
6. The arbitrary frequency, high-precision, low-noise, stepless phase-tuning device according to claim 1, characterized in that: The digital phase-locked loop uses the NCS23345 digital phase-locked loop chip.
7. The arbitrary frequency, high-precision, low-noise, stepless phase modulation device according to claim 1, characterized in that: The simulated phase-locked loop uses the ADF4002 simulated phase-locked loop chip.
8. A high-precision, low-noise, stepless phase modulation method for arbitrary frequencies, employing the high-precision, low-noise, stepless phase modulation device for arbitrary frequencies as described in any one of claims 1-7, characterized in that... Includes the following steps: S1. The receiver receives satellite signals, demodulates the external 1PPS pulse signal and TOD time signal, and then outputs the external 1PPS pulse signal and TOD time signal to the FPGA module. S2, the FPGA module uses the 10M reference clock output from the 10M constant temperature crystal oscillator to divide the frequency and generate a local 1PPS pulse signal; S3, the FPGA module sends the external 1PPS pulse signal and the local 1PPS pulse signal to different measurement channels of the TDC time difference measurement module to measure the phase difference between the two signals and upload them to the MCU module; S4. The MCU module drives the digital-to-analog converter (DAC) to adjust the 10MHz thermostatic crystal oscillator according to the phase difference, so that the 10MHz thermostatic crystal oscillator synchronizes with the star clock signal and outputs a disciplined 10MHz reference clock. S5. Input the tamed 10M reference clock into the digital phase-locked loop, configure the output frequency of the digital phase-locked loop according to the preset output frequency, and make it consistent with the output frequency of the 10M temperature-controlled crystal oscillator. S6. The analog phase-locked loop performs phase detection on the adjustable frequency CLK_CH0 of the digital phase-locked loop and the output frequency CLK_CH1 of the thermostatic crystal oscillator Y1, and outputs a voltage control signal to adjust the thermostatic crystal oscillator Y1 so that the adjustable frequency CLK_CH0 and the output frequency CLK_CH1 of the thermostatic crystal oscillator Y1 are consistent. S7. The MCU module sends a phase adjustment command to the digital phase-locked loop to adjust the phase of the adjustable frequency CLK_CH0 of the digital phase-locked loop. At the same time, the output frequency CLK_CH1 of the thermostatic crystal oscillator Y1 is synchronously changed in phase to achieve stepless phase adjustment. The output frequency CLK_CH1 clock signal of S8 and the constant temperature crystal oscillator Y1 is amplified and filtered with low noise before being output to the external clock at the required output frequency CLK_OUT.
9. The high-precision, low-noise stepless phase modulation method for arbitrary frequencies according to claim 8, characterized in that: When the required output clock frequency CLK_OUT needs to be changed, replace the temperature-controlled crystal oscillator Y1 corresponding to the required frequency, and reconfigure the adjustable frequency CLK_CH0 of the digital phase-locked loop.
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