Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are disclosed. Methods, apparatuses, systems, and techniques for dicing a semiconductor wafer into a plurality of semiconductor devices are provided. In one aspect, a semiconductor device includes a circuit layer and a substrate. The semiconductor device includes four side surfaces and one or more notches extending into a portion of at least one of the four side surfaces, wherein sidewalls of the one or more notches include microcracks extending into the circuit layer, and wherein a remaining portion of the at least one of the four side surfaces is substantially planar and intersects at least one of the one or more notches along a first direction; a portion of one or more of the four side surfaces is substantially planar and extends from a first surface to a second surface of the semiconductor device, the first surface and the second surface being opposite each other along the first direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and manufacturing processes for semiconductor devices. Background Technology

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive due to their ability to increase array density by stacking more layers within a similar footprint. 3D memory devices typically include a memory array of memory cells and peripheral circuitry for facilitating the operation of the memory array. Peripheral circuitry may include capacitors such as metal-oxide-semiconductor capacitors (MOMCAPs).

[0003] The demand for higher-density, cheaper memory devices has led to the formation of memory devices with increased stack thickness and higher chip integration. The increasing number of metal layers and the complex materials within each layer present challenges during packaging and dicing processes. These complex materials and metal layers can challenge dicing methods, resulting in poor edge quality of the memory device. For example, some dicing methods can cut through complex materials, but this reduces wafer strength due to the introduction of edge defects, which can pose significant risks and affect the mechanical properties of the final packaged memory device. Therefore, a dicing method is needed that can maintain high device quality and wafer strength during the fabrication of memory devices. Summary of the Invention

[0004] This disclosure describes methods, apparatus, systems, and techniques for managing capacitor structures in three-dimensional (3D) semiconductor devices.

[0005] One aspect of this disclosure is characterized by a method of forming a semiconductor device. The method includes: providing a semiconductor wafer including a circuit layer and a substrate, wherein the circuit layer is stacked on the substrate along a first direction; forming one or more recesses along a second direction perpendicular to the first direction; and slicing the semiconductor wafer along the first direction to divide the semiconductor wafer into semiconductor devices, wherein a first semiconductor device includes four side surfaces, and a first recess of the one or more recesses is split into two notches of two adjacent semiconductor devices, wherein at least one of the four side surfaces intersects with at least one of the notches and is substantially flat, wherein at least a portion of at least one of the four side surfaces extends along the first direction from a first surface of a corresponding semiconductor device to a second surface, and wherein the first and second side surfaces of the four side surfaces are opposite to each other along the second direction, and the third and fourth side surfaces of the four side surfaces are opposite to each other along the third direction.

[0006] In some embodiments, the semiconductor wafer further includes a slitting line extending along a second direction and a third direction perpendicular to the first and second directions.

[0007] In some embodiments, slicing a semiconductor wafer further includes slicing the circuit layer and the substrate along a slicing line.

[0008] In some embodiments, forming one or more grooves is based on performing laser grooving, wherein laser grooving includes: focusing a laser beam having a first energy level onto the surface of a circuit layer, the surface of the circuit layer being away from the substrate along a first direction; and using the laser beam to ablate a portion of the circuit layer of a semiconductor wafer along the first direction.

[0009] In some implementations, the sidewalls of one or more recesses include microcracks extending in a second direction into the circuit layer.

[0010] In some embodiments, dicing a semiconductor wafer into semiconductor devices includes: dicing the semiconductor wafer along a first direction based on performing a pre-grinding stealth dicing (SDBG).

[0011] In some embodiments, performing SDBG includes: focusing a laser beam having a second energy level onto a semiconductor wafer, wherein the laser beam is internally focused onto a substrate of the semiconductor wafer, and wherein the second energy level of the laser beam is lower than a first energy level of the laser beam; and applying external stress to the substrate of the semiconductor wafer by means of the laser beam to separate the semiconductor devices of the semiconductor wafer from each other.

[0012] In some embodiments, forming one or more grooves is based on performing blade grooving, wherein blade grooving includes: removing a portion of a circuit layer along a first direction using a cutting blade, wherein the cutting blade cuts into the circuit layer of the semiconductor wafer and physically removes the portion of the circuit layer along the first direction.

[0013] In some implementations, the circuit layer includes a notch region connected to one or more recesses.

[0014] Another aspect of this disclosure features a semiconductor device. The semiconductor device includes a circuit layer and a substrate, wherein the circuit layer is stacked on the substrate along a first direction, wherein the semiconductor device includes four side surfaces, and wherein a first side surface and a second side surface of the four side surfaces are opposite to each other along a second direction perpendicular to the first direction, and a third side surface and a fourth side surface of the four side surfaces are opposite to each other along a third direction perpendicular to the first and second directions; one or more notches extend along the first direction into a portion of at least one of the four side surfaces, wherein the sidewalls of the one or more notches include microcracks extending along the second direction into the circuit layer, and wherein the remaining portion of at least one of the four side surfaces is substantially flat and intersects with at least one of the one or more notches along the first direction; and a portion of the one or more side surfaces of the four side surfaces is substantially flat and extends from a first surface of the semiconductor device to a second surface, wherein the first surface and the second surface of the semiconductor device are opposite to each other along the first direction.

[0015] In some implementations, the length of one or more notches along the second direction is greater than 20 μm.

[0016] In some embodiments, the sidewalls of one or more recesses include uneven surfaces.

[0017] In some embodiments, one or more notches extend along a first direction through the circuit layer and into the substrate of the semiconductor device.

[0018] In some embodiments, the number of microcracks on a first portion of the sidewall of one or more notches is greater than the number of microcracks on a second portion of the sidewall of one or more notches, and the first portion of the sidewall of one or more notches is closer to a first surface of the semiconductor device along a first direction than the second portion of the sidewall of one or more notches.

[0019] Another aspect of this disclosure features a semiconductor device. The semiconductor device includes a circuit layer and a substrate, wherein the circuit layer is stacked on the substrate along a first direction, wherein the semiconductor device includes four side surfaces, and wherein a first side surface and a second side surface of the four side surfaces are opposite to each other along a second direction perpendicular to the first direction, and a third side surface and a fourth side surface of the four side surfaces are opposite to each other along a third direction perpendicular to the first and second directions; one or more recesses extend along the first direction into a portion of at least one of the four side surfaces, wherein the remaining portion of at least one of the four side surfaces is substantially flat and intersects with at least one of the one or more recesses along the first direction; and a portion of one or more of the four side surfaces is substantially flat and extends from a first surface of the semiconductor device to a second surface, wherein the first surface and the second surface of the semiconductor device are opposite to each other along the first direction.

[0020] In some implementations, the circuit layer includes a notch region connected to one or more notches.

[0021] In some embodiments, the length of one or more notches along the second direction is in the range of 10 μm to 20 μm.

[0022] In some embodiments, the sidewalls of one or more recesses include substantially flat surfaces.

[0023] In some embodiments, the slope of a first portion of the sidewall of one or more notches is greater than the slope of a second portion of the sidewall of one or more notches, and the first portion of the sidewall of one or more notches is closer to the first surface of the semiconductor device along a first direction than the second portion of the sidewall of one or more notches.

[0024] In some embodiments, one or more notches extend along a first direction into the circuit layer of the semiconductor device.

[0025] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the specification, drawings, and claims. Attached Figure Description

[0026] The accompanying drawings, which are incorporated herein and form a part of this disclosure, illustrate various aspects of this disclosure and, together with the description, further serve to explain the principles of this disclosure and enable those skilled in the art to implement and use this disclosure.

[0027] Figure 1A A perspective view of an exemplary 3D semiconductor wafer is shown.

[0028] Figure 1BA top view of an exemplary hybrid dicing process for a 3D semiconductor wafer is shown.

[0029] Figure 1C A cross-sectional view of two adjacent semiconductor devices is shown during the dicing process.

[0030] Figures 2A-2B A cross-sectional view of an exemplary semiconductor device is shown.

[0031] Figure 2C A top view of an exemplary semiconductor device is shown.

[0032] Figures 3A-3C An exemplary process for manufacturing a semiconductor device is shown.

[0033] Figure 3D It shows along Figure 3C A cross-sectional view of the semiconductor structure with cutting line AA' in the figure.

[0034] Figures 4A-4G A top view of one or more grooves on an exemplary semiconductor wafer is shown.

[0035] Figure 5 A flowchart illustrating an exemplary process for manufacturing a semiconductor device is shown.

[0036] Figure 6 A block diagram of an exemplary system is shown.

[0037] The same reference numerals and designations in the various figures indicate the same elements. It should also be understood that the various exemplary implementations shown in the figures are merely illustrative representations and are not necessarily drawn to scale. Detailed Implementation

[0038] This disclosure discloses a technique relating to a method of manufacturing a semiconductor device. An exemplary method includes: providing a semiconductor wafer including a circuit layer and a substrate, wherein the circuit layer is stacked on the substrate along a first direction and one or more recesses are formed along a second direction perpendicular to the first direction. The method further includes: dicing the semiconductor wafer along the first direction to divide the semiconductor wafer into semiconductor devices, wherein a first semiconductor device includes four side surfaces, and a first recess of one or more recesses is split into two notches of two adjacent semiconductor devices, wherein at least one of the four side surfaces intersects with at least one of the notches and is substantially flat, wherein at least a portion of at least one of the four side surfaces extends along the first direction from a first surface of a corresponding semiconductor device to a second surface, and wherein the first and second side surfaces of the four side surfaces are opposite to each other along the second direction, and the third and fourth side surfaces of the four side surfaces are opposite to each other along the third direction.

[0039] Embodiments of this disclosure can provide one or more of the following technical advantages and / or benefits. First, the method includes a hybrid dicing process capable of manufacturing high-quality semiconductor devices with high wafer strength. Second, one or more grooves between two adjacent semiconductor devices can facilitate the dicing of the semiconductor wafer by providing stress concentration regions that allow for easy separation of the semiconductor devices. In other words, adding one or more grooves can help improve the quality of the manufactured semiconductor device. Third, the dicing process separates the semiconductor devices from each other by applying an external separation force from the substrate to maintain high wafer strength. Additionally, the stress concentration regions created by the one or more grooves also help the separation force propagate from the substrate to the circuit layer. Therefore, semiconductor devices manufactured by the disclosed method can achieve high device quality with high wafer strength.

[0040] Figure 1A A perspective view of an exemplary 3D semiconductor wafer 100 is shown. The semiconductor wafer 100 may include a semiconductor device 102. The semiconductor wafer 100 may include circuit layers (e.g., Figure 1C Circuit layer 108) and substrate (e.g., Figure 1C The substrate 110 is shown in the figure. In some embodiments, the circuit layer 108 may include a plurality of dielectric and metal layers stacked on top of each other in a vertical direction (e.g., the Z direction). In some embodiments, the semiconductor device 102 may be a volatile memory device, such as dynamic random access memory (DRAM). In some embodiments, the semiconductor device 102 may be a video random access memory (VRAM) or a non-volatile memory (NVM) device, such as NAND flash memory or ferroelectric random access memory (FeRAM). In some embodiments, the semiconductor device 102 may be a peripheral circuit layer for different memory devices (e.g., volatile memory devices and non-volatile memory devices). In some embodiments, such as... Figure 1A As shown, the semiconductor wafer 100 may include a dicing line 104 extending along a horizontal direction perpendicular to the Z-direction (e.g., the X and Y directions). In some embodiments, the dicing line 104 is located between two adjacent semiconductor devices 102. The semiconductor devices 102 of the semiconductor wafer 100 can be separated by a hybrid dicing process. In some embodiments, the dicing line 104 may include test circuitry coupled to a circuit layer 108. The test circuitry in the dicing line 104 can be used to test the performance of the semiconductor devices.

[0041] Figure 1B A top view of an exemplary hybrid dicing process for a 3D semiconductor wafer is shown. Figure 1B As shown, the hybrid cutting process includes a two-step cutting process. In some embodiments, the first step of the two-step cutting process forms one or more grooves 106 along a portion of the cutting line 104 (e.g., Figure 1C (As shown). The groove 106 can have various shapes along the horizontal direction. For example, as Figure 1B As shown, groove 106a extends continuously along the Y direction, and groove 106b has a single hole on the cutting line 104. In some embodiments, laser grooving methods (such as...) can be performed. Figure 2A (as shown) or blade grooving method (such as) Figure 2B As shown, groove 106 is formed using laser grooving and blade grooving methods. Groove 106 extends from a first side 100-1 of the semiconductor wafer into the semiconductor wafer 100. For example, as... Figure 1C As shown, the groove 106, created by a laser grooving method or a blade grooving method, extends along the Z-direction. The groove 106 extends from the first side 100-1 of the semiconductor wafer. In some embodiments, the second step of the two-step dicing process dices the semiconductor wafer 100 along the Z-direction via a dicing line 104 to divide the semiconductor wafer 100 into semiconductor devices 102. The dicing of the semiconductor wafer 100 is achieved by performing a stealth dicing before grinding (SDBG) method. The SDBG method separates the semiconductor wafer 100 from the second side 100-2 of the semiconductor wafer 100. For example, as... Figure 1C As shown, the first step of the hybrid dicing process is performed by a laser grooving method or a blade grooving method, which forms a groove 106 from a first side 100-1 of the semiconductor wafer. The groove 106 extends along a portion of the dicing line 104. The second step of the hybrid dicing process is performed by an SDBG method, which separates the semiconductor wafer 100 from a second side 100-2 of the semiconductor wafer 100 along the dicing line 104. The groove 106 of the semiconductor wafer 100 is separated into two notches of two adjacent semiconductor devices 102 (e.g., Figure 2A (notch 208 in the middle).

[0042] In some embodiments, the semiconductor device 102 can be separated by performing a first method. The first method includes two steps. The first step involves forming a groove 106 along the entire slit line 104 by performing a laser grooving method or a blade grooving method, wherein the groove 106 extends from the first side 100-1 into the semiconductor wafer 100. The second step involves separating the semiconductor wafer from the second side 100-2 along the groove 106 by performing an SDBG method. The first method can provide excellent separation capability for different materials (e.g., thick metal layers or dielectric layers); however, since the groove 106 is formed along the entire slit line 104, the first method may result in reduced wafer strength. In some embodiments, the semiconductor device 102 can be separated by performing a second method. The second method separates the semiconductor device 102 by performing an SDBG method along the slit line 104 to separate the semiconductor devices 102 from each other from the second side 100-2 of the semiconductor wafer 100. The second method can maintain higher wafer strength; however, the second method has poorer separation capability for thick metal layers and dielectric layers. Compared to the first and second methods, the hybrid dicing process described in this disclosure provides excellent separation capability for thick metal and dielectric layers by forming a groove 106 from a first side 100-1 of the semiconductor wafer along a portion of the dicing line 104. Since the groove 106 extends only along a portion of the dicing line 104, the hybrid dicing process described in this disclosure also maintains high wafer strength after the semiconductor device 102 is separated.

[0043] Figure 1C A cross-sectional view of two adjacent semiconductor devices during the dicing process is shown. Figure 1C As shown, a recess 106 is located between two adjacent semiconductor devices 102. Semiconductor device 102 may include a circuit layer 108 stacked on top of substrate 110. Substrate 110 may be any suitable semiconductor substrate having any suitable semiconductor material (e.g., single-crystal, polycrystalline, or single-crystal semiconductor). For example, substrate 110 may include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. In some embodiments, substrate 110 may be removed from semiconductor device 102 in subsequent processes of manufacturing semiconductor device 102. Figure 1CAs shown, circuit layer 108 may include a first conductive layer 109a, a second conductive layer 109b, and a third conductive layer 109c stacked on top of each other along the Z-direction. In some embodiments, two adjacent conductive layers are separated by a dielectric layer. In some embodiments, the dielectric layer may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the dielectric layer may include a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof. In some embodiments, the dielectric constant of the high-k dielectric material (e.g., hafnium oxide) is greater than the dielectric constant of the dielectric material (e.g., silicon oxide). For example, the high-k dielectric material (e.g., hafnium oxide) has a dielectric constant greater than 20, and the dielectric material (e.g., silicon oxide) has a dielectric constant of 3.9. Conductive layers 109a, 109b, and 109c may include metallic structures, such as interconnect circuitry of peripheral circuitry surrounded by dielectric material, or test circuitry coupled to semiconductor device 102. Figure 1C For illustrative purposes only, circuit layer 108 may include any number of conductive layers 109a, 109b and 109c separated by dielectric layers.

[0044] In some implementations, such as Figure 1C As shown, along the Y direction, the length of the first end 106-1 of the groove 106 is greater than the length of the second end 106-2 of the groove 106, and the first end 106-1 is farther from the substrate 110 than the second end 106-2 of the groove 106. In some embodiments, the smaller length of the second end 106-2 of the groove 106 creates a stress concentration region that facilitates the SDBG method. In some embodiments, the SDBG method for dicing a semiconductor wafer includes applying external stress in the substrate 110 using a laser source, wherein the laser source is focused in the substrate 110. In some embodiments, the substrate 110 may be thinned during the manufacturing process to facilitate the SDBG method for dicing the semiconductor wafer 100.

[0045] Figure 2A A cross-sectional view of an exemplary semiconductor device 200a is shown. In some embodiments, the semiconductor device 200a can be coupled with... Figure 1A The semiconductor device 102 is similar to or the same as the semiconductor device 200a. The semiconductor device 200a includes a circuit layer 202 and a substrate 204. The circuit layer 202 is stacked on the substrate 204 in a vertical direction (e.g., the Z direction). Figure 2C A top view of an exemplary semiconductor device 200a is shown. Figure 2C As shown, semiconductor device 200a includes four side surfaces 206, wherein a first side surface 206a and a second side surface 206b of the four side surfaces 206 are opposite to each other along a horizontal direction perpendicular to the Z direction (e.g., the X direction). In some embodiments, such as Figure 2C As shown, the third side surface 206c and the fourth side surface 206d of the four side surfaces 206 are opposite each other along a second horizontal direction (e.g., the Y direction) perpendicular to the Z and X directions.

[0046] like Figure 2A and Figure 2C As shown, the semiconductor device 200a may further include one or more recesses 208 extending along the Z-direction into a portion of at least one of the four side surfaces 206. In some embodiments, the sidewalls of the one or more recesses 208 include microcracks 212 extending along the X-direction into the circuit layer 202. The remaining portion of the at least one side surface of the four side surfaces 206 is substantially flat and intersects with at least one of the recesses 208 along the Z-direction. For example, as Figure 2A As shown, the notch 208 extends into a portion 206b-1 of the side surface 206b, wherein the remaining portion 206b-2 of the side surface 206b is substantially flat and intersects with the portion 206b-1 of the side surface 206b. In some embodiments, one or more notches 208 are formed by performing a laser grooving method, and the substantially flat surface of the remaining portion 206b-2 of the side surface 206b is formed by performing an SDBG method.

[0047] In some embodiments, a portion of one or more of the four side surfaces 206 is substantially flat and extends from a first surface 210-1 of the semiconductor device 200a to a second surface 210-2, wherein the first surface 210-1 and the second surface 210-2 of the semiconductor device 200a are opposite to each other along the Z direction. For example, as Figure 2A As shown, side surface 206a includes a substantially flat surface extending from a first surface 210-1 of semiconductor device 200a to a second surface 210-2. In some embodiments, the substantially flat surface of side surface 206a is formed by performing an SDBG method. In some embodiments, the substantially flat surface of side surface 206a and the substantially flat surface of the remaining portion 206b-2 are formed by performing a single SDBG step.

[0048] In some embodiments, circuit layer 202 may include a first conductive layer 203a, a second conductive layer 203b, and a third conductive layer 203c stacked on top of each other along the Z-direction. In some embodiments, two adjacent conductive layers are separated by a dielectric layer. The dielectric layer may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. It may also include a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof. The high-k dielectric material (e.g., hafnium oxide) has a greater dielectric constant than the dielectric material (e.g., silicon oxide). For example, the high-k dielectric material (e.g., hafnium oxide) has a dielectric constant greater than 20, while the dielectric material (e.g., silicon oxide) has a dielectric constant of 3.9. Conductive layers 203a, 203b, and 203c may include metallic structures, such as interconnect circuitry of peripheral circuitry surrounded by dielectric material, and test circuitry coupled to semiconductor device 200a.

[0049] Substrate 204 can be any suitable semiconductor substrate having any suitable semiconductor material (e.g., single crystal, polycrystalline, or single-crystal semiconductor). For example, substrate 204 can include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. In some embodiments, substrate 204 can be removed from semiconductor device 200a in subsequent processes of manufacturing semiconductor device 200a.

[0050] In some embodiments, one or more notches 208 are formed by performing a laser grooving method, in which a high-power laser ablates a portion of the semiconductor device 200a from the first surface 210-1. For example... Figure 2A As shown, the length of one end 208-1 of one or more notches is greater than 20 μm along the X direction, and the sidewalls of one or more notches include uneven surfaces. In some embodiments, one or more notches 208 extend along the Z direction through the circuit layer 202 and into the substrate 204 of the semiconductor device. In some embodiments, the number of microcracks 212 on a first portion of the sidewalls of one or more notches 208 is greater than the number of microcracks 212 on a second portion of the sidewalls of one or more notches 208, and the first portion of the sidewalls of one or more notches 208 is closer along the Z direction to the second surface 210-2 of the semiconductor device 200a than the second portion of the sidewalls of one or more notches 208. For example, as Figure 2AAs shown, the density of microcracks 212 in one or more notches 208 near the second surface 210-2 is higher than the density of microcracks 212 in one or more notches 208 near the first surface 210-1. In some embodiments, the uneven surfaces and microcracks 212 on the sidewalls of one or more notches 208 are the result of laser grooving, in which a high-power laser ablates a portion of the circuit layer of the semiconductor device 200a from the first surface 210-1.

[0051] Figure 2B A cross-sectional view of an exemplary semiconductor device 200b is shown. In some embodiments, the semiconductor device 200b can be coupled with... Figure 2A The semiconductor device 200b is similar to or identical to the semiconductor device 200a, except that one or more notches 214 in the semiconductor device 200b are formed by performing a blade slotting method. The semiconductor device 200b includes a circuit layer 202 and a substrate 204. The circuit layer 202 is stacked on the substrate 204 in a vertical direction (e.g., the Z direction). In some embodiments, the semiconductor device 200b includes four side surfaces 206, wherein a first side surface 206a and a second side surface 206b of the four side surfaces 206 are opposite each other in a horizontal direction perpendicular to the Z direction (e.g., the X direction), as shown below. Figure 2A As shown. In some implementations ( Figure 2B (not shown in the image), the third and fourth side surfaces of the four side surfaces 206 are opposite each other along a second horizontal direction (e.g., the Y direction) perpendicular to the Z and X directions.

[0052] In some embodiments, the semiconductor device 200b may further include one or more recesses 214 extending along the Z-direction to a portion of at least one of the four side surfaces 206, wherein the remaining portion of at least one of the four side surfaces 206 is substantially flat and intersects with at least one of the one or more recesses 214 along the Z-direction. For example, as Figure 2B As shown, the notch 214 extends into a portion 206b-1 of the side surface 206b, wherein the remaining portion 206b-2 of the side surface 206b is substantially flat and intersects with the portion 206b-1 of the side surface 206b. In some embodiments, one or more notches 214 are formed by performing blade grooving, and the substantially flat surface of the remaining portion 206b-2 of the side surface 206b is formed by performing the SDBG method.

[0053] In some embodiments, a portion of one or more of the four side surfaces 206 is substantially flat and extends from a first surface 210-1 of the semiconductor device 200b to a second surface 210-2, wherein the first surface 210-1 and the second surface 210-2 of the semiconductor device 200b are opposite to each other along the Z direction. For example, as Figure 2B As shown, side surface 206a includes a substantially flat surface extending from a first surface 210-1 of semiconductor device 200b to a second surface 210-2. In some embodiments, the substantially flat surface of side surface 206a is formed by performing an SDBG method. In some embodiments, the substantially flat surface of side surface 206a and the substantially flat surface of the remaining portion 206b-2 are formed by performing a single SDBG step.

[0054] In some embodiments, one or more notches 214 are formed by performing a blade grooving method, in which a blade physically removes a portion of the semiconductor device 200b from the first surface 210-1. In some embodiments, the circuit layer 202 includes a notch region 216 connected to the one or more notches 214. In some embodiments, such as Figure 1B As shown, the length of one end 214-1 of one or more notches 214 is in the range of 10 μm to 20 μm along the X direction. In some embodiments, the sidewalls of one or more notches 214 include substantially flat surfaces. In some embodiments, the slope of a first portion 214a of the sidewalls of one or more notches 214 is greater than the slope of a second portion 214b of the sidewalls of one or more notches 214, and the first portion 214a of the sidewalls of one or more notches 214 is closer to the first surface 210-1 of the semiconductor device 200b along the Z direction than the second portion 214b of the sidewalls of one or more notches 214. For example, as Figure 2B As shown, the different slopes of the first portion 214a and the second portion 214b of the sidewall of the notch 214 form a unique shape that matches the blade used during blade grooving. In some embodiments, one or more notches 214 extend along the Z-direction into the circuit layer 202 of the semiconductor device, wherein the depth of the one or more notches 214 corresponds to the size of the blade. In some embodiments, the substantially flat surfaces on the sidewalls of the one or more notches 214 and the notch region 216 are a result of blade grooving, in which the blade physically removes a portion of the circuit layer of the semiconductor device 200a from the first surface 210-1.

[0055] Figures 3A-3D This illustrates the manufacture of semiconductor devices (e.g., such as...). Figure 2A The semiconductor device 200a shown and such Figure 2BAn exemplary process of the semiconductor device 200b shown. Figures 3A-3C A top view of an exemplary semiconductor structure at various stages of the manufacturing process is shown.

[0056] Figure 3A A semiconductor structure 300a is shown. Semiconductor structure 300a includes a semiconductor wafer 302. Semiconductor wafer 302 may include a circuit layer and a substrate, wherein the circuit layer is stacked on the substrate in a vertical direction (e.g., the Z direction). Semiconductor wafer 302 also includes a semiconductor device 304. For example, as... Figure 3A As shown, the semiconductor devices 304 are spaced apart from each other along a horizontal direction perpendicular to the Z direction (e.g., the X and Y directions).

[0057] Figure 3B A semiconductor structure 300b is shown, which can be formed by etching a portion of a circuit layer along the Y direction to form one or more recesses 306. In some embodiments, one or more recesses 306 can be formed by performing a laser grooving method. The laser grooving method includes focusing a laser beam having a first energy level onto the surface of the circuit layer and using the laser beam to ablate a portion of the circuit layer of the semiconductor wafer 302 along the Z direction. In some embodiments, one or more recesses 306 can be formed by performing a blade grooving method. The blade grooving method includes using a cutting blade to remove a portion of the circuit layer along the Z direction, wherein the cutting blade cuts into the circuit layer of the semiconductor wafer 302 and physically removes that portion of the circuit layer along the Z direction. In some embodiments, one or more recesses 306 can help to separate semiconductor devices 304 on the semiconductor wafer 302 from each other by providing stress concentration regions at one end of one or more recesses 306. Figures 4A-4G As shown, one or more grooves 306 can have various shapes and structures along the horizontal direction.

[0058] Figures 4A-4G A top view of one or more grooves on an exemplary semiconductor wafer is shown. Figures 4A-4G It can be used to manufacture, such as Figure 3B This is a part of an exemplary process for the semiconductor device shown. Figures 4A-4G As shown, a semiconductor wafer 400 may include a plurality of semiconductor devices 402 and a sectional line 404 extending in a horizontal direction (e.g., the X and Y directions). The sectional line 404 separates the semiconductor devices 402 from each other along the Z direction. One or more recesses 406 are formed during the manufacturing process to separate the semiconductor devices 402 from each other, wherein the one or more recesses extend along a portion of the sectional line 404. In some embodiments, the one or more recesses 406 may be... Figure 3BOne or more grooves 306 are similar or identical. One or more grooves 406 can have various shapes and structures, such as... Figures 4A-4G As shown. For example, as Figure 4A As shown, one or more grooves 406 can extend continuously along the Y direction. Figure 4B As shown, one or more grooves 406 can extend continuously along the X direction. (As illustrated...) Figure 4C As shown, one or more grooves 406 may extend along the X direction through a portion of the section line 404. Figure 4D As shown, one or more grooves 406 may extend along the Y direction through a portion of the section line 404. Figure 4E As shown, one or more grooves 406 may extend through a portion of the sectional line 404 along both the X and Y directions, and one or more grooves 406 form a cross-shaped structure at the corner of the semiconductor device 402. Figure 4F As shown, one or more grooves 406 may have a circular structure on the cut line 404, wherein one or more grooves 406 are located at the corners of the semiconductor device 402. Figure 4G As shown, one or more grooves 406 extend intermittently through a portion of the section line 404 along the X and Y directions. The shape and structure of the one or more grooves 406 are not limited to... Figures 4A-4G The example shown. For example, one or more grooves 406 may have Figures 4A-4G The combination of various shapes and structures shown.

[0059] Figure 3CA semiconductor structure 300c is shown, which can be formed by dicing a semiconductor wafer 302 along a first direction to divide the semiconductor wafer 302 into semiconductor devices 304. In some embodiments, the semiconductor wafer 302 may include dicing lines 308 extending along the X and Y directions, wherein dicing the semiconductor wafer 302 further includes dicing circuit layers and a substrate along the dicing lines 308. In some embodiments, the semiconductor wafer 302 is diced by performing a pre-grinding stealth dicing (SDBG) method. In some embodiments, one or more recesses 306 extend along a portion of the dicing lines 308, and the SDBG method splits a recess in one or more recesses 306 into two recesses of two adjacent semiconductor devices 304. In some embodiments, the SDBG method includes focusing a laser beam having a second energy level onto the substrate of the semiconductor wafer 302 and applying external stress to the substrate of the semiconductor wafer 302 by the laser beam to dicing the semiconductor devices 304 apart from each other. In some embodiments, the second energy level of the laser beam is lower than the first energy level. In some embodiments, external stress provides a lateral force to separate the semiconductor device 304 from the substrate to the circuit layer. In some embodiments, stress concentration areas created by one or more recesses 306 can facilitate the propagation of the lateral force from the substrate to the circuit layer, thereby increasing the separation force of the semiconductor device 304. In some embodiments, the cut line 308 may include some kind of test circuit coupled to the semiconductor device 304, wherein the test circuit can be used to test the device performance of the semiconductor device 304.

[0060] Figure 3D It shows along Figure 3C A cross-sectional view of the semiconductor structure 300d with cleavage line AA' in the diagram. The semiconductor structure 300d may include a circuit layer 310 stacked on top of the substrate 312. One or more grooves 306 formed by performing a laser grooving method or a blade grooving method extend from the first side 300d-1 of the semiconductor structure 300d. In some embodiments, such as Figure 3D As shown, one or more grooves 306 extend through the circuit layer 310 and into the substrate 312. After forming one or more grooves 306, a laser beam 314 with a second energy level is focused from the second side 300d-2 of the semiconductor structure 300d onto the substrate 312 by performing the SDBG method to separate the semiconductor device 304.

[0061] Figure 5 A flowchart of an exemplary process 500 for manufacturing a semiconductor structure is shown. Process 500 can be performed to form a semiconductor device (e.g., Figure 2A Semiconductor device 200a and Figure 2B (Semiconductor device 200b). See also: Figures 3A-3CTo describe process 500. Process 500 may include forming Figures 3A-3C The process of manufacturing a semiconductor structure in process 500 includes one or more steps. It should be understood that the operations shown in process 500 are not exhaustive, and other operations may be performed before, after, or between any of the shown operations. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 5 The different execution sequences are shown.

[0062] At operation 502, a semiconductor wafer (e.g., Figure 3A Semiconductor wafer 302 in the middle). The semiconductor wafer includes circuit layers (e.g., Figure 2A Circuit layer 202) and substrate (e.g., Figure 2B The substrate 204 in which the circuit layer is stacked on the substrate along a first direction (e.g., the Z direction).

[0063] At operation 504, one or more grooves are formed along a second direction (e.g., the X direction) perpendicular to the first direction. Figure 1C (one or more grooves 106 in the middle).

[0064] At operation 506, the semiconductor wafer is cleaved along a first direction to divide the semiconductor wafer into semiconductor devices (e.g., Figure 1A Semiconductor device 102), wherein the first semiconductor device in the semiconductor device includes four side surfaces (e.g., Figure 2A The side surfaces 206a and 206b in the middle), and the first groove in one or more grooves splits into two notches of two adjacent semiconductor devices (e.g., Figure 2A Notch 208 or Figure 2B (recess 214) wherein at least one of the four side surfaces intersects with at least one recess in the recess and is substantially flat, wherein at least a portion of at least one of the four side surfaces extends along a first direction from the first surface of the corresponding semiconductor device (e.g., Figure 2A The first surface 210-1 in the middle extends to the second surface (e.g., Figure 2A The second surface 210-2 in the middle), and wherein the first side surface of the four side surfaces (e.g., Figure 2A The side surface 206a) and the second side surface (e.g., Figure 2A The side surfaces 206b) are opposite to each other along the second direction, and the third and fourth side surfaces of the four side surfaces are opposite to each other along the third direction.

[0065] In some embodiments, the semiconductor wafer further includes: cutting lines extending along a second direction and a third direction (e.g., the Y direction) perpendicular to the first and second directions. Figure 1A (Section line 104 in the middle).

[0066] In some embodiments, slicing a semiconductor wafer further includes slicing the circuit layer and the substrate along a slicing line.

[0067] In some embodiments, forming one or more grooves is based on performing laser grooving, wherein laser grooving includes focusing a laser beam having a first energy level onto the surface of a circuit layer, the surface of the circuit layer being away from the substrate along a first direction; and using the laser beam to ablate a portion of the circuit layer of a semiconductor wafer along the first direction.

[0068] In some embodiments, the sidewalls of one or more recesses include: microcracks extending in a second direction into the circuit layer (e.g., Figure 2A Microcracks 212 in the middle.

[0069] In some embodiments, dicing a semiconductor wafer into semiconductor devices includes: dicing the semiconductor wafer along a first direction based on performing a pre-grinding stealth dicing (SDBG).

[0070] In some embodiments, performing SDBG includes: focusing a laser beam having a second energy level onto a semiconductor wafer, wherein the laser beam is internally focused onto a substrate of the semiconductor wafer, and wherein the second energy level of the laser beam is lower than a first energy level of the laser beam; and applying external stress to the substrate of the semiconductor wafer by means of the laser beam to separate the semiconductor devices of the semiconductor wafer from each other.

[0071] In some embodiments, forming one or more grooves is based on performing blade grooving, wherein blade grooving includes removing a portion of a circuit layer along a first direction using a cutting blade, wherein the cutting blade cuts into the circuit layer of the semiconductor wafer and physically removes the portion of the circuit layer along the first direction.

[0072] In some implementations, the circuit layer includes a notch region connected to one or more recesses (e.g., Figure 2B (gap area 216 in the middle).

[0073] Figure 6 A block diagram of system 600 is shown, which, according to one or more embodiments of this disclosure, includes one or more semiconductor devices (e.g., memory devices). System 600 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 6As shown, system 600 may include a host device 608 and a memory system 602 having one or more 3D memory devices 604 and a memory controller 606. The host device 608 may include a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host device 608 may be configured to send data to or receive data from one or more 3D memory devices 604.

[0074] 3D memory device 604 can be any 3D memory device disclosed herein, such as Figures 2A-2B The 3D memory device 604 is depicted in the present disclosure. In some embodiments, the 3D memory device 604 includes NAND flash memory. A memory controller 606 (also referred to as controller circuitry) is coupled to the 3D memory device 604 and the host device 608. According to embodiments of the present disclosure, the 3D memory device 604 may include a plurality of conductive interconnects that pass through a cover layer and contact conductive pads in a conductive pad layer, and the memory controller 606 may be coupled to the 3D memory device 604 through at least one of the plurality of conductive interconnects. The memory controller 606 is configured to control the 3D memory device 604. For example, the memory controller 606 may be configured to operate a plurality of channel structures via word lines. The memory controller 606 may manage data stored in the 3D memory device 604 and communicate with the host device 608.

[0075] In some embodiments, the memory controller 606 is designed / configured to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 606 is designed / configured to operate in high duty cycle environments in SSDs or in embedded multimedia cards (eMMCs) used as data storage devices in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. The memory controller 606 may be configured to control the operation of the 3D memory device 604, such as read, erase, and program (or write) operations. The memory controller 606 may also be configured to manage various functions regarding data stored or to be stored in the 3D memory device 604, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 606 is also configured to process error correction codes (ECC) regarding data read from or written to the 3D memory device 604. The memory controller 606 may also perform any other appropriate function, such as formatting the 3D memory device 604.

[0076] The memory controller 606 can communicate with external devices (e.g., host device 608) according to a specific communication protocol. For example, the memory controller 606 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0077] The memory controller 606 and one or more 3D memory devices 604 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 602 can be implemented and packaged into different types of end electronic products. Figure 6 In one example shown, the memory controller 606 and a single 3D memory device 604 can be integrated into the memory card 602. The memory card 602 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMC), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0078] The embodiments, actions, and operations of the subject matter described in this disclosure can be implemented in digital electronic circuits, tangibly embodied computer software or firmware, computer hardware (including the structures disclosed in this disclosure and their structural equivalents), or combinations thereof. Embodiments of the subject matter described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by or control of the operation of a data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagation signal, such as a machine-generated electrical signal, optical signal, or electromagnetic signal, generated to encode information for transmission to a suitable receiving device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination thereof, or a portion thereof. The computer storage medium is not a propagation signal.

[0079] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some implementations," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment must include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other implementations is within the knowledge of those skilled in the art.

[0080] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage. Additionally, again depending at least partly on the context, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described.

[0081] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” not only means “directly on something,” but also includes the meaning of “on something” with an intermediate feature or layer between them. Furthermore, “above” or “on top of” not only means “above something” or “on top of something,” but can also include the meaning of “above something” or “on top of something” without an intermediate feature or layer between them (i.e., directly on something).

[0082] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another (or more) elements or features as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the apparatus during use or process steps. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0083] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore, the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0084] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper overlay structure, or may have a range smaller than that of the lower or upper overlay structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnect lines, and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers.

[0085] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter set for a component or process step during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. As used herein, the range of values ​​may be due to minor variations in manufacturing processes or tolerances. As used herein, the term "about" indicates the value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate the value of a given quantity that varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of the value).

[0086] In this disclosure, the terms "horizontal / horizontally / laterally" mean nominally parallel to the lateral surface of the substrate, and the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate.

[0087] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having strings of vertically oriented memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate.

[0088] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features can be in direct contact, and may also include embodiments where an additional feature can be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or constructions discussed.

[0089] The descriptions of specific implementation methods described above can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance provided herein, such adjustments and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementation methods.

[0090] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims as defined by the claims themselves, but rather as descriptions of features that may be implemented for specific embodiments of a particular invention. In the context of individual embodiments, certain features described in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, one or more features from the claimed combination may be removed from the combination in some cases, and the claims may be for sub-combinations or variations thereof.

[0091] Similarly, although operations are depicted in the accompanying drawings in a specific order and referenced in the claims, this should not be construed as requiring the operations to be performed in the specific order or sequence shown, or requiring all shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0092] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the following claims. For example, the actions cited in the claims can be performed in a different order and still achieve the desired result. As an example, the process depicted in the drawings does not necessarily require the specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0093] The breadth and scope of this disclosure should not be limited to any of the embodiments described above, but should be defined solely by the following claims and their equivalents.

Claims

1. A method of forming a semiconductor device, comprising: A semiconductor wafer including a circuit layer and a substrate is provided, wherein the circuit layer is stacked on the substrate along a first direction; One or more grooves are formed along a second direction perpendicular to the first direction; and The semiconductor wafer is cleaved along the first direction to divide the semiconductor wafer into semiconductor devices, wherein a first semiconductor device in the semiconductor device includes four side surfaces, and a first recess in one or more recesses is split into two notches of two adjacent semiconductor devices. Wherein, at least one of the four side surfaces intersects with at least one of the recesses and is substantially flat, wherein at least a portion of the at least one of the four side surfaces extends from the first surface of the corresponding semiconductor device to the second surface along the first direction, and wherein the first and second side surfaces of the four side surfaces are opposite to each other along the second direction, and the third and fourth side surfaces of the four side surfaces are opposite to each other along a third direction perpendicular to the first and second directions.

2. The method according to claim 1, wherein, The semiconductor wafer further includes: a cutting line extending along the second direction and a third direction perpendicular to the first direction and the second direction.

3. The method according to claim 1 or 2, wherein, The process of slicing the semiconductor wafer further includes slicing the circuit layer and the substrate along the slicing line.

4. The method according to any one of claims 1 to 3, wherein, The formation of the one or more grooves is based on performing laser grooving, wherein the laser grooving includes: A laser beam having a first energy level is focused onto the surface of the circuit layer, the surface of the circuit layer being located away from the substrate along the first direction; and The laser beam is used to ablate a portion of the circuit layer of the semiconductor wafer along the first direction.

5. The method according to any one of claims 1 to 4, wherein, The sidewalls of one or more recesses include microcracks extending into the circuit layer along the second direction.

6. The method according to any one of claims 1 to 5, wherein, Dividing the semiconductor wafer into semiconductor devices includes: dicing the semiconductor wafer along the first direction based on performing a pre-grinding stealth dicing (SDBG).

7. The method according to any one of claims 1 to 6, wherein, Executing the SDBG includes: A laser beam having a second energy level is focused onto the semiconductor wafer, wherein the laser beam is internally focused onto the substrate of the semiconductor wafer, and wherein the second energy level of the laser beam is lower than the first energy level of the laser beam; and External stress is applied to the substrate of the semiconductor wafer by the laser beam to separate the semiconductor devices of the semiconductor wafer from one another.

8. The method according to any one of claims 1 to 3 or claim 6 or 7, wherein, The formation of the one or more grooves is based on performing blade grooving, wherein the blade grooving includes: A portion of the circuit layer is removed along the first direction using a cutting blade, wherein the cutting blade cuts into the circuit layer of the semiconductor wafer and physically removes the portion of the circuit layer along the first direction.

9. The method according to any one of claims 1 to 3 or any one of claims 6 to 8, wherein, The circuit layer includes a notched area connected to the one or more recesses.

10. A semiconductor device, comprising: A circuit layer and a substrate, wherein the circuit layer is stacked on the substrate along a first direction, wherein the semiconductor device includes four side surfaces, and wherein a first side surface and a second side surface of the four side surfaces are opposite to each other along a second direction perpendicular to the first direction, and a third side surface and a fourth side surface of the four side surfaces are opposite to each other along a third direction perpendicular to both the first and second directions; and One or more notches, the notches extending along a first direction into a portion of at least one of the four side surfaces, wherein the sidewalls of the notches include microcracks extending along a second direction into the circuit layer, and wherein the remaining portions of the at least one of the four side surfaces are substantially flat and intersect with at least one of the notches along the first direction. Wherein, a portion of one or more of the four side surfaces is substantially flat and extends from the first surface of the semiconductor device to the second surface, and wherein the first surface and the second surface of the semiconductor device are opposite to each other along the first direction.

11. The semiconductor device according to claim 10, wherein, The length of the one or more notches is greater than 20 μm along the second direction.

12. The semiconductor device according to claim 10 or 11, wherein, The sidewalls of the one or more recesses include uneven surfaces.

13. The semiconductor device according to any one of claims 10 to 12, wherein, The one or more notches extend along the first direction through the circuit layer and into the substrate of the semiconductor device.

14. The semiconductor device according to any one of claims 10 to 13, wherein, The number of microcracks on a first portion of the sidewall of the one or more notches is greater than the number of microcracks on a second portion of the sidewall of the one or more notches, and the first portion of the sidewall of the one or more notches is closer to the first surface of the semiconductor device along the first direction than the second portion of the sidewall of the one or more notches.

15. A semiconductor device, comprising: A circuit layer and a substrate, wherein the circuit layer is stacked on the substrate along a first direction, wherein the semiconductor device includes four side surfaces, and wherein a first side surface and a second side surface of the four side surfaces are opposite to each other along a second direction perpendicular to the first direction, and a third side surface and a fourth side surface of the four side surfaces are opposite to each other along a third direction perpendicular to both the first and second directions; and One or more notches extending along the first direction into a portion of at least one of the four side surfaces, wherein the remaining portion of the at least one of the four side surfaces is substantially flat and intersects with at least one of the one or more notches along the first direction. Wherein, a portion of one or more of the four side surfaces is substantially flat and extends from the first surface of the semiconductor device to the second surface, and wherein the first surface and the second surface of the semiconductor device are opposite to each other along the first direction.

16. The semiconductor device according to claim 15, wherein, The circuit layer includes a notch region connected to the one or more notches.

17. The semiconductor device according to claim 15 or 16, wherein, The length of the one or more notches along the second direction is in the range of 10 μm to 20 μm.

18. The semiconductor device according to any one of claims 15 to 17, wherein, The sidewalls of the one or more recesses comprise substantially flat surfaces.

19. The semiconductor device according to any one of claims 15 to 18, wherein, The slope of a first portion of the sidewall of the one or more notches is greater than the slope of a second portion of the sidewall of the one or more notches, and the first portion of the sidewall of the one or more notches is closer to the first surface of the semiconductor device along the first direction than the second portion of the sidewall of the one or more notches.

20. The semiconductor device according to any one of claims 15 to 19, wherein, The one or more notches extend along the first direction into the circuit layer of the semiconductor device.

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